1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _RTW_HE_H_ 16*4882a593Smuzhiyun #define _RTW_HE_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Set HE MAC Capabilities Information */ 19*4882a593Smuzhiyun #define SET_HE_MAC_CAP_HTC_HE_SUPPORT(_pEleStart, _val) \ 20*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 1, _val) 21*4882a593Smuzhiyun #define SET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(_pEleStart, _val) \ 22*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 1, 1, _val) 23*4882a593Smuzhiyun #define SET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(_pEleStart, _val) \ 24*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 1, _val) 25*4882a593Smuzhiyun #define SET_HE_MAC_CAP_DYNAMIC_FRAG_SUPPORT(_pEleStart, _val) \ 26*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 2, _val) 27*4882a593Smuzhiyun #define SET_HE_MAC_CAP_MAX_FRAG_MSDU_EXP(_pEleStart, _val) \ 28*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 3, _val) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SET_HE_MAC_CAP_MIN_FRAG_SIZE(_pEleStart, _val) \ 31*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) 32*4882a593Smuzhiyun #define SET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(_pEleStart, _val) \ 33*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) 34*4882a593Smuzhiyun #define SET_HE_MAC_CAP_MULTI_TID_AGG_RX_SUPPORT(_pEleStart, _val) \ 35*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 3, _val) 36*4882a593Smuzhiyun #define SET_HE_MAC_CAP_LINK_ADAPT_SUPPORT(_pEleStart, _val) \ 37*4882a593Smuzhiyun SET_BITS_TO_LE_2BYTE((_pEleStart) + 1, 7, 2, _val) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define SET_HE_MAC_CAP_ALL_ACK_SUPPORT(_pEleStart, _val) \ 40*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) 41*4882a593Smuzhiyun #define SET_HE_MAC_CAP_TRS_SUPPORT(_pEleStart, _val) \ 42*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 2, 1, _val) 43*4882a593Smuzhiyun #define SET_HE_MAC_CAP_BRS_SUPPORT(_pEleStart, _val) \ 44*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 3, 1, _val) 45*4882a593Smuzhiyun #define SET_HE_MAC_CAP_BC_TWT_SUPPORT(_pEleStart, _val) \ 46*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 4, 1, _val) 47*4882a593Smuzhiyun #define SET_HE_MAC_CAP_32_BIT_BMP_SUPPORT(_pEleStart, _val) \ 48*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 5, 1, _val) 49*4882a593Smuzhiyun #define SET_HE_MAC_CAP_MU_CASCADE_SUPPORT(_pEleStart, _val) \ 50*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 6, 1, _val) 51*4882a593Smuzhiyun #define SET_HE_MAC_CAP_ACK_ENABLED_AGG_SUPPORT(_pEleStart, _val) \ 52*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 7, 1, _val) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define SET_HE_MAC_CAP_OM_CTRL_SUPPORT(_pEleStart, _val) \ 55*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 1, 1, _val) 56*4882a593Smuzhiyun #define SET_HE_MAC_CAP_OFDMA_RA_SUPPORT(_pEleStart, _val) \ 57*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 2, 1, _val) 58*4882a593Smuzhiyun #define SET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(_pEleStart, _val) \ 59*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 3, 2, _val) 60*4882a593Smuzhiyun #define SET_HE_MAC_CAP_AMSDU_FRAG_SUPPORT(_pEleStart, _val) \ 61*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 5, 1, _val) 62*4882a593Smuzhiyun #define SET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(_pEleStart, _val) \ 63*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 6, 1, _val) 64*4882a593Smuzhiyun #define SET_HE_MAC_CAP_RX_CTRL_FRAME_TO_MULTI_BSS(_pEleStart, _val) \ 65*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 7, 1, _val) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define SET_HE_MAC_CAP_BSRP_BQRP_AMPDU_AGG(_pEleStart, _val) \ 68*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 0, 1, _val) 69*4882a593Smuzhiyun #define SET_HE_MAC_CAP_QTP_SUPPORT(_pEleStart, _val) \ 70*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 1, 1, _val) 71*4882a593Smuzhiyun #define SET_HE_MAC_CAP_BQR_SUPPORT(_pEleStart, _val) \ 72*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 2, 1, _val) 73*4882a593Smuzhiyun #define SET_HE_MAC_CAP_PSR_RESPONDER(_pEleStart, _val) \ 74*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 3, 1, _val) 75*4882a593Smuzhiyun #define SET_HE_MAC_CAP_NDP_FEEDBACK_RPT_SUPPORT(_pEleStart, _val) \ 76*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 4, 1, _val) 77*4882a593Smuzhiyun #define SET_HE_MAC_CAP_OPS_SUPPORT(_pEleStart, _val) \ 78*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 5, 1, _val) 79*4882a593Smuzhiyun #define SET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(_pEleStart, _val) \ 80*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 6, 1, _val) 81*4882a593Smuzhiyun #define SET_HE_MAC_CAP_MULTI_AID_AGG_TX_SUPPORT(_pEleStart, _val) \ 82*4882a593Smuzhiyun SET_BITS_TO_LE_2BYTE((_pEleStart) + 4, 7, 3, _val) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define SET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(_pEleStart, _val) \ 85*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 2, 1, _val) 86*4882a593Smuzhiyun #define SET_HE_MAC_CAP_UL_2_996_TONE_RU_SUPPORT(_pEleStart, _val) \ 87*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 3, 1, _val) 88*4882a593Smuzhiyun #define SET_HE_MAC_CAP_OM_CTRL_UL_MU_DATA_DISABLE_RX(_pEleStart, _val) \ 89*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 4, 1, _val) 90*4882a593Smuzhiyun #define SET_HE_MAC_CAP_HE_DYNAMIC_SM_POWER_SAVE(_pEleStart, _val) \ 91*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 5, 1, _val) 92*4882a593Smuzhiyun #define SET_HE_MAC_CAP_PUNCTURED_SND_SUPPORT(_pEleStart, _val) \ 93*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 6, 1, _val) 94*4882a593Smuzhiyun #define SET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(_pEleStart, _val) \ 95*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 7, 1, _val) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Set HE PHY Capabilities Information */ 98*4882a593Smuzhiyun #define SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(_pEleStart, _val) \ 99*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 1, 7, _val) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PUNCTURED_PREAMBLE_RX(_pEleStart, _val) \ 102*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 4, _val) 103*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DEVICE_CLASS(_pEleStart, _val) \ 104*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 1, _val) 105*4882a593Smuzhiyun #define SET_HE_PHY_CAP_LDPC_IN_PAYLOAD(_pEleStart, _val) \ 106*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 5, 1, _val) 107*4882a593Smuzhiyun #define SET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 108*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 1, _val) 109*4882a593Smuzhiyun #define SET_HE_PHY_CAP_MIDAMBLE_TRX_MAX_NSTS(_pEleStart, _val) \ 110*4882a593Smuzhiyun SET_BITS_TO_LE_2BYTE((_pEleStart) + 1, 7, 2, _val) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(_pEleStart, _val) \ 113*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) 114*4882a593Smuzhiyun #define SET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(_pEleStart, _val) \ 115*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 2, 1, _val) 116*4882a593Smuzhiyun #define SET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(_pEleStart, _val) \ 117*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 3, 1, _val) 118*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DOPPLER_TX(_pEleStart, _val) \ 119*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 4, 1, _val) 120*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DOPPLER_RX(_pEleStart, _val) \ 121*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 5, 1, _val) 122*4882a593Smuzhiyun #define SET_HE_PHY_CAP_FULL_BW_UL_MUMIMO(_pEleStart, _val) \ 123*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 6, 1, _val) 124*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PARTIAL_BW_UL_MUMIMO(_pEleStart, _val) \ 125*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 7, 1, _val) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(_pEleStart, _val) \ 128*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 0, 2, _val) 129*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DCM_MAX_NSS_TX(_pEleStart, _val) \ 130*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 2, 1, _val) 131*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(_pEleStart, _val) \ 132*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 3, 2, _val) 133*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DCM_MAX_NSS_RX(_pEleStart, _val) \ 134*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 5, 1, _val) 135*4882a593Smuzhiyun #define SET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(_pEleStart, _val) \ 136*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 6, 1, _val) 137*4882a593Smuzhiyun #define SET_HE_PHY_CAP_SU_BFER(_pEleStart, _val) \ 138*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 7, 1, _val) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define SET_HE_PHY_CAP_SU_BFEE(_pEleStart, _val) \ 141*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 0, 1, _val) 142*4882a593Smuzhiyun #define SET_HE_PHY_CAP_MU_BFER(_pEleStart, _val) \ 143*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 1, 1, _val) 144*4882a593Smuzhiyun #define SET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(_pEleStart, _val) \ 145*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 2, 3, _val) 146*4882a593Smuzhiyun #define SET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(_pEleStart, _val) \ 147*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 5, 3, _val) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(_pEleStart, _val) \ 150*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 0, 3, _val) 151*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(_pEleStart, _val) \ 152*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 3, 3, _val) 153*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NG_16_SU_FEEDBACK(_pEleStart, _val) \ 154*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 6, 1, _val) 155*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NG_16_MU_FEEDBACK(_pEleStart, _val) \ 156*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 7, 1, _val) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define SET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(_pEleStart, _val) \ 159*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 0, 1, _val) 160*4882a593Smuzhiyun #define SET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(_pEleStart, _val) \ 161*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 1, 1, _val) 162*4882a593Smuzhiyun #define SET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(_pEleStart, _val) \ 163*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 2, 1, _val) 164*4882a593Smuzhiyun #define SET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(_pEleStart, _val) \ 165*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 3, 1, _val) 166*4882a593Smuzhiyun #define SET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(_pEleStart, _val) \ 167*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 4, 1, _val) 168*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(_pEleStart, _val) \ 169*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 5, 1, _val) 170*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PARTIAL_BW_DL_MU_MIMO(_pEleStart, _val) \ 171*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 6, 1, _val) 172*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(_pEleStart, _val) \ 173*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 7, 1, _val) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PSR_BASED_SR_SUPPORT(_pEleStart, _val) \ 176*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 0, 1, _val) 177*4882a593Smuzhiyun #define SET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(_pEleStart, _val) \ 178*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 1, 1, _val) 179*4882a593Smuzhiyun #define SET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 180*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 2, 1, _val) 181*4882a593Smuzhiyun #define SET_HE_PHY_CAP_MAX_NC(_pEleStart, _val) \ 182*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 3, 3, _val) 183*4882a593Smuzhiyun #define SET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(_pEleStart, _val) \ 184*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 6, 1, _val) 185*4882a593Smuzhiyun #define SET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(_pEleStart, _val) \ 186*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 7, 1, _val) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define SET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 189*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 0, 1, _val) 190*4882a593Smuzhiyun #define SET_HE_PHY_CAP_20M_IN_40M_HE_PPDU_IN_2G4(_pEleStart, _val) \ 191*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 1, 1, _val) 192*4882a593Smuzhiyun #define SET_HE_PHY_CAP_20M_IN_160C_160NC_HE_PPDU(_pEleStart, _val) \ 193*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 2, 1, _val) 194*4882a593Smuzhiyun #define SET_HE_PHY_CAP_80M_IN_160C_160NC_HE_PPDU(_pEleStart, _val) \ 195*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 3, 1, _val) 196*4882a593Smuzhiyun #define SET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 197*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 4, 1, _val) 198*4882a593Smuzhiyun #define SET_HE_PHY_CAP_MIDAMBLE_TRX_2X_1X_LTF(_pEleStart, _val) \ 199*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 5, 1, _val) 200*4882a593Smuzhiyun #define SET_HE_PHY_CAP_DCM_MAX_RU(_pEleStart, _val) \ 201*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 6, 2, _val) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define SET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(_pEleStart, _val) \ 204*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 0, 1, _val) 205*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(_pEleStart, _val) \ 206*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 1, 1, _val) 207*4882a593Smuzhiyun #define SET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart, _val) \ 208*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 2, 1, _val) 209*4882a593Smuzhiyun #define SET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart, _val) \ 210*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 3, 1, _val) 211*4882a593Smuzhiyun #define SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(_pEleStart, _val) \ 212*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 4, 1, _val) 213*4882a593Smuzhiyun #define SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(_pEleStart, _val) \ 214*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 5, 1, _val) 215*4882a593Smuzhiyun #define SET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(_pEleStart, _val) \ 216*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 6, 2, _val) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* Set Supported HE-MCS And NSS Set Information */ 219*4882a593Smuzhiyun #define SET_HE_CAP_MCS_1SS(_pEleStart, _val) \ 220*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) 221*4882a593Smuzhiyun #define SET_HE_CAP_MCS_2SS(_pEleStart, _val) \ 222*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) 223*4882a593Smuzhiyun #define SET_HE_CAP_MCS_3SS(_pEleStart, _val) \ 224*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 2, _val) 225*4882a593Smuzhiyun #define SET_HE_CAP_MCS_4SS(_pEleStart, _val) \ 226*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 2, _val) 227*4882a593Smuzhiyun #define SET_HE_CAP_MCS_5SS(_pEleStart, _val) \ 228*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) 229*4882a593Smuzhiyun #define SET_HE_CAP_MCS_6SS(_pEleStart, _val) \ 230*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) 231*4882a593Smuzhiyun #define SET_HE_CAP_MCS_7SS(_pEleStart, _val) \ 232*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 2, _val) 233*4882a593Smuzhiyun #define SET_HE_CAP_MCS_8SS(_pEleStart, _val) \ 234*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 2, _val) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart, _val) \ 237*4882a593Smuzhiyun SET_HE_CAP_MCS_1SS(_pEleStart, _val) 238*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart, _val) \ 239*4882a593Smuzhiyun SET_HE_CAP_MCS_2SS(_pEleStart, _val) 240*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart, _val) \ 241*4882a593Smuzhiyun SET_HE_CAP_MCS_3SS(_pEleStart, _val) 242*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart, _val) \ 243*4882a593Smuzhiyun SET_HE_CAP_MCS_4SS(_pEleStart, _val) 244*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart, _val) \ 245*4882a593Smuzhiyun SET_HE_CAP_MCS_5SS(_pEleStart, _val) 246*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart, _val) \ 247*4882a593Smuzhiyun SET_HE_CAP_MCS_6SS(_pEleStart, _val) 248*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart, _val) \ 249*4882a593Smuzhiyun SET_HE_CAP_MCS_7SS(_pEleStart, _val) 250*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart, _val) \ 251*4882a593Smuzhiyun SET_HE_CAP_MCS_8SS(_pEleStart, _val) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart, _val) \ 254*4882a593Smuzhiyun SET_HE_CAP_MCS_1SS(_pEleStart + 2, _val) 255*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart, _val) \ 256*4882a593Smuzhiyun SET_HE_CAP_MCS_2SS(_pEleStart + 2, _val) 257*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart, _val) \ 258*4882a593Smuzhiyun SET_HE_CAP_MCS_3SS(_pEleStart + 2, _val) 259*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart, _val) \ 260*4882a593Smuzhiyun SET_HE_CAP_MCS_4SS(_pEleStart + 2, _val) 261*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart, _val) \ 262*4882a593Smuzhiyun SET_HE_CAP_MCS_5SS(_pEleStart + 2, _val) 263*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart, _val) \ 264*4882a593Smuzhiyun SET_HE_CAP_MCS_6SS(_pEleStart + 2, _val) 265*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart, _val) \ 266*4882a593Smuzhiyun SET_HE_CAP_MCS_7SS(_pEleStart + 2, _val) 267*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart, _val) \ 268*4882a593Smuzhiyun SET_HE_CAP_MCS_8SS(_pEleStart + 2, _val) 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_1SS(_pEleStart, _val) \ 271*4882a593Smuzhiyun SET_HE_CAP_MCS_1SS(_pEleStart + 4, _val) 272*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_2SS(_pEleStart, _val) \ 273*4882a593Smuzhiyun SET_HE_CAP_MCS_2SS(_pEleStart + 4, _val) 274*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_3SS(_pEleStart, _val) \ 275*4882a593Smuzhiyun SET_HE_CAP_MCS_3SS(_pEleStart + 4, _val) 276*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_4SS(_pEleStart, _val) \ 277*4882a593Smuzhiyun SET_HE_CAP_MCS_4SS(_pEleStart + 4, _val) 278*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_5SS(_pEleStart, _val) \ 279*4882a593Smuzhiyun SET_HE_CAP_MCS_5SS(_pEleStart + 4, _val) 280*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_6SS(_pEleStart, _val) \ 281*4882a593Smuzhiyun SET_HE_CAP_MCS_6SS(_pEleStart + 4, _val) 282*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_7SS(_pEleStart, _val) \ 283*4882a593Smuzhiyun SET_HE_CAP_MCS_7SS(_pEleStart + 4, _val) 284*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_160MHZ_8SS(_pEleStart, _val) \ 285*4882a593Smuzhiyun SET_HE_CAP_MCS_8SS(_pEleStart + 4, _val) 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_1SS(_pEleStart, _val) \ 288*4882a593Smuzhiyun SET_HE_CAP_MCS_1SS(_pEleStart + 6, _val) 289*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_2SS(_pEleStart, _val) \ 290*4882a593Smuzhiyun SET_HE_CAP_MCS_2SS(_pEleStart + 6, _val) 291*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_3SS(_pEleStart, _val) \ 292*4882a593Smuzhiyun SET_HE_CAP_MCS_3SS(_pEleStart + 6, _val) 293*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_4SS(_pEleStart, _val) \ 294*4882a593Smuzhiyun SET_HE_CAP_MCS_4SS(_pEleStart + 6, _val) 295*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_5SS(_pEleStart, _val) \ 296*4882a593Smuzhiyun SET_HE_CAP_MCS_5SS(_pEleStart + 6, _val) 297*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_6SS(_pEleStart, _val) \ 298*4882a593Smuzhiyun SET_HE_CAP_MCS_6SS(_pEleStart + 6, _val) 299*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_7SS(_pEleStart, _val) \ 300*4882a593Smuzhiyun SET_HE_CAP_MCS_7SS(_pEleStart + 6, _val) 301*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_160MHZ_8SS(_pEleStart, _val) \ 302*4882a593Smuzhiyun SET_HE_CAP_MCS_8SS(_pEleStart + 6, _val) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_1SS(_pEleStart, _val) \ 305*4882a593Smuzhiyun SET_HE_CAP_MCS_1SS(_pEleStart + 8, _val) 306*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_2SS(_pEleStart, _val) \ 307*4882a593Smuzhiyun SET_HE_CAP_MCS_2SS(_pEleStart + 8, _val) 308*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_3SS(_pEleStart, _val) \ 309*4882a593Smuzhiyun SET_HE_CAP_MCS_3SS(_pEleStart + 8, _val) 310*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_4SS(_pEleStart, _val) \ 311*4882a593Smuzhiyun SET_HE_CAP_MCS_4SS(_pEleStart + 8, _val) 312*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_5SS(_pEleStart, _val) \ 313*4882a593Smuzhiyun SET_HE_CAP_MCS_5SS(_pEleStart + 8, _val) 314*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_6SS(_pEleStart, _val) \ 315*4882a593Smuzhiyun SET_HE_CAP_MCS_6SS(_pEleStart + 8, _val) 316*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_7SS(_pEleStart, _val) \ 317*4882a593Smuzhiyun SET_HE_CAP_MCS_7SS(_pEleStart + 8, _val) 318*4882a593Smuzhiyun #define SET_HE_CAP_RX_MCS_80_80MHZ_8SS(_pEleStart, _val) \ 319*4882a593Smuzhiyun SET_HE_CAP_MCS_8SS(_pEleStart + 8, _val) 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_1SS(_pEleStart, _val) \ 322*4882a593Smuzhiyun SET_HE_CAP_MCS_1SS(_pEleStart + 10, _val) 323*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_2SS(_pEleStart, _val) \ 324*4882a593Smuzhiyun SET_HE_CAP_MCS_2SS(_pEleStart + 10, _val) 325*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_3SS(_pEleStart, _val) \ 326*4882a593Smuzhiyun SET_HE_CAP_MCS_3SS(_pEleStart + 10, _val) 327*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_4SS(_pEleStart, _val) \ 328*4882a593Smuzhiyun SET_HE_CAP_MCS_4SS(_pEleStart + 10, _val) 329*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_5SS(_pEleStart, _val) \ 330*4882a593Smuzhiyun SET_HE_CAP_MCS_5SS(_pEleStart + 10, _val) 331*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_6SS(_pEleStart, _val) \ 332*4882a593Smuzhiyun SET_HE_CAP_MCS_6SS(_pEleStart + 10, _val) 333*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_7SS(_pEleStart, _val) \ 334*4882a593Smuzhiyun SET_HE_CAP_MCS_7SS(_pEleStart + 10, _val) 335*4882a593Smuzhiyun #define SET_HE_CAP_TX_MCS_80_80MHZ_8SS(_pEleStart, _val) \ 336*4882a593Smuzhiyun SET_HE_CAP_MCS_8SS(_pEleStart + 10, _val) 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* Set PPE Threshold */ 339*4882a593Smuzhiyun #define SET_HE_CAP_PPE_NSTS(_pEleStart, _val) \ 340*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 3, _val) 341*4882a593Smuzhiyun #define SET_HE_CAP_PPE_PU_IDX_BITMASK(_pEleStart, _val) \ 342*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 4, _val) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* Get HE MAC Capabilities Information */ 345*4882a593Smuzhiyun #define GET_HE_MAC_CAP_HTC_HE_SUPPORT(_pEleStart) \ 346*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 1) 347*4882a593Smuzhiyun #define GET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(_pEleStart) \ 348*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 1, 1) 349*4882a593Smuzhiyun #define GET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(_pEleStart) \ 350*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 2, 1) 351*4882a593Smuzhiyun #define GET_HE_MAC_CAP_DYNAMIC_FRAG_SUPPORT(_pEleStart) \ 352*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 3, 2) 353*4882a593Smuzhiyun #define GET_HE_MAC_CAP_MAX_FRAG_MSDU_EXP(_pEleStart) \ 354*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 5, 3) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #define GET_HE_MAC_CAP_MIN_FRAG_SIZE(_pEleStart) \ 357*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) 358*4882a593Smuzhiyun #define GET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(_pEleStart) \ 359*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) 360*4882a593Smuzhiyun #define GET_HE_MAC_CAP_MULTI_TID_AGG_RX_SUPPORT(_pEleStart) \ 361*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 3) 362*4882a593Smuzhiyun #define GET_HE_MAC_CAP_LINK_ADAPT_SUPPORT(_pEleStart) \ 363*4882a593Smuzhiyun LE_BITS_TO_2BYTE((_pEleStart) + 1, 7, 2) 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun #define GET_HE_MAC_CAP_ALL_ACK_SUPPORT(_pEleStart) \ 366*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) 367*4882a593Smuzhiyun #define GET_HE_MAC_CAP_TRS_SUPPORT(_pEleStart) \ 368*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 2, 1) 369*4882a593Smuzhiyun #define GET_HE_MAC_CAP_BRS_SUPPORT(_pEleStart) \ 370*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 3, 1) 371*4882a593Smuzhiyun #define GET_HE_MAC_CAP_BC_TWT_SUPPORT(_pEleStart) \ 372*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 4, 1) 373*4882a593Smuzhiyun #define GET_HE_MAC_CAP_32_BIT_BMP_SUPPORT(_pEleStart) \ 374*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 5, 1) 375*4882a593Smuzhiyun #define GET_HE_MAC_CAP_MU_CASCADE_SUPPORT(_pEleStart) \ 376*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 6, 1) 377*4882a593Smuzhiyun #define GET_HE_MAC_CAP_ACK_ENABLED_AGG_SUPPORT(_pEleStart) \ 378*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 7, 1) 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define GET_HE_MAC_CAP_OM_CTRL_SUPPORT(_pEleStart) \ 381*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 1, 1) 382*4882a593Smuzhiyun #define GET_HE_MAC_CAP_OFDMA_RA_SUPPORT(_pEleStart) \ 383*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 2, 1) 384*4882a593Smuzhiyun #define GET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(_pEleStart) \ 385*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 3, 2) 386*4882a593Smuzhiyun #define GET_HE_MAC_CAP_AMSDU_FRAG_SUPPORT(_pEleStart) \ 387*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 5, 1) 388*4882a593Smuzhiyun #define GET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(_pEleStart) \ 389*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) 390*4882a593Smuzhiyun #define GET_HE_MAC_CAP_RX_CTRL_FRAME_TO_MULTI_BSS(_pEleStart) \ 391*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #define GET_HE_MAC_CAP_BSRP_BQRP_AMPDU_AGG(_pEleStart) \ 394*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 1) 395*4882a593Smuzhiyun #define GET_HE_MAC_CAP_QTP_SUPPORT(_pEleStart) \ 396*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 1, 1) 397*4882a593Smuzhiyun #define GET_HE_MAC_CAP_BQR_SUPPORT(_pEleStart) \ 398*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 2, 1) 399*4882a593Smuzhiyun #define GET_HE_MAC_CAP_PSR_RESPONDER(_pEleStart) \ 400*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 3, 1) 401*4882a593Smuzhiyun #define GET_HE_MAC_CAP_NDP_FEEDBACK_RPT_SUPPORT(_pEleStart) \ 402*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 4, 1) 403*4882a593Smuzhiyun #define GET_HE_MAC_CAP_OPS_SUPPORT(_pEleStart) \ 404*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 1) 405*4882a593Smuzhiyun #define GET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(_pEleStart) \ 406*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 6, 1) 407*4882a593Smuzhiyun #define GET_HE_MAC_CAP_MULTI_AID_AGG_TX_SUPPORT(_pEleStart) \ 408*4882a593Smuzhiyun LE_BITS_TO_2BYTE((_pEleStart) + 4, 7, 3) 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun #define GET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(_pEleStart) \ 411*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 2, 1) 412*4882a593Smuzhiyun #define GET_HE_MAC_CAP_UL_2_996_TONE_RU_SUPPORT(_pEleStart) \ 413*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 3, 1) 414*4882a593Smuzhiyun #define GET_HE_MAC_CAP_OM_CTRL_UL_MU_DATA_DISABLE_RX(_pEleStart) \ 415*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 4, 1) 416*4882a593Smuzhiyun #define GET_HE_MAC_CAP_HE_DYNAMIC_SM_POWER_SAVE(_pEleStart) \ 417*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 5, 1) 418*4882a593Smuzhiyun #define GET_HE_MAC_CAP_PUNCTURED_SND_SUPPORT(_pEleStart) \ 419*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 6, 1) 420*4882a593Smuzhiyun #define GET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(_pEleStart) \ 421*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 7, 1) 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun /* Get HE PHY Capabilities Information */ 424*4882a593Smuzhiyun #define GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(_pEleStart) \ 425*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 1, 7) 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PUNCTURED_PREAMBLE_RX(_pEleStart) \ 428*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 4) 429*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DEVICE_CLASS(_pEleStart) \ 430*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 1) 431*4882a593Smuzhiyun #define GET_HE_PHY_CAP_LDPC_IN_PAYLOAD(_pEleStart) \ 432*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 5, 1) 433*4882a593Smuzhiyun #define GET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart) \ 434*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 1) 435*4882a593Smuzhiyun #define GET_HE_PHY_CAP_MIDAMBLE_TRX_MAX_NSTS(_pEleStart) \ 436*4882a593Smuzhiyun LE_BITS_TO_2BYTE((_pEleStart) + 1, 7, 2) 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(_pEleStart) \ 439*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) 440*4882a593Smuzhiyun #define GET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(_pEleStart) \ 441*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 2, 1) 442*4882a593Smuzhiyun #define GET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(_pEleStart) \ 443*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 3, 1) 444*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DOPPLER_TX(_pEleStart) \ 445*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 4, 1) 446*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DOPPLER_RX(_pEleStart) \ 447*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 5, 1) 448*4882a593Smuzhiyun #define GET_HE_PHY_CAP_FULL_BW_UL_MUMIMO(_pEleStart) \ 449*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 6, 1) 450*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PARTIAL_BW_UL_MUMIMO(_pEleStart) \ 451*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 7, 1) 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(_pEleStart) \ 454*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 2) 455*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DCM_MAX_NSS_TX(_pEleStart) \ 456*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 2, 1) 457*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(_pEleStart) \ 458*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 3, 2) 459*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DCM_MAX_NSS_RX(_pEleStart) \ 460*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 5, 1) 461*4882a593Smuzhiyun #define GET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(_pEleStart) \ 462*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) 463*4882a593Smuzhiyun #define GET_HE_PHY_CAP_SU_BFER(_pEleStart) \ 464*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun #define GET_HE_PHY_CAP_SU_BFEE(_pEleStart) \ 467*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 1) 468*4882a593Smuzhiyun #define GET_HE_PHY_CAP_MU_BFER(_pEleStart) \ 469*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 1, 1) 470*4882a593Smuzhiyun #define GET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(_pEleStart) \ 471*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 2, 3) 472*4882a593Smuzhiyun #define GET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(_pEleStart) \ 473*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 3) 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(_pEleStart) \ 476*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 0, 3) 477*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(_pEleStart) \ 478*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 3, 3) 479*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NG_16_SU_FEEDBACK(_pEleStart) \ 480*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 6, 1) 481*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NG_16_MU_FEEDBACK(_pEleStart) \ 482*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 7, 1) 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun #define GET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(_pEleStart) \ 485*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 0, 1) 486*4882a593Smuzhiyun #define GET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(_pEleStart) \ 487*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 1, 1) 488*4882a593Smuzhiyun #define GET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(_pEleStart) \ 489*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 2, 1) 490*4882a593Smuzhiyun #define GET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(_pEleStart) \ 491*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 3, 1) 492*4882a593Smuzhiyun #define GET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(_pEleStart) \ 493*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 4, 1) 494*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(_pEleStart) \ 495*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 5, 1) 496*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PARTIAL_BW_DL_MU_MIMO(_pEleStart) \ 497*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 6, 1) 498*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(_pEleStart) \ 499*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 7, 1) 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PSR_BASED_SR_SUPPORT(_pEleStart) \ 502*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 0, 1) 503*4882a593Smuzhiyun #define GET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(_pEleStart) \ 504*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 1, 1) 505*4882a593Smuzhiyun #define GET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart) \ 506*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 2, 1) 507*4882a593Smuzhiyun #define GET_HE_PHY_CAP_MAX_NC(_pEleStart) \ 508*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 3, 3) 509*4882a593Smuzhiyun #define GET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(_pEleStart) \ 510*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 6, 1) 511*4882a593Smuzhiyun #define GET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(_pEleStart) \ 512*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 7, 1) 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #define GET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart) \ 515*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 0, 1) 516*4882a593Smuzhiyun #define GET_HE_PHY_CAP_20M_IN_40M_HE_PPDU_IN_2G4(_pEleStart) \ 517*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 1, 1) 518*4882a593Smuzhiyun #define GET_HE_PHY_CAP_20M_IN_160C_160NC_HE_PPDU(_pEleStart) \ 519*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 2, 1) 520*4882a593Smuzhiyun #define GET_HE_PHY_CAP_80M_IN_160C_160NC_HE_PPDU(_pEleStart) \ 521*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 3, 1) 522*4882a593Smuzhiyun #define GET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart) \ 523*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 4, 1) 524*4882a593Smuzhiyun #define GET_HE_PHY_CAP_MIDAMBLE_TRX_2X_1X_LTF(_pEleStart) \ 525*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 5, 1) 526*4882a593Smuzhiyun #define GET_HE_PHY_CAP_DCM_MAX_RU(_pEleStart) \ 527*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 6, 2) 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun #define GET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(_pEleStart) \ 530*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 0, 1) 531*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(_pEleStart) \ 532*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 1, 1) 533*4882a593Smuzhiyun #define GET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart) \ 534*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 2, 1) 535*4882a593Smuzhiyun #define GET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart) \ 536*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 3, 1) 537*4882a593Smuzhiyun #define GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(_pEleStart) \ 538*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 4, 1) 539*4882a593Smuzhiyun #define GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(_pEleStart) \ 540*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 5, 1) 541*4882a593Smuzhiyun #define GET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(_pEleStart) \ 542*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 6, 2) 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun /* Get Supported HE-MCS And NSS Set Information */ 545*4882a593Smuzhiyun #define GET_HE_CAP_MCS_1SS(_pEleStart) \ 546*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 2) 547*4882a593Smuzhiyun #define GET_HE_CAP_MCS_2SS(_pEleStart) \ 548*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 2, 2) 549*4882a593Smuzhiyun #define GET_HE_CAP_MCS_3SS(_pEleStart) \ 550*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 4, 2) 551*4882a593Smuzhiyun #define GET_HE_CAP_MCS_4SS(_pEleStart) \ 552*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 6, 2) 553*4882a593Smuzhiyun #define GET_HE_CAP_MCS_5SS(_pEleStart) \ 554*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) 555*4882a593Smuzhiyun #define GET_HE_CAP_MCS_6SS(_pEleStart) \ 556*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) 557*4882a593Smuzhiyun #define GET_HE_CAP_MCS_7SS(_pEleStart) \ 558*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 2) 559*4882a593Smuzhiyun #define GET_HE_CAP_MCS_8SS(_pEleStart) \ 560*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 2) 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart) \ 563*4882a593Smuzhiyun GET_HE_CAP_MCS_1SS(_pEleStart) 564*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart) \ 565*4882a593Smuzhiyun GET_HE_CAP_MCS_2SS(_pEleStart) 566*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart) \ 567*4882a593Smuzhiyun GET_HE_CAP_MCS_3SS(_pEleStart) 568*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart) \ 569*4882a593Smuzhiyun GET_HE_CAP_MCS_4SS(_pEleStart) 570*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart) \ 571*4882a593Smuzhiyun GET_HE_CAP_MCS_5SS(_pEleStart) 572*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart) \ 573*4882a593Smuzhiyun GET_HE_CAP_MCS_6SS(_pEleStart) 574*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart) \ 575*4882a593Smuzhiyun GET_HE_CAP_MCS_7SS(_pEleStart) 576*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart) \ 577*4882a593Smuzhiyun GET_HE_CAP_MCS_8SS(_pEleStart) 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart) \ 580*4882a593Smuzhiyun GET_HE_CAP_MCS_1SS(_pEleStart + 2) 581*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart) \ 582*4882a593Smuzhiyun GET_HE_CAP_MCS_2SS(_pEleStart + 2) 583*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart) \ 584*4882a593Smuzhiyun GET_HE_CAP_MCS_3SS(_pEleStart + 2) 585*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart) \ 586*4882a593Smuzhiyun GET_HE_CAP_MCS_4SS(_pEleStart + 2) 587*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart) \ 588*4882a593Smuzhiyun GET_HE_CAP_MCS_5SS(_pEleStart + 2) 589*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart) \ 590*4882a593Smuzhiyun GET_HE_CAP_MCS_6SS(_pEleStart + 2) 591*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart) \ 592*4882a593Smuzhiyun GET_HE_CAP_MCS_7SS(_pEleStart + 2) 593*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart) \ 594*4882a593Smuzhiyun GET_HE_CAP_MCS_8SS(_pEleStart + 2) 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_1SS(_pEleStart) \ 597*4882a593Smuzhiyun GET_HE_CAP_MCS_1SS(_pEleStart + 4) 598*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_2SS(_pEleStart) \ 599*4882a593Smuzhiyun GET_HE_CAP_MCS_2SS(_pEleStart + 4) 600*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_3SS(_pEleStart) \ 601*4882a593Smuzhiyun GET_HE_CAP_MCS_3SS(_pEleStart + 4) 602*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_4SS(_pEleStart) \ 603*4882a593Smuzhiyun GET_HE_CAP_MCS_4SS(_pEleStart + 4) 604*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_5SS(_pEleStart) \ 605*4882a593Smuzhiyun GET_HE_CAP_MCS_5SS(_pEleStart + 4) 606*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_6SS(_pEleStart) \ 607*4882a593Smuzhiyun GET_HE_CAP_MCS_6SS(_pEleStart + 4) 608*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_7SS(_pEleStart) \ 609*4882a593Smuzhiyun GET_HE_CAP_MCS_7SS(_pEleStart + 4) 610*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_160MHZ_8SS(_pEleStart) \ 611*4882a593Smuzhiyun GET_HE_CAP_MCS_8SS(_pEleStart + 4) 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_1SS(_pEleStart) \ 614*4882a593Smuzhiyun GET_HE_CAP_MCS_1SS(_pEleStart + 6) 615*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_2SS(_pEleStart) \ 616*4882a593Smuzhiyun GET_HE_CAP_MCS_2SS(_pEleStart + 6) 617*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_3SS(_pEleStart) \ 618*4882a593Smuzhiyun GET_HE_CAP_MCS_3SS(_pEleStart + 6) 619*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_4SS(_pEleStart) \ 620*4882a593Smuzhiyun GET_HE_CAP_MCS_4SS(_pEleStart + 6) 621*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_5SS(_pEleStart) \ 622*4882a593Smuzhiyun GET_HE_CAP_MCS_5SS(_pEleStart + 6) 623*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_6SS(_pEleStart) \ 624*4882a593Smuzhiyun GET_HE_CAP_MCS_6SS(_pEleStart + 6) 625*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_7SS(_pEleStart) \ 626*4882a593Smuzhiyun GET_HE_CAP_MCS_7SS(_pEleStart + 6) 627*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_160MHZ_8SS(_pEleStart) \ 628*4882a593Smuzhiyun GET_HE_CAP_MCS_8SS(_pEleStart + 6) 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_1SS(_pEleStart) \ 631*4882a593Smuzhiyun GET_HE_CAP_MCS_1SS(_pEleStart + 8) 632*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_2SS(_pEleStart) \ 633*4882a593Smuzhiyun GET_HE_CAP_MCS_2SS(_pEleStart + 8) 634*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_3SS(_pEleStart) \ 635*4882a593Smuzhiyun GET_HE_CAP_MCS_3SS(_pEleStart + 8) 636*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_4SS(_pEleStart) \ 637*4882a593Smuzhiyun GET_HE_CAP_MCS_4SS(_pEleStart + 8) 638*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_5SS(_pEleStart) \ 639*4882a593Smuzhiyun GET_HE_CAP_MCS_5SS(_pEleStart + 8) 640*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_6SS(_pEleStart) \ 641*4882a593Smuzhiyun GET_HE_CAP_MCS_6SS(_pEleStart + 8) 642*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_7SS(_pEleStart) \ 643*4882a593Smuzhiyun GET_HE_CAP_MCS_7SS(_pEleStart + 8) 644*4882a593Smuzhiyun #define GET_HE_CAP_RX_MCS_80_80MHZ_8SS(_pEleStart) \ 645*4882a593Smuzhiyun GET_HE_CAP_MCS_8SS(_pEleStart + 8) 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_1SS(_pEleStart) \ 648*4882a593Smuzhiyun GET_HE_CAP_MCS_1SS(_pEleStart + 10) 649*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_2SS(_pEleStart) \ 650*4882a593Smuzhiyun GET_HE_CAP_MCS_2SS(_pEleStart + 10) 651*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_3SS(_pEleStart) \ 652*4882a593Smuzhiyun GET_HE_CAP_MCS_3SS(_pEleStart + 10) 653*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_4SS(_pEleStart) \ 654*4882a593Smuzhiyun GET_HE_CAP_MCS_4SS(_pEleStart + 10) 655*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_5SS(_pEleStart) \ 656*4882a593Smuzhiyun GET_HE_CAP_MCS_5SS(_pEleStart + 10) 657*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_6SS(_pEleStart) \ 658*4882a593Smuzhiyun GET_HE_CAP_MCS_6SS(_pEleStart + 10) 659*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_7SS(_pEleStart) \ 660*4882a593Smuzhiyun GET_HE_CAP_MCS_7SS(_pEleStart + 10) 661*4882a593Smuzhiyun #define GET_HE_CAP_TX_MCS_80_80MHZ_8SS(_pEleStart) \ 662*4882a593Smuzhiyun GET_HE_CAP_MCS_8SS(_pEleStart + 10) 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun /* Get PPE Threshold */ 665*4882a593Smuzhiyun #define GET_HE_CAP_PPE_NSTS(_pEleStart) \ 666*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 3) 667*4882a593Smuzhiyun #define GET_HE_CAP_PPE_PU_IDX_BITMASK(_pEleStart) \ 668*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 3, 4) 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun /* Set HE Operation element */ 671*4882a593Smuzhiyun #define SET_HE_OP_PARA_DEFAULT_PE_DUR(_pEleStart, _val) \ 672*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 3, _val) 673*4882a593Smuzhiyun #define SET_HE_OP_PARA_TWT_REQUIRED(_pEleStart, _val) \ 674*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 1, _val) 675*4882a593Smuzhiyun #define SET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(_pEleStart, _val) \ 676*4882a593Smuzhiyun SET_BITS_TO_LE_2BYTE(_pEleStart, 4, 10, _val) 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun #define SET_HE_OP_PARA_VHT_OP_INFO_PRESENT(_pEleStart, _val) \ 679*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 1, _val) 680*4882a593Smuzhiyun #define SET_HE_OP_PARA_CO_HOSTED_BSS(_pEleStart, _val) \ 681*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 7, 1, _val) 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun #define SET_HE_OP_PARA_ER_SU_DISABLE(_pEleStart, _val) \ 684*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 0, 1, _val) 685*4882a593Smuzhiyun #define SET_HE_OP_PARA_6GHZ_OP_INFO_PRESENT(_pEleStart, _val) \ 686*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun #define SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(_pEleStart, _val) \ 689*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 6, _val) 690*4882a593Smuzhiyun #define SET_HE_OP_BSS_COLOR_INFO_PARTIAL_BSS_COLOR(_pEleStart, _val) \ 691*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val) 692*4882a593Smuzhiyun #define SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(_pEleStart, _val) \ 693*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_1SS(_pEleStart, _val) \ 696*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) 697*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_2SS(_pEleStart, _val) \ 698*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) 699*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_3SS(_pEleStart, _val) \ 700*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 2, _val) 701*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_4SS(_pEleStart, _val) \ 702*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 2, _val) 703*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_5SS(_pEleStart, _val) \ 704*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) 705*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_6SS(_pEleStart, _val) \ 706*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) 707*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_7SS(_pEleStart, _val) \ 708*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 2, _val) 709*4882a593Smuzhiyun #define SET_HE_OP_BASIC_MCS_8SS(_pEleStart, _val) \ 710*4882a593Smuzhiyun SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 2, _val) 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun /* Values in HE spec */ 713*4882a593Smuzhiyun #define TXOP_DUR_RTS_TH_DISABLED 1023 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun /* Get HE Operation element */ 716*4882a593Smuzhiyun #define GET_HE_OP_PARA_DEFAULT_PE_DUR(_pEleStart) \ 717*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 3) 718*4882a593Smuzhiyun #define GET_HE_OP_PARA_TWT_REQUIRED(_pEleStart) \ 719*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 3, 1) 720*4882a593Smuzhiyun #define GET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(_pEleStart) \ 721*4882a593Smuzhiyun LE_BITS_TO_2BYTE(_pEleStart, 4, 10) 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun #define GET_HE_OP_PARA_VHT_OP_INFO_PRESENT(_pEleStart) \ 724*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 1) 725*4882a593Smuzhiyun #define GET_HE_OP_PARA_CO_HOSTED_BSS(_pEleStart) \ 726*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 7, 1) 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun #define GET_HE_OP_PARA_ER_SU_DISABLE(_pEleStart) \ 729*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 1) 730*4882a593Smuzhiyun #define GET_HE_OP_PARA_6GHZ_OP_INFO_PRESENT(_pEleStart) \ 731*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun #define GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(_pEleStart) \ 734*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 6) 735*4882a593Smuzhiyun #define GET_HE_OP_BSS_COLOR_INFO_PARTIAL_BSS_COLOR(_pEleStart) \ 736*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) 737*4882a593Smuzhiyun #define GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(_pEleStart) \ 738*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) 739*4882a593Smuzhiyun 740*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_1SS(_pEleStart) \ 741*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 2) 742*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_2SS(_pEleStart) \ 743*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 2, 2) 744*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_3SS(_pEleStart) \ 745*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 4, 2) 746*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_4SS(_pEleStart) \ 747*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 6, 2) 748*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_5SS(_pEleStart) \ 749*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) 750*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_6SS(_pEleStart) \ 751*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) 752*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_7SS(_pEleStart) \ 753*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 2) 754*4882a593Smuzhiyun #define GET_HE_OP_BASIC_MCS_8SS(_pEleStart) \ 755*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 2) 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun /* Get MU EDCA Parameter Set element */ 758*4882a593Smuzhiyun #define GET_HE_MU_EDCA_QOS_INFO(_pEleStart) \ 759*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 8) 760*4882a593Smuzhiyun #define GET_HE_MU_EDCA_QOS_INFO_UPDATE_CNT(_pEleStart) \ 761*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pEleStart, 0, 4) 762*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BE_AIFSN(_pEleStart) \ 763*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 4) 764*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BE_ACI(_pEleStart) \ 765*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 1, 5, 2) 766*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BE_ECW_MIN_MAX(_pEleStart) \ 767*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 8) 768*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BE_TIMER(_pEleStart) \ 769*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 8) 770*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BK_AIFSN(_pEleStart) \ 771*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 4) 772*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BK_ACI(_pEleStart) \ 773*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 2) 774*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BK_ECW_MIN_MAX(_pEleStart) \ 775*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 5, 0, 8) 776*4882a593Smuzhiyun #define GET_HE_MU_EDCA_BK_TIMER(_pEleStart) \ 777*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 6, 0, 8) 778*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VI_AIFSN(_pEleStart) \ 779*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 0, 4) 780*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VI_ACI(_pEleStart) \ 781*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 7, 5, 2) 782*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VI_ECW_MIN_MAX(_pEleStart) \ 783*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 8, 0, 8) 784*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VI_TIMER(_pEleStart) \ 785*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 9, 0, 8) 786*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VO_AIFSN(_pEleStart) \ 787*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 10, 0, 4) 788*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VO_ACI(_pEleStart) \ 789*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 10, 5, 2) 790*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VO_ECW_MIN_MAX(_pEleStart) \ 791*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 11, 0, 8) 792*4882a593Smuzhiyun #define GET_HE_MU_EDCA_VO_TIMER(_pEleStart) \ 793*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart) + 12, 0, 8) 794*4882a593Smuzhiyun 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun /* HE variant HT Control */ 797*4882a593Smuzhiyun #define HE_VAR_HTC 3 798*4882a593Smuzhiyun 799*4882a593Smuzhiyun #define HE_VAR_HTC_CID_TRS 0 800*4882a593Smuzhiyun #define HE_VAR_HTC_CID_OM 1 801*4882a593Smuzhiyun #define HE_VAR_HTC_CID_HLA 2 802*4882a593Smuzhiyun #define HE_VAR_HTC_CID_BSR 3 803*4882a593Smuzhiyun #define HE_VAR_HTC_CID_UPH 4 804*4882a593Smuzhiyun #define HE_VAR_HTC_CID_BQR 5 805*4882a593Smuzhiyun #define HE_VAR_HTC_CID_CAS 6 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun /* Set HE variant HT Control field */ 808*4882a593Smuzhiyun #define SET_HE_VAR_HTC(_pStart) \ 809*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 0, 2, HE_VAR_HTC) 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_TRS(_pStart) \ 812*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_TRS) 813*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_OM(_pStart) \ 814*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_OM) 815*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_HLA(_pStart) \ 816*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_HLA) 817*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_BSR(_pStart) \ 818*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_BSR) 819*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_UPH(_pStart) \ 820*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_UPH) 821*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_BQR(_pStart) \ 822*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_BQR) 823*4882a593Smuzhiyun #define SET_HE_VAR_HTC_CID_CAS(_pStart) \ 824*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_CAS) 825*4882a593Smuzhiyun 826*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_RX_NSS(_pStart, _val) \ 827*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6, 3, _val) 828*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_CH_WIDTH(_pStart, _val) \ 829*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 3, 2, _val) 830*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_UL_MU_DIS(_pStart, _val) \ 831*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 5, 1, _val) 832*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_TX_NSTS(_pStart, _val) \ 833*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 6, 3, _val) 834*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_ER_SU_DIS(_pStart, _val) \ 835*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 9, 1, _val) 836*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_DL_MU_MIMO_RR(_pStart, _val) \ 837*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 10, 1, _val) 838*4882a593Smuzhiyun #define SET_HE_VAR_HTC_OM_UL_MU_DATA_DIS(_pStart, _val) \ 839*4882a593Smuzhiyun SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 11, 1, _val) 840*4882a593Smuzhiyun 841*4882a593Smuzhiyun /* Get HE variant HT Control field */ 842*4882a593Smuzhiyun #define GET_VAR_HTC(_pStart) \ 843*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pStart, 0, 2) 844*4882a593Smuzhiyun #define GET_HE_VAR_HTC_CID(_pStart) \ 845*4882a593Smuzhiyun LE_BITS_TO_1BYTE(_pStart, 2, 4) 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun #define HE_MCS_SUPP_MSC0_TO_MSC7 0x0 /* 2b00 */ 848*4882a593Smuzhiyun #define HE_MCS_SUPP_MSC0_TO_MSC9 0x1 /* 2b01 */ 849*4882a593Smuzhiyun #define HE_MCS_SUPP_MSC0_TO_MSC11 0x2 /* 2b10 */ 850*4882a593Smuzhiyun #define HE_MSC_NOT_SUPP 0x3 /* 2b11 */ 851*4882a593Smuzhiyun #define HE_MSC_NOT_SUPP_BYTE ((HE_MSC_NOT_SUPP << 6) | (HE_MSC_NOT_SUPP << 4) \ 852*4882a593Smuzhiyun | (HE_MSC_NOT_SUPP << 2) | HE_MSC_NOT_SUPP) 853*4882a593Smuzhiyun 854*4882a593Smuzhiyun #define HE_DEV_CLASS_A 1 855*4882a593Smuzhiyun #define HE_DEV_CLASS_B 0 856*4882a593Smuzhiyun 857*4882a593Smuzhiyun /* 858*4882a593Smuzhiyun * HE_MAC_Cap (6) 859*4882a593Smuzhiyun * HE_PHY_Cap (11) 860*4882a593Smuzhiyun * HE_Support_MCS (4, 8 or 12) 861*4882a593Smuzhiyun * PPE_Thres (variable, max = 25) 862*4882a593Smuzhiyun */ 863*4882a593Smuzhiyun #define HE_CAP_ELE_MAC_CAP_LEN 6 864*4882a593Smuzhiyun #define HE_CAP_ELE_PHY_CAP_LEN 11 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_LEN_RX_80M 2 867*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_LEN_TX_80M 2 868*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_LEN_RX_160M 2 869*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_LEN_TX_160M 2 870*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_LEN_RX_80M_80M 2 871*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_LEN_TX_80M_80M 2 872*4882a593Smuzhiyun #define HE_CAP_ELE_SUPP_MCS_MAX_LEN (HE_CAP_ELE_SUPP_MCS_LEN_RX_80M \ 873*4882a593Smuzhiyun + HE_CAP_ELE_SUPP_MCS_LEN_TX_80M + HE_CAP_ELE_SUPP_MCS_LEN_RX_160M \ 874*4882a593Smuzhiyun + HE_CAP_ELE_SUPP_MCS_LEN_TX_160M + HE_CAP_ELE_SUPP_MCS_LEN_RX_80M_80M \ 875*4882a593Smuzhiyun + HE_CAP_ELE_SUPP_MCS_LEN_TX_80M_80M) 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun #define HE_CAP_ELE_PPE_THRE_MAX_LEN 25 878*4882a593Smuzhiyun 879*4882a593Smuzhiyun #define HE_CAP_ELE_MAX_LEN (1 + HE_CAP_ELE_MAC_CAP_LEN + HE_CAP_ELE_PHY_CAP_LEN \ 880*4882a593Smuzhiyun + HE_CAP_ELE_SUPP_MCS_MAX_LEN + HE_CAP_ELE_PPE_THRE_MAX_LEN) 881*4882a593Smuzhiyun /* #define HE_CAP_MAC_CAP_OFFSET 0 882*4882a593Smuzhiyun #define HE_CAP_PHY_CAP_OFFSET 6 883*4882a593Smuzhiyun #define HE_CAP_SUPPORT_MCS_OFFSET 17 884*4882a593Smuzhiyun */ 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun /* 887*4882a593Smuzhiyun * HE_Ope_Para (3) 888*4882a593Smuzhiyun * BSS_Color (1) 889*4882a593Smuzhiyun * Basic_MCS (2) 890*4882a593Smuzhiyun * VHT_Op (0 or 3) 891*4882a593Smuzhiyun * CoHosted_Bssid_Ind (0 or 1) 892*4882a593Smuzhiyun * 6Ghz_Ope_Info (0 or 5) 893*4882a593Smuzhiyun */ 894*4882a593Smuzhiyun #define HE_OPER_PARAMS_LEN 3 895*4882a593Smuzhiyun #define HE_OPER_BSS_COLOR_INFO_LEN 1 896*4882a593Smuzhiyun #define HE_OPER_BASIC_MCS_LEN 2 897*4882a593Smuzhiyun #define HE_OPER_VHT_OPER_INFO_LEN 3 898*4882a593Smuzhiyun #define HE_OPER_MAX_COHOST_BSSID_LEN 1 899*4882a593Smuzhiyun #define HE_OPER_6G_OPER_INFO_LEN 5 900*4882a593Smuzhiyun 901*4882a593Smuzhiyun #define HE_OPER_ELE_MAX_LEN (1 + HE_OPER_PARAMS_LEN + HE_OPER_BSS_COLOR_INFO_LEN \ 902*4882a593Smuzhiyun + HE_OPER_BASIC_MCS_LEN + HE_OPER_VHT_OPER_INFO_LEN \ 903*4882a593Smuzhiyun + HE_OPER_MAX_COHOST_BSSID_LEN + HE_OPER_6G_OPER_INFO_LEN) 904*4882a593Smuzhiyun /* #define HE_OPER_PARAS_OFFSET 0 905*4882a593Smuzhiyun #define HE_OPER_BSS_COLOR_OFFSET 3 906*4882a593Smuzhiyun #define HE_OPER_BASIC_MCS_OFFSET 4 907*4882a593Smuzhiyun */ 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun #define MAX_HE_GI_TYPE 3 910*4882a593Smuzhiyun #define MAX_HE_MCS_INDEX 12 * 2 /* 1SS + 2SS */ 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun enum rtw_he_actrl_om_mask { 913*4882a593Smuzhiyun OM_RX_NSS = BIT0, 914*4882a593Smuzhiyun OM_CH_BW = BIT1, 915*4882a593Smuzhiyun OM_UL_MU_DIS = BIT2, 916*4882a593Smuzhiyun OM_TX_NSTS = BIT3, 917*4882a593Smuzhiyun OM_ER_SU_DIS = BIT4, 918*4882a593Smuzhiyun OM_DL_MU_RR = BIT5, 919*4882a593Smuzhiyun OM_UL_MU_DATA_DIS = BIT6 920*4882a593Smuzhiyun }; 921*4882a593Smuzhiyun 922*4882a593Smuzhiyun struct rtw_he_actrl_om_ele { 923*4882a593Smuzhiyun u8 rx_nss; 924*4882a593Smuzhiyun u8 channel_width; 925*4882a593Smuzhiyun u8 ul_mu_disable; 926*4882a593Smuzhiyun u8 tx_nsts; 927*4882a593Smuzhiyun u8 er_su_disable; 928*4882a593Smuzhiyun u8 dl_mu_mimo_rr; 929*4882a593Smuzhiyun u8 ul_mu_data_disable; 930*4882a593Smuzhiyun }; 931*4882a593Smuzhiyun 932*4882a593Smuzhiyun 933*4882a593Smuzhiyun struct rtw_he_actrl_om { 934*4882a593Smuzhiyun /* om ctrl flag for normal tx pkt */ 935*4882a593Smuzhiyun u8 actrl_om_normal_tx; 936*4882a593Smuzhiyun u8 actrl_om_normal_tx_cnt; 937*4882a593Smuzhiyun /* current om ctrl element content */ 938*4882a593Smuzhiyun struct rtw_he_actrl_om_ele om_actrl_ele; 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun struct he_priv { 942*4882a593Smuzhiyun u8 he_option; 943*4882a593Smuzhiyun u8 he_cap[HE_CAP_ELE_MAX_LEN]; 944*4882a593Smuzhiyun u8 he_op[HE_OPER_ELE_MAX_LEN]; 945*4882a593Smuzhiyun u8 op_present; 946*4882a593Smuzhiyun u8 he_highest_rate; 947*4882a593Smuzhiyun u8 pre_he_muedca_cnt; 948*4882a593Smuzhiyun struct rtw_he_actrl_om om_info; 949*4882a593Smuzhiyun }; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /*trigger frame*/ 952*4882a593Smuzhiyun #define TRIGGER_FRAME_USER_INFO_SZ 5 /* byte */ 953*4882a593Smuzhiyun #define TRIGGER_FRAME_MIN_LENGTH 24 + TRIGGER_FRAME_USER_INFO_SZ /* byte , aleast one user info !!! */ 954*4882a593Smuzhiyun /*basic tigger frame with 1 byte trigger dependent info */ 955*4882a593Smuzhiyun #define TRIGGER_FRAME_BASIC_USER_INFO_SZ TRIGGER_FRAME_USER_INFO_SZ + 1 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun /*trigger frame User Info*/ 958*4882a593Smuzhiyun #define GET_TRIGGER_FRAME_TYPE(_pEleStart) \ 959*4882a593Smuzhiyun LE_BITS_TO_1BYTE((_pEleStart + 16), 0, 4) 960*4882a593Smuzhiyun 961*4882a593Smuzhiyun #define GET_TRIGGER_FRAME_USER_INFO_AID12(_user_info) \ 962*4882a593Smuzhiyun LE_BITS_TO_2BYTE(_user_info, 0, 12) 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun #define GET_TRIGGER_FRAME_USER_INFO_RUA(_user_info) \ 965*4882a593Smuzhiyun LE_BITS_TO_2BYTE((_user_info + 1), 4, 8) 966*4882a593Smuzhiyun 967*4882a593Smuzhiyun #define GET_TRIGGER_FRAME_USER_INFO_UL_MCS(_user_info) \ 968*4882a593Smuzhiyun LE_BITS_TO_2BYTE((_user_info + 2), 5, 4) 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun 971*4882a593Smuzhiyun enum rtw_he_trigger_frame_type { 972*4882a593Smuzhiyun TRIGGER_FRAME_T_BASIC = 0, 973*4882a593Smuzhiyun TRIGGER_FRAME_T_BFRP, 974*4882a593Smuzhiyun TRIGGER_FRAME_T_MUBAR, 975*4882a593Smuzhiyun TRIGGER_FRAME_T_MURTS, 976*4882a593Smuzhiyun TRIGGER_FRAME_T_BSRP, 977*4882a593Smuzhiyun TRIGGER_FRAME_T_GCR_MUBAR, 978*4882a593Smuzhiyun TRIGGER_FRAME_T_BQRP, 979*4882a593Smuzhiyun TRIGGER_FRAME_T_NFRP = 7, 980*4882a593Smuzhiyun TRIGGER_FRAME_T_RSVD = 8, 981*4882a593Smuzhiyun }; 982*4882a593Smuzhiyun 983*4882a593Smuzhiyun u16 rtw_he_mcs_to_data_rate(u8 bw, u8 gi, u8 he_mcs_rate); 984*4882a593Smuzhiyun void rtw_he_use_default_setting(_adapter *padapter); 985*4882a593Smuzhiyun void update_sta_he_info_apmode(_adapter *padapter, void *sta); 986*4882a593Smuzhiyun void update_hw_he_param(_adapter *padapter); 987*4882a593Smuzhiyun void HE_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); 988*4882a593Smuzhiyun void HE_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); 989*4882a593Smuzhiyun void HE_mu_edca_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE, u8 first); 990*4882a593Smuzhiyun u32 rtw_build_he_cap_ie(_adapter *padapter, u8 *pbuf); 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun struct protocol_cap_t; 993*4882a593Smuzhiyun struct phy_cap_t; 994*4882a593Smuzhiyun u32 rtw_get_dft_he_cap_ie(_adapter *padapter, struct phy_cap_t *phy_cap, 995*4882a593Smuzhiyun struct protocol_cap_t *proto_cap, u8 *pbuf); 996*4882a593Smuzhiyun 997*4882a593Smuzhiyun u32 rtw_restructure_he_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, struct country_chplan *req_chplan); 998*4882a593Smuzhiyun void HEOnAssocRsp(_adapter *padapter); 999*4882a593Smuzhiyun void rtw_he_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork); 1000*4882a593Smuzhiyun void rtw_he_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork); 1001*4882a593Smuzhiyun u8 rtw_he_htc_en(_adapter *padapter, struct sta_info *psta); 1002*4882a593Smuzhiyun void rtw_he_fill_htc(_adapter *padapter, struct pkt_attrib *pattrib, u32 *phtc_buf); 1003*4882a593Smuzhiyun void rtw_he_set_om_info(_adapter *padapter, u8 om_mask, struct rtw_he_actrl_om *om_info); 1004*4882a593Smuzhiyun void rtw_he_init_om_info(_adapter *padapter); 1005*4882a593Smuzhiyun void rtw_process_he_triggerframe(_adapter *padapter,union recv_frame *precv_frame); 1006*4882a593Smuzhiyun void rtw_update_he_ies(_adapter *padapter, WLAN_BSSID_EX *pnetwork); 1007*4882a593Smuzhiyun #endif /* _RTW_HE_H_ */ 1008*4882a593Smuzhiyun 1009