1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _RTW_HE_H_ 16 #define _RTW_HE_H_ 17 18 /* Set HE MAC Capabilities Information */ 19 #define SET_HE_MAC_CAP_HTC_HE_SUPPORT(_pEleStart, _val) \ 20 SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 1, _val) 21 #define SET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(_pEleStart, _val) \ 22 SET_BITS_TO_LE_1BYTE(_pEleStart, 1, 1, _val) 23 #define SET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(_pEleStart, _val) \ 24 SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 1, _val) 25 #define SET_HE_MAC_CAP_DYNAMIC_FRAG_SUPPORT(_pEleStart, _val) \ 26 SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 2, _val) 27 #define SET_HE_MAC_CAP_MAX_FRAG_MSDU_EXP(_pEleStart, _val) \ 28 SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 3, _val) 29 30 #define SET_HE_MAC_CAP_MIN_FRAG_SIZE(_pEleStart, _val) \ 31 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) 32 #define SET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(_pEleStart, _val) \ 33 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) 34 #define SET_HE_MAC_CAP_MULTI_TID_AGG_RX_SUPPORT(_pEleStart, _val) \ 35 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 3, _val) 36 #define SET_HE_MAC_CAP_LINK_ADAPT_SUPPORT(_pEleStart, _val) \ 37 SET_BITS_TO_LE_2BYTE((_pEleStart) + 1, 7, 2, _val) 38 39 #define SET_HE_MAC_CAP_ALL_ACK_SUPPORT(_pEleStart, _val) \ 40 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) 41 #define SET_HE_MAC_CAP_TRS_SUPPORT(_pEleStart, _val) \ 42 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 2, 1, _val) 43 #define SET_HE_MAC_CAP_BRS_SUPPORT(_pEleStart, _val) \ 44 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 3, 1, _val) 45 #define SET_HE_MAC_CAP_BC_TWT_SUPPORT(_pEleStart, _val) \ 46 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 4, 1, _val) 47 #define SET_HE_MAC_CAP_32_BIT_BMP_SUPPORT(_pEleStart, _val) \ 48 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 5, 1, _val) 49 #define SET_HE_MAC_CAP_MU_CASCADE_SUPPORT(_pEleStart, _val) \ 50 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 6, 1, _val) 51 #define SET_HE_MAC_CAP_ACK_ENABLED_AGG_SUPPORT(_pEleStart, _val) \ 52 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 7, 1, _val) 53 54 #define SET_HE_MAC_CAP_OM_CTRL_SUPPORT(_pEleStart, _val) \ 55 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 1, 1, _val) 56 #define SET_HE_MAC_CAP_OFDMA_RA_SUPPORT(_pEleStart, _val) \ 57 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 2, 1, _val) 58 #define SET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(_pEleStart, _val) \ 59 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 3, 2, _val) 60 #define SET_HE_MAC_CAP_AMSDU_FRAG_SUPPORT(_pEleStart, _val) \ 61 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 5, 1, _val) 62 #define SET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(_pEleStart, _val) \ 63 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 6, 1, _val) 64 #define SET_HE_MAC_CAP_RX_CTRL_FRAME_TO_MULTI_BSS(_pEleStart, _val) \ 65 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 7, 1, _val) 66 67 #define SET_HE_MAC_CAP_BSRP_BQRP_AMPDU_AGG(_pEleStart, _val) \ 68 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 0, 1, _val) 69 #define SET_HE_MAC_CAP_QTP_SUPPORT(_pEleStart, _val) \ 70 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 1, 1, _val) 71 #define SET_HE_MAC_CAP_BQR_SUPPORT(_pEleStart, _val) \ 72 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 2, 1, _val) 73 #define SET_HE_MAC_CAP_PSR_RESPONDER(_pEleStart, _val) \ 74 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 3, 1, _val) 75 #define SET_HE_MAC_CAP_NDP_FEEDBACK_RPT_SUPPORT(_pEleStart, _val) \ 76 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 4, 1, _val) 77 #define SET_HE_MAC_CAP_OPS_SUPPORT(_pEleStart, _val) \ 78 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 5, 1, _val) 79 #define SET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(_pEleStart, _val) \ 80 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 6, 1, _val) 81 #define SET_HE_MAC_CAP_MULTI_AID_AGG_TX_SUPPORT(_pEleStart, _val) \ 82 SET_BITS_TO_LE_2BYTE((_pEleStart) + 4, 7, 3, _val) 83 84 #define SET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(_pEleStart, _val) \ 85 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 2, 1, _val) 86 #define SET_HE_MAC_CAP_UL_2_996_TONE_RU_SUPPORT(_pEleStart, _val) \ 87 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 3, 1, _val) 88 #define SET_HE_MAC_CAP_OM_CTRL_UL_MU_DATA_DISABLE_RX(_pEleStart, _val) \ 89 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 4, 1, _val) 90 #define SET_HE_MAC_CAP_HE_DYNAMIC_SM_POWER_SAVE(_pEleStart, _val) \ 91 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 5, 1, _val) 92 #define SET_HE_MAC_CAP_PUNCTURED_SND_SUPPORT(_pEleStart, _val) \ 93 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 6, 1, _val) 94 #define SET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(_pEleStart, _val) \ 95 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 7, 1, _val) 96 97 /* Set HE PHY Capabilities Information */ 98 #define SET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(_pEleStart, _val) \ 99 SET_BITS_TO_LE_1BYTE(_pEleStart, 1, 7, _val) 100 101 #define SET_HE_PHY_CAP_PUNCTURED_PREAMBLE_RX(_pEleStart, _val) \ 102 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 4, _val) 103 #define SET_HE_PHY_CAP_DEVICE_CLASS(_pEleStart, _val) \ 104 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 1, _val) 105 #define SET_HE_PHY_CAP_LDPC_IN_PAYLOAD(_pEleStart, _val) \ 106 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 5, 1, _val) 107 #define SET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 108 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 1, _val) 109 #define SET_HE_PHY_CAP_MIDAMBLE_TRX_MAX_NSTS(_pEleStart, _val) \ 110 SET_BITS_TO_LE_2BYTE((_pEleStart) + 1, 7, 2, _val) 111 112 #define SET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(_pEleStart, _val) \ 113 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) 114 #define SET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(_pEleStart, _val) \ 115 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 2, 1, _val) 116 #define SET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(_pEleStart, _val) \ 117 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 3, 1, _val) 118 #define SET_HE_PHY_CAP_DOPPLER_TX(_pEleStart, _val) \ 119 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 4, 1, _val) 120 #define SET_HE_PHY_CAP_DOPPLER_RX(_pEleStart, _val) \ 121 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 5, 1, _val) 122 #define SET_HE_PHY_CAP_FULL_BW_UL_MUMIMO(_pEleStart, _val) \ 123 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 6, 1, _val) 124 #define SET_HE_PHY_CAP_PARTIAL_BW_UL_MUMIMO(_pEleStart, _val) \ 125 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 7, 1, _val) 126 127 #define SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(_pEleStart, _val) \ 128 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 0, 2, _val) 129 #define SET_HE_PHY_CAP_DCM_MAX_NSS_TX(_pEleStart, _val) \ 130 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 2, 1, _val) 131 #define SET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(_pEleStart, _val) \ 132 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 3, 2, _val) 133 #define SET_HE_PHY_CAP_DCM_MAX_NSS_RX(_pEleStart, _val) \ 134 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 5, 1, _val) 135 #define SET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(_pEleStart, _val) \ 136 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 6, 1, _val) 137 #define SET_HE_PHY_CAP_SU_BFER(_pEleStart, _val) \ 138 SET_BITS_TO_LE_1BYTE((_pEleStart) + 3, 7, 1, _val) 139 140 #define SET_HE_PHY_CAP_SU_BFEE(_pEleStart, _val) \ 141 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 0, 1, _val) 142 #define SET_HE_PHY_CAP_MU_BFER(_pEleStart, _val) \ 143 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 1, 1, _val) 144 #define SET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(_pEleStart, _val) \ 145 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 2, 3, _val) 146 #define SET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(_pEleStart, _val) \ 147 SET_BITS_TO_LE_1BYTE((_pEleStart) + 4, 5, 3, _val) 148 149 #define SET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(_pEleStart, _val) \ 150 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 0, 3, _val) 151 #define SET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(_pEleStart, _val) \ 152 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 3, 3, _val) 153 #define SET_HE_PHY_CAP_NG_16_SU_FEEDBACK(_pEleStart, _val) \ 154 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 6, 1, _val) 155 #define SET_HE_PHY_CAP_NG_16_MU_FEEDBACK(_pEleStart, _val) \ 156 SET_BITS_TO_LE_1BYTE((_pEleStart) + 5, 7, 1, _val) 157 158 #define SET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(_pEleStart, _val) \ 159 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 0, 1, _val) 160 #define SET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(_pEleStart, _val) \ 161 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 1, 1, _val) 162 #define SET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(_pEleStart, _val) \ 163 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 2, 1, _val) 164 #define SET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(_pEleStart, _val) \ 165 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 3, 1, _val) 166 #define SET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(_pEleStart, _val) \ 167 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 4, 1, _val) 168 #define SET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(_pEleStart, _val) \ 169 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 5, 1, _val) 170 #define SET_HE_PHY_CAP_PARTIAL_BW_DL_MU_MIMO(_pEleStart, _val) \ 171 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 6, 1, _val) 172 #define SET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(_pEleStart, _val) \ 173 SET_BITS_TO_LE_1BYTE((_pEleStart) + 6, 7, 1, _val) 174 175 #define SET_HE_PHY_CAP_PSR_BASED_SR_SUPPORT(_pEleStart, _val) \ 176 SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 0, 1, _val) 177 #define SET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(_pEleStart, _val) \ 178 SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 1, 1, _val) 179 #define SET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 180 SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 2, 1, _val) 181 #define SET_HE_PHY_CAP_MAX_NC(_pEleStart, _val) \ 182 SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 3, 3, _val) 183 #define SET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(_pEleStart, _val) \ 184 SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 6, 1, _val) 185 #define SET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(_pEleStart, _val) \ 186 SET_BITS_TO_LE_1BYTE((_pEleStart) + 7, 7, 1, _val) 187 188 #define SET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 189 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 0, 1, _val) 190 #define SET_HE_PHY_CAP_20M_IN_40M_HE_PPDU_IN_2G4(_pEleStart, _val) \ 191 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 1, 1, _val) 192 #define SET_HE_PHY_CAP_20M_IN_160C_160NC_HE_PPDU(_pEleStart, _val) \ 193 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 2, 1, _val) 194 #define SET_HE_PHY_CAP_80M_IN_160C_160NC_HE_PPDU(_pEleStart, _val) \ 195 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 3, 1, _val) 196 #define SET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart, _val) \ 197 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 4, 1, _val) 198 #define SET_HE_PHY_CAP_MIDAMBLE_TRX_2X_1X_LTF(_pEleStart, _val) \ 199 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 5, 1, _val) 200 #define SET_HE_PHY_CAP_DCM_MAX_RU(_pEleStart, _val) \ 201 SET_BITS_TO_LE_1BYTE((_pEleStart) + 8, 6, 2, _val) 202 203 #define SET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(_pEleStart, _val) \ 204 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 0, 1, _val) 205 #define SET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(_pEleStart, _val) \ 206 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 1, 1, _val) 207 #define SET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart, _val) \ 208 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 2, 1, _val) 209 #define SET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart, _val) \ 210 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 3, 1, _val) 211 #define SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(_pEleStart, _val) \ 212 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 4, 1, _val) 213 #define SET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(_pEleStart, _val) \ 214 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 5, 1, _val) 215 #define SET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(_pEleStart, _val) \ 216 SET_BITS_TO_LE_1BYTE((_pEleStart) + 9, 6, 2, _val) 217 218 /* Set Supported HE-MCS And NSS Set Information */ 219 #define SET_HE_CAP_MCS_1SS(_pEleStart, _val) \ 220 SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) 221 #define SET_HE_CAP_MCS_2SS(_pEleStart, _val) \ 222 SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) 223 #define SET_HE_CAP_MCS_3SS(_pEleStart, _val) \ 224 SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 2, _val) 225 #define SET_HE_CAP_MCS_4SS(_pEleStart, _val) \ 226 SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 2, _val) 227 #define SET_HE_CAP_MCS_5SS(_pEleStart, _val) \ 228 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) 229 #define SET_HE_CAP_MCS_6SS(_pEleStart, _val) \ 230 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) 231 #define SET_HE_CAP_MCS_7SS(_pEleStart, _val) \ 232 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 2, _val) 233 #define SET_HE_CAP_MCS_8SS(_pEleStart, _val) \ 234 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 2, _val) 235 236 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart, _val) \ 237 SET_HE_CAP_MCS_1SS(_pEleStart, _val) 238 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart, _val) \ 239 SET_HE_CAP_MCS_2SS(_pEleStart, _val) 240 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart, _val) \ 241 SET_HE_CAP_MCS_3SS(_pEleStart, _val) 242 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart, _val) \ 243 SET_HE_CAP_MCS_4SS(_pEleStart, _val) 244 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart, _val) \ 245 SET_HE_CAP_MCS_5SS(_pEleStart, _val) 246 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart, _val) \ 247 SET_HE_CAP_MCS_6SS(_pEleStart, _val) 248 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart, _val) \ 249 SET_HE_CAP_MCS_7SS(_pEleStart, _val) 250 #define SET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart, _val) \ 251 SET_HE_CAP_MCS_8SS(_pEleStart, _val) 252 253 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart, _val) \ 254 SET_HE_CAP_MCS_1SS(_pEleStart + 2, _val) 255 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart, _val) \ 256 SET_HE_CAP_MCS_2SS(_pEleStart + 2, _val) 257 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart, _val) \ 258 SET_HE_CAP_MCS_3SS(_pEleStart + 2, _val) 259 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart, _val) \ 260 SET_HE_CAP_MCS_4SS(_pEleStart + 2, _val) 261 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart, _val) \ 262 SET_HE_CAP_MCS_5SS(_pEleStart + 2, _val) 263 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart, _val) \ 264 SET_HE_CAP_MCS_6SS(_pEleStart + 2, _val) 265 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart, _val) \ 266 SET_HE_CAP_MCS_7SS(_pEleStart + 2, _val) 267 #define SET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart, _val) \ 268 SET_HE_CAP_MCS_8SS(_pEleStart + 2, _val) 269 270 #define SET_HE_CAP_RX_MCS_160MHZ_1SS(_pEleStart, _val) \ 271 SET_HE_CAP_MCS_1SS(_pEleStart + 4, _val) 272 #define SET_HE_CAP_RX_MCS_160MHZ_2SS(_pEleStart, _val) \ 273 SET_HE_CAP_MCS_2SS(_pEleStart + 4, _val) 274 #define SET_HE_CAP_RX_MCS_160MHZ_3SS(_pEleStart, _val) \ 275 SET_HE_CAP_MCS_3SS(_pEleStart + 4, _val) 276 #define SET_HE_CAP_RX_MCS_160MHZ_4SS(_pEleStart, _val) \ 277 SET_HE_CAP_MCS_4SS(_pEleStart + 4, _val) 278 #define SET_HE_CAP_RX_MCS_160MHZ_5SS(_pEleStart, _val) \ 279 SET_HE_CAP_MCS_5SS(_pEleStart + 4, _val) 280 #define SET_HE_CAP_RX_MCS_160MHZ_6SS(_pEleStart, _val) \ 281 SET_HE_CAP_MCS_6SS(_pEleStart + 4, _val) 282 #define SET_HE_CAP_RX_MCS_160MHZ_7SS(_pEleStart, _val) \ 283 SET_HE_CAP_MCS_7SS(_pEleStart + 4, _val) 284 #define SET_HE_CAP_RX_MCS_160MHZ_8SS(_pEleStart, _val) \ 285 SET_HE_CAP_MCS_8SS(_pEleStart + 4, _val) 286 287 #define SET_HE_CAP_TX_MCS_160MHZ_1SS(_pEleStart, _val) \ 288 SET_HE_CAP_MCS_1SS(_pEleStart + 6, _val) 289 #define SET_HE_CAP_TX_MCS_160MHZ_2SS(_pEleStart, _val) \ 290 SET_HE_CAP_MCS_2SS(_pEleStart + 6, _val) 291 #define SET_HE_CAP_TX_MCS_160MHZ_3SS(_pEleStart, _val) \ 292 SET_HE_CAP_MCS_3SS(_pEleStart + 6, _val) 293 #define SET_HE_CAP_TX_MCS_160MHZ_4SS(_pEleStart, _val) \ 294 SET_HE_CAP_MCS_4SS(_pEleStart + 6, _val) 295 #define SET_HE_CAP_TX_MCS_160MHZ_5SS(_pEleStart, _val) \ 296 SET_HE_CAP_MCS_5SS(_pEleStart + 6, _val) 297 #define SET_HE_CAP_TX_MCS_160MHZ_6SS(_pEleStart, _val) \ 298 SET_HE_CAP_MCS_6SS(_pEleStart + 6, _val) 299 #define SET_HE_CAP_TX_MCS_160MHZ_7SS(_pEleStart, _val) \ 300 SET_HE_CAP_MCS_7SS(_pEleStart + 6, _val) 301 #define SET_HE_CAP_TX_MCS_160MHZ_8SS(_pEleStart, _val) \ 302 SET_HE_CAP_MCS_8SS(_pEleStart + 6, _val) 303 304 #define SET_HE_CAP_RX_MCS_80_80MHZ_1SS(_pEleStart, _val) \ 305 SET_HE_CAP_MCS_1SS(_pEleStart + 8, _val) 306 #define SET_HE_CAP_RX_MCS_80_80MHZ_2SS(_pEleStart, _val) \ 307 SET_HE_CAP_MCS_2SS(_pEleStart + 8, _val) 308 #define SET_HE_CAP_RX_MCS_80_80MHZ_3SS(_pEleStart, _val) \ 309 SET_HE_CAP_MCS_3SS(_pEleStart + 8, _val) 310 #define SET_HE_CAP_RX_MCS_80_80MHZ_4SS(_pEleStart, _val) \ 311 SET_HE_CAP_MCS_4SS(_pEleStart + 8, _val) 312 #define SET_HE_CAP_RX_MCS_80_80MHZ_5SS(_pEleStart, _val) \ 313 SET_HE_CAP_MCS_5SS(_pEleStart + 8, _val) 314 #define SET_HE_CAP_RX_MCS_80_80MHZ_6SS(_pEleStart, _val) \ 315 SET_HE_CAP_MCS_6SS(_pEleStart + 8, _val) 316 #define SET_HE_CAP_RX_MCS_80_80MHZ_7SS(_pEleStart, _val) \ 317 SET_HE_CAP_MCS_7SS(_pEleStart + 8, _val) 318 #define SET_HE_CAP_RX_MCS_80_80MHZ_8SS(_pEleStart, _val) \ 319 SET_HE_CAP_MCS_8SS(_pEleStart + 8, _val) 320 321 #define SET_HE_CAP_TX_MCS_80_80MHZ_1SS(_pEleStart, _val) \ 322 SET_HE_CAP_MCS_1SS(_pEleStart + 10, _val) 323 #define SET_HE_CAP_TX_MCS_80_80MHZ_2SS(_pEleStart, _val) \ 324 SET_HE_CAP_MCS_2SS(_pEleStart + 10, _val) 325 #define SET_HE_CAP_TX_MCS_80_80MHZ_3SS(_pEleStart, _val) \ 326 SET_HE_CAP_MCS_3SS(_pEleStart + 10, _val) 327 #define SET_HE_CAP_TX_MCS_80_80MHZ_4SS(_pEleStart, _val) \ 328 SET_HE_CAP_MCS_4SS(_pEleStart + 10, _val) 329 #define SET_HE_CAP_TX_MCS_80_80MHZ_5SS(_pEleStart, _val) \ 330 SET_HE_CAP_MCS_5SS(_pEleStart + 10, _val) 331 #define SET_HE_CAP_TX_MCS_80_80MHZ_6SS(_pEleStart, _val) \ 332 SET_HE_CAP_MCS_6SS(_pEleStart + 10, _val) 333 #define SET_HE_CAP_TX_MCS_80_80MHZ_7SS(_pEleStart, _val) \ 334 SET_HE_CAP_MCS_7SS(_pEleStart + 10, _val) 335 #define SET_HE_CAP_TX_MCS_80_80MHZ_8SS(_pEleStart, _val) \ 336 SET_HE_CAP_MCS_8SS(_pEleStart + 10, _val) 337 338 /* Set PPE Threshold */ 339 #define SET_HE_CAP_PPE_NSTS(_pEleStart, _val) \ 340 SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 3, _val) 341 #define SET_HE_CAP_PPE_PU_IDX_BITMASK(_pEleStart, _val) \ 342 SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 4, _val) 343 344 /* Get HE MAC Capabilities Information */ 345 #define GET_HE_MAC_CAP_HTC_HE_SUPPORT(_pEleStart) \ 346 LE_BITS_TO_1BYTE(_pEleStart, 0, 1) 347 #define GET_HE_MAC_CAP_TWT_REQUESTER_SUPPORT(_pEleStart) \ 348 LE_BITS_TO_1BYTE(_pEleStart, 1, 1) 349 #define GET_HE_MAC_CAP_TWT_RESPONDER_SUPPORT(_pEleStart) \ 350 LE_BITS_TO_1BYTE(_pEleStart, 2, 1) 351 #define GET_HE_MAC_CAP_DYNAMIC_FRAG_SUPPORT(_pEleStart) \ 352 LE_BITS_TO_1BYTE(_pEleStart, 3, 2) 353 #define GET_HE_MAC_CAP_MAX_FRAG_MSDU_EXP(_pEleStart) \ 354 LE_BITS_TO_1BYTE(_pEleStart, 5, 3) 355 356 #define GET_HE_MAC_CAP_MIN_FRAG_SIZE(_pEleStart) \ 357 LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) 358 #define GET_HE_MAC_CAP_TRI_FRAME_PADDING_DUR(_pEleStart) \ 359 LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) 360 #define GET_HE_MAC_CAP_MULTI_TID_AGG_RX_SUPPORT(_pEleStart) \ 361 LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 3) 362 #define GET_HE_MAC_CAP_LINK_ADAPT_SUPPORT(_pEleStart) \ 363 LE_BITS_TO_2BYTE((_pEleStart) + 1, 7, 2) 364 365 #define GET_HE_MAC_CAP_ALL_ACK_SUPPORT(_pEleStart) \ 366 LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) 367 #define GET_HE_MAC_CAP_TRS_SUPPORT(_pEleStart) \ 368 LE_BITS_TO_1BYTE((_pEleStart) + 2, 2, 1) 369 #define GET_HE_MAC_CAP_BRS_SUPPORT(_pEleStart) \ 370 LE_BITS_TO_1BYTE((_pEleStart) + 2, 3, 1) 371 #define GET_HE_MAC_CAP_BC_TWT_SUPPORT(_pEleStart) \ 372 LE_BITS_TO_1BYTE((_pEleStart) + 2, 4, 1) 373 #define GET_HE_MAC_CAP_32_BIT_BMP_SUPPORT(_pEleStart) \ 374 LE_BITS_TO_1BYTE((_pEleStart) + 2, 5, 1) 375 #define GET_HE_MAC_CAP_MU_CASCADE_SUPPORT(_pEleStart) \ 376 LE_BITS_TO_1BYTE((_pEleStart) + 2, 6, 1) 377 #define GET_HE_MAC_CAP_ACK_ENABLED_AGG_SUPPORT(_pEleStart) \ 378 LE_BITS_TO_1BYTE((_pEleStart) + 2, 7, 1) 379 380 #define GET_HE_MAC_CAP_OM_CTRL_SUPPORT(_pEleStart) \ 381 LE_BITS_TO_1BYTE((_pEleStart) + 3, 1, 1) 382 #define GET_HE_MAC_CAP_OFDMA_RA_SUPPORT(_pEleStart) \ 383 LE_BITS_TO_1BYTE((_pEleStart) + 3, 2, 1) 384 #define GET_HE_MAC_CAP_MAX_AMPDU_LEN_EXP_EXT(_pEleStart) \ 385 LE_BITS_TO_1BYTE((_pEleStart) + 3, 3, 2) 386 #define GET_HE_MAC_CAP_AMSDU_FRAG_SUPPORT(_pEleStart) \ 387 LE_BITS_TO_1BYTE((_pEleStart) + 3, 5, 1) 388 #define GET_HE_MAC_CAP_FLEX_TWT_SCHED_SUPPORT(_pEleStart) \ 389 LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) 390 #define GET_HE_MAC_CAP_RX_CTRL_FRAME_TO_MULTI_BSS(_pEleStart) \ 391 LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) 392 393 #define GET_HE_MAC_CAP_BSRP_BQRP_AMPDU_AGG(_pEleStart) \ 394 LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 1) 395 #define GET_HE_MAC_CAP_QTP_SUPPORT(_pEleStart) \ 396 LE_BITS_TO_1BYTE((_pEleStart) + 4, 1, 1) 397 #define GET_HE_MAC_CAP_BQR_SUPPORT(_pEleStart) \ 398 LE_BITS_TO_1BYTE((_pEleStart) + 4, 2, 1) 399 #define GET_HE_MAC_CAP_PSR_RESPONDER(_pEleStart) \ 400 LE_BITS_TO_1BYTE((_pEleStart) + 4, 3, 1) 401 #define GET_HE_MAC_CAP_NDP_FEEDBACK_RPT_SUPPORT(_pEleStart) \ 402 LE_BITS_TO_1BYTE((_pEleStart) + 4, 4, 1) 403 #define GET_HE_MAC_CAP_OPS_SUPPORT(_pEleStart) \ 404 LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 1) 405 #define GET_HE_MAC_CAP_AMSDU_NOT_UNDER_BA_IN_ACK_EN_AMPDU(_pEleStart) \ 406 LE_BITS_TO_1BYTE((_pEleStart) + 4, 6, 1) 407 #define GET_HE_MAC_CAP_MULTI_AID_AGG_TX_SUPPORT(_pEleStart) \ 408 LE_BITS_TO_2BYTE((_pEleStart) + 4, 7, 3) 409 410 #define GET_HE_MAC_CAP_HE_SUB_CH_SELECTIVE_TX(_pEleStart) \ 411 LE_BITS_TO_1BYTE((_pEleStart) + 5, 2, 1) 412 #define GET_HE_MAC_CAP_UL_2_996_TONE_RU_SUPPORT(_pEleStart) \ 413 LE_BITS_TO_1BYTE((_pEleStart) + 5, 3, 1) 414 #define GET_HE_MAC_CAP_OM_CTRL_UL_MU_DATA_DISABLE_RX(_pEleStart) \ 415 LE_BITS_TO_1BYTE((_pEleStart) + 5, 4, 1) 416 #define GET_HE_MAC_CAP_HE_DYNAMIC_SM_POWER_SAVE(_pEleStart) \ 417 LE_BITS_TO_1BYTE((_pEleStart) + 5, 5, 1) 418 #define GET_HE_MAC_CAP_PUNCTURED_SND_SUPPORT(_pEleStart) \ 419 LE_BITS_TO_1BYTE((_pEleStart) + 5, 6, 1) 420 #define GET_HE_MAC_CAP_HT_VHT_TRIG_FRAME_RX(_pEleStart) \ 421 LE_BITS_TO_1BYTE((_pEleStart) + 5, 7, 1) 422 423 /* Get HE PHY Capabilities Information */ 424 #define GET_HE_PHY_CAP_SUPPORT_CHAN_WIDTH_SET(_pEleStart) \ 425 LE_BITS_TO_1BYTE(_pEleStart, 1, 7) 426 427 #define GET_HE_PHY_CAP_PUNCTURED_PREAMBLE_RX(_pEleStart) \ 428 LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 4) 429 #define GET_HE_PHY_CAP_DEVICE_CLASS(_pEleStart) \ 430 LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 1) 431 #define GET_HE_PHY_CAP_LDPC_IN_PAYLOAD(_pEleStart) \ 432 LE_BITS_TO_1BYTE((_pEleStart) + 1, 5, 1) 433 #define GET_HE_PHY_CAP_SU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart) \ 434 LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 1) 435 #define GET_HE_PHY_CAP_MIDAMBLE_TRX_MAX_NSTS(_pEleStart) \ 436 LE_BITS_TO_2BYTE((_pEleStart) + 1, 7, 2) 437 438 #define GET_HE_PHY_CAP_NDP_4X_LTF_3_POINT_2_GI(_pEleStart) \ 439 LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) 440 #define GET_HE_PHY_CAP_STBC_TX_LESS_THAN_80MHZ(_pEleStart) \ 441 LE_BITS_TO_1BYTE((_pEleStart) + 2, 2, 1) 442 #define GET_HE_PHY_CAP_STBC_RX_LESS_THAN_80MHZ(_pEleStart) \ 443 LE_BITS_TO_1BYTE((_pEleStart) + 2, 3, 1) 444 #define GET_HE_PHY_CAP_DOPPLER_TX(_pEleStart) \ 445 LE_BITS_TO_1BYTE((_pEleStart) + 2, 4, 1) 446 #define GET_HE_PHY_CAP_DOPPLER_RX(_pEleStart) \ 447 LE_BITS_TO_1BYTE((_pEleStart) + 2, 5, 1) 448 #define GET_HE_PHY_CAP_FULL_BW_UL_MUMIMO(_pEleStart) \ 449 LE_BITS_TO_1BYTE((_pEleStart) + 2, 6, 1) 450 #define GET_HE_PHY_CAP_PARTIAL_BW_UL_MUMIMO(_pEleStart) \ 451 LE_BITS_TO_1BYTE((_pEleStart) + 2, 7, 1) 452 453 #define GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_TX(_pEleStart) \ 454 LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 2) 455 #define GET_HE_PHY_CAP_DCM_MAX_NSS_TX(_pEleStart) \ 456 LE_BITS_TO_1BYTE((_pEleStart) + 3, 2, 1) 457 #define GET_HE_PHY_CAP_DCM_MAX_CONSTELLATION_RX(_pEleStart) \ 458 LE_BITS_TO_1BYTE((_pEleStart) + 3, 3, 2) 459 #define GET_HE_PHY_CAP_DCM_MAX_NSS_RX(_pEleStart) \ 460 LE_BITS_TO_1BYTE((_pEleStart) + 3, 5, 1) 461 #define GET_HE_PHY_CAP_RX_PARTIAL_BW_SU_IN_20MHZ_MUPPDU(_pEleStart) \ 462 LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) 463 #define GET_HE_PHY_CAP_SU_BFER(_pEleStart) \ 464 LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) 465 466 #define GET_HE_PHY_CAP_SU_BFEE(_pEleStart) \ 467 LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 1) 468 #define GET_HE_PHY_CAP_MU_BFER(_pEleStart) \ 469 LE_BITS_TO_1BYTE((_pEleStart) + 4, 1, 1) 470 #define GET_HE_PHY_CAP_BFEE_STS_LESS_THAN_80MHZ(_pEleStart) \ 471 LE_BITS_TO_1BYTE((_pEleStart) + 4, 2, 3) 472 #define GET_HE_PHY_CAP_BFEE_STS_GREATER_THAN_80MHZ(_pEleStart) \ 473 LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 3) 474 475 #define GET_HE_PHY_CAP_NUM_SND_DIMEN_LESS_THAN_80MHZ(_pEleStart) \ 476 LE_BITS_TO_1BYTE((_pEleStart) + 5, 0, 3) 477 #define GET_HE_PHY_CAP_NUM_SND_DIMEN_GREATER_THAN_80MHZ(_pEleStart) \ 478 LE_BITS_TO_1BYTE((_pEleStart) + 5, 3, 3) 479 #define GET_HE_PHY_CAP_NG_16_SU_FEEDBACK(_pEleStart) \ 480 LE_BITS_TO_1BYTE((_pEleStart) + 5, 6, 1) 481 #define GET_HE_PHY_CAP_NG_16_MU_FEEDBACK(_pEleStart) \ 482 LE_BITS_TO_1BYTE((_pEleStart) + 5, 7, 1) 483 484 #define GET_HE_PHY_CAP_CODEBOOK_4_2_SU_FEEDBACK(_pEleStart) \ 485 LE_BITS_TO_1BYTE((_pEleStart) + 6, 0, 1) 486 #define GET_HE_PHY_CAP_CODEBOOK_7_5_MU_FEEDBACK(_pEleStart) \ 487 LE_BITS_TO_1BYTE((_pEleStart) + 6, 1, 1) 488 #define GET_HE_PHY_CAP_TRIG_SUBF_FEEDBACK(_pEleStart) \ 489 LE_BITS_TO_1BYTE((_pEleStart) + 6, 2, 1) 490 #define GET_HE_PHY_CAP_TRIG_MUBF_PARTIAL_BW_FEEDBACK(_pEleStart) \ 491 LE_BITS_TO_1BYTE((_pEleStart) + 6, 3, 1) 492 #define GET_HE_PHY_CAP_TRIG_CQI_FEEDBACK(_pEleStart) \ 493 LE_BITS_TO_1BYTE((_pEleStart) + 6, 4, 1) 494 #define GET_HE_PHY_CAP_PARTIAL_BW_EXT_RANGE(_pEleStart) \ 495 LE_BITS_TO_1BYTE((_pEleStart) + 6, 5, 1) 496 #define GET_HE_PHY_CAP_PARTIAL_BW_DL_MU_MIMO(_pEleStart) \ 497 LE_BITS_TO_1BYTE((_pEleStart) + 6, 6, 1) 498 #define GET_HE_PHY_CAP_PPE_THRESHOLD_PRESENT(_pEleStart) \ 499 LE_BITS_TO_1BYTE((_pEleStart) + 6, 7, 1) 500 501 #define GET_HE_PHY_CAP_PSR_BASED_SR_SUPPORT(_pEleStart) \ 502 LE_BITS_TO_1BYTE((_pEleStart) + 7, 0, 1) 503 #define GET_HE_PHY_CAP_PWR_BOOST_FACTOR_SUPPORT(_pEleStart) \ 504 LE_BITS_TO_1BYTE((_pEleStart) + 7, 1, 1) 505 #define GET_HE_PHY_CAP_SU_MU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart) \ 506 LE_BITS_TO_1BYTE((_pEleStart) + 7, 2, 1) 507 #define GET_HE_PHY_CAP_MAX_NC(_pEleStart) \ 508 LE_BITS_TO_1BYTE((_pEleStart) + 7, 3, 3) 509 #define GET_HE_PHY_CAP_STBC_TX_GREATER_THAN_80MHZ(_pEleStart) \ 510 LE_BITS_TO_1BYTE((_pEleStart) + 7, 6, 1) 511 #define GET_HE_PHY_CAP_STBC_RX_GREATER_THAN_80MHZ(_pEleStart) \ 512 LE_BITS_TO_1BYTE((_pEleStart) + 7, 7, 1) 513 514 #define GET_HE_PHY_CAP_ERSU_PPDU_4X_LTF_0_POINT_8_GI(_pEleStart) \ 515 LE_BITS_TO_1BYTE((_pEleStart) + 8, 0, 1) 516 #define GET_HE_PHY_CAP_20M_IN_40M_HE_PPDU_IN_2G4(_pEleStart) \ 517 LE_BITS_TO_1BYTE((_pEleStart) + 8, 1, 1) 518 #define GET_HE_PHY_CAP_20M_IN_160C_160NC_HE_PPDU(_pEleStart) \ 519 LE_BITS_TO_1BYTE((_pEleStart) + 8, 2, 1) 520 #define GET_HE_PHY_CAP_80M_IN_160C_160NC_HE_PPDU(_pEleStart) \ 521 LE_BITS_TO_1BYTE((_pEleStart) + 8, 3, 1) 522 #define GET_HE_PHY_CAP_ERSU_PPDU_1X_LTF_0_POINT_8_GI(_pEleStart) \ 523 LE_BITS_TO_1BYTE((_pEleStart) + 8, 4, 1) 524 #define GET_HE_PHY_CAP_MIDAMBLE_TRX_2X_1X_LTF(_pEleStart) \ 525 LE_BITS_TO_1BYTE((_pEleStart) + 8, 5, 1) 526 #define GET_HE_PHY_CAP_DCM_MAX_RU(_pEleStart) \ 527 LE_BITS_TO_1BYTE((_pEleStart) + 8, 6, 2) 528 529 #define GET_HE_PHY_CAP_LONGER_THAN_16_HESIGB_OFDM_SYM(_pEleStart) \ 530 LE_BITS_TO_1BYTE((_pEleStart) + 9, 0, 1) 531 #define GET_HE_PHY_CAP_NON_TRIGGER_CQI_FEEDBACK(_pEleStart) \ 532 LE_BITS_TO_1BYTE((_pEleStart) + 9, 1, 1) 533 #define GET_HE_PHY_CAP_TX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart) \ 534 LE_BITS_TO_1BYTE((_pEleStart) + 9, 2, 1) 535 #define GET_HE_PHY_CAP_RX_1024_QAM_LESS_THAN_242_TONE_RU(_pEleStart) \ 536 LE_BITS_TO_1BYTE((_pEleStart) + 9, 3, 1) 537 #define GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_CMP_SIGB(_pEleStart) \ 538 LE_BITS_TO_1BYTE((_pEleStart) + 9, 4, 1) 539 #define GET_HE_PHY_CAP_RX_FULLBW_SU_USE_MUPPDU_NONCMP_SIGB(_pEleStart) \ 540 LE_BITS_TO_1BYTE((_pEleStart) + 9, 5, 1) 541 #define GET_HE_PHY_CAP_NOMINAL_PACKET_PADDING(_pEleStart) \ 542 LE_BITS_TO_1BYTE((_pEleStart) + 9, 6, 2) 543 544 /* Get Supported HE-MCS And NSS Set Information */ 545 #define GET_HE_CAP_MCS_1SS(_pEleStart) \ 546 LE_BITS_TO_1BYTE(_pEleStart, 0, 2) 547 #define GET_HE_CAP_MCS_2SS(_pEleStart) \ 548 LE_BITS_TO_1BYTE(_pEleStart, 2, 2) 549 #define GET_HE_CAP_MCS_3SS(_pEleStart) \ 550 LE_BITS_TO_1BYTE(_pEleStart, 4, 2) 551 #define GET_HE_CAP_MCS_4SS(_pEleStart) \ 552 LE_BITS_TO_1BYTE(_pEleStart, 6, 2) 553 #define GET_HE_CAP_MCS_5SS(_pEleStart) \ 554 LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) 555 #define GET_HE_CAP_MCS_6SS(_pEleStart) \ 556 LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) 557 #define GET_HE_CAP_MCS_7SS(_pEleStart) \ 558 LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 2) 559 #define GET_HE_CAP_MCS_8SS(_pEleStart) \ 560 LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 2) 561 562 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart) \ 563 GET_HE_CAP_MCS_1SS(_pEleStart) 564 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart) \ 565 GET_HE_CAP_MCS_2SS(_pEleStart) 566 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart) \ 567 GET_HE_CAP_MCS_3SS(_pEleStart) 568 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart) \ 569 GET_HE_CAP_MCS_4SS(_pEleStart) 570 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart) \ 571 GET_HE_CAP_MCS_5SS(_pEleStart) 572 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart) \ 573 GET_HE_CAP_MCS_6SS(_pEleStart) 574 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart) \ 575 GET_HE_CAP_MCS_7SS(_pEleStart) 576 #define GET_HE_CAP_RX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart) \ 577 GET_HE_CAP_MCS_8SS(_pEleStart) 578 579 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_1SS(_pEleStart) \ 580 GET_HE_CAP_MCS_1SS(_pEleStart + 2) 581 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_2SS(_pEleStart) \ 582 GET_HE_CAP_MCS_2SS(_pEleStart + 2) 583 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_3SS(_pEleStart) \ 584 GET_HE_CAP_MCS_3SS(_pEleStart + 2) 585 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_4SS(_pEleStart) \ 586 GET_HE_CAP_MCS_4SS(_pEleStart + 2) 587 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_5SS(_pEleStart) \ 588 GET_HE_CAP_MCS_5SS(_pEleStart + 2) 589 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_6SS(_pEleStart) \ 590 GET_HE_CAP_MCS_6SS(_pEleStart + 2) 591 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_7SS(_pEleStart) \ 592 GET_HE_CAP_MCS_7SS(_pEleStart + 2) 593 #define GET_HE_CAP_TX_MCS_LESS_THAN_80MHZ_8SS(_pEleStart) \ 594 GET_HE_CAP_MCS_8SS(_pEleStart + 2) 595 596 #define GET_HE_CAP_RX_MCS_160MHZ_1SS(_pEleStart) \ 597 GET_HE_CAP_MCS_1SS(_pEleStart + 4) 598 #define GET_HE_CAP_RX_MCS_160MHZ_2SS(_pEleStart) \ 599 GET_HE_CAP_MCS_2SS(_pEleStart + 4) 600 #define GET_HE_CAP_RX_MCS_160MHZ_3SS(_pEleStart) \ 601 GET_HE_CAP_MCS_3SS(_pEleStart + 4) 602 #define GET_HE_CAP_RX_MCS_160MHZ_4SS(_pEleStart) \ 603 GET_HE_CAP_MCS_4SS(_pEleStart + 4) 604 #define GET_HE_CAP_RX_MCS_160MHZ_5SS(_pEleStart) \ 605 GET_HE_CAP_MCS_5SS(_pEleStart + 4) 606 #define GET_HE_CAP_RX_MCS_160MHZ_6SS(_pEleStart) \ 607 GET_HE_CAP_MCS_6SS(_pEleStart + 4) 608 #define GET_HE_CAP_RX_MCS_160MHZ_7SS(_pEleStart) \ 609 GET_HE_CAP_MCS_7SS(_pEleStart + 4) 610 #define GET_HE_CAP_RX_MCS_160MHZ_8SS(_pEleStart) \ 611 GET_HE_CAP_MCS_8SS(_pEleStart + 4) 612 613 #define GET_HE_CAP_TX_MCS_160MHZ_1SS(_pEleStart) \ 614 GET_HE_CAP_MCS_1SS(_pEleStart + 6) 615 #define GET_HE_CAP_TX_MCS_160MHZ_2SS(_pEleStart) \ 616 GET_HE_CAP_MCS_2SS(_pEleStart + 6) 617 #define GET_HE_CAP_TX_MCS_160MHZ_3SS(_pEleStart) \ 618 GET_HE_CAP_MCS_3SS(_pEleStart + 6) 619 #define GET_HE_CAP_TX_MCS_160MHZ_4SS(_pEleStart) \ 620 GET_HE_CAP_MCS_4SS(_pEleStart + 6) 621 #define GET_HE_CAP_TX_MCS_160MHZ_5SS(_pEleStart) \ 622 GET_HE_CAP_MCS_5SS(_pEleStart + 6) 623 #define GET_HE_CAP_TX_MCS_160MHZ_6SS(_pEleStart) \ 624 GET_HE_CAP_MCS_6SS(_pEleStart + 6) 625 #define GET_HE_CAP_TX_MCS_160MHZ_7SS(_pEleStart) \ 626 GET_HE_CAP_MCS_7SS(_pEleStart + 6) 627 #define GET_HE_CAP_TX_MCS_160MHZ_8SS(_pEleStart) \ 628 GET_HE_CAP_MCS_8SS(_pEleStart + 6) 629 630 #define GET_HE_CAP_RX_MCS_80_80MHZ_1SS(_pEleStart) \ 631 GET_HE_CAP_MCS_1SS(_pEleStart + 8) 632 #define GET_HE_CAP_RX_MCS_80_80MHZ_2SS(_pEleStart) \ 633 GET_HE_CAP_MCS_2SS(_pEleStart + 8) 634 #define GET_HE_CAP_RX_MCS_80_80MHZ_3SS(_pEleStart) \ 635 GET_HE_CAP_MCS_3SS(_pEleStart + 8) 636 #define GET_HE_CAP_RX_MCS_80_80MHZ_4SS(_pEleStart) \ 637 GET_HE_CAP_MCS_4SS(_pEleStart + 8) 638 #define GET_HE_CAP_RX_MCS_80_80MHZ_5SS(_pEleStart) \ 639 GET_HE_CAP_MCS_5SS(_pEleStart + 8) 640 #define GET_HE_CAP_RX_MCS_80_80MHZ_6SS(_pEleStart) \ 641 GET_HE_CAP_MCS_6SS(_pEleStart + 8) 642 #define GET_HE_CAP_RX_MCS_80_80MHZ_7SS(_pEleStart) \ 643 GET_HE_CAP_MCS_7SS(_pEleStart + 8) 644 #define GET_HE_CAP_RX_MCS_80_80MHZ_8SS(_pEleStart) \ 645 GET_HE_CAP_MCS_8SS(_pEleStart + 8) 646 647 #define GET_HE_CAP_TX_MCS_80_80MHZ_1SS(_pEleStart) \ 648 GET_HE_CAP_MCS_1SS(_pEleStart + 10) 649 #define GET_HE_CAP_TX_MCS_80_80MHZ_2SS(_pEleStart) \ 650 GET_HE_CAP_MCS_2SS(_pEleStart + 10) 651 #define GET_HE_CAP_TX_MCS_80_80MHZ_3SS(_pEleStart) \ 652 GET_HE_CAP_MCS_3SS(_pEleStart + 10) 653 #define GET_HE_CAP_TX_MCS_80_80MHZ_4SS(_pEleStart) \ 654 GET_HE_CAP_MCS_4SS(_pEleStart + 10) 655 #define GET_HE_CAP_TX_MCS_80_80MHZ_5SS(_pEleStart) \ 656 GET_HE_CAP_MCS_5SS(_pEleStart + 10) 657 #define GET_HE_CAP_TX_MCS_80_80MHZ_6SS(_pEleStart) \ 658 GET_HE_CAP_MCS_6SS(_pEleStart + 10) 659 #define GET_HE_CAP_TX_MCS_80_80MHZ_7SS(_pEleStart) \ 660 GET_HE_CAP_MCS_7SS(_pEleStart + 10) 661 #define GET_HE_CAP_TX_MCS_80_80MHZ_8SS(_pEleStart) \ 662 GET_HE_CAP_MCS_8SS(_pEleStart + 10) 663 664 /* Get PPE Threshold */ 665 #define GET_HE_CAP_PPE_NSTS(_pEleStart) \ 666 LE_BITS_TO_1BYTE(_pEleStart, 0, 3) 667 #define GET_HE_CAP_PPE_PU_IDX_BITMASK(_pEleStart) \ 668 LE_BITS_TO_1BYTE(_pEleStart, 3, 4) 669 670 /* Set HE Operation element */ 671 #define SET_HE_OP_PARA_DEFAULT_PE_DUR(_pEleStart, _val) \ 672 SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 3, _val) 673 #define SET_HE_OP_PARA_TWT_REQUIRED(_pEleStart, _val) \ 674 SET_BITS_TO_LE_1BYTE(_pEleStart, 3, 1, _val) 675 #define SET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(_pEleStart, _val) \ 676 SET_BITS_TO_LE_2BYTE(_pEleStart, 4, 10, _val) 677 678 #define SET_HE_OP_PARA_VHT_OP_INFO_PRESENT(_pEleStart, _val) \ 679 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 1, _val) 680 #define SET_HE_OP_PARA_CO_HOSTED_BSS(_pEleStart, _val) \ 681 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 7, 1, _val) 682 683 #define SET_HE_OP_PARA_ER_SU_DISABLE(_pEleStart, _val) \ 684 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 0, 1, _val) 685 #define SET_HE_OP_PARA_6GHZ_OP_INFO_PRESENT(_pEleStart, _val) \ 686 SET_BITS_TO_LE_1BYTE((_pEleStart) + 2, 1, 1, _val) 687 688 #define SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(_pEleStart, _val) \ 689 SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 6, _val) 690 #define SET_HE_OP_BSS_COLOR_INFO_PARTIAL_BSS_COLOR(_pEleStart, _val) \ 691 SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val) 692 #define SET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(_pEleStart, _val) \ 693 SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) 694 695 #define SET_HE_OP_BASIC_MCS_1SS(_pEleStart, _val) \ 696 SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) 697 #define SET_HE_OP_BASIC_MCS_2SS(_pEleStart, _val) \ 698 SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) 699 #define SET_HE_OP_BASIC_MCS_3SS(_pEleStart, _val) \ 700 SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 2, _val) 701 #define SET_HE_OP_BASIC_MCS_4SS(_pEleStart, _val) \ 702 SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 2, _val) 703 #define SET_HE_OP_BASIC_MCS_5SS(_pEleStart, _val) \ 704 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 0, 2, _val) 705 #define SET_HE_OP_BASIC_MCS_6SS(_pEleStart, _val) \ 706 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 2, 2, _val) 707 #define SET_HE_OP_BASIC_MCS_7SS(_pEleStart, _val) \ 708 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 4, 2, _val) 709 #define SET_HE_OP_BASIC_MCS_8SS(_pEleStart, _val) \ 710 SET_BITS_TO_LE_1BYTE((_pEleStart) + 1, 6, 2, _val) 711 712 /* Values in HE spec */ 713 #define TXOP_DUR_RTS_TH_DISABLED 1023 714 715 /* Get HE Operation element */ 716 #define GET_HE_OP_PARA_DEFAULT_PE_DUR(_pEleStart) \ 717 LE_BITS_TO_1BYTE(_pEleStart, 0, 3) 718 #define GET_HE_OP_PARA_TWT_REQUIRED(_pEleStart) \ 719 LE_BITS_TO_1BYTE(_pEleStart, 3, 1) 720 #define GET_HE_OP_PARA_TXOP_DUR_RTS_THRESHOLD(_pEleStart) \ 721 LE_BITS_TO_2BYTE(_pEleStart, 4, 10) 722 723 #define GET_HE_OP_PARA_VHT_OP_INFO_PRESENT(_pEleStart) \ 724 LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 1) 725 #define GET_HE_OP_PARA_CO_HOSTED_BSS(_pEleStart) \ 726 LE_BITS_TO_1BYTE((_pEleStart) + 1, 7, 1) 727 728 #define GET_HE_OP_PARA_ER_SU_DISABLE(_pEleStart) \ 729 LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 1) 730 #define GET_HE_OP_PARA_6GHZ_OP_INFO_PRESENT(_pEleStart) \ 731 LE_BITS_TO_1BYTE((_pEleStart) + 2, 1, 1) 732 733 #define GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR(_pEleStart) \ 734 LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 6) 735 #define GET_HE_OP_BSS_COLOR_INFO_PARTIAL_BSS_COLOR(_pEleStart) \ 736 LE_BITS_TO_1BYTE((_pEleStart) + 3, 6, 1) 737 #define GET_HE_OP_BSS_COLOR_INFO_BSS_COLOR_DISABLE(_pEleStart) \ 738 LE_BITS_TO_1BYTE((_pEleStart) + 3, 7, 1) 739 740 #define GET_HE_OP_BASIC_MCS_1SS(_pEleStart) \ 741 LE_BITS_TO_1BYTE(_pEleStart, 0, 2) 742 #define GET_HE_OP_BASIC_MCS_2SS(_pEleStart) \ 743 LE_BITS_TO_1BYTE(_pEleStart, 2, 2) 744 #define GET_HE_OP_BASIC_MCS_3SS(_pEleStart) \ 745 LE_BITS_TO_1BYTE(_pEleStart, 4, 2) 746 #define GET_HE_OP_BASIC_MCS_4SS(_pEleStart) \ 747 LE_BITS_TO_1BYTE(_pEleStart, 6, 2) 748 #define GET_HE_OP_BASIC_MCS_5SS(_pEleStart) \ 749 LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 2) 750 #define GET_HE_OP_BASIC_MCS_6SS(_pEleStart) \ 751 LE_BITS_TO_1BYTE((_pEleStart) + 1, 2, 2) 752 #define GET_HE_OP_BASIC_MCS_7SS(_pEleStart) \ 753 LE_BITS_TO_1BYTE((_pEleStart) + 1, 4, 2) 754 #define GET_HE_OP_BASIC_MCS_8SS(_pEleStart) \ 755 LE_BITS_TO_1BYTE((_pEleStart) + 1, 6, 2) 756 757 /* Get MU EDCA Parameter Set element */ 758 #define GET_HE_MU_EDCA_QOS_INFO(_pEleStart) \ 759 LE_BITS_TO_1BYTE(_pEleStart, 0, 8) 760 #define GET_HE_MU_EDCA_QOS_INFO_UPDATE_CNT(_pEleStart) \ 761 LE_BITS_TO_1BYTE(_pEleStart, 0, 4) 762 #define GET_HE_MU_EDCA_BE_AIFSN(_pEleStart) \ 763 LE_BITS_TO_1BYTE((_pEleStart) + 1, 0, 4) 764 #define GET_HE_MU_EDCA_BE_ACI(_pEleStart) \ 765 LE_BITS_TO_1BYTE((_pEleStart) + 1, 5, 2) 766 #define GET_HE_MU_EDCA_BE_ECW_MIN_MAX(_pEleStart) \ 767 LE_BITS_TO_1BYTE((_pEleStart) + 2, 0, 8) 768 #define GET_HE_MU_EDCA_BE_TIMER(_pEleStart) \ 769 LE_BITS_TO_1BYTE((_pEleStart) + 3, 0, 8) 770 #define GET_HE_MU_EDCA_BK_AIFSN(_pEleStart) \ 771 LE_BITS_TO_1BYTE((_pEleStart) + 4, 0, 4) 772 #define GET_HE_MU_EDCA_BK_ACI(_pEleStart) \ 773 LE_BITS_TO_1BYTE((_pEleStart) + 4, 5, 2) 774 #define GET_HE_MU_EDCA_BK_ECW_MIN_MAX(_pEleStart) \ 775 LE_BITS_TO_1BYTE((_pEleStart) + 5, 0, 8) 776 #define GET_HE_MU_EDCA_BK_TIMER(_pEleStart) \ 777 LE_BITS_TO_1BYTE((_pEleStart) + 6, 0, 8) 778 #define GET_HE_MU_EDCA_VI_AIFSN(_pEleStart) \ 779 LE_BITS_TO_1BYTE((_pEleStart) + 7, 0, 4) 780 #define GET_HE_MU_EDCA_VI_ACI(_pEleStart) \ 781 LE_BITS_TO_1BYTE((_pEleStart) + 7, 5, 2) 782 #define GET_HE_MU_EDCA_VI_ECW_MIN_MAX(_pEleStart) \ 783 LE_BITS_TO_1BYTE((_pEleStart) + 8, 0, 8) 784 #define GET_HE_MU_EDCA_VI_TIMER(_pEleStart) \ 785 LE_BITS_TO_1BYTE((_pEleStart) + 9, 0, 8) 786 #define GET_HE_MU_EDCA_VO_AIFSN(_pEleStart) \ 787 LE_BITS_TO_1BYTE((_pEleStart) + 10, 0, 4) 788 #define GET_HE_MU_EDCA_VO_ACI(_pEleStart) \ 789 LE_BITS_TO_1BYTE((_pEleStart) + 10, 5, 2) 790 #define GET_HE_MU_EDCA_VO_ECW_MIN_MAX(_pEleStart) \ 791 LE_BITS_TO_1BYTE((_pEleStart) + 11, 0, 8) 792 #define GET_HE_MU_EDCA_VO_TIMER(_pEleStart) \ 793 LE_BITS_TO_1BYTE((_pEleStart) + 12, 0, 8) 794 795 796 /* HE variant HT Control */ 797 #define HE_VAR_HTC 3 798 799 #define HE_VAR_HTC_CID_TRS 0 800 #define HE_VAR_HTC_CID_OM 1 801 #define HE_VAR_HTC_CID_HLA 2 802 #define HE_VAR_HTC_CID_BSR 3 803 #define HE_VAR_HTC_CID_UPH 4 804 #define HE_VAR_HTC_CID_BQR 5 805 #define HE_VAR_HTC_CID_CAS 6 806 807 /* Set HE variant HT Control field */ 808 #define SET_HE_VAR_HTC(_pStart) \ 809 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 0, 2, HE_VAR_HTC) 810 811 #define SET_HE_VAR_HTC_CID_TRS(_pStart) \ 812 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_TRS) 813 #define SET_HE_VAR_HTC_CID_OM(_pStart) \ 814 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_OM) 815 #define SET_HE_VAR_HTC_CID_HLA(_pStart) \ 816 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_HLA) 817 #define SET_HE_VAR_HTC_CID_BSR(_pStart) \ 818 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_BSR) 819 #define SET_HE_VAR_HTC_CID_UPH(_pStart) \ 820 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_UPH) 821 #define SET_HE_VAR_HTC_CID_BQR(_pStart) \ 822 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_BQR) 823 #define SET_HE_VAR_HTC_CID_CAS(_pStart) \ 824 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 2, 4, HE_VAR_HTC_CID_CAS) 825 826 #define SET_HE_VAR_HTC_OM_RX_NSS(_pStart, _val) \ 827 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6, 3, _val) 828 #define SET_HE_VAR_HTC_OM_CH_WIDTH(_pStart, _val) \ 829 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 3, 2, _val) 830 #define SET_HE_VAR_HTC_OM_UL_MU_DIS(_pStart, _val) \ 831 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 5, 1, _val) 832 #define SET_HE_VAR_HTC_OM_TX_NSTS(_pStart, _val) \ 833 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 6, 3, _val) 834 #define SET_HE_VAR_HTC_OM_ER_SU_DIS(_pStart, _val) \ 835 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 9, 1, _val) 836 #define SET_HE_VAR_HTC_OM_DL_MU_MIMO_RR(_pStart, _val) \ 837 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 10, 1, _val) 838 #define SET_HE_VAR_HTC_OM_UL_MU_DATA_DIS(_pStart, _val) \ 839 SET_BITS_TO_LE_4BYTE((u8 *)_pStart, 6 + 11, 1, _val) 840 841 /* Get HE variant HT Control field */ 842 #define GET_VAR_HTC(_pStart) \ 843 LE_BITS_TO_1BYTE(_pStart, 0, 2) 844 #define GET_HE_VAR_HTC_CID(_pStart) \ 845 LE_BITS_TO_1BYTE(_pStart, 2, 4) 846 847 #define HE_MCS_SUPP_MSC0_TO_MSC7 0x0 /* 2b00 */ 848 #define HE_MCS_SUPP_MSC0_TO_MSC9 0x1 /* 2b01 */ 849 #define HE_MCS_SUPP_MSC0_TO_MSC11 0x2 /* 2b10 */ 850 #define HE_MSC_NOT_SUPP 0x3 /* 2b11 */ 851 #define HE_MSC_NOT_SUPP_BYTE ((HE_MSC_NOT_SUPP << 6) | (HE_MSC_NOT_SUPP << 4) \ 852 | (HE_MSC_NOT_SUPP << 2) | HE_MSC_NOT_SUPP) 853 854 #define HE_DEV_CLASS_A 1 855 #define HE_DEV_CLASS_B 0 856 857 /* 858 * HE_MAC_Cap (6) 859 * HE_PHY_Cap (11) 860 * HE_Support_MCS (4, 8 or 12) 861 * PPE_Thres (variable, max = 25) 862 */ 863 #define HE_CAP_ELE_MAC_CAP_LEN 6 864 #define HE_CAP_ELE_PHY_CAP_LEN 11 865 866 #define HE_CAP_ELE_SUPP_MCS_LEN_RX_80M 2 867 #define HE_CAP_ELE_SUPP_MCS_LEN_TX_80M 2 868 #define HE_CAP_ELE_SUPP_MCS_LEN_RX_160M 2 869 #define HE_CAP_ELE_SUPP_MCS_LEN_TX_160M 2 870 #define HE_CAP_ELE_SUPP_MCS_LEN_RX_80M_80M 2 871 #define HE_CAP_ELE_SUPP_MCS_LEN_TX_80M_80M 2 872 #define HE_CAP_ELE_SUPP_MCS_MAX_LEN (HE_CAP_ELE_SUPP_MCS_LEN_RX_80M \ 873 + HE_CAP_ELE_SUPP_MCS_LEN_TX_80M + HE_CAP_ELE_SUPP_MCS_LEN_RX_160M \ 874 + HE_CAP_ELE_SUPP_MCS_LEN_TX_160M + HE_CAP_ELE_SUPP_MCS_LEN_RX_80M_80M \ 875 + HE_CAP_ELE_SUPP_MCS_LEN_TX_80M_80M) 876 877 #define HE_CAP_ELE_PPE_THRE_MAX_LEN 25 878 879 #define HE_CAP_ELE_MAX_LEN (1 + HE_CAP_ELE_MAC_CAP_LEN + HE_CAP_ELE_PHY_CAP_LEN \ 880 + HE_CAP_ELE_SUPP_MCS_MAX_LEN + HE_CAP_ELE_PPE_THRE_MAX_LEN) 881 /* #define HE_CAP_MAC_CAP_OFFSET 0 882 #define HE_CAP_PHY_CAP_OFFSET 6 883 #define HE_CAP_SUPPORT_MCS_OFFSET 17 884 */ 885 886 /* 887 * HE_Ope_Para (3) 888 * BSS_Color (1) 889 * Basic_MCS (2) 890 * VHT_Op (0 or 3) 891 * CoHosted_Bssid_Ind (0 or 1) 892 * 6Ghz_Ope_Info (0 or 5) 893 */ 894 #define HE_OPER_PARAMS_LEN 3 895 #define HE_OPER_BSS_COLOR_INFO_LEN 1 896 #define HE_OPER_BASIC_MCS_LEN 2 897 #define HE_OPER_VHT_OPER_INFO_LEN 3 898 #define HE_OPER_MAX_COHOST_BSSID_LEN 1 899 #define HE_OPER_6G_OPER_INFO_LEN 5 900 901 #define HE_OPER_ELE_MAX_LEN (1 + HE_OPER_PARAMS_LEN + HE_OPER_BSS_COLOR_INFO_LEN \ 902 + HE_OPER_BASIC_MCS_LEN + HE_OPER_VHT_OPER_INFO_LEN \ 903 + HE_OPER_MAX_COHOST_BSSID_LEN + HE_OPER_6G_OPER_INFO_LEN) 904 /* #define HE_OPER_PARAS_OFFSET 0 905 #define HE_OPER_BSS_COLOR_OFFSET 3 906 #define HE_OPER_BASIC_MCS_OFFSET 4 907 */ 908 909 #define MAX_HE_GI_TYPE 3 910 #define MAX_HE_MCS_INDEX 12 * 2 /* 1SS + 2SS */ 911 912 enum rtw_he_actrl_om_mask { 913 OM_RX_NSS = BIT0, 914 OM_CH_BW = BIT1, 915 OM_UL_MU_DIS = BIT2, 916 OM_TX_NSTS = BIT3, 917 OM_ER_SU_DIS = BIT4, 918 OM_DL_MU_RR = BIT5, 919 OM_UL_MU_DATA_DIS = BIT6 920 }; 921 922 struct rtw_he_actrl_om_ele { 923 u8 rx_nss; 924 u8 channel_width; 925 u8 ul_mu_disable; 926 u8 tx_nsts; 927 u8 er_su_disable; 928 u8 dl_mu_mimo_rr; 929 u8 ul_mu_data_disable; 930 }; 931 932 933 struct rtw_he_actrl_om { 934 /* om ctrl flag for normal tx pkt */ 935 u8 actrl_om_normal_tx; 936 u8 actrl_om_normal_tx_cnt; 937 /* current om ctrl element content */ 938 struct rtw_he_actrl_om_ele om_actrl_ele; 939 }; 940 941 struct he_priv { 942 u8 he_option; 943 u8 he_cap[HE_CAP_ELE_MAX_LEN]; 944 u8 he_op[HE_OPER_ELE_MAX_LEN]; 945 u8 op_present; 946 u8 he_highest_rate; 947 u8 pre_he_muedca_cnt; 948 struct rtw_he_actrl_om om_info; 949 }; 950 951 /*trigger frame*/ 952 #define TRIGGER_FRAME_USER_INFO_SZ 5 /* byte */ 953 #define TRIGGER_FRAME_MIN_LENGTH 24 + TRIGGER_FRAME_USER_INFO_SZ /* byte , aleast one user info !!! */ 954 /*basic tigger frame with 1 byte trigger dependent info */ 955 #define TRIGGER_FRAME_BASIC_USER_INFO_SZ TRIGGER_FRAME_USER_INFO_SZ + 1 956 957 /*trigger frame User Info*/ 958 #define GET_TRIGGER_FRAME_TYPE(_pEleStart) \ 959 LE_BITS_TO_1BYTE((_pEleStart + 16), 0, 4) 960 961 #define GET_TRIGGER_FRAME_USER_INFO_AID12(_user_info) \ 962 LE_BITS_TO_2BYTE(_user_info, 0, 12) 963 964 #define GET_TRIGGER_FRAME_USER_INFO_RUA(_user_info) \ 965 LE_BITS_TO_2BYTE((_user_info + 1), 4, 8) 966 967 #define GET_TRIGGER_FRAME_USER_INFO_UL_MCS(_user_info) \ 968 LE_BITS_TO_2BYTE((_user_info + 2), 5, 4) 969 970 971 enum rtw_he_trigger_frame_type { 972 TRIGGER_FRAME_T_BASIC = 0, 973 TRIGGER_FRAME_T_BFRP, 974 TRIGGER_FRAME_T_MUBAR, 975 TRIGGER_FRAME_T_MURTS, 976 TRIGGER_FRAME_T_BSRP, 977 TRIGGER_FRAME_T_GCR_MUBAR, 978 TRIGGER_FRAME_T_BQRP, 979 TRIGGER_FRAME_T_NFRP = 7, 980 TRIGGER_FRAME_T_RSVD = 8, 981 }; 982 983 u16 rtw_he_mcs_to_data_rate(u8 bw, u8 gi, u8 he_mcs_rate); 984 void rtw_he_use_default_setting(_adapter *padapter); 985 void update_sta_he_info_apmode(_adapter *padapter, void *sta); 986 void update_hw_he_param(_adapter *padapter); 987 void HE_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); 988 void HE_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); 989 void HE_mu_edca_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE, u8 first); 990 u32 rtw_build_he_cap_ie(_adapter *padapter, u8 *pbuf); 991 992 struct protocol_cap_t; 993 struct phy_cap_t; 994 u32 rtw_get_dft_he_cap_ie(_adapter *padapter, struct phy_cap_t *phy_cap, 995 struct protocol_cap_t *proto_cap, u8 *pbuf); 996 997 u32 rtw_restructure_he_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, struct country_chplan *req_chplan); 998 void HEOnAssocRsp(_adapter *padapter); 999 void rtw_he_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork); 1000 void rtw_he_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork); 1001 u8 rtw_he_htc_en(_adapter *padapter, struct sta_info *psta); 1002 void rtw_he_fill_htc(_adapter *padapter, struct pkt_attrib *pattrib, u32 *phtc_buf); 1003 void rtw_he_set_om_info(_adapter *padapter, u8 om_mask, struct rtw_he_actrl_om *om_info); 1004 void rtw_he_init_om_info(_adapter *padapter); 1005 void rtw_process_he_triggerframe(_adapter *padapter,union recv_frame *precv_frame); 1006 void rtw_update_he_ies(_adapter *padapter, WLAN_BSSID_EX *pnetwork); 1007 #endif /* _RTW_HE_H_ */ 1008 1009