1 /****************************************************************************** 2 * 3 * Copyright(c) 2012 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 /***************************************************************************** 16 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. 17 * 18 * Module: __INC_HAL8192SPHYREG_H 19 * 20 * 21 * Note: 1. Define PMAC/BB register map 22 * 2. Define RF register map 23 * 3. PMAC/BB register bit mask. 24 * 4. RF reg bit mask. 25 * 5. Other BB/RF relative definition. 26 * 27 * 28 * Export: Constants, macro, functions(API), global variables(None). 29 * 30 * Abbrev: 31 * 32 * History: 33 * Data Who Remark 34 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 35 * 2. Reorganize code architecture. 36 * 09/25/2008 MH 1. Add RL6052 register definition 37 * 38 *****************************************************************************/ 39 #ifndef __INC_HAL8192EPHYREG_H 40 #define __INC_HAL8192EPHYREG_H 41 42 43 /*--------------------------Define Parameters-------------------------------*/ 44 45 /* ************************************************************ 46 * 8192S Regsiter offset definition 47 * ************************************************************ */ 48 49 /* 50 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 51 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 52 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 53 * 3. RF register 0x00-2E 54 * 4. Bit Mask for BB/RF register 55 * 5. Other defintion for BB/RF R/W 56 * */ 57 58 59 /* 60 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 61 * 1. Page1(0x100) 62 * */ 63 #define rPMAC_Reset 0x100 64 #define rPMAC_TxStart 0x104 65 #define rPMAC_TxLegacySIG 0x108 66 #define rPMAC_TxHTSIG1 0x10c 67 #define rPMAC_TxHTSIG2 0x110 68 #define rPMAC_PHYDebug 0x114 69 #define rPMAC_TxPacketNum 0x118 70 #define rPMAC_TxIdle 0x11c 71 #define rPMAC_TxMACHeader0 0x120 72 #define rPMAC_TxMACHeader1 0x124 73 #define rPMAC_TxMACHeader2 0x128 74 #define rPMAC_TxMACHeader3 0x12c 75 #define rPMAC_TxMACHeader4 0x130 76 #define rPMAC_TxMACHeader5 0x134 77 #define rPMAC_TxDataType 0x138 78 #define rPMAC_TxRandomSeed 0x13c 79 #define rPMAC_CCKPLCPPreamble 0x140 80 #define rPMAC_CCKPLCPHeader 0x144 81 #define rPMAC_CCKCRC16 0x148 82 #define rPMAC_OFDMRxCRC32OK 0x170 83 #define rPMAC_OFDMRxCRC32Er 0x174 84 #define rPMAC_OFDMRxParityEr 0x178 85 #define rPMAC_OFDMRxCRC8Er 0x17c 86 #define rPMAC_CCKCRxRC16Er 0x180 87 #define rPMAC_CCKCRxRC32Er 0x184 88 #define rPMAC_CCKCRxRC32OK 0x188 89 #define rPMAC_TxStatus 0x18c 90 91 92 /* 93 * 3. Page8(0x800) 94 * */ 95 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 96 97 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 98 #define rFPGA0_PSDFunction 0x808 99 100 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 101 102 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 103 #define rFPGA0_RFTiming2 0x814 104 105 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 106 #define rFPGA0_XA_HSSIParameter2 0x824 107 #define rFPGA0_XB_HSSIParameter1 0x828 108 #define rFPGA0_XB_HSSIParameter2 0x82c 109 110 #define rFPGA0_XA_LSSIParameter 0x840 111 #define rFPGA0_XB_LSSIParameter 0x844 112 113 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 114 #define rFPGA0_RFSleepUpParameter 0x854 115 116 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 117 #define rFPGA0_XCD_SwitchControl 0x85c 118 119 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 120 #define rFPGA0_XB_RFInterfaceOE 0x864 121 122 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 123 #define rFPGA0_XCD_RFInterfaceSW 0x874 124 125 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 126 #define rFPGA0_XCD_RFParameter 0x87c 127 128 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 129 #define rFPGA0_AnalogParameter2 0x884 130 #define rFPGA0_AnalogParameter3 0x888 131 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 132 #define rFPGA0_AnalogParameter4 0x88c 133 134 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 135 #define rFPGA0_XB_LSSIReadBack 0x8a4 136 #define rFPGA0_XC_LSSIReadBack 0x8a8 137 #define rFPGA0_XD_LSSIReadBack 0x8ac 138 139 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 140 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 141 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 142 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 143 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 144 145 /* 146 * 4. Page9(0x900) 147 * */ 148 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 149 150 #define rFPGA1_TxBlock 0x904 /* Useless now */ 151 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 152 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 153 154 /* 155 * 5. PageA(0xA00) 156 * 157 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 158 #define rCCK0_System 0xa00 159 160 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 161 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 162 163 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 164 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 165 166 #define rCCK0_RxHP 0xa14 167 168 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 169 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 170 171 #define rCCK0_TxFilter1 0xa20 172 #define rCCK0_TxFilter2 0xa24 173 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 174 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 175 #define rCCK0_TRSSIReport 0xa50 176 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 177 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 178 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 179 180 /* 181 * PageB(0xB00) 182 * */ 183 #define rPdp_AntA 0xb00 184 #define rPdp_AntA_4 0xb04 185 #define rConfig_Pmpd_AntA 0xb28 186 #define rConfig_ram64x16 0xb2c 187 188 #define rConfig_AntA 0xb68 189 #define rConfig_AntB 0xb6c 190 #define rPdp_AntB 0xb70 191 #define rPdp_AntB_4 0xb74 192 #define rConfig_Pmpd_AntB 0xb98 193 #define rAPK 0xbd8 194 195 196 197 /* 198 * 6. PageC(0xC00) 199 * */ 200 #define rOFDM0_LSTF 0xc00 201 202 #define rOFDM0_TRxPathEnable 0xc04 203 #define rOFDM0_TRMuxPar 0xc08 204 #define rOFDM0_TRSWIsolation 0xc0c 205 206 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 207 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 208 #define rOFDM0_XBRxAFE 0xc18 209 #define rOFDM0_XBRxIQImbalance 0xc1c 210 #define rOFDM0_XCRxAFE 0xc20 211 #define rOFDM0_XCRxIQImbalance 0xc24 212 #define rOFDM0_XDRxAFE 0xc28 213 #define rOFDM0_XDRxIQImbalance 0xc2c 214 215 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 216 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 217 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 218 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 219 220 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 221 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 222 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 223 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 224 225 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 226 #define rOFDM0_XAAGCCore2 0xc54 227 #define rOFDM0_XBAGCCore1 0xc58 228 #define rOFDM0_XBAGCCore2 0xc5c 229 #define rOFDM0_XCAGCCore1 0xc60 230 #define rOFDM0_XCAGCCore2 0xc64 231 #define rOFDM0_XDAGCCore1 0xc68 232 #define rOFDM0_XDAGCCore2 0xc6c 233 234 #define rOFDM0_AGCParameter1 0xc70 235 #define rOFDM0_AGCParameter2 0xc74 236 #define rOFDM0_AGCRSSITable 0xc78 237 #define rOFDM0_HTSTFAGC 0xc7c 238 239 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 240 #define rOFDM0_XATxAFE 0xc84 241 #define rOFDM0_XBTxIQImbalance 0xc88 242 #define rOFDM0_XBTxAFE 0xc8c 243 #define rOFDM0_XCTxIQImbalance 0xc90 244 #define rOFDM0_XCTxAFE 0xc94 245 #define rOFDM0_XDTxIQImbalance 0xc98 246 #define rOFDM0_XDTxAFE 0xc9c 247 248 #define rOFDM0_RxIQExtAnta 0xca0 249 #define rOFDM0_TxCoeff1 0xca4 250 #define rOFDM0_TxCoeff2 0xca8 251 #define rOFDM0_TxCoeff3 0xcac 252 #define rOFDM0_TxCoeff4 0xcb0 253 #define rOFDM0_TxCoeff5 0xcb4 254 #define rOFDM0_RxHPParameter 0xce0 255 #define rOFDM0_TxPseudoNoiseWgt 0xce4 256 #define rOFDM0_FrameSync 0xcf0 257 #define rOFDM0_DFSReport 0xcf4 258 259 260 /* 261 * 7. PageD(0xD00) 262 * */ 263 #define rOFDM1_LSTF 0xd00 264 #define rOFDM1_TRxPathEnable 0xd04 265 266 #define rOFDM1_CFO 0xd08 /* No setting now */ 267 #define rOFDM1_CSI1 0xd10 268 #define rOFDM1_SBD 0xd14 269 #define rOFDM1_CSI2 0xd18 270 #define rOFDM1_CFOTracking 0xd2c 271 #define rOFDM1_TRxMesaure1 0xd34 272 #define rOFDM1_IntfDet 0xd3c 273 #define rOFDM1_PseudoNoiseStateAB 0xd50 274 #define rOFDM1_PseudoNoiseStateCD 0xd54 275 #define rOFDM1_RxPseudoNoiseWgt 0xd58 276 277 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 278 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 279 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 280 281 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 282 #define rOFDM_ShortCFOCD 0xdb0 283 #define rOFDM_LongCFOAB 0xdb4 284 #define rOFDM_LongCFOCD 0xdb8 285 #define rOFDM_TailCFOAB 0xdbc 286 #define rOFDM_TailCFOCD 0xdc0 287 #define rOFDM_PWMeasure1 0xdc4 288 #define rOFDM_PWMeasure2 0xdc8 289 #define rOFDM_BWReport 0xdcc 290 #define rOFDM_AGCReport 0xdd0 291 #define rOFDM_RxSNR 0xdd4 292 #define rOFDM_RxEVMCSI 0xdd8 293 #define rOFDM_SIGReport 0xddc 294 295 296 /* 297 * 8. PageE(0xE00) 298 * */ 299 #define rTxAGC_A_Rate18_06 0xe00 300 #define rTxAGC_A_Rate54_24 0xe04 301 #define rTxAGC_A_CCK1_Mcs32 0xe08 302 #define rTxAGC_A_Mcs03_Mcs00 0xe10 303 #define rTxAGC_A_Mcs07_Mcs04 0xe14 304 #define rTxAGC_A_Mcs11_Mcs08 0xe18 305 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 306 307 #define rTxAGC_B_Rate18_06 0x830 308 #define rTxAGC_B_Rate54_24 0x834 309 #define rTxAGC_B_CCK1_55_Mcs32 0x838 310 #define rTxAGC_B_Mcs03_Mcs00 0x83c 311 #define rTxAGC_B_Mcs07_Mcs04 0x848 312 #define rTxAGC_B_Mcs11_Mcs08 0x84c 313 #define rTxAGC_B_Mcs15_Mcs12 0x868 314 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 315 316 #define rFPGA0_IQK 0xe28 317 #define rTx_IQK_Tone_A 0xe30 318 #define rRx_IQK_Tone_A 0xe34 319 #define rTx_IQK_PI_A 0xe38 320 #define rRx_IQK_PI_A 0xe3c 321 322 #define rTx_IQK 0xe40 323 #define rRx_IQK 0xe44 324 #define rIQK_AGC_Pts 0xe48 325 #define rIQK_AGC_Rsp 0xe4c 326 #define rTx_IQK_Tone_B 0xe50 327 #define rRx_IQK_Tone_B 0xe54 328 #define rTx_IQK_PI_B 0xe58 329 #define rRx_IQK_PI_B 0xe5c 330 #define rIQK_AGC_Cont 0xe60 331 332 #define rBlue_Tooth 0xe6c 333 #define rRx_Wait_CCA 0xe70 334 #define rTx_CCK_RFON 0xe74 335 #define rTx_CCK_BBON 0xe78 336 #define rTx_OFDM_RFON 0xe7c 337 #define rTx_OFDM_BBON 0xe80 338 #define rTx_To_Rx 0xe84 339 #define rTx_To_Tx 0xe88 340 #define rRx_CCK 0xe8c 341 342 #define rTx_Power_Before_IQK_A 0xe94 343 #define rTx_Power_After_IQK_A 0xe9c 344 345 #define rRx_Power_Before_IQK_A 0xea0 346 #define rRx_Power_Before_IQK_A_2 0xea4 347 #define rRx_Power_After_IQK_A 0xea8 348 #define rRx_Power_After_IQK_A_2 0xeac 349 350 #define rTx_Power_Before_IQK_B 0xeb4 351 #define rTx_Power_After_IQK_B 0xebc 352 353 #define rRx_Power_Before_IQK_B 0xec0 354 #define rRx_Power_Before_IQK_B_2 0xec4 355 #define rRx_Power_After_IQK_B 0xec8 356 #define rRx_Power_After_IQK_B_2 0xecc 357 358 #define rRx_OFDM 0xed0 359 #define rRx_Wait_RIFS 0xed4 360 #define rRx_TO_Rx 0xed8 361 #define rStandby 0xedc 362 #define rSleep 0xee0 363 #define rPMPD_ANAEN 0xeec 364 365 /* 366 * 7. RF Register 0x00-0x2E (RF 8256) 367 * RF-0222D 0x00-3F 368 * 369 * Zebra1 */ 370 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 371 #define rZebra1_TRxEnable1 0x1 372 #define rZebra1_TRxEnable2 0x2 373 #define rZebra1_AGC 0x4 374 #define rZebra1_ChargePump 0x5 375 #define rZebra1_Channel 0x7 /* RF channel switch */ 376 377 /* #endif */ 378 #define rZebra1_TxGain 0x8 /* Useless now */ 379 #define rZebra1_TxLPF 0x9 380 #define rZebra1_RxLPF 0xb 381 #define rZebra1_RxHPFCorner 0xc 382 383 /* Zebra4 */ 384 #define rGlobalCtrl 0 /* Useless now */ 385 #define rRTL8256_TxLPF 19 386 #define rRTL8256_RxLPF 11 387 388 /* RTL8258 */ 389 #define rRTL8258_TxLPF 0x11 /* Useless now */ 390 #define rRTL8258_RxLPF 0x13 391 #define rRTL8258_RSSILPF 0xa 392 393 /* 394 * RL6052 Register definition 395 * */ 396 #define RF_AC 0x00 /* */ 397 398 #define RF_IQADJ_G1 0x01 /* */ 399 #define RF_IQADJ_G2 0x02 /* */ 400 401 #define RF_POW_TRSW 0x05 /* */ 402 403 #define RF_GAIN_RX 0x06 /* */ 404 #define RF_GAIN_TX 0x07 /* */ 405 406 #define RF_TXM_IDAC 0x08 /* */ 407 #define RF_IPA_G 0x09 /* */ 408 #define RF_TXBIAS_G 0x0A 409 #define RF_TXPA_AG 0x0B 410 #define RF_IPA_A 0x0C /* */ 411 #define RF_TXBIAS_A 0x0D 412 #define RF_BS_PA_APSET_G9_G11 0x0E 413 #define RF_BS_IQGEN 0x0F /* */ 414 415 #define RF_MODE1 0x10 /* */ 416 #define RF_MODE2 0x11 /* */ 417 418 #define RF_RX_AGC_HP 0x12 /* */ 419 #define RF_TX_AGC 0x13 /* */ 420 #define RF_BIAS 0x14 /* */ 421 #define RF_IPA 0x15 /* */ 422 #define RF_TXBIAS 0x16 423 #define RF_POW_ABILITY 0x17 /* */ 424 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 425 #define RF_TOP 0x19 /* */ 426 427 #define RF_RX_G1 0x1A /* */ 428 #define RF_RX_G2 0x1B /* */ 429 430 #define RF_RX_BB2 0x1C /* */ 431 #define RF_RX_BB1 0x1D /* */ 432 433 #define RF_RCK1 0x1E /* */ 434 #define RF_RCK2 0x1F /* */ 435 436 #define RF_TX_G1 0x20 /* */ 437 #define RF_TX_G2 0x21 /* */ 438 #define RF_TX_G3 0x22 /* */ 439 440 #define RF_TX_BB1 0x23 /* */ 441 442 #define RF_T_METER_8192E 0x42 /* */ 443 #define RF_T_METER_88E 0x42 444 #define RF_T_METER 0x24 /* */ 445 446 /* #endif */ 447 448 #define RF_SYN_G1 0x25 /* RF TX Power control */ 449 #define RF_SYN_G2 0x26 /* RF TX Power control */ 450 #define RF_SYN_G3 0x27 /* RF TX Power control */ 451 #define RF_SYN_G4 0x28 /* RF TX Power control */ 452 #define RF_SYN_G5 0x29 /* RF TX Power control */ 453 #define RF_SYN_G6 0x2A /* RF TX Power control */ 454 #define RF_SYN_G7 0x2B /* RF TX Power control */ 455 #define RF_SYN_G8 0x2C /* RF TX Power control */ 456 457 #define RF_RCK_OS 0x30 /* RF TX PA control */ 458 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 459 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 460 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 461 #define RF_TX_BIAS_A 0x35 462 #define RF_TX_BIAS_D 0x36 463 #define RF_LOBF_9 0x38 464 #define RF_RXRF_A3 0x3C /* */ 465 #define RF_TRSW 0x3F 466 467 #define RF_TXRF_A2 0x41 468 #define RF_TXPA_G4 0x46 469 #define RF_TXPA_A4 0x4B 470 #define RF_0x52 0x52 471 #define RF_LDO 0xB1 472 #define RF_WE_LUT 0xEF 473 474 475 /* 476 * Bit Mask 477 * 478 * 1. Page1(0x100) */ 479 #define bBBResetB 0x100 /* Useless now? */ 480 #define bGlobalResetB 0x200 481 #define bOFDMTxStart 0x4 482 #define bCCKTxStart 0x8 483 #define bCRC32Debug 0x100 484 #define bPMACLoopback 0x10 485 #define bTxLSIG 0xffffff 486 #define bOFDMTxRate 0xf 487 #define bOFDMTxReserved 0x10 488 #define bOFDMTxLength 0x1ffe0 489 #define bOFDMTxParity 0x20000 490 #define bTxHTSIG1 0xffffff 491 #define bTxHTMCSRate 0x7f 492 #define bTxHTBW 0x80 493 #define bTxHTLength 0xffff00 494 #define bTxHTSIG2 0xffffff 495 #define bTxHTSmoothing 0x1 496 #define bTxHTSounding 0x2 497 #define bTxHTReserved 0x4 498 #define bTxHTAggreation 0x8 499 #define bTxHTSTBC 0x30 500 #define bTxHTAdvanceCoding 0x40 501 #define bTxHTShortGI 0x80 502 #define bTxHTNumberHT_LTF 0x300 503 #define bTxHTCRC8 0x3fc00 504 #define bCounterReset 0x10000 505 #define bNumOfOFDMTx 0xffff 506 #define bNumOfCCKTx 0xffff0000 507 #define bTxIdleInterval 0xffff 508 #define bOFDMService 0xffff0000 509 #define bTxMACHeader 0xffffffff 510 #define bTxDataInit 0xff 511 #define bTxHTMode 0x100 512 #define bTxDataType 0x30000 513 #define bTxRandomSeed 0xffffffff 514 #define bCCKTxPreamble 0x1 515 #define bCCKTxSFD 0xffff0000 516 #define bCCKTxSIG 0xff 517 #define bCCKTxService 0xff00 518 #define bCCKLengthExt 0x8000 519 #define bCCKTxLength 0xffff0000 520 #define bCCKTxCRC16 0xffff 521 #define bCCKTxStatus 0x1 522 #define bOFDMTxStatus 0x2 523 524 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 525 #define RF_TX_GAIN_OFFSET_8192E(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 526 527 528 /* 2. Page8(0x800) */ 529 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 530 #define bJapanMode 0x2 531 #define bCCKTxSC 0x30 532 #define bCCKEn 0x1000000 533 #define bOFDMEn 0x2000000 534 535 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 536 #define bOFDMTxDACPhase 0x40000 537 #define bXATxAGC 0x3f 538 539 #define bAntennaSelect 0x0300 540 541 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 542 #define bXCTxAGC 0xf000 543 #define bXDTxAGC 0xf0000 544 545 #define bPAStart 0xf0000000 /* Useless now */ 546 #define bTRStart 0x00f00000 547 #define bRFStart 0x0000f000 548 #define bBBStart 0x000000f0 549 #define bBBCCKStart 0x0000000f 550 #define bPAEnd 0xf /* Reg0x814 */ 551 #define bTREnd 0x0f000000 552 #define bRFEnd 0x000f0000 553 #define bCCAMask 0x000000f0 /* T2R */ 554 #define bR2RCCAMask 0x00000f00 555 #define bHSSI_R2TDelay 0xf8000000 556 #define bHSSI_T2RDelay 0xf80000 557 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 558 #define bIGFromCCK 0x200 559 #define bAGCAddress 0x3f 560 #define bRxHPTx 0x7000 561 #define bRxHPT2R 0x38000 562 #define bRxHPCCKIni 0xc0000 563 #define bAGCTxCode 0xc00000 564 #define bAGCRxCode 0x300000 565 566 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 567 #define b3WireAddressLength 0x400 568 569 #define b3WireRFPowerDown 0x1 /* Useless now 570 * #define bHWSISelect 0x8 */ 571 #define b5GPAPEPolarity 0x40000000 572 #define b2GPAPEPolarity 0x80000000 573 #define bRFSW_TxDefaultAnt 0x3 574 #define bRFSW_TxOptionAnt 0x30 575 #define bRFSW_RxDefaultAnt 0x300 576 #define bRFSW_RxOptionAnt 0x3000 577 #define bRFSI_3WireData 0x1 578 #define bRFSI_3WireClock 0x2 579 #define bRFSI_3WireLoad 0x4 580 #define bRFSI_3WireRW 0x8 581 #define bRFSI_3Wire 0xf 582 583 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 584 585 #define bRFSI_TRSW 0x20 /* Useless now */ 586 #define bRFSI_TRSWB 0x40 587 #define bRFSI_ANTSW 0x100 588 #define bRFSI_ANTSWB 0x200 589 #define bRFSI_PAPE 0x400 590 #define bRFSI_PAPE5G 0x800 591 #define bBandSelect 0x1 592 #define bHTSIG2_GI 0x80 593 #define bHTSIG2_Smoothing 0x01 594 #define bHTSIG2_Sounding 0x02 595 #define bHTSIG2_Aggreaton 0x08 596 #define bHTSIG2_STBC 0x30 597 #define bHTSIG2_AdvCoding 0x40 598 #define bHTSIG2_NumOfHTLTF 0x300 599 #define bHTSIG2_CRC8 0x3fc 600 #define bHTSIG1_MCS 0x7f 601 #define bHTSIG1_BandWidth 0x80 602 #define bHTSIG1_HTLength 0xffff 603 #define bLSIG_Rate 0xf 604 #define bLSIG_Reserved 0x10 605 #define bLSIG_Length 0x1fffe 606 #define bLSIG_Parity 0x20 607 #define bCCKRxPhase 0x4 608 609 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 610 611 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 612 613 #define bLSSIReadBackData 0xfffff /* T65 RF */ 614 615 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 616 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 617 #define bRegulator0Standby 0x1 618 #define bRegulatorPLLStandby 0x2 619 #define bRegulator1Standby 0x4 620 #define bPLLPowerUp 0x8 621 #define bDPLLPowerUp 0x10 622 #define bDA10PowerUp 0x20 623 #define bAD7PowerUp 0x200 624 #define bDA6PowerUp 0x2000 625 #define bXtalPowerUp 0x4000 626 #define b40MDClkPowerUP 0x8000 627 #define bDA6DebugMode 0x20000 628 #define bDA6Swing 0x380000 629 630 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 631 632 #define b80MClkDelay 0x18000000 /* Useless */ 633 #define bAFEWatchDogEnable 0x20000000 634 635 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 636 #define bXtalCap23 0x3 637 #define bXtalCap92x 0x0f000000 638 #define bXtalCap 0x0f000000 639 640 #define bIntDifClkEnable 0x400 /* Useless */ 641 #define bExtSigClkEnable 0x800 642 #define bBandgapMbiasPowerUp 0x10000 643 #define bAD11SHGain 0xc0000 644 #define bAD11InputRange 0x700000 645 #define bAD11OPCurrent 0x3800000 646 #define bIPathLoopback 0x4000000 647 #define bQPathLoopback 0x8000000 648 #define bAFELoopback 0x10000000 649 #define bDA10Swing 0x7e0 650 #define bDA10Reverse 0x800 651 #define bDAClkSource 0x1000 652 #define bAD7InputRange 0x6000 653 #define bAD7Gain 0x38000 654 #define bAD7OutputCMMode 0x40000 655 #define bAD7InputCMMode 0x380000 656 #define bAD7Current 0xc00000 657 #define bRegulatorAdjust 0x7000000 658 #define bAD11PowerUpAtTx 0x1 659 #define bDA10PSAtTx 0x10 660 #define bAD11PowerUpAtRx 0x100 661 #define bDA10PSAtRx 0x1000 662 #define bCCKRxAGCFormat 0x200 663 #define bPSDFFTSamplepPoint 0xc000 664 #define bPSDAverageNum 0x3000 665 #define bIQPathControl 0xc00 666 #define bPSDFreq 0x3ff 667 #define bPSDAntennaPath 0x30 668 #define bPSDIQSwitch 0x40 669 #define bPSDRxTrigger 0x400000 670 #define bPSDTxTrigger 0x80000000 671 #define bPSDSineToneScale 0x7f000000 672 #define bPSDReport 0xffff 673 674 /* 3. Page9(0x900) */ 675 #define bOFDMTxSC 0x30000000 /* Useless */ 676 #define bCCKTxOn 0x1 677 #define bOFDMTxOn 0x2 678 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 679 #define bDebugItem 0xff /* reset debug page and LWord */ 680 #define bAntL 0x10 681 #define bAntNonHT 0x100 682 #define bAntHT1 0x1000 683 #define bAntHT2 0x10000 684 #define bAntHT1S1 0x100000 685 #define bAntNonHTS1 0x1000000 686 687 /* 4. PageA(0xA00) */ 688 #define bCCKBBMode 0x3 /* Useless */ 689 #define bCCKTxPowerSaving 0x80 690 #define bCCKRxPowerSaving 0x40 691 692 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 693 694 #define bCCKScramble 0x8 /* Useless */ 695 #define bCCKAntDiversity 0x8000 696 #define bCCKCarrierRecovery 0x4000 697 #define bCCKTxRate 0x3000 698 #define bCCKDCCancel 0x0800 699 #define bCCKISICancel 0x0400 700 #define bCCKMatchFilter 0x0200 701 #define bCCKEqualizer 0x0100 702 #define bCCKPreambleDetect 0x800000 703 #define bCCKFastFalseCCA 0x400000 704 #define bCCKChEstStart 0x300000 705 #define bCCKCCACount 0x080000 706 #define bCCKcs_lim 0x070000 707 #define bCCKBistMode 0x80000000 708 #define bCCKCCAMask 0x40000000 709 #define bCCKTxDACPhase 0x4 710 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 711 #define bCCKr_cp_mode0 0x0100 712 #define bCCKTxDCOffset 0xf0 713 #define bCCKRxDCOffset 0xf 714 #define bCCKCCAMode 0xc000 715 #define bCCKFalseCS_lim 0x3f00 716 #define bCCKCS_ratio 0xc00000 717 #define bCCKCorgBit_sel 0x300000 718 #define bCCKPD_lim 0x0f0000 719 #define bCCKNewCCA 0x80000000 720 #define bCCKRxHPofIG 0x8000 721 #define bCCKRxIG 0x7f00 722 #define bCCKLNAPolarity 0x800000 723 #define bCCKRx1stGain 0x7f0000 724 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 725 #define bCCKRxAGCSatLevel 0x1f000000 726 #define bCCKRxAGCSatCount 0xe0 727 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 728 #define bCCKFixedRxAGC 0x8000 729 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 730 #define bCCKAntennaPolarity 0x2000 731 #define bCCKTxFilterType 0x0c00 732 #define bCCKRxAGCReportType 0x0300 733 #define bCCKRxDAGCEn 0x80000000 734 #define bCCKRxDAGCPeriod 0x20000000 735 #define bCCKRxDAGCSatLevel 0x1f000000 736 #define bCCKTimingRecovery 0x800000 737 #define bCCKTxC0 0x3f0000 738 #define bCCKTxC1 0x3f000000 739 #define bCCKTxC2 0x3f 740 #define bCCKTxC3 0x3f00 741 #define bCCKTxC4 0x3f0000 742 #define bCCKTxC5 0x3f000000 743 #define bCCKTxC6 0x3f 744 #define bCCKTxC7 0x3f00 745 #define bCCKDebugPort 0xff0000 746 #define bCCKDACDebug 0x0f000000 747 #define bCCKFalseAlarmEnable 0x8000 748 #define bCCKFalseAlarmRead 0x4000 749 #define bCCKTRSSI 0x7f 750 #define bCCKRxAGCReport 0xfe 751 #define bCCKRxReport_AntSel 0x80000000 752 #define bCCKRxReport_MFOff 0x40000000 753 #define bCCKRxRxReport_SQLoss 0x20000000 754 #define bCCKRxReport_Pktloss 0x10000000 755 #define bCCKRxReport_Lockedbit 0x08000000 756 #define bCCKRxReport_RateError 0x04000000 757 #define bCCKRxReport_RxRate 0x03000000 758 #define bCCKRxFACounterLower 0xff 759 #define bCCKRxFACounterUpper 0xff000000 760 #define bCCKRxHPAGCStart 0xe000 761 #define bCCKRxHPAGCFinal 0x1c00 762 #define bCCKRxFalseAlarmEnable 0x8000 763 #define bCCKFACounterFreeze 0x4000 764 #define bCCKTxPathSel 0x10000000 765 #define bCCKDefaultRxPath 0xc000000 766 #define bCCKOptionRxPath 0x3000000 767 768 /* 5. PageC(0xC00) */ 769 #define bNumOfSTF 0x3 /* Useless */ 770 #define bShift_L 0xc0 771 #define bGI_TH 0xc 772 #define bRxPathA 0x1 773 #define bRxPathB 0x2 774 #define bRxPathC 0x4 775 #define bRxPathD 0x8 776 #define bTxPathA 0x1 777 #define bTxPathB 0x2 778 #define bTxPathC 0x4 779 #define bTxPathD 0x8 780 #define bTRSSIFreq 0x200 781 #define bADCBackoff 0x3000 782 #define bDFIRBackoff 0xc000 783 #define bTRSSILatchPhase 0x10000 784 #define bRxIDCOffset 0xff 785 #define bRxQDCOffset 0xff00 786 #define bRxDFIRMode 0x1800000 787 #define bRxDCNFType 0xe000000 788 #define bRXIQImb_A 0x3ff 789 #define bRXIQImb_B 0xfc00 790 #define bRXIQImb_C 0x3f0000 791 #define bRXIQImb_D 0xffc00000 792 #define bDC_dc_Notch 0x60000 793 #define bRxNBINotch 0x1f000000 794 #define bPD_TH 0xf 795 #define bPD_TH_Opt2 0xc000 796 #define bPWED_TH 0x700 797 #define bIfMF_Win_L 0x800 798 #define bPD_Option 0x1000 799 #define bMF_Win_L 0xe000 800 #define bBW_Search_L 0x30000 801 #define bwin_enh_L 0xc0000 802 #define bBW_TH 0x700000 803 #define bED_TH2 0x3800000 804 #define bBW_option 0x4000000 805 #define bRatio_TH 0x18000000 806 #define bWindow_L 0xe0000000 807 #define bSBD_Option 0x1 808 #define bFrame_TH 0x1c 809 #define bFS_Option 0x60 810 #define bDC_Slope_check 0x80 811 #define bFGuard_Counter_DC_L 0xe00 812 #define bFrame_Weight_Short 0x7000 813 #define bSub_Tune 0xe00000 814 #define bFrame_DC_Length 0xe000000 815 #define bSBD_start_offset 0x30000000 816 #define bFrame_TH_2 0x7 817 #define bFrame_GI2_TH 0x38 818 #define bGI2_Sync_en 0x40 819 #define bSarch_Short_Early 0x300 820 #define bSarch_Short_Late 0xc00 821 #define bSarch_GI2_Late 0x70000 822 #define bCFOAntSum 0x1 823 #define bCFOAcc 0x2 824 #define bCFOStartOffset 0xc 825 #define bCFOLookBack 0x70 826 #define bCFOSumWeight 0x80 827 #define bDAGCEnable 0x10000 828 #define bTXIQImb_A 0x3ff 829 #define bTXIQImb_B 0xfc00 830 #define bTXIQImb_C 0x3f0000 831 #define bTXIQImb_D 0xffc00000 832 #define bTxIDCOffset 0xff 833 #define bTxQDCOffset 0xff00 834 #define bTxDFIRMode 0x10000 835 #define bTxPesudoNoiseOn 0x4000000 836 #define bTxPesudoNoise_A 0xff 837 #define bTxPesudoNoise_B 0xff00 838 #define bTxPesudoNoise_C 0xff0000 839 #define bTxPesudoNoise_D 0xff000000 840 #define bCCADropOption 0x20000 841 #define bCCADropThres 0xfff00000 842 #define bEDCCA_H 0xf 843 #define bEDCCA_L 0xf0 844 #define bLambda_ED 0x300 845 #define bRxInitialGain 0x7f 846 #define bRxAntDivEn 0x80 847 #define bRxAGCAddressForLNA 0x7f00 848 #define bRxHighPowerFlow 0x8000 849 #define bRxAGCFreezeThres 0xc0000 850 #define bRxFreezeStep_AGC1 0x300000 851 #define bRxFreezeStep_AGC2 0xc00000 852 #define bRxFreezeStep_AGC3 0x3000000 853 #define bRxFreezeStep_AGC0 0xc000000 854 #define bRxRssi_Cmp_En 0x10000000 855 #define bRxQuickAGCEn 0x20000000 856 #define bRxAGCFreezeThresMode 0x40000000 857 #define bRxOverFlowCheckType 0x80000000 858 #define bRxAGCShift 0x7f 859 #define bTRSW_Tri_Only 0x80 860 #define bPowerThres 0x300 861 #define bRxAGCEn 0x1 862 #define bRxAGCTogetherEn 0x2 863 #define bRxAGCMin 0x4 864 #define bRxHP_Ini 0x7 865 #define bRxHP_TRLNA 0x70 866 #define bRxHP_RSSI 0x700 867 #define bRxHP_BBP1 0x7000 868 #define bRxHP_BBP2 0x70000 869 #define bRxHP_BBP3 0x700000 870 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 871 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 872 #define bRxSettle_TRSW 0x7 873 #define bRxSettle_LNA 0x38 874 #define bRxSettle_RSSI 0x1c0 875 #define bRxSettle_BBP 0xe00 876 #define bRxSettle_RxHP 0x7000 877 #define bRxSettle_AntSW_RSSI 0x38000 878 #define bRxSettle_AntSW 0xc0000 879 #define bRxProcessTime_DAGC 0x300000 880 #define bRxSettle_HSSI 0x400000 881 #define bRxProcessTime_BBPPW 0x800000 882 #define bRxAntennaPowerShift 0x3000000 883 #define bRSSITableSelect 0xc000000 884 #define bRxHP_Final 0x7000000 885 #define bRxHTSettle_BBP 0x7 886 #define bRxHTSettle_HSSI 0x8 887 #define bRxHTSettle_RxHP 0x70 888 #define bRxHTSettle_BBPPW 0x80 889 #define bRxHTSettle_Idle 0x300 890 #define bRxHTSettle_Reserved 0x1c00 891 #define bRxHTRxHPEn 0x8000 892 #define bRxHTAGCFreezeThres 0x30000 893 #define bRxHTAGCTogetherEn 0x40000 894 #define bRxHTAGCMin 0x80000 895 #define bRxHTAGCEn 0x100000 896 #define bRxHTDAGCEn 0x200000 897 #define bRxHTRxHP_BBP 0x1c00000 898 #define bRxHTRxHP_Final 0xe0000000 899 #define bRxPWRatioTH 0x3 900 #define bRxPWRatioEn 0x4 901 #define bRxMFHold 0x3800 902 #define bRxPD_Delay_TH1 0x38 903 #define bRxPD_Delay_TH2 0x1c0 904 #define bRxPD_DC_COUNT_MAX 0x600 905 /* #define bRxMF_Hold 0x3800 */ 906 #define bRxPD_Delay_TH 0x8000 907 #define bRxProcess_Delay 0xf0000 908 #define bRxSearchrange_GI2_Early 0x700000 909 #define bRxFrame_Guard_Counter_L 0x3800000 910 #define bRxSGI_Guard_L 0xc000000 911 #define bRxSGI_Search_L 0x30000000 912 #define bRxSGI_TH 0xc0000000 913 #define bDFSCnt0 0xff 914 #define bDFSCnt1 0xff00 915 #define bDFSFlag 0xf0000 916 #define bMFWeightSum 0x300000 917 #define bMinIdxTH 0x7f000000 918 #define bDAFormat 0x40000 919 #define bTxChEmuEnable 0x01000000 920 #define bTRSWIsolation_A 0x7f 921 #define bTRSWIsolation_B 0x7f00 922 #define bTRSWIsolation_C 0x7f0000 923 #define bTRSWIsolation_D 0x7f000000 924 #define bExtLNAGain 0x7c00 925 926 /* 6. PageE(0xE00) */ 927 #define bSTBCEn 0x4 /* Useless */ 928 #define bAntennaMapping 0x10 929 #define bNss 0x20 930 #define bCFOAntSumD 0x200 931 #define bPHYCounterReset 0x8000000 932 #define bCFOReportGet 0x4000000 933 #define bOFDMContinueTx 0x10000000 934 #define bOFDMSingleCarrier 0x20000000 935 #define bOFDMSingleTone 0x40000000 936 /* #define bRxPath1 0x01 */ 937 /* #define bRxPath2 0x02 */ 938 /* #define bRxPath3 0x04 */ 939 /* #define bRxPath4 0x08 */ 940 /* #define bTxPath1 0x10 */ 941 /* #define bTxPath2 0x20 */ 942 #define bHTDetect 0x100 943 #define bCFOEn 0x10000 944 #define bCFOValue 0xfff00000 945 #define bSigTone_Re 0x3f 946 #define bSigTone_Im 0x7f00 947 #define bCounter_CCA 0xffff 948 #define bCounter_ParityFail 0xffff0000 949 #define bCounter_RateIllegal 0xffff 950 #define bCounter_CRC8Fail 0xffff0000 951 #define bCounter_MCSNoSupport 0xffff 952 #define bCounter_FastSync 0xffff 953 #define bShortCFO 0xfff 954 #define bShortCFOTLength 12 /* total */ 955 #define bShortCFOFLength 11 /* fraction */ 956 #define bLongCFO 0x7ff 957 #define bLongCFOTLength 11 958 #define bLongCFOFLength 11 959 #define bTailCFO 0x1fff 960 #define bTailCFOTLength 13 961 #define bTailCFOFLength 12 962 #define bmax_en_pwdB 0xffff 963 #define bCC_power_dB 0xffff0000 964 #define bnoise_pwdB 0xffff 965 #define bPowerMeasTLength 10 966 #define bPowerMeasFLength 3 967 #define bRx_HT_BW 0x1 968 #define bRxSC 0x6 969 #define bRx_HT 0x8 970 #define bNB_intf_det_on 0x1 971 #define bIntf_win_len_cfg 0x30 972 #define bNB_Intf_TH_cfg 0x1c0 973 #define bRFGain 0x3f 974 #define bTableSel 0x40 975 #define bTRSW 0x80 976 #define bRxSNR_A 0xff 977 #define bRxSNR_B 0xff00 978 #define bRxSNR_C 0xff0000 979 #define bRxSNR_D 0xff000000 980 #define bSNREVMTLength 8 981 #define bSNREVMFLength 1 982 #define bCSI1st 0xff 983 #define bCSI2nd 0xff00 984 #define bRxEVM1st 0xff0000 985 #define bRxEVM2nd 0xff000000 986 #define bSIGEVM 0xff 987 #define bPWDB 0xff00 988 #define bSGIEN 0x10000 989 990 #define bSFactorQAM1 0xf /* Useless */ 991 #define bSFactorQAM2 0xf0 992 #define bSFactorQAM3 0xf00 993 #define bSFactorQAM4 0xf000 994 #define bSFactorQAM5 0xf0000 995 #define bSFactorQAM6 0xf0000 996 #define bSFactorQAM7 0xf00000 997 #define bSFactorQAM8 0xf000000 998 #define bSFactorQAM9 0xf0000000 999 #define bCSIScheme 0x100000 1000 1001 #define bNoiseLvlTopSet 0x3 /* Useless */ 1002 #define bChSmooth 0x4 1003 #define bChSmoothCfg1 0x38 1004 #define bChSmoothCfg2 0x1c0 1005 #define bChSmoothCfg3 0xe00 1006 #define bChSmoothCfg4 0x7000 1007 #define bMRCMode 0x800000 1008 #define bTHEVMCfg 0x7000000 1009 1010 #define bLoopFitType 0x1 /* Useless */ 1011 #define bUpdCFO 0x40 1012 #define bUpdCFOOffData 0x80 1013 #define bAdvUpdCFO 0x100 1014 #define bAdvTimeCtrl 0x800 1015 #define bUpdClko 0x1000 1016 #define bFC 0x6000 1017 #define bTrackingMode 0x8000 1018 #define bPhCmpEnable 0x10000 1019 #define bUpdClkoLTF 0x20000 1020 #define bComChCFO 0x40000 1021 #define bCSIEstiMode 0x80000 1022 #define bAdvUpdEqz 0x100000 1023 #define bUChCfg 0x7000000 1024 #define bUpdEqz 0x8000000 1025 1026 /* Rx Pseduo noise */ 1027 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1028 #define bRxPesudoNoise_A 0xff 1029 #define bRxPesudoNoise_B 0xff00 1030 #define bRxPesudoNoise_C 0xff0000 1031 #define bRxPesudoNoise_D 0xff000000 1032 #define bPesudoNoiseState_A 0xffff 1033 #define bPesudoNoiseState_B 0xffff0000 1034 #define bPesudoNoiseState_C 0xffff 1035 #define bPesudoNoiseState_D 0xffff0000 1036 1037 /* 7. RF Register 1038 * Zebra1 */ 1039 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1040 #define bZebra1_TRxControl 0xc00 1041 #define bZebra1_TRxGainSetting 0x07f 1042 #define bZebra1_RxCorner 0xc00 1043 #define bZebra1_TxChargePump 0x38 1044 #define bZebra1_RxChargePump 0x7 1045 #define bZebra1_ChannelNum 0xf80 1046 #define bZebra1_TxLPFBW 0x400 1047 #define bZebra1_RxLPFBW 0x600 1048 1049 /* Zebra4 */ 1050 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1051 #define bRTL8256RegModeCtrl0 0x40 1052 #define bRTL8256_TxLPFBW 0x18 1053 #define bRTL8256_RxLPFBW 0x600 1054 1055 /* RTL8258 */ 1056 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1057 #define bRTL8258_RxLPFBW 0xc00 1058 #define bRTL8258_RSSILPFBW 0xc0 1059 1060 1061 /* 1062 * Other Definition 1063 * */ 1064 1065 /* byte endable for sb_write */ 1066 #define bByte0 0x1 /* Useless */ 1067 #define bByte1 0x2 1068 #define bByte2 0x4 1069 #define bByte3 0x8 1070 #define bWord0 0x3 1071 #define bWord1 0xc 1072 #define bDWord 0xf 1073 1074 /* for PutRegsetting & GetRegSetting BitMask */ 1075 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1076 #define bMaskByte1 0xff00 1077 #define bMaskByte2 0xff0000 1078 #define bMaskByte3 0xff000000 1079 #define bMaskHWord 0xffff0000 1080 #define bMaskLWord 0x0000ffff 1081 #define bMaskDWord 0xffffffff 1082 #define bMaskH3Bytes 0xffffff00 1083 #define bMask12Bits 0xfff 1084 #define bMaskH4Bits 0xf0000000 1085 #define bMaskOFDM_D 0xffc00000 1086 #define bMaskCCK 0x3f3f3f3f 1087 1088 /* for PutRFRegsetting & GetRFRegSetting BitMask 1089 * #define bMask12Bits 0xfffff */ /* RF Reg mask bits 1090 * #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ 1091 #define bRFRegOffsetMask 0xfffff 1092 1093 #define bEnable 0x1 /* Useless */ 1094 #define bDisable 0x0 1095 1096 #define LeftAntenna 0x0 /* Useless */ 1097 #define RightAntenna 0x1 1098 1099 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1100 #define tUpdateRxCounter 100 /* 100ms */ 1101 1102 #define rateCCK 0 /* Useless */ 1103 #define rateOFDM 1 1104 #define rateHT 2 1105 1106 /* define Register-End */ 1107 #define bPMAC_End 0x1ff /* Useless */ 1108 #define bFPGAPHY0_End 0x8ff 1109 #define bFPGAPHY1_End 0x9ff 1110 #define bCCKPHY0_End 0xaff 1111 #define bOFDMPHY0_End 0xcff 1112 #define bOFDMPHY1_End 0xdff 1113 1114 /* define max debug item in each debug page 1115 * #define bMaxItem_FPGA_PHY0 0x9 1116 * #define bMaxItem_FPGA_PHY1 0x3 1117 * #define bMaxItem_PHY_11B 0x16 1118 * #define bMaxItem_OFDM_PHY0 0x29 1119 * #define bMaxItem_OFDM_PHY1 0x0 */ 1120 1121 #define bPMACControl 0x0 /* Useless */ 1122 #define bWMACControl 0x1 1123 #define bWNICControl 0x2 1124 1125 #define PathA 0x0 /* Useless */ 1126 #define PathB 0x1 1127 #define PathC 0x2 1128 #define PathD 0x3 1129 1130 1131 /* RSSI Dump Message */ 1132 #define rA_RSSIDump_92E 0xcb0 1133 #define rB_RSSIDump_92E 0xcb1 1134 #define rS1_RXevmDump_92E 0xcb2 1135 #define rS2_RXevmDump_92E 0xcb3 1136 #define rA_RXsnrDump_92E 0xcb4 1137 #define rB_RXsnrDump_92E 0xcb5 1138 #define rA_CfoShortDump_92E 0xcb6 1139 #define rB_CfoShortDump_92E 0xcb8 1140 #define rA_CfoLongDump_92E 0xcba 1141 #define rB_CfoLongDump_92E 0xcbc 1142 1143 /*--------------------------Define Parameters-------------------------------*/ 1144 1145 1146 #endif /* __INC_HAL8188EPHYREG_H */ 1147