1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8188EPHYREG_H__ 16 #define __INC_HAL8188EPHYREG_H__ 17 /*--------------------------Define Parameters-------------------------------*/ 18 /* 19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 20 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 22 * 3. RF register 0x00-2E 23 * 4. Bit Mask for BB/RF register 24 * 5. Other defintion for BB/RF R/W 25 * */ 26 27 28 /* 29 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 30 * 1. Page1(0x100) 31 * */ 32 #define rPMAC_Reset 0x100 33 #define rPMAC_TxStart 0x104 34 #define rPMAC_TxLegacySIG 0x108 35 #define rPMAC_TxHTSIG1 0x10c 36 #define rPMAC_TxHTSIG2 0x110 37 #define rPMAC_PHYDebug 0x114 38 #define rPMAC_TxPacketNum 0x118 39 #define rPMAC_TxIdle 0x11c 40 #define rPMAC_TxMACHeader0 0x120 41 #define rPMAC_TxMACHeader1 0x124 42 #define rPMAC_TxMACHeader2 0x128 43 #define rPMAC_TxMACHeader3 0x12c 44 #define rPMAC_TxMACHeader4 0x130 45 #define rPMAC_TxMACHeader5 0x134 46 #define rPMAC_TxDataType 0x138 47 #define rPMAC_TxRandomSeed 0x13c 48 #define rPMAC_CCKPLCPPreamble 0x140 49 #define rPMAC_CCKPLCPHeader 0x144 50 #define rPMAC_CCKCRC16 0x148 51 #define rPMAC_OFDMRxCRC32OK 0x170 52 #define rPMAC_OFDMRxCRC32Er 0x174 53 #define rPMAC_OFDMRxParityEr 0x178 54 #define rPMAC_OFDMRxCRC8Er 0x17c 55 #define rPMAC_CCKCRxRC16Er 0x180 56 #define rPMAC_CCKCRxRC32Er 0x184 57 #define rPMAC_CCKCRxRC32OK 0x188 58 #define rPMAC_TxStatus 0x18c 59 60 /* 61 * 2. Page2(0x200) 62 * 63 * The following two definition are only used for USB interface. */ 64 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 65 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 66 67 /* 68 * 3. Page8(0x800) 69 * */ 70 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 71 72 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 73 #define rFPGA0_PSDFunction 0x808 74 75 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 76 77 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 78 #define rFPGA0_RFTiming2 0x814 79 80 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 81 #define rFPGA0_XA_HSSIParameter2 0x824 82 #define rFPGA0_XB_HSSIParameter1 0x828 83 #define rFPGA0_XB_HSSIParameter2 0x82c 84 85 #define rFPGA0_XA_LSSIParameter 0x840 86 #define rFPGA0_XB_LSSIParameter 0x844 87 88 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 89 #define rFPGA0_RFSleepUpParameter 0x854 90 91 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 92 #define rFPGA0_XCD_SwitchControl 0x85c 93 94 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 95 #define rFPGA0_XB_RFInterfaceOE 0x864 96 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 97 #define rFPGA0_XCD_RFInterfaceSW 0x874 98 99 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 100 #define rFPGA0_XCD_RFParameter 0x87c 101 102 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 103 #define rFPGA0_AnalogParameter2 0x884 104 #define rFPGA0_AnalogParameter3 0x888 105 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 106 #define rFPGA0_AnalogParameter4 0x88c 107 108 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 109 #define rFPGA0_XB_LSSIReadBack 0x8a4 110 #define rFPGA0_XC_LSSIReadBack 0x8a8 111 #define rFPGA0_XD_LSSIReadBack 0x8ac 112 113 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 114 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 115 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 116 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 117 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 118 119 /* 120 * 4. Page9(0x900) 121 * */ 122 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 123 124 #define rFPGA1_TxBlock 0x904 /* Useless now */ 125 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 126 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 127 128 /* 129 * 5. PageA(0xA00) 130 * 131 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 132 #define rCCK0_System 0xa00 133 134 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 135 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 136 137 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 138 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 139 140 #define rCCK0_RxHP 0xa14 141 142 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 143 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 144 145 #define rCCK0_TxFilter1 0xa20 146 #define rCCK0_TxFilter2 0xa24 147 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 148 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 149 #define rCCK0_TRSSIReport 0xa50 150 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 151 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 152 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 153 154 /* 155 * PageB(0xB00) 156 * */ 157 #define rPdp_AntA 0xb00 158 #define rPdp_AntA_4 0xb04 159 #define rConfig_Pmpd_AntA 0xb28 160 #define rConfig_ram64x16 0xb2c 161 #define rConfig_AntA 0xb68 162 #define rConfig_AntB 0xb6c 163 #define rPdp_AntB 0xb70 164 #define rPdp_AntB_4 0xb74 165 #define rConfig_Pmpd_AntB 0xb98 166 #define rAPK 0xbd8 167 168 169 170 /* 171 * 6. PageC(0xC00) 172 * */ 173 #define rOFDM0_LSTF 0xc00 174 175 #define rOFDM0_TRxPathEnable 0xc04 176 #define rOFDM0_TRMuxPar 0xc08 177 #define rOFDM0_TRSWIsolation 0xc0c 178 179 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 180 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 181 #define rOFDM0_XBRxAFE 0xc18 182 #define rOFDM0_XBRxIQImbalance 0xc1c 183 #define rOFDM0_XCRxAFE 0xc20 184 #define rOFDM0_XCRxIQImbalance 0xc24 185 #define rOFDM0_XDRxAFE 0xc28 186 #define rOFDM0_XDRxIQImbalance 0xc2c 187 188 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 189 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 190 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 191 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 192 193 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 194 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 195 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 196 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 197 198 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 199 #define rOFDM0_XAAGCCore2 0xc54 200 #define rOFDM0_XBAGCCore1 0xc58 201 #define rOFDM0_XBAGCCore2 0xc5c 202 #define rOFDM0_XCAGCCore1 0xc60 203 #define rOFDM0_XCAGCCore2 0xc64 204 #define rOFDM0_XDAGCCore1 0xc68 205 #define rOFDM0_XDAGCCore2 0xc6c 206 207 #define rOFDM0_AGCParameter1 0xc70 208 #define rOFDM0_AGCParameter2 0xc74 209 #define rOFDM0_AGCRSSITable 0xc78 210 #define rOFDM0_HTSTFAGC 0xc7c 211 212 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 213 #define rOFDM0_XATxAFE 0xc84 214 #define rOFDM0_XBTxIQImbalance 0xc88 215 #define rOFDM0_XBTxAFE 0xc8c 216 #define rOFDM0_XCTxIQImbalance 0xc90 217 #define rOFDM0_XCTxAFE 0xc94 218 #define rOFDM0_XDTxIQImbalance 0xc98 219 #define rOFDM0_XDTxAFE 0xc9c 220 221 #define rOFDM0_RxIQExtAnta 0xca0 222 #define rOFDM0_TxCoeff1 0xca4 223 #define rOFDM0_TxCoeff2 0xca8 224 #define rOFDM0_TxCoeff3 0xcac 225 #define rOFDM0_TxCoeff4 0xcb0 226 #define rOFDM0_TxCoeff5 0xcb4 227 #define rOFDM0_TxCoeff6 0xcb8 228 #define rOFDM0_RxHPParameter 0xce0 229 #define rOFDM0_TxPseudoNoiseWgt 0xce4 230 #define rOFDM0_FrameSync 0xcf0 231 #define rOFDM0_DFSReport 0xcf4 232 233 234 /* 235 * 7. PageD(0xD00) 236 * */ 237 #define rOFDM1_LSTF 0xd00 238 #define rOFDM1_TRxPathEnable 0xd04 239 240 #define rOFDM1_CFO 0xd08 /* No setting now */ 241 #define rOFDM1_CSI1 0xd10 242 #define rOFDM1_SBD 0xd14 243 #define rOFDM1_CSI2 0xd18 244 #define rOFDM1_CFOTracking 0xd2c 245 #define rOFDM1_TRxMesaure1 0xd34 246 #define rOFDM1_IntfDet 0xd3c 247 #define rOFDM1_csi_fix_mask1 0xd40 248 #define rOFDM1_csi_fix_mask2 0xd44 249 #define rOFDM1_PseudoNoiseStateAB 0xd50 250 #define rOFDM1_PseudoNoiseStateCD 0xd54 251 #define rOFDM1_RxPseudoNoiseWgt 0xd58 252 253 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 254 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 255 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 256 257 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 258 #define rOFDM_ShortCFOCD 0xdb0 259 #define rOFDM_LongCFOAB 0xdb4 260 #define rOFDM_LongCFOCD 0xdb8 261 #define rOFDM_TailCFOAB 0xdbc 262 #define rOFDM_TailCFOCD 0xdc0 263 #define rOFDM_PWMeasure1 0xdc4 264 #define rOFDM_PWMeasure2 0xdc8 265 #define rOFDM_BWReport 0xdcc 266 #define rOFDM_AGCReport 0xdd0 267 #define rOFDM_RxSNR 0xdd4 268 #define rOFDM_RxEVMCSI 0xdd8 269 #define rOFDM_SIGReport 0xddc 270 271 272 /* 273 * 8. PageE(0xE00) 274 * */ 275 #define rTxAGC_A_Rate18_06 0xe00 276 #define rTxAGC_A_Rate54_24 0xe04 277 #define rTxAGC_A_CCK1_Mcs32 0xe08 278 #define rTxAGC_A_Mcs03_Mcs00 0xe10 279 #define rTxAGC_A_Mcs07_Mcs04 0xe14 280 #define rTxAGC_A_Mcs11_Mcs08 0xe18 281 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 282 283 #define rTxAGC_B_Rate18_06 0x830 284 #define rTxAGC_B_Rate54_24 0x834 285 #define rTxAGC_B_CCK1_55_Mcs32 0x838 286 #define rTxAGC_B_Mcs03_Mcs00 0x83c 287 #define rTxAGC_B_Mcs07_Mcs04 0x848 288 #define rTxAGC_B_Mcs11_Mcs08 0x84c 289 #define rTxAGC_B_Mcs15_Mcs12 0x868 290 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 291 292 #define rFPGA0_IQK 0xe28 293 #define rTx_IQK_Tone_A 0xe30 294 #define rRx_IQK_Tone_A 0xe34 295 #define rTx_IQK_PI_A 0xe38 296 #define rRx_IQK_PI_A 0xe3c 297 298 #define rTx_IQK 0xe40 299 #define rRx_IQK 0xe44 300 #define rIQK_AGC_Pts 0xe48 301 #define rIQK_AGC_Rsp 0xe4c 302 #define rTx_IQK_Tone_B 0xe50 303 #define rRx_IQK_Tone_B 0xe54 304 #define rTx_IQK_PI_B 0xe58 305 #define rRx_IQK_PI_B 0xe5c 306 #define rIQK_AGC_Cont 0xe60 307 308 #define rBlue_Tooth 0xe6c 309 #define rRx_Wait_CCA 0xe70 310 #define rTx_CCK_RFON 0xe74 311 #define rTx_CCK_BBON 0xe78 312 #define rTx_OFDM_RFON 0xe7c 313 #define rTx_OFDM_BBON 0xe80 314 #define rTx_To_Rx 0xe84 315 #define rTx_To_Tx 0xe88 316 #define rRx_CCK 0xe8c 317 318 #define rTx_Power_Before_IQK_A 0xe94 319 #define rTx_Power_After_IQK_A 0xe9c 320 321 #define rRx_Power_Before_IQK_A 0xea0 322 #define rRx_Power_Before_IQK_A_2 0xea4 323 #define rRx_Power_After_IQK_A 0xea8 324 #define rRx_Power_After_IQK_A_2 0xeac 325 326 #define rTx_Power_Before_IQK_B 0xeb4 327 #define rTx_Power_After_IQK_B 0xebc 328 329 #define rRx_Power_Before_IQK_B 0xec0 330 #define rRx_Power_Before_IQK_B_2 0xec4 331 #define rRx_Power_After_IQK_B 0xec8 332 #define rRx_Power_After_IQK_B_2 0xecc 333 334 #define rRx_OFDM 0xed0 335 #define rRx_Wait_RIFS 0xed4 336 #define rRx_TO_Rx 0xed8 337 #define rStandby 0xedc 338 #define rSleep 0xee0 339 #define rPMPD_ANAEN 0xeec 340 341 /* 342 * 7. RF Register 0x00-0x2E (RF 8256) 343 * RF-0222D 0x00-3F 344 * 345 * Zebra1 */ 346 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 347 #define rZebra1_TRxEnable1 0x1 348 #define rZebra1_TRxEnable2 0x2 349 #define rZebra1_AGC 0x4 350 #define rZebra1_ChargePump 0x5 351 #define rZebra1_Channel 0x7 /* RF channel switch */ 352 353 /* #endif */ 354 #define rZebra1_TxGain 0x8 /* Useless now */ 355 #define rZebra1_TxLPF 0x9 356 #define rZebra1_RxLPF 0xb 357 #define rZebra1_RxHPFCorner 0xc 358 359 /* Zebra4 */ 360 #define rGlobalCtrl 0 /* Useless now */ 361 #define rRTL8256_TxLPF 19 362 #define rRTL8256_RxLPF 11 363 364 /* RTL8258 */ 365 #define rRTL8258_TxLPF 0x11 /* Useless now */ 366 #define rRTL8258_RxLPF 0x13 367 #define rRTL8258_RSSILPF 0xa 368 369 /* 370 * RL6052 Register definition 371 * */ 372 #define RF_AC 0x00 /* */ 373 374 #define RF_IQADJ_G1 0x01 /* */ 375 #define RF_IQADJ_G2 0x02 /* */ 376 377 #define RF_POW_TRSW 0x05 /* */ 378 379 #define RF_GAIN_RX 0x06 /* */ 380 #define RF_GAIN_TX 0x07 /* */ 381 382 #define RF_TXM_IDAC 0x08 /* */ 383 #define RF_IPA_G 0x09 /* */ 384 #define RF_TXBIAS_G 0x0A 385 #define RF_TXPA_AG 0x0B 386 #define RF_IPA_A 0x0C /* */ 387 #define RF_TXBIAS_A 0x0D 388 #define RF_BS_PA_APSET_G9_G11 0x0E 389 #define RF_BS_IQGEN 0x0F /* */ 390 391 #define RF_MODE1 0x10 /* */ 392 #define RF_MODE2 0x11 /* */ 393 394 #define RF_RX_AGC_HP 0x12 /* */ 395 #define RF_TX_AGC 0x13 /* */ 396 #define RF_BIAS 0x14 /* */ 397 #define RF_IPA 0x15 /* */ 398 #define RF_TXBIAS 0x16 399 #define RF_POW_ABILITY 0x17 /* */ 400 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 401 #define RF_TOP 0x19 /* */ 402 403 #define RF_RX_G1 0x1A /* */ 404 #define RF_RX_G2 0x1B /* */ 405 406 #define RF_RX_BB2 0x1C /* */ 407 #define RF_RX_BB1 0x1D /* */ 408 409 #define RF_RCK1 0x1E /* */ 410 #define RF_RCK2 0x1F /* */ 411 412 #define RF_TX_G1 0x20 /* */ 413 #define RF_TX_G2 0x21 /* */ 414 #define RF_TX_G3 0x22 /* */ 415 416 #define RF_TX_BB1 0x23 /* */ 417 418 #define RF_T_METER_88E 0x42 /* */ 419 #define RF_T_METER 0x24 /* */ 420 421 #define RF_SYN_G1 0x25 /* RF TX Power control */ 422 #define RF_SYN_G2 0x26 /* RF TX Power control */ 423 #define RF_SYN_G3 0x27 /* RF TX Power control */ 424 #define RF_SYN_G4 0x28 /* RF TX Power control */ 425 #define RF_SYN_G5 0x29 /* RF TX Power control */ 426 #define RF_SYN_G6 0x2A /* RF TX Power control */ 427 #define RF_SYN_G7 0x2B /* RF TX Power control */ 428 #define RF_SYN_G8 0x2C /* RF TX Power control */ 429 430 #define RF_RCK_OS 0x30 /* RF TX PA control */ 431 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 432 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 433 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 434 #define RF_TX_BIAS_A 0x35 435 #define RF_TX_BIAS_D 0x36 436 #define RF_LOBF_9 0x38 437 #define RF_RXRF_A3 0x3C /* */ 438 #define RF_TRSW 0x3F 439 440 #define RF_TXRF_A2 0x41 441 #define RF_TXPA_G4 0x46 442 #define RF_TXPA_A4 0x4B 443 #define RF_0x52 0x52 444 #define RF_WE_LUT 0xEF 445 446 447 /* 448 * Bit Mask 449 * 450 * 1. Page1(0x100) */ 451 #define bBBResetB 0x100 /* Useless now? */ 452 #define bGlobalResetB 0x200 453 #define bOFDMTxStart 0x4 454 #define bCCKTxStart 0x8 455 #define bCRC32Debug 0x100 456 #define bPMACLoopback 0x10 457 #define bTxLSIG 0xffffff 458 #define bOFDMTxRate 0xf 459 #define bOFDMTxReserved 0x10 460 #define bOFDMTxLength 0x1ffe0 461 #define bOFDMTxParity 0x20000 462 #define bTxHTSIG1 0xffffff 463 #define bTxHTMCSRate 0x7f 464 #define bTxHTBW 0x80 465 #define bTxHTLength 0xffff00 466 #define bTxHTSIG2 0xffffff 467 #define bTxHTSmoothing 0x1 468 #define bTxHTSounding 0x2 469 #define bTxHTReserved 0x4 470 #define bTxHTAggreation 0x8 471 #define bTxHTSTBC 0x30 472 #define bTxHTAdvanceCoding 0x40 473 #define bTxHTShortGI 0x80 474 #define bTxHTNumberHT_LTF 0x300 475 #define bTxHTCRC8 0x3fc00 476 #define bCounterReset 0x10000 477 #define bNumOfOFDMTx 0xffff 478 #define bNumOfCCKTx 0xffff0000 479 #define bTxIdleInterval 0xffff 480 #define bOFDMService 0xffff0000 481 #define bTxMACHeader 0xffffffff 482 #define bTxDataInit 0xff 483 #define bTxHTMode 0x100 484 #define bTxDataType 0x30000 485 #define bTxRandomSeed 0xffffffff 486 #define bCCKTxPreamble 0x1 487 #define bCCKTxSFD 0xffff0000 488 #define bCCKTxSIG 0xff 489 #define bCCKTxService 0xff00 490 #define bCCKLengthExt 0x8000 491 #define bCCKTxLength 0xffff0000 492 #define bCCKTxCRC16 0xffff 493 #define bCCKTxStatus 0x1 494 #define bOFDMTxStatus 0x2 495 496 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 497 498 /* 2. Page8(0x800) */ 499 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 500 #define bJapanMode 0x2 501 #define bCCKTxSC 0x30 502 #define bCCKEn 0x1000000 503 #define bOFDMEn 0x2000000 504 505 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 506 #define bOFDMTxDACPhase 0x40000 507 #define bXATxAGC 0x3f 508 509 #define bAntennaSelect 0x0300 510 511 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 512 #define bXCTxAGC 0xf000 513 #define bXDTxAGC 0xf0000 514 515 #define bPAStart 0xf0000000 /* Useless now */ 516 #define bTRStart 0x00f00000 517 #define bRFStart 0x0000f000 518 #define bBBStart 0x000000f0 519 #define bBBCCKStart 0x0000000f 520 #define bPAEnd 0xf /* Reg0x814 */ 521 #define bTREnd 0x0f000000 522 #define bRFEnd 0x000f0000 523 #define bCCAMask 0x000000f0 /* T2R */ 524 #define bR2RCCAMask 0x00000f00 525 #define bHSSI_R2TDelay 0xf8000000 526 #define bHSSI_T2RDelay 0xf80000 527 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 528 #define bIGFromCCK 0x200 529 #define bAGCAddress 0x3f 530 #define bRxHPTx 0x7000 531 #define bRxHPT2R 0x38000 532 #define bRxHPCCKIni 0xc0000 533 #define bAGCTxCode 0xc00000 534 #define bAGCRxCode 0x300000 535 536 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 537 #define b3WireAddressLength 0x400 538 539 #define b3WireRFPowerDown 0x1 /* Useless now 540 * #define bHWSISelect 0x8 */ 541 #define b5GPAPEPolarity 0x40000000 542 #define b2GPAPEPolarity 0x80000000 543 #define bRFSW_TxDefaultAnt 0x3 544 #define bRFSW_TxOptionAnt 0x30 545 #define bRFSW_RxDefaultAnt 0x300 546 #define bRFSW_RxOptionAnt 0x3000 547 #define bRFSI_3WireData 0x1 548 #define bRFSI_3WireClock 0x2 549 #define bRFSI_3WireLoad 0x4 550 #define bRFSI_3WireRW 0x8 551 #define bRFSI_3Wire 0xf 552 553 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 554 555 #define bRFSI_TRSW 0x20 /* Useless now */ 556 #define bRFSI_TRSWB 0x40 557 #define bRFSI_ANTSW 0x100 558 #define bRFSI_ANTSWB 0x200 559 #define bRFSI_PAPE 0x400 560 #define bRFSI_PAPE5G 0x800 561 #define bBandSelect 0x1 562 #define bHTSIG2_GI 0x80 563 #define bHTSIG2_Smoothing 0x01 564 #define bHTSIG2_Sounding 0x02 565 #define bHTSIG2_Aggreaton 0x08 566 #define bHTSIG2_STBC 0x30 567 #define bHTSIG2_AdvCoding 0x40 568 #define bHTSIG2_NumOfHTLTF 0x300 569 #define bHTSIG2_CRC8 0x3fc 570 #define bHTSIG1_MCS 0x7f 571 #define bHTSIG1_BandWidth 0x80 572 #define bHTSIG1_HTLength 0xffff 573 #define bLSIG_Rate 0xf 574 #define bLSIG_Reserved 0x10 575 #define bLSIG_Length 0x1fffe 576 #define bLSIG_Parity 0x20 577 #define bCCKRxPhase 0x4 578 579 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 580 581 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 582 583 #define bLSSIReadBackData 0xfffff /* T65 RF */ 584 585 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 586 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 587 #define bRegulator0Standby 0x1 588 #define bRegulatorPLLStandby 0x2 589 #define bRegulator1Standby 0x4 590 #define bPLLPowerUp 0x8 591 #define bDPLLPowerUp 0x10 592 #define bDA10PowerUp 0x20 593 #define bAD7PowerUp 0x200 594 #define bDA6PowerUp 0x2000 595 #define bXtalPowerUp 0x4000 596 #define b40MDClkPowerUP 0x8000 597 #define bDA6DebugMode 0x20000 598 #define bDA6Swing 0x380000 599 600 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 601 602 #define b80MClkDelay 0x18000000 /* Useless */ 603 #define bAFEWatchDogEnable 0x20000000 604 605 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 606 #define bXtalCap23 0x3 607 #define bXtalCap92x 0x0f000000 608 #define bXtalCap 0x0f000000 609 610 #define bIntDifClkEnable 0x400 /* Useless */ 611 #define bExtSigClkEnable 0x800 612 #define bBandgapMbiasPowerUp 0x10000 613 #define bAD11SHGain 0xc0000 614 #define bAD11InputRange 0x700000 615 #define bAD11OPCurrent 0x3800000 616 #define bIPathLoopback 0x4000000 617 #define bQPathLoopback 0x8000000 618 #define bAFELoopback 0x10000000 619 #define bDA10Swing 0x7e0 620 #define bDA10Reverse 0x800 621 #define bDAClkSource 0x1000 622 #define bAD7InputRange 0x6000 623 #define bAD7Gain 0x38000 624 #define bAD7OutputCMMode 0x40000 625 #define bAD7InputCMMode 0x380000 626 #define bAD7Current 0xc00000 627 #define bRegulatorAdjust 0x7000000 628 #define bAD11PowerUpAtTx 0x1 629 #define bDA10PSAtTx 0x10 630 #define bAD11PowerUpAtRx 0x100 631 #define bDA10PSAtRx 0x1000 632 #define bCCKRxAGCFormat 0x200 633 #define bPSDFFTSamplepPoint 0xc000 634 #define bPSDAverageNum 0x3000 635 #define bIQPathControl 0xc00 636 #define bPSDFreq 0x3ff 637 #define bPSDAntennaPath 0x30 638 #define bPSDIQSwitch 0x40 639 #define bPSDRxTrigger 0x400000 640 #define bPSDTxTrigger 0x80000000 641 #define bPSDSineToneScale 0x7f000000 642 #define bPSDReport 0xffff 643 644 /* 3. Page9(0x900) */ 645 #define bOFDMTxSC 0x30000000 /* Useless */ 646 #define bCCKTxOn 0x1 647 #define bOFDMTxOn 0x2 648 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 649 #define bDebugItem 0xff /* reset debug page and LWord */ 650 #define bAntL 0x10 651 #define bAntNonHT 0x100 652 #define bAntHT1 0x1000 653 #define bAntHT2 0x10000 654 #define bAntHT1S1 0x100000 655 #define bAntNonHTS1 0x1000000 656 657 /* 4. PageA(0xA00) */ 658 #define bCCKBBMode 0x3 /* Useless */ 659 #define bCCKTxPowerSaving 0x80 660 #define bCCKRxPowerSaving 0x40 661 662 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 663 664 #define bCCKScramble 0x8 /* Useless */ 665 #define bCCKAntDiversity 0x8000 666 #define bCCKCarrierRecovery 0x4000 667 #define bCCKTxRate 0x3000 668 #define bCCKDCCancel 0x0800 669 #define bCCKISICancel 0x0400 670 #define bCCKMatchFilter 0x0200 671 #define bCCKEqualizer 0x0100 672 #define bCCKPreambleDetect 0x800000 673 #define bCCKFastFalseCCA 0x400000 674 #define bCCKChEstStart 0x300000 675 #define bCCKCCACount 0x080000 676 #define bCCKcs_lim 0x070000 677 #define bCCKBistMode 0x80000000 678 #define bCCKCCAMask 0x40000000 679 #define bCCKTxDACPhase 0x4 680 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 681 #define bCCKr_cp_mode0 0x0100 682 #define bCCKTxDCOffset 0xf0 683 #define bCCKRxDCOffset 0xf 684 #define bCCKCCAMode 0xc000 685 #define bCCKFalseCS_lim 0x3f00 686 #define bCCKCS_ratio 0xc00000 687 #define bCCKCorgBit_sel 0x300000 688 #define bCCKPD_lim 0x0f0000 689 #define bCCKNewCCA 0x80000000 690 #define bCCKRxHPofIG 0x8000 691 #define bCCKRxIG 0x7f00 692 #define bCCKLNAPolarity 0x800000 693 #define bCCKRx1stGain 0x7f0000 694 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 695 #define bCCKRxAGCSatLevel 0x1f000000 696 #define bCCKRxAGCSatCount 0xe0 697 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 698 #define bCCKFixedRxAGC 0x8000 699 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 700 #define bCCKAntennaPolarity 0x2000 701 #define bCCKTxFilterType 0x0c00 702 #define bCCKRxAGCReportType 0x0300 703 #define bCCKRxDAGCEn 0x80000000 704 #define bCCKRxDAGCPeriod 0x20000000 705 #define bCCKRxDAGCSatLevel 0x1f000000 706 #define bCCKTimingRecovery 0x800000 707 #define bCCKTxC0 0x3f0000 708 #define bCCKTxC1 0x3f000000 709 #define bCCKTxC2 0x3f 710 #define bCCKTxC3 0x3f00 711 #define bCCKTxC4 0x3f0000 712 #define bCCKTxC5 0x3f000000 713 #define bCCKTxC6 0x3f 714 #define bCCKTxC7 0x3f00 715 #define bCCKDebugPort 0xff0000 716 #define bCCKDACDebug 0x0f000000 717 #define bCCKFalseAlarmEnable 0x8000 718 #define bCCKFalseAlarmRead 0x4000 719 #define bCCKTRSSI 0x7f 720 #define bCCKRxAGCReport 0xfe 721 #define bCCKRxReport_AntSel 0x80000000 722 #define bCCKRxReport_MFOff 0x40000000 723 #define bCCKRxRxReport_SQLoss 0x20000000 724 #define bCCKRxReport_Pktloss 0x10000000 725 #define bCCKRxReport_Lockedbit 0x08000000 726 #define bCCKRxReport_RateError 0x04000000 727 #define bCCKRxReport_RxRate 0x03000000 728 #define bCCKRxFACounterLower 0xff 729 #define bCCKRxFACounterUpper 0xff000000 730 #define bCCKRxHPAGCStart 0xe000 731 #define bCCKRxHPAGCFinal 0x1c00 732 #define bCCKRxFalseAlarmEnable 0x8000 733 #define bCCKFACounterFreeze 0x4000 734 #define bCCKTxPathSel 0x10000000 735 #define bCCKDefaultRxPath 0xc000000 736 #define bCCKOptionRxPath 0x3000000 737 738 /* 5. PageC(0xC00) */ 739 #define bNumOfSTF 0x3 /* Useless */ 740 #define bShift_L 0xc0 741 #define bGI_TH 0xc 742 #define bRxPathA 0x1 743 #define bRxPathB 0x2 744 #define bRxPathC 0x4 745 #define bRxPathD 0x8 746 #define bTxPathA 0x1 747 #define bTxPathB 0x2 748 #define bTxPathC 0x4 749 #define bTxPathD 0x8 750 #define bTRSSIFreq 0x200 751 #define bADCBackoff 0x3000 752 #define bDFIRBackoff 0xc000 753 #define bTRSSILatchPhase 0x10000 754 #define bRxIDCOffset 0xff 755 #define bRxQDCOffset 0xff00 756 #define bRxDFIRMode 0x1800000 757 #define bRxDCNFType 0xe000000 758 #define bRXIQImb_A 0x3ff 759 #define bRXIQImb_B 0xfc00 760 #define bRXIQImb_C 0x3f0000 761 #define bRXIQImb_D 0xffc00000 762 #define bDC_dc_Notch 0x60000 763 #define bRxNBINotch 0x1f000000 764 #define bPD_TH 0xf 765 #define bPD_TH_Opt2 0xc000 766 #define bPWED_TH 0x700 767 #define bIfMF_Win_L 0x800 768 #define bPD_Option 0x1000 769 #define bMF_Win_L 0xe000 770 #define bBW_Search_L 0x30000 771 #define bwin_enh_L 0xc0000 772 #define bBW_TH 0x700000 773 #define bED_TH2 0x3800000 774 #define bBW_option 0x4000000 775 #define bRatio_TH 0x18000000 776 #define bWindow_L 0xe0000000 777 #define bSBD_Option 0x1 778 #define bFrame_TH 0x1c 779 #define bFS_Option 0x60 780 #define bDC_Slope_check 0x80 781 #define bFGuard_Counter_DC_L 0xe00 782 #define bFrame_Weight_Short 0x7000 783 #define bSub_Tune 0xe00000 784 #define bFrame_DC_Length 0xe000000 785 #define bSBD_start_offset 0x30000000 786 #define bFrame_TH_2 0x7 787 #define bFrame_GI2_TH 0x38 788 #define bGI2_Sync_en 0x40 789 #define bSarch_Short_Early 0x300 790 #define bSarch_Short_Late 0xc00 791 #define bSarch_GI2_Late 0x70000 792 #define bCFOAntSum 0x1 793 #define bCFOAcc 0x2 794 #define bCFOStartOffset 0xc 795 #define bCFOLookBack 0x70 796 #define bCFOSumWeight 0x80 797 #define bDAGCEnable 0x10000 798 #define bTXIQImb_A 0x3ff 799 #define bTXIQImb_B 0xfc00 800 #define bTXIQImb_C 0x3f0000 801 #define bTXIQImb_D 0xffc00000 802 #define bTxIDCOffset 0xff 803 #define bTxQDCOffset 0xff00 804 #define bTxDFIRMode 0x10000 805 #define bTxPesudoNoiseOn 0x4000000 806 #define bTxPesudoNoise_A 0xff 807 #define bTxPesudoNoise_B 0xff00 808 #define bTxPesudoNoise_C 0xff0000 809 #define bTxPesudoNoise_D 0xff000000 810 #define bCCADropOption 0x20000 811 #define bCCADropThres 0xfff00000 812 #define bEDCCA_H 0xf 813 #define bEDCCA_L 0xf0 814 #define bLambda_ED 0x300 815 #define bRxInitialGain 0x7f 816 #define bRxAntDivEn 0x80 817 #define bRxAGCAddressForLNA 0x7f00 818 #define bRxHighPowerFlow 0x8000 819 #define bRxAGCFreezeThres 0xc0000 820 #define bRxFreezeStep_AGC1 0x300000 821 #define bRxFreezeStep_AGC2 0xc00000 822 #define bRxFreezeStep_AGC3 0x3000000 823 #define bRxFreezeStep_AGC0 0xc000000 824 #define bRxRssi_Cmp_En 0x10000000 825 #define bRxQuickAGCEn 0x20000000 826 #define bRxAGCFreezeThresMode 0x40000000 827 #define bRxOverFlowCheckType 0x80000000 828 #define bRxAGCShift 0x7f 829 #define bTRSW_Tri_Only 0x80 830 #define bPowerThres 0x300 831 #define bRxAGCEn 0x1 832 #define bRxAGCTogetherEn 0x2 833 #define bRxAGCMin 0x4 834 #define bRxHP_Ini 0x7 835 #define bRxHP_TRLNA 0x70 836 #define bRxHP_RSSI 0x700 837 #define bRxHP_BBP1 0x7000 838 #define bRxHP_BBP2 0x70000 839 #define bRxHP_BBP3 0x700000 840 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 841 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 842 #define bRxSettle_TRSW 0x7 843 #define bRxSettle_LNA 0x38 844 #define bRxSettle_RSSI 0x1c0 845 #define bRxSettle_BBP 0xe00 846 #define bRxSettle_RxHP 0x7000 847 #define bRxSettle_AntSW_RSSI 0x38000 848 #define bRxSettle_AntSW 0xc0000 849 #define bRxProcessTime_DAGC 0x300000 850 #define bRxSettle_HSSI 0x400000 851 #define bRxProcessTime_BBPPW 0x800000 852 #define bRxAntennaPowerShift 0x3000000 853 #define bRSSITableSelect 0xc000000 854 #define bRxHP_Final 0x7000000 855 #define bRxHTSettle_BBP 0x7 856 #define bRxHTSettle_HSSI 0x8 857 #define bRxHTSettle_RxHP 0x70 858 #define bRxHTSettle_BBPPW 0x80 859 #define bRxHTSettle_Idle 0x300 860 #define bRxHTSettle_Reserved 0x1c00 861 #define bRxHTRxHPEn 0x8000 862 #define bRxHTAGCFreezeThres 0x30000 863 #define bRxHTAGCTogetherEn 0x40000 864 #define bRxHTAGCMin 0x80000 865 #define bRxHTAGCEn 0x100000 866 #define bRxHTDAGCEn 0x200000 867 #define bRxHTRxHP_BBP 0x1c00000 868 #define bRxHTRxHP_Final 0xe0000000 869 #define bRxPWRatioTH 0x3 870 #define bRxPWRatioEn 0x4 871 #define bRxMFHold 0x3800 872 #define bRxPD_Delay_TH1 0x38 873 #define bRxPD_Delay_TH2 0x1c0 874 #define bRxPD_DC_COUNT_MAX 0x600 875 /* #define bRxMF_Hold 0x3800 */ 876 #define bRxPD_Delay_TH 0x8000 877 #define bRxProcess_Delay 0xf0000 878 #define bRxSearchrange_GI2_Early 0x700000 879 #define bRxFrame_Guard_Counter_L 0x3800000 880 #define bRxSGI_Guard_L 0xc000000 881 #define bRxSGI_Search_L 0x30000000 882 #define bRxSGI_TH 0xc0000000 883 #define bDFSCnt0 0xff 884 #define bDFSCnt1 0xff00 885 #define bDFSFlag 0xf0000 886 #define bMFWeightSum 0x300000 887 #define bMinIdxTH 0x7f000000 888 #define bDAFormat 0x40000 889 #define bTxChEmuEnable 0x01000000 890 #define bTRSWIsolation_A 0x7f 891 #define bTRSWIsolation_B 0x7f00 892 #define bTRSWIsolation_C 0x7f0000 893 #define bTRSWIsolation_D 0x7f000000 894 #define bExtLNAGain 0x7c00 895 896 /* 6. PageE(0xE00) */ 897 #define bSTBCEn 0x4 /* Useless */ 898 #define bAntennaMapping 0x10 899 #define bNss 0x20 900 #define bCFOAntSumD 0x200 901 #define bPHYCounterReset 0x8000000 902 #define bCFOReportGet 0x4000000 903 #define bOFDMContinueTx 0x10000000 904 #define bOFDMSingleCarrier 0x20000000 905 #define bOFDMSingleTone 0x40000000 906 /* #define bRxPath1 0x01 */ 907 /* #define bRxPath2 0x02 */ 908 /* #define bRxPath3 0x04 */ 909 /* #define bRxPath4 0x08 */ 910 /* #define bTxPath1 0x10 */ 911 /* #define bTxPath2 0x20 */ 912 #define bHTDetect 0x100 913 #define bCFOEn 0x10000 914 #define bCFOValue 0xfff00000 915 #define bSigTone_Re 0x3f 916 #define bSigTone_Im 0x7f00 917 #define bCounter_CCA 0xffff 918 #define bCounter_ParityFail 0xffff0000 919 #define bCounter_RateIllegal 0xffff 920 #define bCounter_CRC8Fail 0xffff0000 921 #define bCounter_MCSNoSupport 0xffff 922 #define bCounter_FastSync 0xffff 923 #define bShortCFO 0xfff 924 #define bShortCFOTLength 12 /* total */ 925 #define bShortCFOFLength 11 /* fraction */ 926 #define bLongCFO 0x7ff 927 #define bLongCFOTLength 11 928 #define bLongCFOFLength 11 929 #define bTailCFO 0x1fff 930 #define bTailCFOTLength 13 931 #define bTailCFOFLength 12 932 #define bmax_en_pwdB 0xffff 933 #define bCC_power_dB 0xffff0000 934 #define bnoise_pwdB 0xffff 935 #define bPowerMeasTLength 10 936 #define bPowerMeasFLength 3 937 #define bRx_HT_BW 0x1 938 #define bRxSC 0x6 939 #define bRx_HT 0x8 940 #define bNB_intf_det_on 0x1 941 #define bIntf_win_len_cfg 0x30 942 #define bNB_Intf_TH_cfg 0x1c0 943 #define bRFGain 0x3f 944 #define bTableSel 0x40 945 #define bTRSW 0x80 946 #define bRxSNR_A 0xff 947 #define bRxSNR_B 0xff00 948 #define bRxSNR_C 0xff0000 949 #define bRxSNR_D 0xff000000 950 #define bSNREVMTLength 8 951 #define bSNREVMFLength 1 952 #define bCSI1st 0xff 953 #define bCSI2nd 0xff00 954 #define bRxEVM1st 0xff0000 955 #define bRxEVM2nd 0xff000000 956 #define bSIGEVM 0xff 957 #define bPWDB 0xff00 958 #define bSGIEN 0x10000 959 960 #define bSFactorQAM1 0xf /* Useless */ 961 #define bSFactorQAM2 0xf0 962 #define bSFactorQAM3 0xf00 963 #define bSFactorQAM4 0xf000 964 #define bSFactorQAM5 0xf0000 965 #define bSFactorQAM6 0xf0000 966 #define bSFactorQAM7 0xf00000 967 #define bSFactorQAM8 0xf000000 968 #define bSFactorQAM9 0xf0000000 969 #define bCSIScheme 0x100000 970 971 #define bNoiseLvlTopSet 0x3 /* Useless */ 972 #define bChSmooth 0x4 973 #define bChSmoothCfg1 0x38 974 #define bChSmoothCfg2 0x1c0 975 #define bChSmoothCfg3 0xe00 976 #define bChSmoothCfg4 0x7000 977 #define bMRCMode 0x800000 978 #define bTHEVMCfg 0x7000000 979 980 #define bLoopFitType 0x1 /* Useless */ 981 #define bUpdCFO 0x40 982 #define bUpdCFOOffData 0x80 983 #define bAdvUpdCFO 0x100 984 #define bAdvTimeCtrl 0x800 985 #define bUpdClko 0x1000 986 #define bFC 0x6000 987 #define bTrackingMode 0x8000 988 #define bPhCmpEnable 0x10000 989 #define bUpdClkoLTF 0x20000 990 #define bComChCFO 0x40000 991 #define bCSIEstiMode 0x80000 992 #define bAdvUpdEqz 0x100000 993 #define bUChCfg 0x7000000 994 #define bUpdEqz 0x8000000 995 996 /* Rx Pseduo noise */ 997 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 998 #define bRxPesudoNoise_A 0xff 999 #define bRxPesudoNoise_B 0xff00 1000 #define bRxPesudoNoise_C 0xff0000 1001 #define bRxPesudoNoise_D 0xff000000 1002 #define bPesudoNoiseState_A 0xffff 1003 #define bPesudoNoiseState_B 0xffff0000 1004 #define bPesudoNoiseState_C 0xffff 1005 #define bPesudoNoiseState_D 0xffff0000 1006 1007 /* 7. RF Register 1008 * Zebra1 */ 1009 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1010 #define bZebra1_TRxControl 0xc00 1011 #define bZebra1_TRxGainSetting 0x07f 1012 #define bZebra1_RxCorner 0xc00 1013 #define bZebra1_TxChargePump 0x38 1014 #define bZebra1_RxChargePump 0x7 1015 #define bZebra1_ChannelNum 0xf80 1016 #define bZebra1_TxLPFBW 0x400 1017 #define bZebra1_RxLPFBW 0x600 1018 1019 /* Zebra4 */ 1020 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1021 #define bRTL8256RegModeCtrl0 0x40 1022 #define bRTL8256_TxLPFBW 0x18 1023 #define bRTL8256_RxLPFBW 0x600 1024 1025 /* RTL8258 */ 1026 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1027 #define bRTL8258_RxLPFBW 0xc00 1028 #define bRTL8258_RSSILPFBW 0xc0 1029 1030 1031 /* 1032 * Other Definition 1033 * */ 1034 1035 /* byte endable for sb_write */ 1036 #define bByte0 0x1 /* Useless */ 1037 #define bByte1 0x2 1038 #define bByte2 0x4 1039 #define bByte3 0x8 1040 #define bWord0 0x3 1041 #define bWord1 0xc 1042 #define bDWord 0xf 1043 1044 /* for PutRegsetting & GetRegSetting BitMask */ 1045 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1046 #define bMaskByte1 0xff00 1047 #define bMaskByte2 0xff0000 1048 #define bMaskByte3 0xff000000 1049 #define bMaskHWord 0xffff0000 1050 #define bMaskLWord 0x0000ffff 1051 #define bMaskDWord 0xffffffff 1052 #define bMaskH3Bytes 0xffffff00 1053 #define bMask12Bits 0xfff 1054 #define bMaskH4Bits 0xf0000000 1055 #define bMaskOFDM_D 0xffc00000 1056 #define bMaskCCK 0x3f3f3f3f 1057 1058 1059 1060 #define bEnable 0x1 /* Useless */ 1061 #define bDisable 0x0 1062 1063 #define LeftAntenna 0x0 /* Useless */ 1064 #define RightAntenna 0x1 1065 1066 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1067 #define tUpdateRxCounter 100 /* 100ms */ 1068 1069 #define rateCCK 0 /* Useless */ 1070 #define rateOFDM 1 1071 #define rateHT 2 1072 1073 /* define Register-End */ 1074 #define bPMAC_End 0x1ff /* Useless */ 1075 #define bFPGAPHY0_End 0x8ff 1076 #define bFPGAPHY1_End 0x9ff 1077 #define bCCKPHY0_End 0xaff 1078 #define bOFDMPHY0_End 0xcff 1079 #define bOFDMPHY1_End 0xdff 1080 1081 /* define max debug item in each debug page 1082 * #define bMaxItem_FPGA_PHY0 0x9 1083 * #define bMaxItem_FPGA_PHY1 0x3 1084 * #define bMaxItem_PHY_11B 0x16 1085 * #define bMaxItem_OFDM_PHY0 0x29 1086 * #define bMaxItem_OFDM_PHY1 0x0 */ 1087 1088 #define bPMACControl 0x0 /* Useless */ 1089 #define bWMACControl 0x1 1090 #define bWNICControl 0x2 1091 1092 #define PathA 0x0 /* Useless */ 1093 #define PathB 0x1 1094 #define PathC 0x2 1095 #define PathD 0x3 1096 1097 /*--------------------------Define Parameters-------------------------------*/ 1098 1099 1100 #endif 1101