1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDM_AUTO_DBG_H__ 27 #define __PHYDM_AUTO_DBG_H__ 28 29 #define AUTO_DBG_VERSION "1.0" /* @2017.05.015 Dino, Add phydm_auto_dbg.h*/ 30 31 /* @1 ============================================================ 32 * 1 Definition 33 * 1 ============================================================ 34 */ 35 36 #define AUTO_CHK_HANG_STEP_MAX 3 37 #define DBGPORT_CHK_NUM 6 38 39 #ifdef PHYDM_AUTO_DEGBUG 40 41 /* @1 ============================================================ 42 * 1 enumeration 43 * 1 ============================================================ 44 */ 45 46 enum auto_dbg_type_e { 47 AUTO_DBG_STOP = 0, 48 AUTO_DBG_CHECK_HANG = 1, 49 AUTO_DBG_CHECK_RA = 2, 50 AUTO_DBG_CHECK_DIG = 3 51 }; 52 53 /* @1 ============================================================ 54 * 1 structure 55 * 1 ============================================================ 56 */ 57 58 struct n_dbgport_803 { 59 /*@BYTE 3*/ 60 u8 bb_rst_b : 1; 61 u8 glb_rst_b : 1; 62 u8 zero_1bit_1 : 1; 63 u8 ofdm_rst_b : 1; 64 u8 cck_txpe : 1; 65 u8 ofdm_txpe : 1; 66 u8 phy_tx_on : 1; 67 u8 tdrdy : 1; 68 /*@BYTE 2*/ 69 u8 txd : 8; 70 /*@BYTE 1*/ 71 u8 cck_cca_pp : 1; 72 u8 ofdm_cca_pp : 1; 73 u8 rx_rst : 1; 74 u8 rdrdy : 1; 75 u8 rxd_7_4 : 4; 76 /*@BYTE 0*/ 77 u8 rxd_3_0 : 4; 78 u8 ofdm_tx_en : 1; 79 u8 cck_tx_en : 1; 80 u8 zero_1bit_2 : 1; 81 u8 clk_80m : 1; 82 }; 83 84 struct phydm_auto_dbg_struct { 85 enum auto_dbg_type_e auto_dbg_type; 86 u8 dbg_step; 87 u16 dbg_port_table[DBGPORT_CHK_NUM]; 88 u32 dbg_port_val[DBGPORT_CHK_NUM]; 89 u16 ofdm_t_cnt; 90 u16 ofdm_r_cnt; 91 u16 cck_t_cnt; 92 u16 cck_r_cnt; 93 u16 ofdm_crc_error_cnt; 94 u16 cck_crc_error_cnt; 95 }; 96 97 /* @1 ============================================================ 98 * 1 function prototype 99 * 1 ============================================================ 100 */ 101 102 void phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len); 103 104 void phydm_auto_dbg_console( 105 void *dm_void, 106 char input[][16], 107 u32 *_used, 108 char *output, 109 u32 *_out_len); 110 111 void phydm_auto_dbg_engine(void *dm_void); 112 113 void phydm_auto_dbg_engine_init(void *dm_void); 114 #endif 115 #endif 116