1 /******************************************************************************
2 *
3 * Copyright(c) 2013 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include <rtw_odm.h>
17 #include <hal_data.h>
18
rtw_phydm_ability_ops(_adapter * adapter,HAL_PHYDM_OPS ops,u32 ability)19 u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
20 {
21 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
22 struct dm_struct *podmpriv = &pHalData->odmpriv;
23 u32 result = 0;
24
25 switch (ops) {
26 case HAL_PHYDM_DIS_ALL_FUNC:
27 podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
28 halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
29 break;
30 case HAL_PHYDM_FUNC_SET:
31 podmpriv->support_ability |= ability;
32 break;
33 case HAL_PHYDM_FUNC_CLR:
34 podmpriv->support_ability &= ~(ability);
35 break;
36 case HAL_PHYDM_ABILITY_BK:
37 /* dm flag backup*/
38 podmpriv->bk_support_ability = podmpriv->support_ability;
39 pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
40 break;
41 case HAL_PHYDM_ABILITY_RESTORE:
42 /* restore dm flag */
43 podmpriv->support_ability = podmpriv->bk_support_ability;
44 halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
45 break;
46 case HAL_PHYDM_ABILITY_SET:
47 podmpriv->support_ability = ability;
48 break;
49 case HAL_PHYDM_ABILITY_GET:
50 result = podmpriv->support_ability;
51 break;
52 }
53 return result;
54 }
55
56 /* set ODM_CMNINFO_IC_TYPE based on chip_type */
rtw_odm_init_ic_type(_adapter * adapter)57 void rtw_odm_init_ic_type(_adapter *adapter)
58 {
59 struct dm_struct *odm = adapter_to_phydm(adapter);
60 u32 ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
61
62 rtw_warn_on(!ic_type);
63
64 odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
65 }
66
rtw_odm_adaptivity_ver_msg(void * sel,_adapter * adapter)67 void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
68 {
69 RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
70 }
71
72 #define RTW_ADAPTIVITY_EN_DISABLE 0
73 #define RTW_ADAPTIVITY_EN_ENABLE 1
74 #define RTW_ADAPTIVITY_EN_AUTO 2
75
rtw_odm_adaptivity_en_msg(void * sel,_adapter * adapter)76 void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
77 {
78 struct registry_priv *regsty = &adapter->registrypriv;
79
80 RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
81
82 if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
83 _RTW_PRINT_SEL(sel, "DISABLE\n");
84 else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
85 _RTW_PRINT_SEL(sel, "ENABLE\n");
86 else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO)
87 _RTW_PRINT_SEL(sel, "AUTO\n");
88 else
89 _RTW_PRINT_SEL(sel, "INVALID\n");
90 }
91
92 #define RTW_ADAPTIVITY_MODE_NORMAL 0
93 #define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
94
rtw_odm_adaptivity_mode_msg(void * sel,_adapter * adapter)95 void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
96 {
97 struct registry_priv *regsty = &adapter->registrypriv;
98
99 if (regsty->adaptivity_en != RTW_ADAPTIVITY_EN_ENABLE)
100 return;
101
102 RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
103
104 if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
105 _RTW_PRINT_SEL(sel, "NORMAL\n");
106 else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
107 _RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
108 else
109 _RTW_PRINT_SEL(sel, "INVALID\n");
110 }
111
rtw_odm_adaptivity_config_msg(void * sel,_adapter * adapter)112 void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
113 {
114 rtw_odm_adaptivity_ver_msg(sel, adapter);
115 rtw_odm_adaptivity_en_msg(sel, adapter);
116 rtw_odm_adaptivity_mode_msg(sel, adapter);
117 }
118
rtw_odm_adaptivity_needed(_adapter * adapter)119 bool rtw_odm_adaptivity_needed(_adapter *adapter)
120 {
121 struct registry_priv *regsty = &adapter->registrypriv;
122 bool ret = _FALSE;
123
124 if (regsty->adaptivity_en)
125 ret = _TRUE;
126
127 return ret;
128 }
129
rtw_odm_adaptivity_update(struct dvobj_priv * dvobj)130 void rtw_odm_adaptivity_update(struct dvobj_priv *dvobj)
131 {
132 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(dvobj_get_primary_adapter(dvobj));
133 struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
134 struct dm_struct *odm = dvobj_to_phydm(dvobj);
135 u8 edcca_mode = RTW_EDCCA_NORMAL;
136
137 if (hal_data->current_band_type == BAND_ON_2_4G)
138 edcca_mode = rfctl->edcca_mode_2g;
139 #if CONFIG_IEEE80211_BAND_5GHZ
140 else if (hal_data->current_band_type == BAND_ON_5G)
141 edcca_mode = rfctl->edcca_mode_5g;
142 #endif
143 #if CONFIG_IEEE80211_BAND_6GHZ
144 else if (hal_data->current_band_type == BAND_ON_6G)
145 edcca_mode = rfctl->edcca_mode_6g;
146 #endif
147
148 rfctl->adaptivity_en = (edcca_mode == RTW_EDCCA_NORMAL || edcca_mode == RTW_EDCCA_MODE_NUM) ? 0 : 1;
149 phydm_adaptivity_info_init(odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, edcca_mode == RTW_EDCCA_CS ? TRUE : FALSE);
150 }
151
rtw_odm_adaptivity_parm_msg(void * sel,_adapter * adapter)152 void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
153 {
154 struct dm_struct *odm = adapter_to_phydm(adapter);
155
156 rtw_odm_adaptivity_config_msg(sel, adapter);
157
158 RTW_PRINT_SEL(sel, "%10s %16s\n"
159 , "th_l2h_ini", "th_edcca_hl_diff");
160 RTW_PRINT_SEL(sel, "0x%-8x %-16d\n"
161 , (u8)odm->th_l2h_ini
162 , odm->th_edcca_hl_diff
163 );
164 }
165
rtw_odm_adaptivity_parm_set(_adapter * adapter,s8 th_l2h_ini,s8 th_edcca_hl_diff)166 void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)
167 {
168 struct dm_struct *odm = adapter_to_phydm(adapter);
169
170 odm->th_l2h_ini = th_l2h_ini;
171 odm->th_edcca_hl_diff = th_edcca_hl_diff;
172 }
173
rtw_odm_get_perpkt_rssi(void * sel,_adapter * adapter)174 void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
175 {
176 struct dm_struct *odm = adapter_to_phydm(adapter);
177
178 RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
179 HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
180 }
181
182
rtw_odm_acquirespinlock(_adapter * adapter,enum rt_spinlock_type type)183 void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type)
184 {
185 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
186 _irqL irqL;
187
188 switch (type) {
189 case RT_IQK_SPINLOCK:
190 _enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
191 break;
192 default:
193 break;
194 }
195 }
196
rtw_odm_releasespinlock(_adapter * adapter,enum rt_spinlock_type type)197 void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type)
198 {
199 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
200 _irqL irqL;
201
202 switch (type) {
203 case RT_IQK_SPINLOCK:
204 _exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
205 break;
206 default:
207 break;
208 }
209 }
210
rtw_odm_get_tx_power_mbm(struct dm_struct * dm,u8 rfpath,u8 rate,u8 bw,u8 cch)211 s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch)
212 {
213 return phy_get_txpwr_single_mbm(dm->adapter, rfpath, mgn_rate_to_rs(rate), rate, bw, cch, 0, 0, 0, NULL);
214 }
215
216 #ifdef CONFIG_DFS_MASTER
rtw_odm_radar_detect_reset(_adapter * adapter)217 inline void rtw_odm_radar_detect_reset(_adapter *adapter)
218 {
219 phydm_radar_detect_reset(adapter_to_phydm(adapter));
220 }
221
rtw_odm_radar_detect_disable(_adapter * adapter)222 inline void rtw_odm_radar_detect_disable(_adapter *adapter)
223 {
224 phydm_radar_detect_disable(adapter_to_phydm(adapter));
225 }
226
227 /* called after ch, bw is set */
rtw_odm_radar_detect_enable(_adapter * adapter)228 inline void rtw_odm_radar_detect_enable(_adapter *adapter)
229 {
230 phydm_radar_detect_enable(adapter_to_phydm(adapter));
231 }
232
rtw_odm_radar_detect(_adapter * adapter)233 inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
234 {
235 return phydm_radar_detect(adapter_to_phydm(adapter));
236 }
237
238 static enum phydm_dfs_region_domain _rtw_dfs_regd_to_phydm[] = {
239 [RTW_DFS_REGD_NONE] = PHYDM_DFS_DOMAIN_UNKNOWN,
240 [RTW_DFS_REGD_FCC] = PHYDM_DFS_DOMAIN_FCC,
241 [RTW_DFS_REGD_MKK] = PHYDM_DFS_DOMAIN_MKK,
242 [RTW_DFS_REGD_ETSI] = PHYDM_DFS_DOMAIN_ETSI,
243 };
244
245 #define rtw_dfs_regd_to_phydm(region) (((region) >= RTW_DFS_REGD_NUM) ? _rtw_dfs_regd_to_phydm[RTW_DFS_REGD_NONE] : _rtw_dfs_regd_to_phydm[(region)])
246
rtw_odm_update_dfs_region(struct dvobj_priv * dvobj)247 void rtw_odm_update_dfs_region(struct dvobj_priv *dvobj)
248 {
249 odm_cmn_info_init(dvobj_to_phydm(dvobj), ODM_CMNINFO_DFS_REGION_DOMAIN, rtw_dfs_regd_to_phydm(rtw_rfctl_get_dfs_domain(dvobj_to_rfctl(dvobj))));
250 }
251
rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv * dvobj)252 inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
253 {
254 return phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
255 }
256 #endif /* CONFIG_DFS_MASTER */
257
rtw_odm_parse_rx_phy_status_chinfo(union recv_frame * rframe,u8 * phys)258 void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
259 {
260 #ifndef DBG_RX_PHYSTATUS_CHINFO
261 #define DBG_RX_PHYSTATUS_CHINFO 0
262 #endif
263
264 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
265 _adapter *adapter = rframe->u.hdr.adapter;
266 struct dm_struct *phydm = adapter_to_phydm(adapter);
267 struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
268 u8 *wlanhdr = get_recvframe_data(rframe);
269
270 if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
271 /*
272 * 8723D:
273 * type_0(CCK)
274 * l_rxsc
275 * is filled with primary channel SC, not real rxsc.
276 * 0:LSC, 1:USC
277 * type_1(OFDM)
278 * rf_mode
279 * RF bandwidth when RX
280 * l_rxsc(legacy), ht_rxsc
281 * see below RXSC N-series
282 * type_2(Not used)
283 */
284 /*
285 * 8821C, 8822B:
286 * type_0(CCK)
287 * l_rxsc
288 * is filled with primary channel SC, not real rxsc.
289 * 0:LSC, 1:USC
290 * type_1(OFDM)
291 * rf_mode
292 * RF bandwidth when RX
293 * l_rxsc(legacy), ht_rxsc
294 * see below RXSC AC-series
295 * type_2(Not used)
296 */
297
298 if ((*phys & 0xf) == 0) {
299 struct phy_sts_rpt_jgr2_type0 *phys_t0 = (struct phy_sts_rpt_jgr2_type0 *)phys;
300
301 if (DBG_RX_PHYSTATUS_CHINFO) {
302 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
303 , *phys & 0xf
304 , MAC_ARG(get_ta(wlanhdr))
305 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
306 , HDATA_RATE(attrib->data_rate)
307 , phys_t0->band, phys_t0->channel, phys_t0->rxsc
308 );
309 }
310
311 } else if ((*phys & 0xf) == 1) {
312 struct phy_sts_rpt_jgr2_type1 *phys_t1 = (struct phy_sts_rpt_jgr2_type1 *)phys;
313 u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
314 u8 pkt_cch = 0;
315 u8 pkt_bw = CHANNEL_WIDTH_20;
316
317 #if ODM_IC_11N_SERIES_SUPPORT
318 if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
319 /* RXSC N-series */
320 #define RXSC_DUP 0
321 #define RXSC_LSC 1
322 #define RXSC_USC 2
323 #define RXSC_40M 3
324
325 static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
326
327 if (phys_t1->rf_mode == 0) {
328 pkt_cch = phys_t1->channel;
329 pkt_bw = CHANNEL_WIDTH_20;
330 } else if (phys_t1->rf_mode == 1) {
331 if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
332 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
333 pkt_bw = CHANNEL_WIDTH_20;
334 } else if (rxsc == RXSC_40M) {
335 pkt_cch = phys_t1->channel;
336 pkt_bw = CHANNEL_WIDTH_40;
337 }
338 } else
339 rtw_warn_on(1);
340
341 goto type1_end;
342 }
343 #endif /* ODM_IC_11N_SERIES_SUPPORT */
344
345 #if ODM_IC_11AC_SERIES_SUPPORT
346 if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
347 /* RXSC AC-series */
348 #define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */
349
350 #define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */
351 #define RXSC_L20M_OF_160M 6
352 #define RXSC_L20M_OF_80M 4
353 #define RXSC_L20M_OF_40M 2
354 #define RXSC_U20M_OF_40M 1
355 #define RXSC_U20M_OF_80M 3
356 #define RXSC_U20M_OF_160M 5
357 #define RXSC_UU20M_OF_160M 7
358
359 #define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */
360 #define RXSC_L40M_OF_80M 10
361 #define RXSC_U40M_OF_80M 9
362 #define RXSC_U40M_OF_160M 11
363
364 #define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */
365 #define RXSC_U80M_OF_160M 13
366
367 static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
368
369 if (phys_t1->rf_mode == 0) {
370 /* RF 20MHz */
371 pkt_cch = phys_t1->channel;
372 pkt_bw = CHANNEL_WIDTH_20;
373 goto type1_end;
374 }
375
376 if (rxsc == 0) {
377 /* RF and RX with same BW */
378 if (attrib->data_rate >= DESC_RATEMCS0) {
379 pkt_cch = phys_t1->channel;
380 pkt_bw = phys_t1->rf_mode;
381 }
382 goto type1_end;
383 }
384
385 if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
386 || (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
387 || (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
388 ) {
389 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
390 pkt_bw = CHANNEL_WIDTH_20;
391 } else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
392 || (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
393 ) {
394 if (attrib->data_rate >= DESC_RATEMCS0) {
395 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
396 pkt_bw = CHANNEL_WIDTH_40;
397 }
398 } else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
399 ) {
400 if (attrib->data_rate >= DESC_RATEMCS0) {
401 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
402 pkt_bw = CHANNEL_WIDTH_80;
403 }
404 } else
405 rtw_warn_on(1);
406
407 }
408 #endif /* ODM_IC_11AC_SERIES_SUPPORT */
409
410 type1_end:
411 if (DBG_RX_PHYSTATUS_CHINFO) {
412 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
413 , *phys & 0xf
414 , MAC_ARG(get_ta(wlanhdr))
415 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
416 , HDATA_RATE(attrib->data_rate)
417 , phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
418 , pkt_cch, pkt_bw
419 );
420 }
421
422 /* for now, only return cneter channel of 20MHz packet */
423 if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
424 attrib->ch = pkt_cch;
425
426 } else {
427 struct phy_sts_rpt_jgr2_type2 *phys_t2 = (struct phy_sts_rpt_jgr2_type2 *)phys;
428
429 if (DBG_RX_PHYSTATUS_CHINFO) {
430 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
431 , *phys & 0xf
432 , MAC_ARG(get_ta(wlanhdr))
433 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
434 , HDATA_RATE(attrib->data_rate)
435 , phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
436 );
437 }
438 }
439 }
440 #endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
441
442 }
443
444 #if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
445 void
debug_DACK(struct dm_struct * dm)446 debug_DACK(
447 struct dm_struct *dm
448 )
449 {
450 //P_PHYDM_FUNC dm;
451 //dm = &(SysMib.ODM.Phydm);
452 //PIQK_OFFLOAD_PARM pIQK_info;
453 //pIQK_info= &(SysMib.ODM.IQKParm);
454 u8 i;
455 u32 temp1, temp2, temp3;
456
457 temp1 = odm_get_bb_reg(dm, 0x1860, bMaskDWord);
458 temp2 = odm_get_bb_reg(dm, 0x4160, bMaskDWord);
459 temp3 = odm_get_bb_reg(dm, 0x9b4, bMaskDWord);
460
461 odm_set_bb_reg(dm, 0x9b4, bMaskDWord, 0xdb66db00);
462
463 //pathA
464 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
465 odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
466
467 RTW_INFO("path A i\n");
468 //i
469 for (i = 0; i < 0xf; i++) {
470 odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
471 RTW_INFO("[0][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000));
472 //pIQK_info->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
473 }
474 RTW_INFO("path A q\n");
475 //q
476 for (i = 0; i < 0xf; i++) {
477 odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
478 RTW_INFO("[0][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000));
479 //pIQK_info->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
480 }
481 //pathB
482 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
483 odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
484
485 RTW_INFO("\npath B i\n");
486 //i
487 for (i = 0; i < 0xf; i++) {
488 odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
489 RTW_INFO("[1][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x4510,0x7fc0000));
490 //pIQK_info->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
491 }
492 RTW_INFO("path B q\n");
493 //q
494 for (i = 0; i < 0xf; i++) {
495 odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
496 RTW_INFO("[1][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x453c,0x7fc0000));
497 //pIQK_info->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
498 }
499
500 //restore to normal
501 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
502 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
503 odm_set_bb_reg(dm, 0x1860, bMaskDWord, temp1);
504 odm_set_bb_reg(dm, 0x4160, bMaskDWord, temp2);
505 odm_set_bb_reg(dm, 0x9b4, bMaskDWord, temp3);
506
507
508 }
509
510 void
debug_IQK(struct dm_struct * dm,IN u8 idx,IN u8 path)511 debug_IQK(
512 struct dm_struct *dm,
513 IN u8 idx,
514 IN u8 path
515 )
516 {
517 u8 i, ch;
518 u32 tmp;
519 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
520
521 RTW_INFO("idx = %d, path = %d\n", idx, path);
522
523 odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);
524
525 if (idx == TX_IQK) {//TXCFIR
526 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
527 } else {//RXCFIR
528 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
529 }
530 odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
531 odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
532 for (i = 0; i <= 16; i++) {
533 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
534 tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
535 RTW_INFO("iqk_cfir_real[%d][%d][%d] = 0x%x\n", path, idx, i, ((tmp & 0x0fff0000) >> 16));
536 //iqk_info->iqk_cfir_real[ch][path][idx][i] =
537 // (tmp & 0x0fff0000) >> 16;
538 RTW_INFO("iqk_cfir_imag[%d][%d][%d] = 0x%x\n", path, idx, i, (tmp & 0x0fff));
539 //iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0x0fff;
540 }
541 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
542 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
543 }
544
545 __odm_func__ void
debug_information_8822c(struct dm_struct * dm)546 debug_information_8822c(
547 struct dm_struct *dm)
548 {
549 struct dm_dpk_info *dpk_info = &dm->dpk_info;
550
551 u32 reg_rf18;
552
553 if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
554 dpk_info->is_tssi_mode = true;
555 else
556 dpk_info->is_tssi_mode = false;
557
558 reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
559
560 dpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
561 dpk_info->dpk_ch = (u8)reg_rf18 & 0xff;
562 dpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
563
564 RTW_INFO("[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
565 dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? "2G" : "5G",
566 dpk_info->dpk_ch,
567 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
568 }
569
570 extern void _dpk_get_coef_8822c(void *dm_void, u8 path);
571
572 __odm_func__ void
debug_reload_data_8822c(void * dm_void)573 debug_reload_data_8822c(
574 void *dm_void)
575 {
576 struct dm_struct *dm = (struct dm_struct *)dm_void;
577 struct dm_dpk_info *dpk_info = &dm->dpk_info;
578
579 u8 path;
580 u32 u32tmp;
581
582 debug_information_8822c(dm);
583
584 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
585
586 RTW_INFO("[DPK] Reload path: 0x%x\n", path);
587
588 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
589
590 /*txagc bnd*/
591 if (dpk_info->dpk_band == 0x0)
592 u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
593 else
594 u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
595
596 RTW_INFO("[DPK] txagc bnd = 0x%08x\n", u32tmp);
597
598 u32tmp = odm_get_bb_reg(dm, R_0x1b64, MASKBYTE3);
599 RTW_INFO("[DPK] dpk_txagc = 0x%08x\n", u32tmp);
600
601 //debug_coef_write_8822c(dm, path, dpk_info->dpk_path_ok & BIT(path) >> path);
602 _dpk_get_coef_8822c(dm, path);
603
604 //debug_one_shot_8822c(dm, path, DPK_ON);
605
606 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
607
608 if (path == RF_PATH_A)
609 u32tmp = odm_get_bb_reg(dm, R_0x1b04, 0x0fffffff);
610 else
611 u32tmp = odm_get_bb_reg(dm, R_0x1b5c, 0x0fffffff);
612
613 RTW_INFO("[DPK] dpk_gs = 0x%08x\n", u32tmp);
614
615 }
616 }
617
odm_lps_pg_debug_8822c(void * dm_void)618 void odm_lps_pg_debug_8822c(void *dm_void)
619 {
620 struct dm_struct *dm = (struct dm_struct *)dm_void;
621
622 debug_DACK(dm);
623 debug_IQK(dm, TX_IQK, RF_PATH_A);
624 debug_IQK(dm, RX_IQK, RF_PATH_A);
625 debug_IQK(dm, TX_IQK, RF_PATH_B);
626 debug_IQK(dm, RX_IQK, RF_PATH_B);
627 debug_reload_data_8822c(dm);
628 }
629 #endif /* defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG) */
630
631