1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 /***************************************************************************** 16 * 17 * Module: __RTW_MP_PHY_REGDEF_H_ 18 * 19 * 20 * Note: 1. Define PMAC/BB register map 21 * 2. Define RF register map 22 * 3. PMAC/BB register bit mask. 23 * 4. RF reg bit mask. 24 * 5. Other BB/RF relative definition. 25 * 26 * 27 * Export: Constants, macro, functions(API), global variables(None). 28 * 29 * Abbrev: 30 * 31 * History: 32 * Data Who Remark 33 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 34 * 2. Reorganize code architecture. 35 * 09/25/2008 MH 1. Add RL6052 register definition 36 * 37 *****************************************************************************/ 38 #ifndef __RTW_MP_PHY_REGDEF_H_ 39 #define __RTW_MP_PHY_REGDEF_H_ 40 41 42 /*--------------------------Define Parameters-------------------------------*/ 43 44 /* ************************************************************ 45 * 8192S Regsiter offset definition 46 * ************************************************************ */ 47 48 /* 49 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 50 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 51 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 52 * 3. RF register 0x00-2E 53 * 4. Bit Mask for BB/RF register 54 * 5. Other defintion for BB/RF R/W 55 * */ 56 57 58 /* 59 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 60 * 1. Page1(0x100) 61 * */ 62 #define rPMAC_Reset 0x100 63 #define rPMAC_TxStart 0x104 64 #define rPMAC_TxLegacySIG 0x108 65 #define rPMAC_TxHTSIG1 0x10c 66 #define rPMAC_TxHTSIG2 0x110 67 #define rPMAC_PHYDebug 0x114 68 #define rPMAC_TxPacketNum 0x118 69 #define rPMAC_TxIdle 0x11c 70 #define rPMAC_TxMACHeader0 0x120 71 #define rPMAC_TxMACHeader1 0x124 72 #define rPMAC_TxMACHeader2 0x128 73 #define rPMAC_TxMACHeader3 0x12c 74 #define rPMAC_TxMACHeader4 0x130 75 #define rPMAC_TxMACHeader5 0x134 76 #define rPMAC_TxDataType 0x138 77 #define rPMAC_TxRandomSeed 0x13c 78 #define rPMAC_CCKPLCPPreamble 0x140 79 #define rPMAC_CCKPLCPHeader 0x144 80 #define rPMAC_CCKCRC16 0x148 81 #define rPMAC_OFDMRxCRC32OK 0x170 82 #define rPMAC_OFDMRxCRC32Er 0x174 83 #define rPMAC_OFDMRxParityEr 0x178 84 #define rPMAC_OFDMRxCRC8Er 0x17c 85 #define rPMAC_CCKCRxRC16Er 0x180 86 #define rPMAC_CCKCRxRC32Er 0x184 87 #define rPMAC_CCKCRxRC32OK 0x188 88 #define rPMAC_TxStatus 0x18c 89 90 /* 91 * 2. Page2(0x200) 92 * 93 * The following two definition are only used for USB interface. 94 * #define RF_BB_CMD_ADDR 0x02c0 */ /* RF/BB read/write command address. 95 * #define RF_BB_CMD_DATA 0x02c4 */ /* RF/BB read/write command data. */ 96 97 /* 98 * 3. Page8(0x800) 99 * */ 100 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 101 102 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 103 #define rFPGA0_PSDFunction 0x808 104 105 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 106 107 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 108 #define rFPGA0_RFTiming2 0x814 109 /* #define rFPGA0_XC_RFTiming 0x818 */ 110 /* #define rFPGA0_XD_RFTiming 0x81c */ 111 112 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 113 #define rFPGA0_XA_HSSIParameter2 0x824 114 #define rFPGA0_XB_HSSIParameter1 0x828 115 #define rFPGA0_XB_HSSIParameter2 0x82c 116 #define rFPGA0_XC_HSSIParameter1 0x830 117 #define rFPGA0_XC_HSSIParameter2 0x834 118 #define rFPGA0_XD_HSSIParameter1 0x838 119 #define rFPGA0_XD_HSSIParameter2 0x83c 120 #define rFPGA0_XA_LSSIParameter 0x840 121 #define rFPGA0_XB_LSSIParameter 0x844 122 #define rFPGA0_XC_LSSIParameter 0x848 123 #define rFPGA0_XD_LSSIParameter 0x84c 124 125 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 126 #define rFPGA0_RFSleepUpParameter 0x854 127 128 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 129 #define rFPGA0_XCD_SwitchControl 0x85c 130 131 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 132 #define rFPGA0_XB_RFInterfaceOE 0x864 133 #define rFPGA0_XC_RFInterfaceOE 0x868 134 #define rFPGA0_XD_RFInterfaceOE 0x86c 135 136 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 137 #define rFPGA0_XCD_RFInterfaceSW 0x874 138 139 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 140 #define rFPGA0_XCD_RFParameter 0x87c 141 142 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 143 #define rFPGA0_AnalogParameter2 0x884 144 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 145 #define rFPGA0_AnalogParameter4 0x88c 146 147 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 148 #define rFPGA0_XB_LSSIReadBack 0x8a4 149 #define rFPGA0_XC_LSSIReadBack 0x8a8 150 #define rFPGA0_XD_LSSIReadBack 0x8ac 151 152 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 153 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 154 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 155 156 /* 157 * 4. Page9(0x900) 158 * */ 159 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 160 161 #define rFPGA1_TxBlock 0x904 /* Useless now */ 162 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 163 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 164 #define rS0S1_PathSwitch 0x948 165 166 /* 167 * 5. PageA(0xA00) 168 * 169 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 170 #define rCCK0_System 0xa00 171 172 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 173 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 174 175 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 176 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 177 178 #define rCCK0_RxHP 0xa14 179 180 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 181 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 182 183 #define rCCK0_TxFilter1 0xa20 184 #define rCCK0_TxFilter2 0xa24 185 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 186 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 187 #define rCCK0_TRSSIReport 0xa50 188 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 189 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 190 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 191 192 /* 193 * 6. PageC(0xC00) 194 * */ 195 #define rOFDM0_LSTF 0xc00 196 197 #define rOFDM0_TRxPathEnable 0xc04 198 #define rOFDM0_TRMuxPar 0xc08 199 #define rOFDM0_TRSWIsolation 0xc0c 200 201 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 202 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 203 #define rOFDM0_XBRxAFE 0xc18 204 #define rOFDM0_XBRxIQImbalance 0xc1c 205 #define rOFDM0_XCRxAFE 0xc20 206 #define rOFDM0_XCRxIQImbalance 0xc24 207 #define rOFDM0_XDRxAFE 0xc28 208 #define rOFDM0_XDRxIQImbalance 0xc2c 209 210 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 211 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 212 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 213 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 214 215 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 216 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 217 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 218 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 219 220 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 221 #define rOFDM0_XAAGCCore2 0xc54 222 #define rOFDM0_XBAGCCore1 0xc58 223 #define rOFDM0_XBAGCCore2 0xc5c 224 #define rOFDM0_XCAGCCore1 0xc60 225 #define rOFDM0_XCAGCCore2 0xc64 226 #define rOFDM0_XDAGCCore1 0xc68 227 #define rOFDM0_XDAGCCore2 0xc6c 228 229 #define rOFDM0_AGCParameter1 0xc70 230 #define rOFDM0_AGCParameter2 0xc74 231 #define rOFDM0_AGCRSSITable 0xc78 232 #define rOFDM0_HTSTFAGC 0xc7c 233 234 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 235 #define rOFDM0_XATxAFE 0xc84 236 #define rOFDM0_XBTxIQImbalance 0xc88 237 #define rOFDM0_XBTxAFE 0xc8c 238 #define rOFDM0_XCTxIQImbalance 0xc90 239 #define rOFDM0_XCTxAFE 0xc94 240 #define rOFDM0_XDTxIQImbalance 0xc98 241 #define rOFDM0_XDTxAFE 0xc9c 242 #define rOFDM0_RxIQExtAnta 0xca0 243 244 #define rOFDM0_RxHPParameter 0xce0 245 #define rOFDM0_TxPseudoNoiseWgt 0xce4 246 #define rOFDM0_FrameSync 0xcf0 247 #define rOFDM0_DFSReport 0xcf4 248 #define rOFDM0_TxCoeff1 0xca4 249 #define rOFDM0_TxCoeff2 0xca8 250 #define rOFDM0_TxCoeff3 0xcac 251 #define rOFDM0_TxCoeff4 0xcb0 252 #define rOFDM0_TxCoeff5 0xcb4 253 #define rOFDM0_TxCoeff6 0xcb8 254 255 256 /* 257 * 7. PageD(0xD00) 258 * */ 259 #define rOFDM1_LSTF 0xd00 260 #define rOFDM1_TRxPathEnable 0xd04 261 262 #define rOFDM1_CFO 0xd08 /* No setting now */ 263 #define rOFDM1_CSI1 0xd10 264 #define rOFDM1_SBD 0xd14 265 #define rOFDM1_CSI2 0xd18 266 #define rOFDM1_CFOTracking 0xd2c 267 #define rOFDM1_TRxMesaure1 0xd34 268 #define rOFDM1_IntfDet 0xd3c 269 #define rOFDM1_PseudoNoiseStateAB 0xd50 270 #define rOFDM1_PseudoNoiseStateCD 0xd54 271 #define rOFDM1_RxPseudoNoiseWgt 0xd58 272 273 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 274 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 275 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 276 277 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 278 #define rOFDM_ShortCFOCD 0xdb0 279 #define rOFDM_LongCFOAB 0xdb4 280 #define rOFDM_LongCFOCD 0xdb8 281 #define rOFDM_TailCFOAB 0xdbc 282 #define rOFDM_TailCFOCD 0xdc0 283 #define rOFDM_PWMeasure1 0xdc4 284 #define rOFDM_PWMeasure2 0xdc8 285 #define rOFDM_BWReport 0xdcc 286 #define rOFDM_AGCReport 0xdd0 287 #define rOFDM_RxSNR 0xdd4 288 #define rOFDM_RxEVMCSI 0xdd8 289 #define rOFDM_SIGReport 0xddc 290 291 292 /* 293 * 8. PageE(0xE00) 294 * */ 295 #define rTxAGC_Rate18_06 0xe00 296 #define rTxAGC_Rate54_24 0xe04 297 #define rTxAGC_CCK_Mcs32 0xe08 298 #define rTxAGC_Mcs03_Mcs00 0xe10 299 #define rTxAGC_Mcs07_Mcs04 0xe14 300 #define rTxAGC_Mcs11_Mcs08 0xe18 301 #define rTxAGC_Mcs15_Mcs12 0xe1c 302 303 /* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */ 304 #define rRx_Wait_CCCA 0xe70 305 #define rAnapar_Ctrl_BB 0xee0 306 307 /* 308 * 7. RF Register 0x00-0x2E (RF 8256) 309 * RF-0222D 0x00-3F 310 * 311 * Zebra1 */ 312 #define RTL92SE_FPGA_VERIFY 0 313 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 314 #define rZebra1_TRxEnable1 0x1 315 #define rZebra1_TRxEnable2 0x2 316 #define rZebra1_AGC 0x4 317 #define rZebra1_ChargePump 0x5 318 /* #if (RTL92SE_FPGA_VERIFY == 1) */ 319 #define rZebra1_Channel 0x7 /* RF channel switch 320 * #else */ 321 322 /* #endif */ 323 #define rZebra1_TxGain 0x8 /* Useless now */ 324 #define rZebra1_TxLPF 0x9 325 #define rZebra1_RxLPF 0xb 326 #define rZebra1_RxHPFCorner 0xc 327 328 /* Zebra4 */ 329 #define rGlobalCtrl 0 /* Useless now */ 330 #define rRTL8256_TxLPF 19 331 #define rRTL8256_RxLPF 11 332 333 /* RTL8258 */ 334 #define rRTL8258_TxLPF 0x11 /* Useless now */ 335 #define rRTL8258_RxLPF 0x13 336 #define rRTL8258_RSSILPF 0xa 337 338 /* 339 * RL6052 Register definition 340 * */ 341 #define RF_AC 0x00 /* */ 342 343 #define RF_IQADJ_G1 0x01 /* */ 344 #define RF_IQADJ_G2 0x02 /* */ 345 #define RF_POW_TRSW 0x05 /* */ 346 347 #define RF_GAIN_RX 0x06 /* */ 348 #define RF_GAIN_TX 0x07 /* */ 349 350 #define RF_TXM_IDAC 0x08 /* */ 351 #define RF_BS_IQGEN 0x0F /* */ 352 353 #define RF_MODE1 0x10 /* */ 354 #define RF_MODE2 0x11 /* */ 355 356 #define RF_RX_AGC_HP 0x12 /* */ 357 #define RF_TX_AGC 0x13 /* */ 358 #define RF_BIAS 0x14 /* */ 359 #define RF_IPA 0x15 /* */ 360 #define RF_TXBIAS 0x16 361 #define RF_POW_ABILITY 0x17 /* */ 362 #define RF_MODE_AG 0x18 /* */ 363 #define rRfChannel 0x18 /* RF channel and BW switch */ 364 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 365 #define RF_TOP 0x19 /* */ 366 367 #define RF_RX_G1 0x1A /* */ 368 #define RF_RX_G2 0x1B /* */ 369 370 #define RF_RX_BB2 0x1C /* */ 371 #define RF_RX_BB1 0x1D /* */ 372 373 #define RF_RCK1 0x1E /* */ 374 #define RF_RCK2 0x1F /* */ 375 376 #define RF_TX_G1 0x20 /* */ 377 #define RF_TX_G2 0x21 /* */ 378 #define RF_TX_G3 0x22 /* */ 379 380 #define RF_TX_BB1 0x23 /* */ 381 382 #define RF_T_METER 0x24 /* */ 383 384 #define RF_SYN_G1 0x25 /* RF TX Power control */ 385 #define RF_SYN_G2 0x26 /* RF TX Power control */ 386 #define RF_SYN_G3 0x27 /* RF TX Power control */ 387 #define RF_SYN_G4 0x28 /* RF TX Power control */ 388 #define RF_SYN_G5 0x29 /* RF TX Power control */ 389 #define RF_SYN_G6 0x2A /* RF TX Power control */ 390 #define RF_SYN_G7 0x2B /* RF TX Power control */ 391 #define RF_SYN_G8 0x2C /* RF TX Power control */ 392 393 #define RF_RCK_OS 0x30 /* RF TX PA control */ 394 395 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 396 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 397 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 398 399 /* 400 * Bit Mask 401 * 402 * 1. Page1(0x100) */ 403 #define bBBResetB 0x100 /* Useless now? */ 404 #define bGlobalResetB 0x200 405 #define bOFDMTxStart 0x4 406 #define bCCKTxStart 0x8 407 #define bCRC32Debug 0x100 408 #define bPMACLoopback 0x10 409 #define bTxLSIG 0xffffff 410 #define bOFDMTxRate 0xf 411 #define bOFDMTxReserved 0x10 412 #define bOFDMTxLength 0x1ffe0 413 #define bOFDMTxParity 0x20000 414 #define bTxHTSIG1 0xffffff 415 #define bTxHTMCSRate 0x7f 416 #define bTxHTBW 0x80 417 #define bTxHTLength 0xffff00 418 #define bTxHTSIG2 0xffffff 419 #define bTxHTSmoothing 0x1 420 #define bTxHTSounding 0x2 421 #define bTxHTReserved 0x4 422 #define bTxHTAggreation 0x8 423 #define bTxHTSTBC 0x30 424 #define bTxHTAdvanceCoding 0x40 425 #define bTxHTShortGI 0x80 426 #define bTxHTNumberHT_LTF 0x300 427 #define bTxHTCRC8 0x3fc00 428 #define bCounterReset 0x10000 429 #define bNumOfOFDMTx 0xffff 430 #define bNumOfCCKTx 0xffff0000 431 #define bTxIdleInterval 0xffff 432 #define bOFDMService 0xffff0000 433 #define bTxMACHeader 0xffffffff 434 #define bTxDataInit 0xff 435 #define bTxHTMode 0x100 436 #define bTxDataType 0x30000 437 #define bTxRandomSeed 0xffffffff 438 #define bCCKTxPreamble 0x1 439 #define bCCKTxSFD 0xffff0000 440 #define bCCKTxSIG 0xff 441 #define bCCKTxService 0xff00 442 #define bCCKLengthExt 0x8000 443 #define bCCKTxLength 0xffff0000 444 #define bCCKTxCRC16 0xffff 445 #define bCCKTxStatus 0x1 446 #define bOFDMTxStatus 0x2 447 448 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 449 450 /* 2. Page8(0x800) */ 451 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 452 #define bJapanMode 0x2 453 #define bCCKTxSC 0x30 454 #define bCCKEn 0x1000000 455 #define bOFDMEn 0x2000000 456 457 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 458 #define bOFDMTxDACPhase 0x40000 459 #define bXATxAGC 0x3f 460 461 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 462 #define bXCTxAGC 0xf000 463 #define bXDTxAGC 0xf0000 464 465 #define bPAStart 0xf0000000 /* Useless now */ 466 #define bTRStart 0x00f00000 467 #define bRFStart 0x0000f000 468 #define bBBStart 0x000000f0 469 #define bBBCCKStart 0x0000000f 470 #define bPAEnd 0xf /* Reg0x814 */ 471 #define bTREnd 0x0f000000 472 #define bRFEnd 0x000f0000 473 #define bCCAMask 0x000000f0 /* T2R */ 474 #define bR2RCCAMask 0x00000f00 475 #define bHSSI_R2TDelay 0xf8000000 476 #define bHSSI_T2RDelay 0xf80000 477 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 478 #define bIGFromCCK 0x200 479 #define bAGCAddress 0x3f 480 #define bRxHPTx 0x7000 481 #define bRxHPT2R 0x38000 482 #define bRxHPCCKIni 0xc0000 483 #define bAGCTxCode 0xc00000 484 #define bAGCRxCode 0x300000 485 486 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 487 #define b3WireAddressLength 0x400 488 489 #define b3WireRFPowerDown 0x1 /* Useless now 490 * #define bHWSISelect 0x8 */ 491 #define b5GPAPEPolarity 0x40000000 492 #define b2GPAPEPolarity 0x80000000 493 #define bRFSW_TxDefaultAnt 0x3 494 #define bRFSW_TxOptionAnt 0x30 495 #define bRFSW_RxDefaultAnt 0x300 496 #define bRFSW_RxOptionAnt 0x3000 497 #define bRFSI_3WireData 0x1 498 #define bRFSI_3WireClock 0x2 499 #define bRFSI_3WireLoad 0x4 500 #define bRFSI_3WireRW 0x8 501 #define bRFSI_3Wire 0xf 502 503 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 504 505 #define bRFSI_TRSW 0x20 /* Useless now */ 506 #define bRFSI_TRSWB 0x40 507 #define bRFSI_ANTSW 0x100 508 #define bRFSI_ANTSWB 0x200 509 #define bRFSI_PAPE 0x400 510 #define bRFSI_PAPE5G 0x800 511 #define bBandSelect 0x1 512 #define bHTSIG2_GI 0x80 513 #define bHTSIG2_Smoothing 0x01 514 #define bHTSIG2_Sounding 0x02 515 #define bHTSIG2_Aggreaton 0x08 516 #define bHTSIG2_STBC 0x30 517 #define bHTSIG2_AdvCoding 0x40 518 #define bHTSIG2_NumOfHTLTF 0x300 519 #define bHTSIG2_CRC8 0x3fc 520 #define bHTSIG1_MCS 0x7f 521 #define bHTSIG1_BandWidth 0x80 522 #define bHTSIG1_HTLength 0xffff 523 #define bLSIG_Rate 0xf 524 #define bLSIG_Reserved 0x10 525 #define bLSIG_Length 0x1fffe 526 #define bLSIG_Parity 0x20 527 #define bCCKRxPhase 0x4 528 #if (RTL92SE_FPGA_VERIFY == 1) 529 #define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */ /* Reg 0x824 rFPGA0_XA_HSSIParameter2 */ 530 #else 531 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 532 #endif 533 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 534 #if (RTL92SE_FPGA_VERIFY == 1) 535 #define bLSSIReadBackData 0xfff /* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */ 536 #else 537 #define bLSSIReadBackData 0xfffff /* T65 RF */ 538 #endif 539 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 540 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 541 #define bRegulator0Standby 0x1 542 #define bRegulatorPLLStandby 0x2 543 #define bRegulator1Standby 0x4 544 #define bPLLPowerUp 0x8 545 #define bDPLLPowerUp 0x10 546 #define bDA10PowerUp 0x20 547 #define bAD7PowerUp 0x200 548 #define bDA6PowerUp 0x2000 549 #define bXtalPowerUp 0x4000 550 #define b40MDClkPowerUP 0x8000 551 #define bDA6DebugMode 0x20000 552 #define bDA6Swing 0x380000 553 554 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 555 556 #define b80MClkDelay 0x18000000 /* Useless */ 557 #define bAFEWatchDogEnable 0x20000000 558 559 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 560 #define bXtalCap23 0x3 561 #define bXtalCap92x 0x0f000000 562 #define bXtalCap 0x0f000000 563 564 #define bIntDifClkEnable 0x400 /* Useless */ 565 #define bExtSigClkEnable 0x800 566 #define bBandgapMbiasPowerUp 0x10000 567 #define bAD11SHGain 0xc0000 568 #define bAD11InputRange 0x700000 569 #define bAD11OPCurrent 0x3800000 570 #define bIPathLoopback 0x4000000 571 #define bQPathLoopback 0x8000000 572 #define bAFELoopback 0x10000000 573 #define bDA10Swing 0x7e0 574 #define bDA10Reverse 0x800 575 #define bDAClkSource 0x1000 576 #define bAD7InputRange 0x6000 577 #define bAD7Gain 0x38000 578 #define bAD7OutputCMMode 0x40000 579 #define bAD7InputCMMode 0x380000 580 #define bAD7Current 0xc00000 581 #define bRegulatorAdjust 0x7000000 582 #define bAD11PowerUpAtTx 0x1 583 #define bDA10PSAtTx 0x10 584 #define bAD11PowerUpAtRx 0x100 585 #define bDA10PSAtRx 0x1000 586 #define bCCKRxAGCFormat 0x200 587 #define bPSDFFTSamplepPoint 0xc000 588 #define bPSDAverageNum 0x3000 589 #define bIQPathControl 0xc00 590 #define bPSDFreq 0x3ff 591 #define bPSDAntennaPath 0x30 592 #define bPSDIQSwitch 0x40 593 #define bPSDRxTrigger 0x400000 594 #define bPSDTxTrigger 0x80000000 595 #define bPSDSineToneScale 0x7f000000 596 #define bPSDReport 0xffff 597 598 /* 3. Page9(0x900) */ 599 #define bOFDMTxSC 0x30000000 /* Useless */ 600 #define bCCKTxOn 0x1 601 #define bOFDMTxOn 0x2 602 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 603 #define bDebugItem 0xff /* reset debug page and LWord */ 604 #define bAntL 0x10 605 #define bAntNonHT 0x100 606 #define bAntHT1 0x1000 607 #define bAntHT2 0x10000 608 #define bAntHT1S1 0x100000 609 #define bAntNonHTS1 0x1000000 610 611 /* 4. PageA(0xA00) */ 612 #define bCCKBBMode 0x3 /* Useless */ 613 #define bCCKTxPowerSaving 0x80 614 #define bCCKRxPowerSaving 0x40 615 616 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 617 618 #define bCCKScramble 0x8 /* Useless */ 619 #define bCCKAntDiversity 0x8000 620 #define bCCKCarrierRecovery 0x4000 621 #define bCCKTxRate 0x3000 622 #define bCCKDCCancel 0x0800 623 #define bCCKISICancel 0x0400 624 #define bCCKMatchFilter 0x0200 625 #define bCCKEqualizer 0x0100 626 #define bCCKPreambleDetect 0x800000 627 #define bCCKFastFalseCCA 0x400000 628 #define bCCKChEstStart 0x300000 629 #define bCCKCCACount 0x080000 630 #define bCCKcs_lim 0x070000 631 #define bCCKBistMode 0x80000000 632 #define bCCKCCAMask 0x40000000 633 #define bCCKTxDACPhase 0x4 634 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 635 #define bCCKr_cp_mode0 0x0100 636 #define bCCKTxDCOffset 0xf0 637 #define bCCKRxDCOffset 0xf 638 #define bCCKCCAMode 0xc000 639 #define bCCKFalseCS_lim 0x3f00 640 #define bCCKCS_ratio 0xc00000 641 #define bCCKCorgBit_sel 0x300000 642 #define bCCKPD_lim 0x0f0000 643 #define bCCKNewCCA 0x80000000 644 #define bCCKRxHPofIG 0x8000 645 #define bCCKRxIG 0x7f00 646 #define bCCKLNAPolarity 0x800000 647 #define bCCKRx1stGain 0x7f0000 648 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 649 #define bCCKRxAGCSatLevel 0x1f000000 650 #define bCCKRxAGCSatCount 0xe0 651 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 652 #define bCCKFixedRxAGC 0x8000 653 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 654 #define bCCKAntennaPolarity 0x2000 655 #define bCCKTxFilterType 0x0c00 656 #define bCCKRxAGCReportType 0x0300 657 #define bCCKRxDAGCEn 0x80000000 658 #define bCCKRxDAGCPeriod 0x20000000 659 #define bCCKRxDAGCSatLevel 0x1f000000 660 #define bCCKTimingRecovery 0x800000 661 #define bCCKTxC0 0x3f0000 662 #define bCCKTxC1 0x3f000000 663 #define bCCKTxC2 0x3f 664 #define bCCKTxC3 0x3f00 665 #define bCCKTxC4 0x3f0000 666 #define bCCKTxC5 0x3f000000 667 #define bCCKTxC6 0x3f 668 #define bCCKTxC7 0x3f00 669 #define bCCKDebugPort 0xff0000 670 #define bCCKDACDebug 0x0f000000 671 #define bCCKFalseAlarmEnable 0x8000 672 #define bCCKFalseAlarmRead 0x4000 673 #define bCCKTRSSI 0x7f 674 #define bCCKRxAGCReport 0xfe 675 #define bCCKRxReport_AntSel 0x80000000 676 #define bCCKRxReport_MFOff 0x40000000 677 #define bCCKRxRxReport_SQLoss 0x20000000 678 #define bCCKRxReport_Pktloss 0x10000000 679 #define bCCKRxReport_Lockedbit 0x08000000 680 #define bCCKRxReport_RateError 0x04000000 681 #define bCCKRxReport_RxRate 0x03000000 682 #define bCCKRxFACounterLower 0xff 683 #define bCCKRxFACounterUpper 0xff000000 684 #define bCCKRxHPAGCStart 0xe000 685 #define bCCKRxHPAGCFinal 0x1c00 686 #define bCCKRxFalseAlarmEnable 0x8000 687 #define bCCKFACounterFreeze 0x4000 688 #define bCCKTxPathSel 0x10000000 689 #define bCCKDefaultRxPath 0xc000000 690 #define bCCKOptionRxPath 0x3000000 691 692 /* 5. PageC(0xC00) */ 693 #define bNumOfSTF 0x3 /* Useless */ 694 #define bShift_L 0xc0 695 #define bGI_TH 0xc 696 #define bRxPathA 0x1 697 #define bRxPathB 0x2 698 #define bRxPathC 0x4 699 #define bRxPathD 0x8 700 #define bTxPathA 0x1 701 #define bTxPathB 0x2 702 #define bTxPathC 0x4 703 #define bTxPathD 0x8 704 #define bTRSSIFreq 0x200 705 #define bADCBackoff 0x3000 706 #define bDFIRBackoff 0xc000 707 #define bTRSSILatchPhase 0x10000 708 #define bRxIDCOffset 0xff 709 #define bRxQDCOffset 0xff00 710 #define bRxDFIRMode 0x1800000 711 #define bRxDCNFType 0xe000000 712 #define bRXIQImb_A 0x3ff 713 #define bRXIQImb_B 0xfc00 714 #define bRXIQImb_C 0x3f0000 715 #define bRXIQImb_D 0xffc00000 716 #define bDC_dc_Notch 0x60000 717 #define bRxNBINotch 0x1f000000 718 #define bPD_TH 0xf 719 #define bPD_TH_Opt2 0xc000 720 #define bPWED_TH 0x700 721 #define bIfMF_Win_L 0x800 722 #define bPD_Option 0x1000 723 #define bMF_Win_L 0xe000 724 #define bBW_Search_L 0x30000 725 #define bwin_enh_L 0xc0000 726 #define bBW_TH 0x700000 727 #define bED_TH2 0x3800000 728 #define bBW_option 0x4000000 729 #define bRatio_TH 0x18000000 730 #define bWindow_L 0xe0000000 731 #define bSBD_Option 0x1 732 #define bFrame_TH 0x1c 733 #define bFS_Option 0x60 734 #define bDC_Slope_check 0x80 735 #define bFGuard_Counter_DC_L 0xe00 736 #define bFrame_Weight_Short 0x7000 737 #define bSub_Tune 0xe00000 738 #define bFrame_DC_Length 0xe000000 739 #define bSBD_start_offset 0x30000000 740 #define bFrame_TH_2 0x7 741 #define bFrame_GI2_TH 0x38 742 #define bGI2_Sync_en 0x40 743 #define bSarch_Short_Early 0x300 744 #define bSarch_Short_Late 0xc00 745 #define bSarch_GI2_Late 0x70000 746 #define bCFOAntSum 0x1 747 #define bCFOAcc 0x2 748 #define bCFOStartOffset 0xc 749 #define bCFOLookBack 0x70 750 #define bCFOSumWeight 0x80 751 #define bDAGCEnable 0x10000 752 #define bTXIQImb_A 0x3ff 753 #define bTXIQImb_B 0xfc00 754 #define bTXIQImb_C 0x3f0000 755 #define bTXIQImb_D 0xffc00000 756 #define bTxIDCOffset 0xff 757 #define bTxQDCOffset 0xff00 758 #define bTxDFIRMode 0x10000 759 #define bTxPesudoNoiseOn 0x4000000 760 #define bTxPesudoNoise_A 0xff 761 #define bTxPesudoNoise_B 0xff00 762 #define bTxPesudoNoise_C 0xff0000 763 #define bTxPesudoNoise_D 0xff000000 764 #define bCCADropOption 0x20000 765 #define bCCADropThres 0xfff00000 766 #define bEDCCA_H 0xf 767 #define bEDCCA_L 0xf0 768 #define bLambda_ED 0x300 769 #define bRxInitialGain 0x7f 770 #define bRxAntDivEn 0x80 771 #define bRxAGCAddressForLNA 0x7f00 772 #define bRxHighPowerFlow 0x8000 773 #define bRxAGCFreezeThres 0xc0000 774 #define bRxFreezeStep_AGC1 0x300000 775 #define bRxFreezeStep_AGC2 0xc00000 776 #define bRxFreezeStep_AGC3 0x3000000 777 #define bRxFreezeStep_AGC0 0xc000000 778 #define bRxRssi_Cmp_En 0x10000000 779 #define bRxQuickAGCEn 0x20000000 780 #define bRxAGCFreezeThresMode 0x40000000 781 #define bRxOverFlowCheckType 0x80000000 782 #define bRxAGCShift 0x7f 783 #define bTRSW_Tri_Only 0x80 784 #define bPowerThres 0x300 785 #define bRxAGCEn 0x1 786 #define bRxAGCTogetherEn 0x2 787 #define bRxAGCMin 0x4 788 #define bRxHP_Ini 0x7 789 #define bRxHP_TRLNA 0x70 790 #define bRxHP_RSSI 0x700 791 #define bRxHP_BBP1 0x7000 792 #define bRxHP_BBP2 0x70000 793 #define bRxHP_BBP3 0x700000 794 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 795 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 796 #define bRxSettle_TRSW 0x7 797 #define bRxSettle_LNA 0x38 798 #define bRxSettle_RSSI 0x1c0 799 #define bRxSettle_BBP 0xe00 800 #define bRxSettle_RxHP 0x7000 801 #define bRxSettle_AntSW_RSSI 0x38000 802 #define bRxSettle_AntSW 0xc0000 803 #define bRxProcessTime_DAGC 0x300000 804 #define bRxSettle_HSSI 0x400000 805 #define bRxProcessTime_BBPPW 0x800000 806 #define bRxAntennaPowerShift 0x3000000 807 #define bRSSITableSelect 0xc000000 808 #define bRxHP_Final 0x7000000 809 #define bRxHTSettle_BBP 0x7 810 #define bRxHTSettle_HSSI 0x8 811 #define bRxHTSettle_RxHP 0x70 812 #define bRxHTSettle_BBPPW 0x80 813 #define bRxHTSettle_Idle 0x300 814 #define bRxHTSettle_Reserved 0x1c00 815 #define bRxHTRxHPEn 0x8000 816 #define bRxHTAGCFreezeThres 0x30000 817 #define bRxHTAGCTogetherEn 0x40000 818 #define bRxHTAGCMin 0x80000 819 #define bRxHTAGCEn 0x100000 820 #define bRxHTDAGCEn 0x200000 821 #define bRxHTRxHP_BBP 0x1c00000 822 #define bRxHTRxHP_Final 0xe0000000 823 #define bRxPWRatioTH 0x3 824 #define bRxPWRatioEn 0x4 825 #define bRxMFHold 0x3800 826 #define bRxPD_Delay_TH1 0x38 827 #define bRxPD_Delay_TH2 0x1c0 828 #define bRxPD_DC_COUNT_MAX 0x600 829 /* #define bRxMF_Hold 0x3800 */ 830 #define bRxPD_Delay_TH 0x8000 831 #define bRxProcess_Delay 0xf0000 832 #define bRxSearchrange_GI2_Early 0x700000 833 #define bRxFrame_Guard_Counter_L 0x3800000 834 #define bRxSGI_Guard_L 0xc000000 835 #define bRxSGI_Search_L 0x30000000 836 #define bRxSGI_TH 0xc0000000 837 #define bDFSCnt0 0xff 838 #define bDFSCnt1 0xff00 839 #define bDFSFlag 0xf0000 840 #define bMFWeightSum 0x300000 841 #define bMinIdxTH 0x7f000000 842 #define bDAFormat 0x40000 843 #define bTxChEmuEnable 0x01000000 844 #define bTRSWIsolation_A 0x7f 845 #define bTRSWIsolation_B 0x7f00 846 #define bTRSWIsolation_C 0x7f0000 847 #define bTRSWIsolation_D 0x7f000000 848 #define bExtLNAGain 0x7c00 849 850 /* 6. PageE(0xE00) */ 851 #define bSTBCEn 0x4 /* Useless */ 852 #define bAntennaMapping 0x10 853 #define bNss 0x20 854 #define bCFOAntSumD 0x200 855 #define bPHYCounterReset 0x8000000 856 #define bCFOReportGet 0x4000000 857 #define bOFDMContinueTx 0x10000000 858 #define bOFDMSingleCarrier 0x20000000 859 #define bOFDMSingleTone 0x40000000 860 /* #define bRxPath1 0x01 */ 861 /* #define bRxPath2 0x02 */ 862 /* #define bRxPath3 0x04 */ 863 /* #define bRxPath4 0x08 */ 864 /* #define bTxPath1 0x10 */ 865 /* #define bTxPath2 0x20 */ 866 #define bHTDetect 0x100 867 #define bCFOEn 0x10000 868 #define bCFOValue 0xfff00000 869 #define bSigTone_Re 0x3f 870 #define bSigTone_Im 0x7f00 871 #define bCounter_CCA 0xffff 872 #define bCounter_ParityFail 0xffff0000 873 #define bCounter_RateIllegal 0xffff 874 #define bCounter_CRC8Fail 0xffff0000 875 #define bCounter_MCSNoSupport 0xffff 876 #define bCounter_FastSync 0xffff 877 #define bShortCFO 0xfff 878 #define bShortCFOTLength 12 /* total */ 879 #define bShortCFOFLength 11 /* fraction */ 880 #define bLongCFO 0x7ff 881 #define bLongCFOTLength 11 882 #define bLongCFOFLength 11 883 #define bTailCFO 0x1fff 884 #define bTailCFOTLength 13 885 #define bTailCFOFLength 12 886 #define bmax_en_pwdB 0xffff 887 #define bCC_power_dB 0xffff0000 888 #define bnoise_pwdB 0xffff 889 #define bPowerMeasTLength 10 890 #define bPowerMeasFLength 3 891 #define bRx_HT_BW 0x1 892 #define bRxSC 0x6 893 #define bRx_HT 0x8 894 #define bNB_intf_det_on 0x1 895 #define bIntf_win_len_cfg 0x30 896 #define bNB_Intf_TH_cfg 0x1c0 897 #define bRFGain 0x3f 898 #define bTableSel 0x40 899 #define bTRSW 0x80 900 #define bRxSNR_A 0xff 901 #define bRxSNR_B 0xff00 902 #define bRxSNR_C 0xff0000 903 #define bRxSNR_D 0xff000000 904 #define bSNREVMTLength 8 905 #define bSNREVMFLength 1 906 #define bCSI1st 0xff 907 #define bCSI2nd 0xff00 908 #define bRxEVM1st 0xff0000 909 #define bRxEVM2nd 0xff000000 910 #define bSIGEVM 0xff 911 #define bPWDB 0xff00 912 #define bSGIEN 0x10000 913 914 #define bSFactorQAM1 0xf /* Useless */ 915 #define bSFactorQAM2 0xf0 916 #define bSFactorQAM3 0xf00 917 #define bSFactorQAM4 0xf000 918 #define bSFactorQAM5 0xf0000 919 #define bSFactorQAM6 0xf0000 920 #define bSFactorQAM7 0xf00000 921 #define bSFactorQAM8 0xf000000 922 #define bSFactorQAM9 0xf0000000 923 #define bCSIScheme 0x100000 924 925 #define bNoiseLvlTopSet 0x3 /* Useless */ 926 #define bChSmooth 0x4 927 #define bChSmoothCfg1 0x38 928 #define bChSmoothCfg2 0x1c0 929 #define bChSmoothCfg3 0xe00 930 #define bChSmoothCfg4 0x7000 931 #define bMRCMode 0x800000 932 #define bTHEVMCfg 0x7000000 933 934 #define bLoopFitType 0x1 /* Useless */ 935 #define bUpdCFO 0x40 936 #define bUpdCFOOffData 0x80 937 #define bAdvUpdCFO 0x100 938 #define bAdvTimeCtrl 0x800 939 #define bUpdClko 0x1000 940 #define bFC 0x6000 941 #define bTrackingMode 0x8000 942 #define bPhCmpEnable 0x10000 943 #define bUpdClkoLTF 0x20000 944 #define bComChCFO 0x40000 945 #define bCSIEstiMode 0x80000 946 #define bAdvUpdEqz 0x100000 947 #define bUChCfg 0x7000000 948 #define bUpdEqz 0x8000000 949 950 #define bTxAGCRate18_06 0x7f7f7f7f /* Useless */ 951 #define bTxAGCRate54_24 0x7f7f7f7f 952 #define bTxAGCRateMCS32 0x7f 953 #define bTxAGCRateCCK 0x7f00 954 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 955 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 956 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 957 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 958 959 /* Rx Pseduo noise */ 960 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 961 #define bRxPesudoNoise_A 0xff 962 #define bRxPesudoNoise_B 0xff00 963 #define bRxPesudoNoise_C 0xff0000 964 #define bRxPesudoNoise_D 0xff000000 965 #define bPesudoNoiseState_A 0xffff 966 #define bPesudoNoiseState_B 0xffff0000 967 #define bPesudoNoiseState_C 0xffff 968 #define bPesudoNoiseState_D 0xffff0000 969 970 /* 7. RF Register 971 * Zebra1 */ 972 #define bZebra1_HSSIEnable 0x8 /* Useless */ 973 #define bZebra1_TRxControl 0xc00 974 #define bZebra1_TRxGainSetting 0x07f 975 #define bZebra1_RxCorner 0xc00 976 #define bZebra1_TxChargePump 0x38 977 #define bZebra1_RxChargePump 0x7 978 #define bZebra1_ChannelNum 0xf80 979 #define bZebra1_TxLPFBW 0x400 980 #define bZebra1_RxLPFBW 0x600 981 982 /* Zebra4 */ 983 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 984 #define bRTL8256RegModeCtrl0 0x40 985 #define bRTL8256_TxLPFBW 0x18 986 #define bRTL8256_RxLPFBW 0x600 987 988 /* RTL8258 */ 989 #define bRTL8258_TxLPFBW 0xc /* Useless */ 990 #define bRTL8258_RxLPFBW 0xc00 991 #define bRTL8258_RSSILPFBW 0xc0 992 993 994 /* 995 * Other Definition 996 * */ 997 998 /* byte endable for sb_write */ 999 #define bByte0 0x1 /* Useless */ 1000 #define bByte1 0x2 1001 #define bByte2 0x4 1002 #define bByte3 0x8 1003 #define bWord0 0x3 1004 #define bWord1 0xc 1005 #define bDWord 0xf 1006 1007 /* for PutRegsetting & GetRegSetting BitMask */ 1008 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1009 #define bMaskByte1 0xff00 1010 #define bMaskByte2 0xff0000 1011 #define bMaskByte3 0xff000000 1012 #define bMaskHWord 0xffff0000 1013 #define bMaskLWord 0x0000ffff 1014 #define bMaskDWord 0xffffffff 1015 #define bMaskH4Bits 0xf0000000 1016 #define bMaskH3Bytes 0xffffff00 1017 #define bMaskOFDM_D 0xffc00000 1018 #define bMaskCCK 0x3f3f3f3f 1019 #define bMask12Bits 0xfff 1020 1021 /* for PutRFRegsetting & GetRFRegSetting BitMask */ 1022 #if (RTL92SE_FPGA_VERIFY == 1) 1023 /* #define bMask12Bits 0xfff */ /* RF Reg mask bits */ 1024 /* #define bMask20Bits 0xfff */ /* RF Reg mask bits T65 RF */ 1025 #define bRFRegOffsetMask 0xfff 1026 #else 1027 /* #define bMask12Bits 0xfffff */ /* RF Reg mask bits */ 1028 /* #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ 1029 #define bRFRegOffsetMask 0xfffff 1030 #endif 1031 #define bEnable 0x1 /* Useless */ 1032 #define bDisable 0x0 1033 1034 #define LeftAntenna 0x0 /* Useless */ 1035 #define RightAntenna 0x1 1036 1037 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1038 #define tUpdateRxCounter 100 /* 100ms */ 1039 1040 #define rateCCK 0 /* Useless */ 1041 #define rateOFDM 1 1042 #define rateHT 2 1043 1044 /* define Register-End */ 1045 #define bPMAC_End 0x1ff /* Useless */ 1046 #define bFPGAPHY0_End 0x8ff 1047 #define bFPGAPHY1_End 0x9ff 1048 #define bCCKPHY0_End 0xaff 1049 #define bOFDMPHY0_End 0xcff 1050 #define bOFDMPHY1_End 0xdff 1051 1052 /* define max debug item in each debug page 1053 * #define bMaxItem_FPGA_PHY0 0x9 1054 * #define bMaxItem_FPGA_PHY1 0x3 1055 * #define bMaxItem_PHY_11B 0x16 1056 * #define bMaxItem_OFDM_PHY0 0x29 1057 * #define bMaxItem_OFDM_PHY1 0x0 */ 1058 1059 #define bPMACControl 0x0 /* Useless */ 1060 #define bWMACControl 0x1 1061 #define bWNICControl 0x2 1062 1063 #if 0 1064 #define ANTENNA_A 0x1 /* Useless */ 1065 #define ANTENNA_B 0x2 1066 #define ANTENNA_AB 0x3 /* ANTENNA_A | ANTENNA_B */ 1067 1068 #define ANTENNA_C 0x4 1069 #define ANTENNA_D 0x8 1070 #endif 1071 1072 #define RCR_AAP BIT(0) /* accept all physical address */ 1073 #define RCR_APM BIT(1) /* accept physical match */ 1074 #define RCR_AM BIT(2) /* accept multicast */ 1075 #define RCR_AB BIT(3) /* accept broadcast */ 1076 #define RCR_ACRC32 BIT(5) /* accept error packet */ 1077 #define RCR_9356SEL BIT(6) 1078 #define RCR_AICV BIT(9) /* Accept ICV error packet */ 1079 #define RCR_RXFTH0 (BIT(13) | BIT(14) | BIT(15)) /* Rx FIFO threshold */ 1080 #define RCR_ADF BIT(18) /* Accept Data(frame type) frame */ 1081 #define RCR_ACF BIT(19) /* Accept control frame */ 1082 #define RCR_AMF BIT(20) /* Accept management frame */ 1083 #define RCR_ADD3 BIT(21) 1084 #define RCR_APWRMGT BIT(22) /* Accept power management packet */ 1085 #define RCR_CBSSID BIT(23) /* Accept BSSID match packet */ 1086 #define RCR_ENMARP BIT(28) /* enable mac auto reset phy */ 1087 #define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */ 1088 #define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */ 1089 #define RCR_OnlyErlPkt BIT(31) /* Rx Early mode is performed for packet size greater than 1536 */ 1090 1091 /*--------------------------Define Parameters-------------------------------*/ 1092 1093 1094 #endif /* __INC_HAL8192SPHYREG_H */ 1095