1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8723BPHYREG_H__ 16 #define __INC_HAL8723BPHYREG_H__ 17 18 #define rSYM_WLBT_PAPE_SEL 0x64 19 /* 20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 21 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 23 * 3. RF register 0x00-2E 24 * 4. Bit Mask for BB/RF register 25 * 5. Other defintion for BB/RF R/W 26 * */ 27 28 29 /* 30 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 31 * 1. Page1(0x100) 32 * */ 33 #define rPMAC_Reset 0x100 34 #define rPMAC_TxStart 0x104 35 #define rPMAC_TxLegacySIG 0x108 36 #define rPMAC_TxHTSIG1 0x10c 37 #define rPMAC_TxHTSIG2 0x110 38 #define rPMAC_PHYDebug 0x114 39 #define rPMAC_TxPacketNum 0x118 40 #define rPMAC_TxIdle 0x11c 41 #define rPMAC_TxMACHeader0 0x120 42 #define rPMAC_TxMACHeader1 0x124 43 #define rPMAC_TxMACHeader2 0x128 44 #define rPMAC_TxMACHeader3 0x12c 45 #define rPMAC_TxMACHeader4 0x130 46 #define rPMAC_TxMACHeader5 0x134 47 #define rPMAC_TxDataType 0x138 48 #define rPMAC_TxRandomSeed 0x13c 49 #define rPMAC_CCKPLCPPreamble 0x140 50 #define rPMAC_CCKPLCPHeader 0x144 51 #define rPMAC_CCKCRC16 0x148 52 #define rPMAC_OFDMRxCRC32OK 0x170 53 #define rPMAC_OFDMRxCRC32Er 0x174 54 #define rPMAC_OFDMRxParityEr 0x178 55 #define rPMAC_OFDMRxCRC8Er 0x17c 56 #define rPMAC_CCKCRxRC16Er 0x180 57 #define rPMAC_CCKCRxRC32Er 0x184 58 #define rPMAC_CCKCRxRC32OK 0x188 59 #define rPMAC_TxStatus 0x18c 60 61 /* 62 * 2. Page2(0x200) 63 * 64 * The following two definition are only used for USB interface. */ 65 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 66 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 67 68 /* 69 * 3. Page8(0x800) 70 * */ 71 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 72 73 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 74 #define rFPGA0_PSDFunction 0x808 75 76 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 77 78 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 79 #define rFPGA0_RFTiming2 0x814 80 81 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 82 #define rFPGA0_XA_HSSIParameter2 0x824 83 #define rFPGA0_XB_HSSIParameter1 0x828 84 #define rFPGA0_XB_HSSIParameter2 0x82c 85 #define rTxAGC_B_Rate18_06 0x830 86 #define rTxAGC_B_Rate54_24 0x834 87 #define rTxAGC_B_CCK1_55_Mcs32 0x838 88 #define rTxAGC_B_Mcs03_Mcs00 0x83c 89 90 #define rTxAGC_B_Mcs07_Mcs04 0x848 91 #define rTxAGC_B_Mcs11_Mcs08 0x84c 92 93 #define rFPGA0_XA_LSSIParameter 0x840 94 #define rFPGA0_XB_LSSIParameter 0x844 95 96 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 97 #define rFPGA0_RFSleepUpParameter 0x854 98 99 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 100 #define rFPGA0_XCD_SwitchControl 0x85c 101 102 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 103 #define rFPGA0_XB_RFInterfaceOE 0x864 104 105 #define rTxAGC_B_Mcs15_Mcs12 0x868 106 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 107 108 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 109 #define rFPGA0_XCD_RFInterfaceSW 0x874 110 111 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 112 #define rFPGA0_XCD_RFParameter 0x87c 113 114 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 115 #define rFPGA0_AnalogParameter2 0x884 116 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 117 #define rFPGA0_AnalogParameter4 0x88c 118 119 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 120 #define rFPGA0_XB_LSSIReadBack 0x8a4 121 #define rFPGA0_XC_LSSIReadBack 0x8a8 122 #define rFPGA0_XD_LSSIReadBack 0x8ac 123 124 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 125 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 126 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 127 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 128 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 129 130 /* 131 * 4. Page9(0x900) 132 * */ 133 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 134 #define rFPGA1_TxBlock 0x904 /* Useless now */ 135 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 136 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 137 #define rDPDT_control 0x92c 138 #define rfe_ctrl_anta_src 0x930 139 #define rS0S1_PathSwitch 0x948 140 141 /* 142 * 5. PageA(0xA00) 143 * 144 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 145 #define rCCK0_System 0xa00 146 147 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 148 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 149 150 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 151 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 152 153 #define rCCK0_RxHP 0xa14 154 155 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 156 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 157 158 #define rCCK0_TxFilter1 0xa20 159 #define rCCK0_TxFilter2 0xa24 160 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 161 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 162 #define rCCK0_TRSSIReport 0xa50 163 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 164 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 165 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 166 167 /* 168 * PageB(0xB00) 169 * */ 170 #define rPdp_AntA 0xb00 171 #define rPdp_AntA_4 0xb04 172 #define rPdp_AntA_8 0xb08 173 #define rPdp_AntA_C 0xb0c 174 #define rPdp_AntA_10 0xb10 175 #define rPdp_AntA_14 0xb14 176 #define rPdp_AntA_18 0xb18 177 #define rPdp_AntA_1C 0xb1c 178 #define rPdp_AntA_20 0xb20 179 #define rPdp_AntA_24 0xb24 180 181 #define rConfig_Pmpd_AntA 0xb28 182 #define rConfig_ram64x16 0xb2c 183 184 #define rBndA 0xb30 185 #define rHssiPar 0xb34 186 187 #define rConfig_AntA 0xb68 188 #define rConfig_AntB 0xb6c 189 190 #define rPdp_AntB 0xb70 191 #define rPdp_AntB_4 0xb74 192 #define rPdp_AntB_8 0xb78 193 #define rPdp_AntB_C 0xb7c 194 #define rPdp_AntB_10 0xb80 195 #define rPdp_AntB_14 0xb84 196 #define rPdp_AntB_18 0xb88 197 #define rPdp_AntB_1C 0xb8c 198 #define rPdp_AntB_20 0xb90 199 #define rPdp_AntB_24 0xb94 200 201 #define rConfig_Pmpd_AntB 0xb98 202 203 #define rBndB 0xba0 204 205 #define rAPK 0xbd8 206 #define rPm_Rx0_AntA 0xbdc 207 #define rPm_Rx1_AntA 0xbe0 208 #define rPm_Rx2_AntA 0xbe4 209 #define rPm_Rx3_AntA 0xbe8 210 #define rPm_Rx0_AntB 0xbec 211 #define rPm_Rx1_AntB 0xbf0 212 #define rPm_Rx2_AntB 0xbf4 213 #define rPm_Rx3_AntB 0xbf8 214 /* 215 * 6. PageC(0xC00) 216 * */ 217 #define rOFDM0_LSTF 0xc00 218 219 #define rOFDM0_TRxPathEnable 0xc04 220 #define rOFDM0_TRMuxPar 0xc08 221 #define rOFDM0_TRSWIsolation 0xc0c 222 223 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 224 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 225 #define rOFDM0_XBRxAFE 0xc18 226 #define rOFDM0_XBRxIQImbalance 0xc1c 227 #define rOFDM0_XCRxAFE 0xc20 228 #define rOFDM0_XCRxIQImbalance 0xc24 229 #define rOFDM0_XDRxAFE 0xc28 230 #define rOFDM0_XDRxIQImbalance 0xc2c 231 232 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 233 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 234 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 235 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 236 237 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 238 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 239 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 240 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 241 242 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 243 #define rOFDM0_XAAGCCore2 0xc54 244 #define rOFDM0_XBAGCCore1 0xc58 245 #define rOFDM0_XBAGCCore2 0xc5c 246 #define rOFDM0_XCAGCCore1 0xc60 247 #define rOFDM0_XCAGCCore2 0xc64 248 #define rOFDM0_XDAGCCore1 0xc68 249 #define rOFDM0_XDAGCCore2 0xc6c 250 251 #define rOFDM0_AGCParameter1 0xc70 252 #define rOFDM0_AGCParameter2 0xc74 253 #define rOFDM0_AGCRSSITable 0xc78 254 #define rOFDM0_HTSTFAGC 0xc7c 255 256 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 257 #define rOFDM0_XATxAFE 0xc84 258 #define rOFDM0_XBTxIQImbalance 0xc88 259 #define rOFDM0_XBTxAFE 0xc8c 260 #define rOFDM0_XCTxIQImbalance 0xc90 261 #define rOFDM0_XCTxAFE 0xc94 262 #define rOFDM0_XDTxIQImbalance 0xc98 263 #define rOFDM0_XDTxAFE 0xc9c 264 265 #define rOFDM0_RxIQExtAnta 0xca0 266 #define rOFDM0_TxCoeff1 0xca4 267 #define rOFDM0_TxCoeff2 0xca8 268 #define rOFDM0_TxCoeff3 0xcac 269 #define rOFDM0_TxCoeff4 0xcb0 270 #define rOFDM0_TxCoeff5 0xcb4 271 #define rOFDM0_TxCoeff6 0xcb8 272 #define rOFDM0_RxHPParameter 0xce0 273 #define rOFDM0_TxPseudoNoiseWgt 0xce4 274 #define rOFDM0_FrameSync 0xcf0 275 #define rOFDM0_DFSReport 0xcf4 276 277 /* 278 * 7. PageD(0xD00) 279 * */ 280 #define rOFDM1_LSTF 0xd00 281 #define rOFDM1_TRxPathEnable 0xd04 282 283 #define rOFDM1_CFO 0xd08 /* No setting now */ 284 #define rOFDM1_CSI1 0xd10 285 #define rOFDM1_SBD 0xd14 286 #define rOFDM1_CSI2 0xd18 287 #define rOFDM1_CFOTracking 0xd2c 288 #define rOFDM1_TRxMesaure1 0xd34 289 #define rOFDM1_IntfDet 0xd3c 290 #define rOFDM1_PseudoNoiseStateAB 0xd50 291 #define rOFDM1_PseudoNoiseStateCD 0xd54 292 #define rOFDM1_RxPseudoNoiseWgt 0xd58 293 294 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 295 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 296 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 297 298 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 299 #define rOFDM_ShortCFOCD 0xdb0 300 #define rOFDM_LongCFOAB 0xdb4 301 #define rOFDM_LongCFOCD 0xdb8 302 #define rOFDM_TailCFOAB 0xdbc 303 #define rOFDM_TailCFOCD 0xdc0 304 #define rOFDM_PWMeasure1 0xdc4 305 #define rOFDM_PWMeasure2 0xdc8 306 #define rOFDM_BWReport 0xdcc 307 #define rOFDM_AGCReport 0xdd0 308 #define rOFDM_RxSNR 0xdd4 309 #define rOFDM_RxEVMCSI 0xdd8 310 #define rOFDM_SIGReport 0xddc 311 312 313 /* 314 * 8. PageE(0xE00) 315 * */ 316 #define rTxAGC_A_Rate18_06 0xe00 317 #define rTxAGC_A_Rate54_24 0xe04 318 #define rTxAGC_A_CCK1_Mcs32 0xe08 319 #define rTxAGC_A_Mcs03_Mcs00 0xe10 320 #define rTxAGC_A_Mcs07_Mcs04 0xe14 321 #define rTxAGC_A_Mcs11_Mcs08 0xe18 322 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 323 324 #define rFPGA0_IQK 0xe28 325 #define rTx_IQK_Tone_A 0xe30 326 #define rRx_IQK_Tone_A 0xe34 327 #define rTx_IQK_PI_A 0xe38 328 #define rRx_IQK_PI_A 0xe3c 329 330 #define rTx_IQK 0xe40 331 #define rRx_IQK 0xe44 332 #define rIQK_AGC_Pts 0xe48 333 #define rIQK_AGC_Rsp 0xe4c 334 #define rTx_IQK_Tone_B 0xe50 335 #define rRx_IQK_Tone_B 0xe54 336 #define rTx_IQK_PI_B 0xe58 337 #define rRx_IQK_PI_B 0xe5c 338 #define rIQK_AGC_Cont 0xe60 339 340 #define rBlue_Tooth 0xe6c 341 #define rRx_Wait_CCA 0xe70 342 #define rTx_CCK_RFON 0xe74 343 #define rTx_CCK_BBON 0xe78 344 #define rTx_OFDM_RFON 0xe7c 345 #define rTx_OFDM_BBON 0xe80 346 #define rTx_To_Rx 0xe84 347 #define rTx_To_Tx 0xe88 348 #define rRx_CCK 0xe8c 349 350 #define rTx_Power_Before_IQK_A 0xe94 351 #define rTx_Power_After_IQK_A 0xe9c 352 353 #define rRx_Power_Before_IQK_A 0xea0 354 #define rRx_Power_Before_IQK_A_2 0xea4 355 #define rRx_Power_After_IQK_A 0xea8 356 #define rRx_Power_After_IQK_A_2 0xeac 357 358 #define rTx_Power_Before_IQK_B 0xeb4 359 #define rTx_Power_After_IQK_B 0xebc 360 361 #define rRx_Power_Before_IQK_B 0xec0 362 #define rRx_Power_Before_IQK_B_2 0xec4 363 #define rRx_Power_After_IQK_B 0xec8 364 #define rRx_Power_After_IQK_B_2 0xecc 365 366 #define rRx_OFDM 0xed0 367 #define rRx_Wait_RIFS 0xed4 368 #define rRx_TO_Rx 0xed8 369 #define rStandby 0xedc 370 #define rSleep 0xee0 371 #define rPMPD_ANAEN 0xeec 372 373 /* 374 * 7. RF Register 0x00-0x2E (RF 8256) 375 * RF-0222D 0x00-3F 376 * 377 * Zebra1 */ 378 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 379 #define rZebra1_TRxEnable1 0x1 380 #define rZebra1_TRxEnable2 0x2 381 #define rZebra1_AGC 0x4 382 #define rZebra1_ChargePump 0x5 383 #define rZebra1_Channel 0x7 /* RF channel switch */ 384 385 /* #endif */ 386 #define rZebra1_TxGain 0x8 /* Useless now */ 387 #define rZebra1_TxLPF 0x9 388 #define rZebra1_RxLPF 0xb 389 #define rZebra1_RxHPFCorner 0xc 390 391 /* Zebra4 */ 392 #define rGlobalCtrl 0 /* Useless now */ 393 #define rRTL8256_TxLPF 19 394 #define rRTL8256_RxLPF 11 395 396 /* RTL8258 */ 397 #define rRTL8258_TxLPF 0x11 /* Useless now */ 398 #define rRTL8258_RxLPF 0x13 399 #define rRTL8258_RSSILPF 0xa 400 401 /* 402 * RL6052 Register definition 403 * */ 404 #define RF_AC 0x00 /* */ 405 406 #define RF_IQADJ_G1 0x01 /* */ 407 #define RF_IQADJ_G2 0x02 /* */ 408 #define RF_BS_PA_APSET_G1_G4 0x03 409 #define RF_BS_PA_APSET_G5_G8 0x04 410 #define RF_POW_TRSW 0x05 /* */ 411 412 #define RF_GAIN_RX 0x06 /* */ 413 #define RF_GAIN_TX 0x07 /* */ 414 415 #define RF_TXM_IDAC 0x08 /* */ 416 #define RF_IPA_G 0x09 /* */ 417 #define RF_TXBIAS_G 0x0A 418 #define RF_TXPA_AG 0x0B 419 #define RF_IPA_A 0x0C /* */ 420 #define RF_TXBIAS_A 0x0D 421 #define RF_BS_PA_APSET_G9_G11 0x0E 422 #define RF_BS_IQGEN 0x0F /* */ 423 424 #define RF_MODE1 0x10 /* */ 425 #define RF_MODE2 0x11 /* */ 426 427 #define RF_RX_AGC_HP 0x12 /* */ 428 #define RF_TX_AGC 0x13 /* */ 429 #define RF_BIAS 0x14 /* */ 430 #define RF_IPA 0x15 /* */ 431 #define RF_TXBIAS 0x16 432 #define RF_POW_ABILITY 0x17 /* */ 433 #define RF_MODE_AG 0x18 /* */ 434 #define rRfChannel 0x18 /* RF channel and BW switch */ 435 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 436 #define RF_TOP 0x19 /* */ 437 438 #define RF_RX_G1 0x1A /* */ 439 #define RF_RX_G2 0x1B /* */ 440 441 #define RF_RX_BB2 0x1C /* */ 442 #define RF_RX_BB1 0x1D /* */ 443 444 #define RF_RCK1 0x1E /* */ 445 #define RF_RCK2 0x1F /* */ 446 447 #define RF_TX_G1 0x20 /* */ 448 #define RF_TX_G2 0x21 /* */ 449 #define RF_TX_G3 0x22 /* */ 450 451 #define RF_TX_BB1 0x23 /* */ 452 453 #define RF_T_METER 0x24 /* */ 454 455 #define RF_SYN_G1 0x25 /* RF TX Power control */ 456 #define RF_SYN_G2 0x26 /* RF TX Power control */ 457 #define RF_SYN_G3 0x27 /* RF TX Power control */ 458 #define RF_SYN_G4 0x28 /* RF TX Power control */ 459 #define RF_SYN_G5 0x29 /* RF TX Power control */ 460 #define RF_SYN_G6 0x2A /* RF TX Power control */ 461 #define RF_SYN_G7 0x2B /* RF TX Power control */ 462 #define RF_SYN_G8 0x2C /* RF TX Power control */ 463 464 #define RF_RCK_OS 0x30 /* RF TX PA control */ 465 466 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 467 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 468 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 469 #define RF_TX_BIAS_A 0x35 470 #define RF_TX_BIAS_D 0x36 471 #define RF_LOBF_9 0x38 472 #define RF_RXRF_A3 0x3C /* */ 473 #define RF_TRSW 0x3F 474 475 #define RF_TXRF_A2 0x41 476 #define RF_TXPA_G4 0x46 477 #define RF_TXPA_A4 0x4B 478 #define RF_0x52 0x52 479 #define RF_WE_LUT 0xEF 480 #define RF_S0S1 0xB0 481 482 /* 483 * Bit Mask 484 * 485 * 1. Page1(0x100) */ 486 #define bBBResetB 0x100 /* Useless now? */ 487 #define bGlobalResetB 0x200 488 #define bOFDMTxStart 0x4 489 #define bCCKTxStart 0x8 490 #define bCRC32Debug 0x100 491 #define bPMACLoopback 0x10 492 #define bTxLSIG 0xffffff 493 #define bOFDMTxRate 0xf 494 #define bOFDMTxReserved 0x10 495 #define bOFDMTxLength 0x1ffe0 496 #define bOFDMTxParity 0x20000 497 #define bTxHTSIG1 0xffffff 498 #define bTxHTMCSRate 0x7f 499 #define bTxHTBW 0x80 500 #define bTxHTLength 0xffff00 501 #define bTxHTSIG2 0xffffff 502 #define bTxHTSmoothing 0x1 503 #define bTxHTSounding 0x2 504 #define bTxHTReserved 0x4 505 #define bTxHTAggreation 0x8 506 #define bTxHTSTBC 0x30 507 #define bTxHTAdvanceCoding 0x40 508 #define bTxHTShortGI 0x80 509 #define bTxHTNumberHT_LTF 0x300 510 #define bTxHTCRC8 0x3fc00 511 #define bCounterReset 0x10000 512 #define bNumOfOFDMTx 0xffff 513 #define bNumOfCCKTx 0xffff0000 514 #define bTxIdleInterval 0xffff 515 #define bOFDMService 0xffff0000 516 #define bTxMACHeader 0xffffffff 517 #define bTxDataInit 0xff 518 #define bTxHTMode 0x100 519 #define bTxDataType 0x30000 520 #define bTxRandomSeed 0xffffffff 521 #define bCCKTxPreamble 0x1 522 #define bCCKTxSFD 0xffff0000 523 #define bCCKTxSIG 0xff 524 #define bCCKTxService 0xff00 525 #define bCCKLengthExt 0x8000 526 #define bCCKTxLength 0xffff0000 527 #define bCCKTxCRC16 0xffff 528 #define bCCKTxStatus 0x1 529 #define bOFDMTxStatus 0x2 530 531 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 532 533 /* 2. Page8(0x800) */ 534 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 535 #define bJapanMode 0x2 536 #define bCCKTxSC 0x30 537 #define bCCKEn 0x1000000 538 #define bOFDMEn 0x2000000 539 540 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 541 #define bOFDMTxDACPhase 0x40000 542 #define bXATxAGC 0x3f 543 544 #define bAntennaSelect 0x0300 545 546 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 547 #define bXCTxAGC 0xf000 548 #define bXDTxAGC 0xf0000 549 550 #define bPAStart 0xf0000000 /* Useless now */ 551 #define bTRStart 0x00f00000 552 #define bRFStart 0x0000f000 553 #define bBBStart 0x000000f0 554 #define bBBCCKStart 0x0000000f 555 #define bPAEnd 0xf /* Reg0x814 */ 556 #define bTREnd 0x0f000000 557 #define bRFEnd 0x000f0000 558 #define bCCAMask 0x000000f0 /* T2R */ 559 #define bR2RCCAMask 0x00000f00 560 #define bHSSI_R2TDelay 0xf8000000 561 #define bHSSI_T2RDelay 0xf80000 562 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 563 #define bIGFromCCK 0x200 564 #define bAGCAddress 0x3f 565 #define bRxHPTx 0x7000 566 #define bRxHPT2R 0x38000 567 #define bRxHPCCKIni 0xc0000 568 #define bAGCTxCode 0xc00000 569 #define bAGCRxCode 0x300000 570 571 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 572 #define b3WireAddressLength 0x400 573 574 #define b3WireRFPowerDown 0x1 /* Useless now 575 * #define bHWSISelect 0x8 */ 576 #define b5GPAPEPolarity 0x40000000 577 #define b2GPAPEPolarity 0x80000000 578 #define bRFSW_TxDefaultAnt 0x3 579 #define bRFSW_TxOptionAnt 0x30 580 #define bRFSW_RxDefaultAnt 0x300 581 #define bRFSW_RxOptionAnt 0x3000 582 #define bRFSI_3WireData 0x1 583 #define bRFSI_3WireClock 0x2 584 #define bRFSI_3WireLoad 0x4 585 #define bRFSI_3WireRW 0x8 586 #define bRFSI_3Wire 0xf 587 588 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 589 590 #define bRFSI_TRSW 0x20 /* Useless now */ 591 #define bRFSI_TRSWB 0x40 592 #define bRFSI_ANTSW 0x100 593 #define bRFSI_ANTSWB 0x200 594 #define bRFSI_PAPE 0x400 595 #define bRFSI_PAPE5G 0x800 596 #define bBandSelect 0x1 597 #define bHTSIG2_GI 0x80 598 #define bHTSIG2_Smoothing 0x01 599 #define bHTSIG2_Sounding 0x02 600 #define bHTSIG2_Aggreaton 0x08 601 #define bHTSIG2_STBC 0x30 602 #define bHTSIG2_AdvCoding 0x40 603 #define bHTSIG2_NumOfHTLTF 0x300 604 #define bHTSIG2_CRC8 0x3fc 605 #define bHTSIG1_MCS 0x7f 606 #define bHTSIG1_BandWidth 0x80 607 #define bHTSIG1_HTLength 0xffff 608 #define bLSIG_Rate 0xf 609 #define bLSIG_Reserved 0x10 610 #define bLSIG_Length 0x1fffe 611 #define bLSIG_Parity 0x20 612 #define bCCKRxPhase 0x4 613 614 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 615 616 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 617 618 #define bLSSIReadBackData 0xfffff /* T65 RF */ 619 620 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 621 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 622 #define bRegulator0Standby 0x1 623 #define bRegulatorPLLStandby 0x2 624 #define bRegulator1Standby 0x4 625 #define bPLLPowerUp 0x8 626 #define bDPLLPowerUp 0x10 627 #define bDA10PowerUp 0x20 628 #define bAD7PowerUp 0x200 629 #define bDA6PowerUp 0x2000 630 #define bXtalPowerUp 0x4000 631 #define b40MDClkPowerUP 0x8000 632 #define bDA6DebugMode 0x20000 633 #define bDA6Swing 0x380000 634 635 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 636 637 #define b80MClkDelay 0x18000000 /* Useless */ 638 #define bAFEWatchDogEnable 0x20000000 639 640 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 641 #define bXtalCap23 0x3 642 #define bXtalCap92x 0x0f000000 643 #define bXtalCap 0x0f000000 644 645 #define bIntDifClkEnable 0x400 /* Useless */ 646 #define bExtSigClkEnable 0x800 647 #define bBandgapMbiasPowerUp 0x10000 648 #define bAD11SHGain 0xc0000 649 #define bAD11InputRange 0x700000 650 #define bAD11OPCurrent 0x3800000 651 #define bIPathLoopback 0x4000000 652 #define bQPathLoopback 0x8000000 653 #define bAFELoopback 0x10000000 654 #define bDA10Swing 0x7e0 655 #define bDA10Reverse 0x800 656 #define bDAClkSource 0x1000 657 #define bAD7InputRange 0x6000 658 #define bAD7Gain 0x38000 659 #define bAD7OutputCMMode 0x40000 660 #define bAD7InputCMMode 0x380000 661 #define bAD7Current 0xc00000 662 #define bRegulatorAdjust 0x7000000 663 #define bAD11PowerUpAtTx 0x1 664 #define bDA10PSAtTx 0x10 665 #define bAD11PowerUpAtRx 0x100 666 #define bDA10PSAtRx 0x1000 667 #define bCCKRxAGCFormat 0x200 668 #define bPSDFFTSamplepPoint 0xc000 669 #define bPSDAverageNum 0x3000 670 #define bIQPathControl 0xc00 671 #define bPSDFreq 0x3ff 672 #define bPSDAntennaPath 0x30 673 #define bPSDIQSwitch 0x40 674 #define bPSDRxTrigger 0x400000 675 #define bPSDTxTrigger 0x80000000 676 #define bPSDSineToneScale 0x7f000000 677 #define bPSDReport 0xffff 678 679 /* 3. Page9(0x900) */ 680 #define bOFDMTxSC 0x30000000 /* Useless */ 681 #define bCCKTxOn 0x1 682 #define bOFDMTxOn 0x2 683 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 684 #define bDebugItem 0xff /* reset debug page and LWord */ 685 #define bAntL 0x10 686 #define bAntNonHT 0x100 687 #define bAntHT1 0x1000 688 #define bAntHT2 0x10000 689 #define bAntHT1S1 0x100000 690 #define bAntNonHTS1 0x1000000 691 692 /* 4. PageA(0xA00) */ 693 #define bCCKBBMode 0x3 /* Useless */ 694 #define bCCKTxPowerSaving 0x80 695 #define bCCKRxPowerSaving 0x40 696 697 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 698 699 #define bCCKScramble 0x8 /* Useless */ 700 #define bCCKAntDiversity 0x8000 701 #define bCCKCarrierRecovery 0x4000 702 #define bCCKTxRate 0x3000 703 #define bCCKDCCancel 0x0800 704 #define bCCKISICancel 0x0400 705 #define bCCKMatchFilter 0x0200 706 #define bCCKEqualizer 0x0100 707 #define bCCKPreambleDetect 0x800000 708 #define bCCKFastFalseCCA 0x400000 709 #define bCCKChEstStart 0x300000 710 #define bCCKCCACount 0x080000 711 #define bCCKcs_lim 0x070000 712 #define bCCKBistMode 0x80000000 713 #define bCCKCCAMask 0x40000000 714 #define bCCKTxDACPhase 0x4 715 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 716 #define bCCKr_cp_mode0 0x0100 717 #define bCCKTxDCOffset 0xf0 718 #define bCCKRxDCOffset 0xf 719 #define bCCKCCAMode 0xc000 720 #define bCCKFalseCS_lim 0x3f00 721 #define bCCKCS_ratio 0xc00000 722 #define bCCKCorgBit_sel 0x300000 723 #define bCCKPD_lim 0x0f0000 724 #define bCCKNewCCA 0x80000000 725 #define bCCKRxHPofIG 0x8000 726 #define bCCKRxIG 0x7f00 727 #define bCCKLNAPolarity 0x800000 728 #define bCCKRx1stGain 0x7f0000 729 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 730 #define bCCKRxAGCSatLevel 0x1f000000 731 #define bCCKRxAGCSatCount 0xe0 732 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 733 #define bCCKFixedRxAGC 0x8000 734 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 735 #define bCCKAntennaPolarity 0x2000 736 #define bCCKTxFilterType 0x0c00 737 #define bCCKRxAGCReportType 0x0300 738 #define bCCKRxDAGCEn 0x80000000 739 #define bCCKRxDAGCPeriod 0x20000000 740 #define bCCKRxDAGCSatLevel 0x1f000000 741 #define bCCKTimingRecovery 0x800000 742 #define bCCKTxC0 0x3f0000 743 #define bCCKTxC1 0x3f000000 744 #define bCCKTxC2 0x3f 745 #define bCCKTxC3 0x3f00 746 #define bCCKTxC4 0x3f0000 747 #define bCCKTxC5 0x3f000000 748 #define bCCKTxC6 0x3f 749 #define bCCKTxC7 0x3f00 750 #define bCCKDebugPort 0xff0000 751 #define bCCKDACDebug 0x0f000000 752 #define bCCKFalseAlarmEnable 0x8000 753 #define bCCKFalseAlarmRead 0x4000 754 #define bCCKTRSSI 0x7f 755 #define bCCKRxAGCReport 0xfe 756 #define bCCKRxReport_AntSel 0x80000000 757 #define bCCKRxReport_MFOff 0x40000000 758 #define bCCKRxRxReport_SQLoss 0x20000000 759 #define bCCKRxReport_Pktloss 0x10000000 760 #define bCCKRxReport_Lockedbit 0x08000000 761 #define bCCKRxReport_RateError 0x04000000 762 #define bCCKRxReport_RxRate 0x03000000 763 #define bCCKRxFACounterLower 0xff 764 #define bCCKRxFACounterUpper 0xff000000 765 #define bCCKRxHPAGCStart 0xe000 766 #define bCCKRxHPAGCFinal 0x1c00 767 #define bCCKRxFalseAlarmEnable 0x8000 768 #define bCCKFACounterFreeze 0x4000 769 #define bCCKTxPathSel 0x10000000 770 #define bCCKDefaultRxPath 0xc000000 771 #define bCCKOptionRxPath 0x3000000 772 773 /* 5. PageC(0xC00) */ 774 #define bNumOfSTF 0x3 /* Useless */ 775 #define bShift_L 0xc0 776 #define bGI_TH 0xc 777 #define bRxPathA 0x1 778 #define bRxPathB 0x2 779 #define bRxPathC 0x4 780 #define bRxPathD 0x8 781 #define bTxPathA 0x1 782 #define bTxPathB 0x2 783 #define bTxPathC 0x4 784 #define bTxPathD 0x8 785 #define bTRSSIFreq 0x200 786 #define bADCBackoff 0x3000 787 #define bDFIRBackoff 0xc000 788 #define bTRSSILatchPhase 0x10000 789 #define bRxIDCOffset 0xff 790 #define bRxQDCOffset 0xff00 791 #define bRxDFIRMode 0x1800000 792 #define bRxDCNFType 0xe000000 793 #define bRXIQImb_A 0x3ff 794 #define bRXIQImb_B 0xfc00 795 #define bRXIQImb_C 0x3f0000 796 #define bRXIQImb_D 0xffc00000 797 #define bDC_dc_Notch 0x60000 798 #define bRxNBINotch 0x1f000000 799 #define bPD_TH 0xf 800 #define bPD_TH_Opt2 0xc000 801 #define bPWED_TH 0x700 802 #define bIfMF_Win_L 0x800 803 #define bPD_Option 0x1000 804 #define bMF_Win_L 0xe000 805 #define bBW_Search_L 0x30000 806 #define bwin_enh_L 0xc0000 807 #define bBW_TH 0x700000 808 #define bED_TH2 0x3800000 809 #define bBW_option 0x4000000 810 #define bRatio_TH 0x18000000 811 #define bWindow_L 0xe0000000 812 #define bSBD_Option 0x1 813 #define bFrame_TH 0x1c 814 #define bFS_Option 0x60 815 #define bDC_Slope_check 0x80 816 #define bFGuard_Counter_DC_L 0xe00 817 #define bFrame_Weight_Short 0x7000 818 #define bSub_Tune 0xe00000 819 #define bFrame_DC_Length 0xe000000 820 #define bSBD_start_offset 0x30000000 821 #define bFrame_TH_2 0x7 822 #define bFrame_GI2_TH 0x38 823 #define bGI2_Sync_en 0x40 824 #define bSarch_Short_Early 0x300 825 #define bSarch_Short_Late 0xc00 826 #define bSarch_GI2_Late 0x70000 827 #define bCFOAntSum 0x1 828 #define bCFOAcc 0x2 829 #define bCFOStartOffset 0xc 830 #define bCFOLookBack 0x70 831 #define bCFOSumWeight 0x80 832 #define bDAGCEnable 0x10000 833 #define bTXIQImb_A 0x3ff 834 #define bTXIQImb_B 0xfc00 835 #define bTXIQImb_C 0x3f0000 836 #define bTXIQImb_D 0xffc00000 837 #define bTxIDCOffset 0xff 838 #define bTxQDCOffset 0xff00 839 #define bTxDFIRMode 0x10000 840 #define bTxPesudoNoiseOn 0x4000000 841 #define bTxPesudoNoise_A 0xff 842 #define bTxPesudoNoise_B 0xff00 843 #define bTxPesudoNoise_C 0xff0000 844 #define bTxPesudoNoise_D 0xff000000 845 #define bCCADropOption 0x20000 846 #define bCCADropThres 0xfff00000 847 #define bEDCCA_H 0xf 848 #define bEDCCA_L 0xf0 849 #define bLambda_ED 0x300 850 #define bRxInitialGain 0x7f 851 #define bRxAntDivEn 0x80 852 #define bRxAGCAddressForLNA 0x7f00 853 #define bRxHighPowerFlow 0x8000 854 #define bRxAGCFreezeThres 0xc0000 855 #define bRxFreezeStep_AGC1 0x300000 856 #define bRxFreezeStep_AGC2 0xc00000 857 #define bRxFreezeStep_AGC3 0x3000000 858 #define bRxFreezeStep_AGC0 0xc000000 859 #define bRxRssi_Cmp_En 0x10000000 860 #define bRxQuickAGCEn 0x20000000 861 #define bRxAGCFreezeThresMode 0x40000000 862 #define bRxOverFlowCheckType 0x80000000 863 #define bRxAGCShift 0x7f 864 #define bTRSW_Tri_Only 0x80 865 #define bPowerThres 0x300 866 #define bRxAGCEn 0x1 867 #define bRxAGCTogetherEn 0x2 868 #define bRxAGCMin 0x4 869 #define bRxHP_Ini 0x7 870 #define bRxHP_TRLNA 0x70 871 #define bRxHP_RSSI 0x700 872 #define bRxHP_BBP1 0x7000 873 #define bRxHP_BBP2 0x70000 874 #define bRxHP_BBP3 0x700000 875 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 876 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 877 #define bRxSettle_TRSW 0x7 878 #define bRxSettle_LNA 0x38 879 #define bRxSettle_RSSI 0x1c0 880 #define bRxSettle_BBP 0xe00 881 #define bRxSettle_RxHP 0x7000 882 #define bRxSettle_AntSW_RSSI 0x38000 883 #define bRxSettle_AntSW 0xc0000 884 #define bRxProcessTime_DAGC 0x300000 885 #define bRxSettle_HSSI 0x400000 886 #define bRxProcessTime_BBPPW 0x800000 887 #define bRxAntennaPowerShift 0x3000000 888 #define bRSSITableSelect 0xc000000 889 #define bRxHP_Final 0x7000000 890 #define bRxHTSettle_BBP 0x7 891 #define bRxHTSettle_HSSI 0x8 892 #define bRxHTSettle_RxHP 0x70 893 #define bRxHTSettle_BBPPW 0x80 894 #define bRxHTSettle_Idle 0x300 895 #define bRxHTSettle_Reserved 0x1c00 896 #define bRxHTRxHPEn 0x8000 897 #define bRxHTAGCFreezeThres 0x30000 898 #define bRxHTAGCTogetherEn 0x40000 899 #define bRxHTAGCMin 0x80000 900 #define bRxHTAGCEn 0x100000 901 #define bRxHTDAGCEn 0x200000 902 #define bRxHTRxHP_BBP 0x1c00000 903 #define bRxHTRxHP_Final 0xe0000000 904 #define bRxPWRatioTH 0x3 905 #define bRxPWRatioEn 0x4 906 #define bRxMFHold 0x3800 907 #define bRxPD_Delay_TH1 0x38 908 #define bRxPD_Delay_TH2 0x1c0 909 #define bRxPD_DC_COUNT_MAX 0x600 910 /* #define bRxMF_Hold 0x3800 */ 911 #define bRxPD_Delay_TH 0x8000 912 #define bRxProcess_Delay 0xf0000 913 #define bRxSearchrange_GI2_Early 0x700000 914 #define bRxFrame_Guard_Counter_L 0x3800000 915 #define bRxSGI_Guard_L 0xc000000 916 #define bRxSGI_Search_L 0x30000000 917 #define bRxSGI_TH 0xc0000000 918 #define bDFSCnt0 0xff 919 #define bDFSCnt1 0xff00 920 #define bDFSFlag 0xf0000 921 #define bMFWeightSum 0x300000 922 #define bMinIdxTH 0x7f000000 923 #define bDAFormat 0x40000 924 #define bTxChEmuEnable 0x01000000 925 #define bTRSWIsolation_A 0x7f 926 #define bTRSWIsolation_B 0x7f00 927 #define bTRSWIsolation_C 0x7f0000 928 #define bTRSWIsolation_D 0x7f000000 929 #define bExtLNAGain 0x7c00 930 931 /* 6. PageE(0xE00) */ 932 #define bSTBCEn 0x4 /* Useless */ 933 #define bAntennaMapping 0x10 934 #define bNss 0x20 935 #define bCFOAntSumD 0x200 936 #define bPHYCounterReset 0x8000000 937 #define bCFOReportGet 0x4000000 938 #define bOFDMContinueTx 0x10000000 939 #define bOFDMSingleCarrier 0x20000000 940 #define bOFDMSingleTone 0x40000000 941 /* #define bRxPath1 0x01 */ 942 /* #define bRxPath2 0x02 */ 943 /* #define bRxPath3 0x04 */ 944 /* #define bRxPath4 0x08 */ 945 /* #define bTxPath1 0x10 */ 946 /* #define bTxPath2 0x20 */ 947 #define bHTDetect 0x100 948 #define bCFOEn 0x10000 949 #define bCFOValue 0xfff00000 950 #define bSigTone_Re 0x3f 951 #define bSigTone_Im 0x7f00 952 #define bCounter_CCA 0xffff 953 #define bCounter_ParityFail 0xffff0000 954 #define bCounter_RateIllegal 0xffff 955 #define bCounter_CRC8Fail 0xffff0000 956 #define bCounter_MCSNoSupport 0xffff 957 #define bCounter_FastSync 0xffff 958 #define bShortCFO 0xfff 959 #define bShortCFOTLength 12 /* total */ 960 #define bShortCFOFLength 11 /* fraction */ 961 #define bLongCFO 0x7ff 962 #define bLongCFOTLength 11 963 #define bLongCFOFLength 11 964 #define bTailCFO 0x1fff 965 #define bTailCFOTLength 13 966 #define bTailCFOFLength 12 967 #define bmax_en_pwdB 0xffff 968 #define bCC_power_dB 0xffff0000 969 #define bnoise_pwdB 0xffff 970 #define bPowerMeasTLength 10 971 #define bPowerMeasFLength 3 972 #define bRx_HT_BW 0x1 973 #define bRxSC 0x6 974 #define bRx_HT 0x8 975 #define bNB_intf_det_on 0x1 976 #define bIntf_win_len_cfg 0x30 977 #define bNB_Intf_TH_cfg 0x1c0 978 #define bRFGain 0x3f 979 #define bTableSel 0x40 980 #define bTRSW 0x80 981 #define bRxSNR_A 0xff 982 #define bRxSNR_B 0xff00 983 #define bRxSNR_C 0xff0000 984 #define bRxSNR_D 0xff000000 985 #define bSNREVMTLength 8 986 #define bSNREVMFLength 1 987 #define bCSI1st 0xff 988 #define bCSI2nd 0xff00 989 #define bRxEVM1st 0xff0000 990 #define bRxEVM2nd 0xff000000 991 #define bSIGEVM 0xff 992 #define bPWDB 0xff00 993 #define bSGIEN 0x10000 994 995 #define bSFactorQAM1 0xf /* Useless */ 996 #define bSFactorQAM2 0xf0 997 #define bSFactorQAM3 0xf00 998 #define bSFactorQAM4 0xf000 999 #define bSFactorQAM5 0xf0000 1000 #define bSFactorQAM6 0xf0000 1001 #define bSFactorQAM7 0xf00000 1002 #define bSFactorQAM8 0xf000000 1003 #define bSFactorQAM9 0xf0000000 1004 #define bCSIScheme 0x100000 1005 1006 #define bNoiseLvlTopSet 0x3 /* Useless */ 1007 #define bChSmooth 0x4 1008 #define bChSmoothCfg1 0x38 1009 #define bChSmoothCfg2 0x1c0 1010 #define bChSmoothCfg3 0xe00 1011 #define bChSmoothCfg4 0x7000 1012 #define bMRCMode 0x800000 1013 #define bTHEVMCfg 0x7000000 1014 1015 #define bLoopFitType 0x1 /* Useless */ 1016 #define bUpdCFO 0x40 1017 #define bUpdCFOOffData 0x80 1018 #define bAdvUpdCFO 0x100 1019 #define bAdvTimeCtrl 0x800 1020 #define bUpdClko 0x1000 1021 #define bFC 0x6000 1022 #define bTrackingMode 0x8000 1023 #define bPhCmpEnable 0x10000 1024 #define bUpdClkoLTF 0x20000 1025 #define bComChCFO 0x40000 1026 #define bCSIEstiMode 0x80000 1027 #define bAdvUpdEqz 0x100000 1028 #define bUChCfg 0x7000000 1029 #define bUpdEqz 0x8000000 1030 1031 /* Rx Pseduo noise */ 1032 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1033 #define bRxPesudoNoise_A 0xff 1034 #define bRxPesudoNoise_B 0xff00 1035 #define bRxPesudoNoise_C 0xff0000 1036 #define bRxPesudoNoise_D 0xff000000 1037 #define bPesudoNoiseState_A 0xffff 1038 #define bPesudoNoiseState_B 0xffff0000 1039 #define bPesudoNoiseState_C 0xffff 1040 #define bPesudoNoiseState_D 0xffff0000 1041 1042 /* 7. RF Register 1043 * Zebra1 */ 1044 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1045 #define bZebra1_TRxControl 0xc00 1046 #define bZebra1_TRxGainSetting 0x07f 1047 #define bZebra1_RxCorner 0xc00 1048 #define bZebra1_TxChargePump 0x38 1049 #define bZebra1_RxChargePump 0x7 1050 #define bZebra1_ChannelNum 0xf80 1051 #define bZebra1_TxLPFBW 0x400 1052 #define bZebra1_RxLPFBW 0x600 1053 1054 /* Zebra4 */ 1055 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1056 #define bRTL8256RegModeCtrl0 0x40 1057 #define bRTL8256_TxLPFBW 0x18 1058 #define bRTL8256_RxLPFBW 0x600 1059 1060 /* RTL8258 */ 1061 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1062 #define bRTL8258_RxLPFBW 0xc00 1063 #define bRTL8258_RSSILPFBW 0xc0 1064 1065 1066 /* 1067 * Other Definition 1068 * */ 1069 1070 /* byte endable for sb_write */ 1071 #define bByte0 0x1 /* Useless */ 1072 #define bByte1 0x2 1073 #define bByte2 0x4 1074 #define bByte3 0x8 1075 #define bWord0 0x3 1076 #define bWord1 0xc 1077 #define bDWord 0xf 1078 1079 /* for PutRegsetting & GetRegSetting BitMask */ 1080 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1081 #define bMaskByte1 0xff00 1082 #define bMaskByte2 0xff0000 1083 #define bMaskByte3 0xff000000 1084 #define bMaskHWord 0xffff0000 1085 #define bMaskLWord 0x0000ffff 1086 #define bMaskDWord 0xffffffff 1087 #define bMaskH3Bytes 0xffffff00 1088 #define bMask12Bits 0xfff 1089 #define bMaskH4Bits 0xf0000000 1090 #define bMaskOFDM_D 0xffc00000 1091 #define bMaskCCK 0x3f3f3f3f 1092 1093 1094 #define bEnable 0x1 /* Useless */ 1095 #define bDisable 0x0 1096 1097 #define LeftAntenna 0x0 /* Useless */ 1098 #define RightAntenna 0x1 1099 1100 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1101 #define tUpdateRxCounter 100 /* 100ms */ 1102 1103 #define rateCCK 0 /* Useless */ 1104 #define rateOFDM 1 1105 #define rateHT 2 1106 1107 /* define Register-End */ 1108 #define bPMAC_End 0x1ff /* Useless */ 1109 #define bFPGAPHY0_End 0x8ff 1110 #define bFPGAPHY1_End 0x9ff 1111 #define bCCKPHY0_End 0xaff 1112 #define bOFDMPHY0_End 0xcff 1113 #define bOFDMPHY1_End 0xdff 1114 1115 /* define max debug item in each debug page 1116 * #define bMaxItem_FPGA_PHY0 0x9 1117 * #define bMaxItem_FPGA_PHY1 0x3 1118 * #define bMaxItem_PHY_11B 0x16 1119 * #define bMaxItem_OFDM_PHY0 0x29 1120 * #define bMaxItem_OFDM_PHY1 0x0 */ 1121 1122 #define bPMACControl 0x0 /* Useless */ 1123 #define bWMACControl 0x1 1124 #define bWNICControl 0x2 1125 1126 #define PathA 0x0 /* Useless */ 1127 #define PathB 0x1 1128 #define PathC 0x2 1129 #define PathD 0x3 1130 1131 #endif 1132