1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
34 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_start_cck_cont_tx_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)35 void phydm_start_cck_cont_tx_jgr3(void *dm_void,
36 struct phydm_pmac_info *tx_info)
37 {
38 struct dm_struct *dm = (struct dm_struct *)dm_void;
39 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
40 u8 rate = tx_info->tx_rate; /* HW rate */
41
42 /* if CCK block on? */
43 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
44 odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
45 if (dm->support_ic_type & ODM_RTL8723F) {
46 odm_set_bb_reg(dm, R_0x2a08, BIT(21)|BIT(20), rate);
47 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
48 } else {
49 /* Turn Off All Test mode */
50 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
51
52 odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
53 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
54 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
55
56 /* Fix rate selection issue */
57 odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
58 /* set RX weighting for path I & Q to 0 */
59 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
60 /* set loopback mode */
61 odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
62 }
63 pmac_tx->cck_cont_tx = true;
64 pmac_tx->ofdm_cont_tx = false;
65 }
66
phydm_stop_cck_cont_tx_jgr3(void * dm_void)67 void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
68 {
69 struct dm_struct *dm = (struct dm_struct *)dm_void;
70 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
71
72 pmac_tx->cck_cont_tx = false;
73 pmac_tx->ofdm_cont_tx = false;
74
75 if (dm->support_ic_type & ODM_RTL8723F) {
76 /* @Disable pmac tx_en*/
77 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
78 } else {
79 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
80 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
81
82 /* back to default */
83 odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
84 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
85 odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
86 }
87 /* BB Reset */
88 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
89 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
90 }
91
phydm_start_ofdm_cont_tx_jgr3(void * dm_void)92 void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
93 {
94 struct dm_struct *dm = (struct dm_struct *)dm_void;
95 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
96
97 /* 1. if OFDM block on */
98 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
99 odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
100 if (!(dm->support_ic_type & ODM_RTL8723F)) {
101
102 /* 2. set CCK test mode off, set to CCK normal mode */
103 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
104
105 /* 3. turn on scramble setting */
106 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
107 }
108 /* 4. Turn On Continue Tx and turn off the other test modes. */
109 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
110
111 pmac_tx->cck_cont_tx = false;
112 pmac_tx->ofdm_cont_tx = true;
113 }
114
phydm_stop_ofdm_cont_tx_jgr3(void * dm_void)115 void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
116 {
117 struct dm_struct *dm = (struct dm_struct *)dm_void;
118 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
119
120 pmac_tx->cck_cont_tx = false;
121 pmac_tx->ofdm_cont_tx = false;
122
123 /* Turn Off All Test mode */
124 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
125
126 /* Delay 10 ms */
127 ODM_delay_ms(10);
128
129 /* BB Reset */
130 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
131 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
132 }
133
phydm_stop_pmac_tx_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)134 void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
135 {
136 struct dm_struct *dm = (struct dm_struct *)dm_void;
137 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
138 u32 tmp = 0;
139
140 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
141 if (dm->support_ic_type & ODM_RTL8723F) {
142 if (tx_info->mode == CONT_TX) {
143 if (pmac_tx->is_cck_rate) {
144 /* TX Stop */
145 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
146 /* Clear BB cont tx */
147 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
148 /* Clear PMAC cont tx */
149 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
150 /* Clear TX Stop */
151 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
152 phydm_stop_cck_cont_tx_jgr3(dm);
153 } else
154 phydm_stop_ofdm_cont_tx_jgr3(dm);
155 } else {
156 if (pmac_tx->is_cck_rate) {
157 /* packet_count = 0x1 */
158 odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, 0x1);
159 /* @Disable pmac tx_en*/
160 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
161 /* @Enable pmac tx_en*/
162 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
163 phydm_stop_cck_cont_tx_jgr3(dm);
164 }
165 }
166 }else {
167 if (tx_info->mode == CONT_TX) {
168 if (pmac_tx->is_cck_rate)
169 phydm_stop_cck_cont_tx_jgr3(dm);
170 else
171 phydm_stop_ofdm_cont_tx_jgr3(dm);
172 }
173 }
174 }
175
phydm_set_mac_phy_txinfo_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)176 void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
177 struct phydm_pmac_info *tx_info)
178 {
179 struct dm_struct *dm = (struct dm_struct *)dm_void;
180 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
181 u32 tmp = 0;
182
183 odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);
184
185 /*0x900[1] ndp_sound */
186 odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);
187
188 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
189 tx_info->m_stbc = tx_info->m_stbc - 1;
190 #endif
191 /*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
192 tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
193 ((tx_info->m_stbc) << 6);
194 odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);
195
196 if (tx_info->tx_sc == 1) /*upper*/
197 odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
198 else if (tx_info->tx_sc == 2) /*lower*/
199 odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
200 else /* duplicate*/
201 odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
202
203 if (pmac_tx->is_ht_rate) {
204 odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
205 odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
206 } else if (pmac_tx->is_vht_rate) {
207 odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
208 odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
209 } else {
210 odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
211 odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
212 }
213
214 /* for TX interval */
215 odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
216 }
217
phydm_set_sig_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)218 void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
219 {
220 struct dm_struct *dm = (struct dm_struct *)dm_void;
221 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
222 u32 tmp = 0;
223
224 if (pmac_tx->is_cck_rate)
225 return;
226
227 odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
228
229 /* L-SIG */
230 tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
231 tx_info->lsig[0]);
232 odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
233 if (pmac_tx->is_ht_rate) {
234 /* HT SIG */
235 tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
236 tx_info->ht_sig[0]);
237 odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
238 tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
239 tx_info->ht_sig[3]);
240 odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
241 } else if (pmac_tx->is_vht_rate) {
242 /* VHT SIG A/B/serv_field/delimiter */
243 tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
244 tx_info->vht_sig_a[1],
245 tx_info->vht_sig_a[0]);
246 odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
247 tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
248 tx_info->vht_sig_a[4],
249 tx_info->vht_sig_a[3]);
250 odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
251 tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
252 tx_info->vht_sig_b[1],
253 tx_info->vht_sig_b[0]);
254 odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
255 odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);
256
257 tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
258 tx_info->vht_delimiter[2],
259 tx_info->vht_delimiter[1],
260 tx_info->vht_delimiter[0]);
261 odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
262 }
263 }
264
phydm_set_cck_preamble_hdr_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)265 void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
266 struct phydm_pmac_info *tx_info)
267 {
268 struct dm_struct *dm = (struct dm_struct *)dm_void;
269 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
270 u32 tmp = 0;
271 u8 rate = tx_info->tx_rate; /* HW rate */
272
273 if (!pmac_tx->is_cck_rate)
274 return;
275
276 if (dm->support_ic_type & ODM_RTL8723F) {
277 #if (RTL8723F_SUPPORT)
278 odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, tx_info->packet_count);
279 odm_set_bb_reg(dm, R_0x2a08, BIT(22), tx_info->service_field_bit2);
280 odm_set_bb_reg(dm, R_0x2a08, BIT(21) | BIT(20), rate);
281 odm_set_bb_reg(dm, R_0x2a08, 0x1ffff, tx_info->packet_length);
282 /* turn on scrambler */
283 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
284
285 if (tx_info->is_short_preamble)
286 odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x1);
287 else
288 odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x0);
289 #endif
290 } else {
291 tmp = tx_info->packet_count | (tx_info->sfd << 16);
292 odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
293 tmp = tx_info->signal_field | (tx_info->service_field << 8) |
294 (tx_info->length << 16);
295 odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
296 tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
297 odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
298
299 if (tx_info->is_short_preamble)
300 odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
301 else
302 odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
303 }
304 }
305
phydm_set_mode_jgr3(void * dm_void,struct phydm_pmac_info * tx_info,enum phydm_pmac_mode mode)306 void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
307 enum phydm_pmac_mode mode)
308 {
309 struct dm_struct *dm = (struct dm_struct *)dm_void;
310 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
311
312 if (mode == CONT_TX) {
313 tx_info->packet_count = 1;
314
315 if (pmac_tx->is_cck_rate)
316 phydm_start_cck_cont_tx_jgr3(dm, tx_info);
317 else
318 phydm_start_ofdm_cont_tx_jgr3(dm);
319 }
320 }
321
phydm_set_pmac_txon_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)322 void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
323 {
324 struct dm_struct *dm = (struct dm_struct *)dm_void;
325 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
326
327 odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */
328
329 if (dm->support_ic_type & ODM_RTL8723F) {
330 if (pmac_tx->is_cck_rate) {
331 if (tx_info->mode == CONT_TX) {
332 /* BB and PMAC cont tx */
333 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
334 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
335 }
336 /* TX CCK ON */
337 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
338 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
339 } else {
340 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x0); /*TX Ofdm OFF */
341 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
342 }
343 } else {
344 /*mac scramble seed setting, only in 8198F */
345 #if (RTL8198F_SUPPORT)
346 if (dm->support_ic_type & ODM_RTL8198F)
347 if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
348 odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
349 #endif
350
351 if (pmac_tx->is_cck_rate){
352 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
353 odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
354 } else {
355 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
356 }
357 }
358 }
359
phydm_set_pmac_tx_jgr3(void * dm_void,struct phydm_pmac_info * tx_info,enum rf_path mpt_rf_path)360 void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
361 enum rf_path mpt_rf_path)
362 {
363 struct dm_struct *dm = (struct dm_struct *)dm_void;
364 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
365
366 pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
367 pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
368 pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
369 pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
370 pmac_tx->path = mpt_rf_path;
371
372 if (!tx_info->en_pmac_tx) {
373 phydm_stop_pmac_tx_jgr3(dm, tx_info);
374 return;
375 }
376
377 phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
378
379 if (pmac_tx->is_cck_rate)
380 phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
381 else
382 phydm_set_sig_jgr3(dm, tx_info);
383
384 phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
385 phydm_set_pmac_txon_jgr3(dm, tx_info);
386 }
387
phydm_set_tmac_tx_jgr3(void * dm_void)388 void phydm_set_tmac_tx_jgr3(void *dm_void)
389 {
390 struct dm_struct *dm = (struct dm_struct *)dm_void;
391
392 /* Turn on TMAC */
393 if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
394 odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);
395
396 /* mac scramble seed setting, only in 8198F */
397 #if (RTL8198F_SUPPORT)
398 if (dm->support_ic_type & ODM_RTL8198F)
399 if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
400 odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
401 #endif
402
403 /* Turn on TMAC CCK */
404 if (!(dm->support_ic_type & ODM_RTL8723F)) {
405 if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
406 odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
407 }
408 }
409 #endif
410
phydm_start_cck_cont_tx(void * dm_void,struct phydm_pmac_info * tx_info)411 void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
412 {
413 struct dm_struct *dm = (struct dm_struct *)dm_void;
414
415 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
416 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
417 phydm_start_cck_cont_tx_jgr3(dm, tx_info);
418 #endif
419 }
420
phydm_stop_cck_cont_tx(void * dm_void)421 void phydm_stop_cck_cont_tx(void *dm_void)
422 {
423 struct dm_struct *dm = (struct dm_struct *)dm_void;
424
425 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
426 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
427 phydm_stop_cck_cont_tx_jgr3(dm);
428 #endif
429 }
430
phydm_start_ofdm_cont_tx(void * dm_void)431 void phydm_start_ofdm_cont_tx(void *dm_void)
432 {
433 struct dm_struct *dm = (struct dm_struct *)dm_void;
434
435 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
436 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
437 phydm_start_ofdm_cont_tx_jgr3(dm);
438 #endif
439 }
440
phydm_stop_ofdm_cont_tx(void * dm_void)441 void phydm_stop_ofdm_cont_tx(void *dm_void)
442 {
443 struct dm_struct *dm = (struct dm_struct *)dm_void;
444
445 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
446 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
447 phydm_stop_ofdm_cont_tx_jgr3(dm);
448 #endif
449 }
450
phydm_set_pmac_tx(void * dm_void,struct phydm_pmac_info * tx_info,enum rf_path mpt_rf_path)451 void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
452 enum rf_path mpt_rf_path)
453 {
454 struct dm_struct *dm = (struct dm_struct *)dm_void;
455
456 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
457 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
458 phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
459 #endif
460 }
461
phydm_set_tmac_tx(void * dm_void)462 void phydm_set_tmac_tx(void *dm_void)
463 {
464 struct dm_struct *dm = (struct dm_struct *)dm_void;
465
466 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
467 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
468 phydm_set_tmac_tx_jgr3(dm);
469 #endif
470 }
471
phydm_pmac_tx_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)472 void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
473 char *output, u32 *_out_len)
474 {
475 struct dm_struct *dm = (struct dm_struct *)dm_void;
476 struct phydm_pmac_info tx_info;
477 char help[] = "-h";
478 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
479 u32 var[10] = {0};
480 u32 used = *_used;
481 u32 out_len = *_out_len;
482 u8 i = 0;
483 u32 tx_cnt = 0x0;
484 u8 poll_cnt = 0x0;
485
486 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
487
488 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
489 return;
490
491 if ((strcmp(input[1], help) == 0)) {
492 PDM_SNPF(out_len, used, output + used, out_len - used,
493 "[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
494 } else {
495 for (i = 1; i < 7; i++) {
496 if (input[i + 1]) {
497 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
498 &var[i]);
499 }
500 }
501
502 odm_memory_set(dm, &tx_info, 0, sizeof(struct phydm_pmac_info));
503 tx_info.en_pmac_tx = true;
504 tx_info.mode = PKTS_TX;
505 tx_info.ndp_sound = false;
506 tx_info.bw = CHANNEL_WIDTH_20;
507 tx_info.tx_sc = 0x0; /*duplicate*/
508 tx_info.m_stbc = 0x0; /*disable*/
509 tx_info.packet_period = 2000; /*d'500 us*/
510 tx_info.tx_rate = (u8)var[1];
511 tx_info.packet_count = (u32)var[2];
512
513 if (tx_info.tx_rate == ODM_RATE1M) {
514 tx_info.signal_field = 0xa; /*rate = 1M*/
515 tx_info.service_field = 0x0;
516 if (dm->support_ic_type & ODM_RTL8723F) {
517 tx_info.service_field_bit2= 0x1;
518 tx_info.packet_length = 1000; /*1000 bytes*/
519 }
520 tx_info.length = 8000; /*d'8000 us=1000 bytes*/
521 tx_info.crc16[0] = 0x60;
522 tx_info.crc16[1] = 0x8e;
523 /*long preamble*/
524 tx_info.is_short_preamble = false;
525 tx_info.sfd = 0xf3a0;
526 } else if (tx_info.tx_rate == ODM_RATE6M) {
527 /*l-sig[3:0] = rate = 6M = 0xb*/
528 /*l-sig[16:5] = length = 1000 bytes*/
529 /*l-sig[17] = parity = 1*/
530 tx_info.lsig[0] = 0xb;
531 tx_info.lsig[1] = 0x7d;
532 tx_info.lsig[2] = 0x2;
533 }
534 phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
535 PHYDM_SNPRINT_SIZE);
536 PDM_SNPF(out_len, used, output + used, out_len - used,
537 "rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
538 dbg_buf, tx_info.packet_count);
539
540 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
541 PDM_SNPF(out_len, used, output + used, out_len - used,
542 "check trx idle failed, please try again.\n");
543 return;
544 }
545
546 phydm_reset_bb_hw_cnt(dm);
547 phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
548
549 PDM_SNPF(out_len, used, output + used, out_len - used,
550 "pmac_tx enabled, please wait for tx_cnt = %d\n",
551 tx_info.packet_count);
552 while (1) {
553 if (phydm_is_cck_rate(dm, tx_info.tx_rate))
554 tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
555 MASKLWORD);
556 else
557 tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
558 MASKLWORD);
559
560 if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
561 break;
562
563 ODM_delay_ms(100);
564 poll_cnt++;
565 }
566
567 if (tx_cnt < tx_info.packet_count)
568 PDM_SNPF(out_len, used, output + used, out_len - used,
569 "polling time out(1s), tx_cnt = %d\n", tx_cnt);
570 else
571 PDM_SNPF(out_len, used, output + used, out_len - used,
572 "pmac_tx finished, poll_cnt = %d\n", poll_cnt);
573
574 tx_info.en_pmac_tx = false;
575 phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
576 phydm_set_tmac_tx(dm);
577 PDM_SNPF(out_len, used, output + used, out_len - used,
578 "Stop pmac_tx and turn on true mac mode.\n");
579
580 phydm_stop_ic_trx(dm, PHYDM_REVERT);
581 }
582 *_used = used;
583 *_out_len = out_len;
584 }
585 #endif