1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*************************************************************
27 * include files
28 ************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 /**************************************************
33 * This function is for inband noise test utility only
34 * To obtain the inband noise level(dbm), do the following.
35 * 1. disable DIG and Power Saving
36 * 2. Set initial gain = 0x1a
37 * 3. Stop updating idle time pwer report (for driver read)
38 * - 0x80c[25]
39 *
40 *************************************************/
41
phydm_set_noise_data_sum(struct noise_level * noise_data,u8 max_rf_path)42 void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
43 {
44 u8 i = 0;
45
46 for (i = RF_PATH_A; i < max_rf_path; i++) {
47 if (noise_data->valid_cnt[i])
48 noise_data->sum[i] /= noise_data->valid_cnt[i];
49 else
50 noise_data->sum[i] = 0;
51 }
52 }
53
54 #if (ODM_IC_11N_SERIES_SUPPORT)
odm_inband_noise_monitor_n(struct dm_struct * dm,u8 is_pause_dig,u8 igi,u32 max_time)55 s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,
56 u32 max_time)
57 {
58 u32 tmp4b;
59 u8 max_rf_path = 0, i = 0;
60 u8 reg_c50, reg_c58, valid_done = 0;
61 struct noise_level noise_data;
62 u64 start = 0, func_start = 0, func_end = 0;
63 s8 val_s8 = 0;
64
65 func_start = odm_get_current_time(dm);
66 dm->noise_level.noise_all = 0;
67
68 if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
69 max_rf_path = 2;
70 else
71 max_rf_path = 1;
72
73 PHYDM_DBG(dm, DBG_ENV_MNTR,
74 "odm_DebugControlInbandNoise_Nseries() ==>\n");
75
76 odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
77 /* step 1. Disable DIG && Set initial gain. */
78
79 if (is_pause_dig)
80 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
81
82 /* step 3. Get noise power level */
83 start = odm_get_current_time(dm);
84 while (1) {
85 /* Stop updating idle time pwer report (for driver read) */
86 odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
87
88 /* Read Noise Floor Report */
89 tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);
90
91 /* update idle time pwer report per 5us */
92 odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
93
94 ODM_delay_us(5);
95
96 noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
97 noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
98
99 for (i = RF_PATH_A; i < max_rf_path; i++) {
100 noise_data.sval[i] = (s8)noise_data.value[i];
101 noise_data.sval[i] /= 2;
102 }
103
104 for (i = RF_PATH_A; i < max_rf_path; i++) {
105 if (noise_data.valid_cnt[i] >= VALID_CNT)
106 continue;
107
108 noise_data.valid_cnt[i]++;
109 noise_data.sum[i] += noise_data.sval[i];
110 PHYDM_DBG(dm, DBG_ENV_MNTR,
111 "rf_path:%d Valid sval=%d\n", i,
112 noise_data.sval[i]);
113 PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n",
114 noise_data.sum[i]);
115 if (noise_data.valid_cnt[i] == VALID_CNT)
116 valid_done++;
117 }
118 if (valid_done == max_rf_path ||
119 (odm_get_progressing_time(dm, start) > max_time)) {
120 phydm_set_noise_data_sum(&noise_data, max_rf_path);
121 break;
122 }
123 }
124 reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
125 reg_c50 &= ~BIT(7);
126 val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
127 dm->noise_level.noise[RF_PATH_A] = val_s8;
128 dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
129
130 if (max_rf_path == 2) {
131 reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
132 reg_c58 &= ~BIT(7);
133 val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
134 dm->noise_level.noise[RF_PATH_B] = val_s8;
135 dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
136 }
137 dm->noise_level.noise_all /= max_rf_path;
138
139 PHYDM_DBG(dm, DBG_ENV_MNTR,
140 "noise_a = %d, noise_b = %d, noise_all = %d\n",
141 dm->noise_level.noise[RF_PATH_A],
142 dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
143
144 /* step 4. Recover the Dig */
145 if (is_pause_dig)
146 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
147 func_end = odm_get_progressing_time(dm, func_start);
148
149 PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
150 return dm->noise_level.noise_all;
151 }
152 #endif
153
154 #if (ODM_IC_11AC_SERIES_SUPPORT)
phydm_idle_noise_measure_ac(struct dm_struct * dm,u8 pause_dig,u8 igi,u32 max_time)155 s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,
156 u8 igi, u32 max_time)
157 {
158 u32 tmp4b;
159 u8 max_rf_path = 0, i = 0;
160 u8 reg_c50, reg_e50, valid_done = 0;
161 u64 start = 0, func_start = 0, func_end = 0;
162 struct noise_level noise_data;
163 s8 val_s8 = 0;
164
165 func_start = odm_get_current_time(dm);
166 dm->noise_level.noise_all = 0;
167
168 if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
169 max_rf_path = 2;
170 else
171 max_rf_path = 1;
172
173 PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__);
174
175 odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
176
177 /*Step 1. Disable DIG && Set initial gain.*/
178
179 if (pause_dig)
180 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
181
182 /*Step 2. Get noise power level*/
183 start = odm_get_current_time(dm);
184
185 while (1) {
186 /*Stop updating idle time pwer report (for driver read)*/
187 odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);
188
189 /*Read Noise Floor Report*/
190 tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);
191
192 /*update idle time pwer report per 5us*/
193 odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);
194
195 ODM_delay_us(5);
196
197 noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
198 noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
199
200 for (i = RF_PATH_A; i < max_rf_path; i++) {
201 noise_data.sval[i] = (s8)noise_data.value[i];
202 noise_data.sval[i] = noise_data.sval[i] >> 1;
203 }
204
205 for (i = RF_PATH_A; i < max_rf_path; i++) {
206 if (noise_data.valid_cnt[i] >= VALID_CNT)
207 continue;
208
209 noise_data.valid_cnt[i]++;
210 noise_data.sum[i] += noise_data.sval[i];
211 PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n",
212 i, noise_data.sval[i]);
213 PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n",
214 noise_data.sum[i]);
215 if (noise_data.valid_cnt[i] == VALID_CNT)
216 valid_done++;
217 }
218
219 if (valid_done == max_rf_path ||
220 (odm_get_progressing_time(dm, start) > max_time)) {
221 phydm_set_noise_data_sum(&noise_data, max_rf_path);
222 break;
223 }
224 }
225 reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
226 reg_c50 &= ~BIT(7);
227 val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
228 dm->noise_level.noise[RF_PATH_A] = val_s8;
229 dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
230
231 if (max_rf_path == 2) {
232 reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);
233 reg_e50 &= ~BIT(7);
234 val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
235 dm->noise_level.noise[RF_PATH_B] = val_s8;
236 dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
237 }
238 dm->noise_level.noise_all /= max_rf_path;
239
240 PHYDM_DBG(dm, DBG_ENV_MNTR,
241 "noise_a = %d, noise_b = %d, noise_all = %d\n",
242 dm->noise_level.noise[RF_PATH_A],
243 dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
244
245 /*Step 3. Recover the Dig*/
246 if (pause_dig)
247 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
248 func_end = odm_get_progressing_time(dm, func_start);
249
250 PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
251 return dm->noise_level.noise_all;
252 }
253
odm_inband_noise_monitor_ac(struct dm_struct * dm,u8 pause_dig,u8 igi,u32 max_time)254 s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
255 u32 max_time)
256 {
257 s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
258 s32 value32, pwdb_A = 0, sval, noise, sum = 0;
259 boolean pd_flag;
260 u8 valid_cnt = 0;
261 u8 invalid_cnt = 0;
262 u64 start = 0, func_start = 0, func_end = 0, proc_time = 0;
263 s32 val_s32 = 0;
264 s16 rpt = 0;
265 u8 val_u8 = 0;
266
267 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
268 rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);
269 return rpt;
270 }
271
272 if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
273 return 0;
274
275 func_start = odm_get_current_time(dm);
276 dm->noise_level.noise_all = 0;
277
278 PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__);
279
280 /* step 1. Disable DIG && Set initial gain. */
281 if (pause_dig)
282 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
283
284 /* step 3. Get noise power level */
285 start = odm_get_current_time(dm);
286
287 /* step 3. Get noise power level */
288 while (1) {
289 /*Set IGI=0x1C */
290 odm_write_dig(dm, 0x1C);
291 /*stop CK320&CK88 */
292 odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);
293 /*Read path-A */
294 /*set debug port*/
295 odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);
296 /*read debug port*/
297 value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
298 /*rxi_buf_anta=RegFA0[19:10]*/
299 rxi_buf_anta = (value32 & 0xFFC00) >> 10;
300 rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
301
302 pd_flag = (boolean)((value32 & BIT(31)) >> 31);
303
304 /*Not in packet detection period or Tx state */
305 if (!pd_flag || rxi_buf_anta != 0x200) {
306 /*sign conversion*/
307 rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
308 rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
309
310 val_s32 = rxi_buf_anta * rxi_buf_anta +
311 rxq_buf_anta * rxq_buf_anta;
312 /*S(10,9)*S(10,9)=S(20,18)*/
313 pwdb_A = odm_pwdb_conversion(val_s32, 20, 18);
314
315 PHYDM_DBG(dm, DBG_ENV_MNTR,
316 "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
317 pwdb_A, rxi_buf_anta & 0x3FF,
318 rxq_buf_anta & 0x3FF);
319 }
320 /*Start CK320&CK88*/
321 odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);
322 /*@BB Reset*/
323 val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));
324 odm_write_1byte(dm, 0x02, val_u8);
325 val_u8 = odm_read_1byte(dm, 0x02) | BIT(0);
326 odm_write_1byte(dm, 0x02, val_u8);
327 /*PMAC Reset*/
328 val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));
329 odm_write_1byte(dm, 0xB03, val_u8);
330 val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);
331 odm_write_1byte(dm, 0xB03, val_u8);
332 /*@CCK Reset*/
333 if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
334 val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));
335 odm_write_1byte(dm, 0x80B, val_u8);
336 val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);
337 odm_write_1byte(dm, 0x80B, val_u8);
338 }
339
340 sval = pwdb_A;
341
342 if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {
343 valid_cnt++;
344 sum += sval;
345 PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
346 PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
347 if (valid_cnt >= VALID_CNT ||
348 (odm_get_progressing_time(dm, start) > max_time)) {
349 sum /= VALID_CNT;
350 PHYDM_DBG(dm, DBG_ENV_MNTR,
351 "After divided, sum = %d\n", sum);
352 break;
353 }
354 } else {
355 /*Invalid sval and return -110 dBm*/
356 invalid_cnt++;
357 PHYDM_DBG(dm, DBG_ENV_MNTR, "Invalid sval\n");
358 if (invalid_cnt >= VALID_CNT + 5) {
359 PHYDM_DBG(dm, DBG_ENV_MNTR,
360 "Invalid count > TH, Return -110, Break!!\n");
361 return -110;
362 }
363 }
364 }
365
366 /*@ADC backoff is 12dB,*/
367 /*Ptarget=0x1C-110=-82dBm*/
368 noise = sum + 12 + 0x1C - 110;
369
370 /*Offset*/
371 noise = noise - 3;
372 PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise);
373 dm->noise_level.noise_all = (s16)noise;
374
375 /* step 4. Recover the Dig*/
376 if (pause_dig)
377 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
378
379 func_end = odm_get_progressing_time(dm, func_start);
380
381 PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__);
382
383 return dm->noise_level.noise_all;
384 }
385 #endif
386
odm_inband_noise_monitor(void * dm_void,u8 pause_dig,u8 igi,u32 max_time)387 s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,
388 u32 max_time)
389 {
390 struct dm_struct *dm = (struct dm_struct *)dm_void;
391 s16 val = 0;
392
393 igi = 0x32;
394
395 /* since HW ability is about +15~-35,
396 * we fix IGI = -60 for maximum coverage
397 */
398 #if (ODM_IC_11AC_SERIES_SUPPORT)
399 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
400 val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);
401 #endif
402
403 #if (ODM_IC_11N_SERIES_SUPPORT)
404 if (dm->support_ic_type & ODM_IC_11N_SERIES)
405 val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);
406 #endif
407
408 return val;
409 }
410
phydm_noisy_detection(void * dm_void)411 void phydm_noisy_detection(void *dm_void)
412 {
413 struct dm_struct *dm = (struct dm_struct *)dm_void;
414 u32 total_fa_cnt, total_cca_cnt;
415 u32 score = 0, i, score_smooth;
416
417 total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
418 total_fa_cnt = dm->false_alm_cnt.cnt_all;
419
420 #if 0
421 if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* @87.5 */
422 ;
423 else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* @75 */
424 ;
425 else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* @56.25 */
426 ;
427 else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* @50 */
428 ;
429 else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* @43.75 */
430 ;
431 else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* @37.5 */
432 ;
433 else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* @31.25% */
434 ;
435 else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* @25% */
436 ;
437 else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* @18.75% */
438 ;
439 else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* @12.5% */
440 ;
441 else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* @6.25% */
442 ;
443 #endif
444 for (i = 0; i <= 16; i++) {
445 if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
446 score = 16 - i;
447 break;
448 }
449 }
450
451 /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
452 dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +
453 (score << 2);
454
455 /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
456 if (total_cca_cnt >= 300)
457 score_smooth = (dm->noisy_decision_smooth + 3) >> 3;
458 else
459 score_smooth = 0;
460
461 dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
462
463 PHYDM_DBG(dm, DBG_ENV_MNTR,
464 "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
465 total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
466 score_smooth, dm->noisy_decision);
467 }
468