1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_MP_SUPPORT
34 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
35
phydm_mp_set_single_tone_jgr3(void * dm_void,boolean is_single_tone,u8 path)36 void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
37 u8 path)
38 {
39 struct dm_struct *dm = (struct dm_struct *)dm_void;
40 struct phydm_mp *mp = &dm->dm_mp_table;
41 u8 start = RF_PATH_A, end = RF_PATH_A;
42 u8 i = 0;
43 u8 max_rf_path = RF_PATH_A;
44 u8 central_ch = 0;
45 boolean is_2g_ch = false;
46
47 switch (path) {
48 case RF_PATH_A:
49 case RF_PATH_B:
50 case RF_PATH_C:
51 case RF_PATH_D:
52 start = path;
53 end = path;
54 break;
55 case RF_PATH_AB:
56 start = RF_PATH_A;
57 end = RF_PATH_B;
58 break;
59 #if (defined(PHYDM_COMPILE_IC_4SS))
60 case RF_PATH_AC:
61 start = RF_PATH_A;
62 end = RF_PATH_C;
63 break;
64 case RF_PATH_AD:
65 start = RF_PATH_A;
66 end = RF_PATH_D;
67 break;
68 case RF_PATH_BC:
69 start = RF_PATH_B;
70 end = RF_PATH_C;
71 break;
72 case RF_PATH_BD:
73 start = RF_PATH_B;
74 end = RF_PATH_D;
75 break;
76 case RF_PATH_CD:
77 start = RF_PATH_C;
78 end = RF_PATH_D;
79 break;
80 case RF_PATH_ABC:
81 start = RF_PATH_A;
82 end = RF_PATH_C;
83 break;
84 case RF_PATH_ABD:
85 start = RF_PATH_A;
86 end = RF_PATH_D;
87 break;
88 case RF_PATH_ACD:
89 start = RF_PATH_A;
90 end = RF_PATH_D;
91 break;
92 case RF_PATH_BCD:
93 start = RF_PATH_B;
94 end = RF_PATH_D;
95 break;
96 case RF_PATH_ABCD:
97 start = RF_PATH_A;
98 end = RF_PATH_D;
99 break;
100 #endif
101 }
102
103 central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
104 is_2g_ch = (central_ch <= 14) ? true : false;
105
106 if (dm->support_ic_type & ODM_RTL8723F)
107 max_rf_path = RF_PATH_C;
108 else
109 max_rf_path = RF_PATH_MEM_SIZE;
110
111 if (is_single_tone) {
112 /*Disable CCA*/
113 if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
114 if(!(dm->support_ic_type & ODM_RTL8723F)) {
115 odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
116 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
117 }
118 }
119 /*Disable CCK CCA*/
120 if(dm->support_ic_type & ODM_RTL8723F)
121 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
122 /*Disable OFDM CCA*/
123 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
124
125 if (dm->support_ic_type & ODM_RTL8723F) {
126 for (i = start; i <= end; i++) {
127 if (i < max_rf_path) {
128 odm_set_rf_reg(dm, i, RF_0x5, BIT(0), 0x0);
129 mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
130 /*Tx mode: RF0x00[19:16]=4'b0010 */
131 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
132 /*Lowest RF gain index: RF_0x1[5:0] TX power*/
133 mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
134 odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
135 /*RF LO enabled */
136 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
137 }
138 }
139 } else {
140 for (i = start; i <= end; i++) {
141 if (i < max_rf_path) {
142 mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
143 /*Tx mode: RF0x00[19:16]=4'b0010 */
144 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
145 /*Lowest RF gain index: RF_0x0[4:0] = 0*/
146 odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
147 /*RF LO enabled */
148 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
149 }
150 }
151 }
152
153 #if (RTL8814B_SUPPORT)
154 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
155 mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
156 dm, RF_SYN0, RF_0x0, RFREG_MASK);
157 /*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
158 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
159 0x1f, 0x0);
160 /*RF LO enabled */
161 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
162 BIT(1), 0x1);
163 /*SYN1*/
164 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
165 mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
166 dm, RF_SYN1, RF_0x0,
167 RFREG_MASK);
168 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
169 RF_0x0, 0x1f,
170 0x0);
171 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
172 RF_0x58, BIT(1),
173 0x1);
174 }
175 }
176 #endif
177 } else {
178 /*Enable CCA*/
179 if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
180 if(!(dm->support_ic_type & ODM_RTL8723F)) {
181 odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
182 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
183 }
184 }
185 /*Enable CCK CCA*/
186 if(dm->support_ic_type & ODM_RTL8723F)
187 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
188 /*Enable OFDM CCA*/
189 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
190
191 if(dm->support_ic_type & ODM_RTL8723F) {
192 for (i = start; i <= end; i++) {
193 if (i < max_rf_path) {
194 odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
195 odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
196 /*RF LO disabled */
197 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
198 odm_set_rf_reg(dm, i, RF_0x5, BIT(0), 0x1);
199 }
200 }
201 } else {
202 for (i = start; i <= end; i++) {
203 if (i < max_rf_path) {
204 odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
205 /*RF LO disabled */
206 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
207 }
208 }
209 }
210 #if (RTL8814B_SUPPORT)
211 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
212 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
213 RFREG_MASK,
214 mp->rf0_syn[RF_SYN0]);
215 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
216 BIT(1), 0x0);
217 /*SYN1*/
218 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
219 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
220 RF_0x0,
221 RFREG_MASK,
222 mp->rf0_syn[RF_SYN1]);
223 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
224 RF_0x58, BIT(1),
225 0x0);
226 }
227 }
228 #endif
229 }
230 }
231
phydm_mp_set_carrier_supp_jgr3(void * dm_void,boolean is_carrier_supp,u32 rate_index)232 void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
233 u32 rate_index)
234 {
235 struct dm_struct *dm = (struct dm_struct *)dm_void;
236 struct phydm_mp *mp = &dm->dm_mp_table;
237
238 if (is_carrier_supp) {
239 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
240 /*if CCK block on? */
241 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
242 odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
243
244 if(dm->support_ic_type & ODM_RTL8723F){
245 /* @Carrier suppress tx */
246 odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
247 /*turn off scramble setting */
248 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
249 /*Set CCK Tx Test Rate, set TxRate to 2Mbps */
250 odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
251 /* BB and PMAC cont tx */
252 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
253 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
254 /* TX CCK ON */
255 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
256 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
257 }
258 else {
259 /*Turn Off All Test mode */
260 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
261
262 /*transmit mode */
263 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
264 /*turn off scramble setting */
265 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
266 /*Set CCK Tx Test Rate, set TxRate to 1Mbps */
267 odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
268 }
269 }
270 } else { /*Stop Carrier Suppression. */
271 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
272 if(dm->support_ic_type & ODM_RTL8723F) {
273 /* TX Stop */
274 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
275 /* Clear BB cont tx */
276 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
277 /* Clear PMAC cont tx */
278 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
279 /* Clear TX Stop */
280 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
281 /* normal mode */
282 odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
283 /* turn on scramble setting */
284 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
285 }
286 else {
287 /*normal mode */
288 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
289 /*turn on scramble setting */
290 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
291 }
292 /*BB Reset */
293 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
294 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
295 }
296 }
297 }
298
phydm_mp_set_single_carrier_jgr3(void * dm_void,boolean is_single_carrier)299 void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
300 {
301 struct dm_struct *dm = (struct dm_struct *)dm_void;
302 struct phydm_mp *mp = &dm->dm_mp_table;
303
304 if (is_single_carrier) {
305 /*1. if OFDM block on? */
306 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
307 odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
308
309 if (dm->support_ic_type & ODM_RTL8723F) {
310 /*3. turn on scramble setting */
311 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
312 /*4. Turn On single carrier. */
313 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
314 }
315 else {
316 /*2. set CCK test mode off, set to CCK normal mode */
317 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
318 /*3. turn on scramble setting */
319 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
320 /*4. Turn On single carrier. */
321 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
322 }
323 } else {
324 /*Turn off all test modes. */
325 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
326
327 /*Delay 10 ms */
328 ODM_delay_ms(10);
329
330 /*BB Reset*/
331 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
332 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
333 }
334 }
335
phydm_mp_get_tx_ok_jgr3(void * dm_void,u32 rate_index)336 void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
337 {
338 struct dm_struct *dm = (struct dm_struct *)dm_void;
339 struct phydm_mp *mp = &dm->dm_mp_table;
340
341 if (phydm_is_cck_rate(dm, (u8)rate_index))
342 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
343 else
344 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
345 }
346
phydm_mp_get_rx_ok_jgr3(void * dm_void)347 void phydm_mp_get_rx_ok_jgr3(void *dm_void)
348 {
349 struct dm_struct *dm = (struct dm_struct *)dm_void;
350 struct phydm_mp *mp = &dm->dm_mp_table;
351
352 u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
353 u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
354 if(dm->support_ic_type & ODM_RTL8723F)
355 cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
356 else
357 cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
358 ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
359 ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
360 vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
361 if(dm->support_ic_type & ODM_RTL8723F)
362 cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
363 else
364 cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
365 ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
366 ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
367 vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
368
369 mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
370 mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
371 mp->io_value = (u32)mp->rx_phy_ok_cnt;
372 }
373 #endif
phydm_mp_set_crystal_cap(void * dm_void,u8 crystal_cap)374 void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
375 {
376 struct dm_struct *dm = (struct dm_struct *)dm_void;
377
378 phydm_set_crystal_cap(dm, crystal_cap);
379 }
380
phydm_mp_set_single_tone(void * dm_void,boolean is_single_tone,u8 path)381 void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
382 {
383 struct dm_struct *dm = (struct dm_struct *)dm_void;
384
385 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
386 phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
387 }
388
phydm_mp_set_carrier_supp(void * dm_void,boolean is_carrier_supp,u32 rate_index)389 void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
390 u32 rate_index)
391 {
392 struct dm_struct *dm = (struct dm_struct *)dm_void;
393
394 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
395 phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
396 }
397
phydm_mp_set_single_carrier(void * dm_void,boolean is_single_carrier)398 void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
399 {
400 struct dm_struct *dm = (struct dm_struct *)dm_void;
401
402 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
403 phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
404 }
phydm_mp_reset_rx_counters_phy(void * dm_void)405 void phydm_mp_reset_rx_counters_phy(void *dm_void)
406 {
407 struct dm_struct *dm = (struct dm_struct *)dm_void;
408
409 phydm_reset_bb_hw_cnt(dm);
410 }
411
phydm_mp_get_tx_ok(void * dm_void,u32 rate_index)412 void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
413 {
414 struct dm_struct *dm = (struct dm_struct *)dm_void;
415
416 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
417 phydm_mp_get_tx_ok_jgr3(dm, rate_index);
418 }
419
phydm_mp_get_rx_ok(void * dm_void)420 void phydm_mp_get_rx_ok(void *dm_void)
421 {
422 struct dm_struct *dm = (struct dm_struct *)dm_void;
423
424 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
425 phydm_mp_get_rx_ok_jgr3(dm);
426 }
427 #endif
428