1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_SUPPORT_CCKPD
34 #ifdef PHYDM_COMPILE_CCKPD_TYPE1
phydm_write_cck_pd_type1(void * dm_void,u8 cca_th)35 void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th)
36 {
37 struct dm_struct *dm = (struct dm_struct *)dm_void;
38 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
39
40 PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n",
41 __func__, cca_th);
42
43 odm_write_1byte(dm, R_0xa0a, cca_th);
44 cckpd_t->cur_cck_cca_thres = cca_th;
45 }
46
phydm_set_cckpd_lv_type1(void * dm_void,enum cckpd_lv lv)47 void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
51 u8 pd_th = 0;
52
53 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
54 PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
55
56 if (cckpd_t->cck_pd_lv == lv) {
57 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
58 return;
59 }
60
61 cckpd_t->cck_pd_lv = lv;
62 cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
63
64 if (lv == CCK_PD_LV_4)
65 pd_th = 0xed;
66 else if (lv == CCK_PD_LV_3)
67 pd_th = 0xdd;
68 else if (lv == CCK_PD_LV_2)
69 pd_th = 0xcd;
70 else if (lv == CCK_PD_LV_1)
71 pd_th = 0x83;
72 else if (lv == CCK_PD_LV_0)
73 pd_th = 0x40;
74
75 phydm_write_cck_pd_type1(dm, pd_th);
76 }
77
phydm_cckpd_type1(void * dm_void)78 void phydm_cckpd_type1(void *dm_void)
79 {
80 struct dm_struct *dm = (struct dm_struct *)dm_void;
81 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
82 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
83 enum cckpd_lv lv = CCK_PD_LV_INIT;
84 boolean is_update = true;
85
86 if (dm->is_linked) {
87 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
88 if (dm->support_ic_type & ODM_RTL8822B) {
89 if (dm->rssi_min > 35) {
90 lv = CCK_PD_LV_2;
91 } else if (dm->rssi_min > 20) {
92 if (cckpd_t->cck_fa_ma > 500)
93 lv = CCK_PD_LV_2;
94 else if (cckpd_t->cck_fa_ma < 250)
95 lv = CCK_PD_LV_1;
96 else
97 is_update = false;
98 } else { /*RSSI < 20*/
99 lv = CCK_PD_LV_1;
100 }
101 } else {
102 if (dm->rssi_min > 60) {
103 lv = CCK_PD_LV_3;
104 } else if (dm->rssi_min > 35) {
105 lv = CCK_PD_LV_2;
106 } else if (dm->rssi_min > 20) {
107 if (cckpd_t->cck_fa_ma > 500)
108 lv = CCK_PD_LV_2;
109 else if (cckpd_t->cck_fa_ma < 250)
110 lv = CCK_PD_LV_1;
111 else
112 is_update = false;
113 } else { /*RSSI < 20*/
114 lv = CCK_PD_LV_1;
115 }
116 }
117 #else /*ODM_AP*/
118 if (dig_t->cur_ig_value > 0x32) {
119 lv = CCK_PD_LV_4;
120 // remove lv4 only for 8822b
121 if (dm->support_ic_type & ODM_RTL8822B) {
122 lv = CCK_PD_LV_3;
123 }
124 } else if (dig_t->cur_ig_value > 0x2a) {
125 lv = CCK_PD_LV_3;
126 } else if (dig_t->cur_ig_value > 0x24) {
127 lv = CCK_PD_LV_2;
128 } else {
129 lv = CCK_PD_LV_1;
130 }
131 #endif
132 } else {
133 if (cckpd_t->cck_fa_ma > 1000)
134 lv = CCK_PD_LV_1;
135 else if (cckpd_t->cck_fa_ma < 500)
136 lv = CCK_PD_LV_0;
137 else
138 is_update = false;
139 }
140
141 /*[Abnormal case] =================================================*/
142 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
143 /*@HP 22B LPS power consumption issue & [PCIE-1596]*/
144 if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) {
145 lv = CCK_PD_LV_0;
146 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
147 } else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) &&
148 cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) {
149 lv = CCK_PD_LV_1;
150 cckpd_t->cck_pd_lv = lv;
151 phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/
152 is_update = false;
153 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n");
154 }
155 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
156 #ifdef MCR_WIRELESS_EXTEND
157 lv = CCK_PD_LV_2;
158 cckpd_t->cck_pd_lv = lv;
159 phydm_write_cck_pd_type1(dm, 0x43);
160 is_update = false;
161 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n");
162 #endif
163 #endif
164 /*=================================================================*/
165
166 if (is_update)
167 phydm_set_cckpd_lv_type1(dm, lv);
168
169 PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n",
170 dm->is_linked, cckpd_t->cck_pd_lv,
171 cckpd_t->cur_cck_cca_thres);
172 }
173 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/
174
175 #ifdef PHYDM_COMPILE_CCKPD_TYPE2
phydm_write_cck_pd_type2(void * dm_void,u8 cca_th,u8 cca_th_aaa)176 void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa)
177 {
178 struct dm_struct *dm = (struct dm_struct *)dm_void;
179 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
180
181 PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n",
182 __func__, cca_th, cca_th_aaa);
183
184 odm_set_bb_reg(dm, R_0xa08, 0x3f0000, cca_th);
185 odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa);
186 cckpd_t->cur_cck_cca_thres = cca_th;
187 cckpd_t->cck_cca_th_aaa = cca_th_aaa;
188 }
189
phydm_set_cckpd_lv_type2(void * dm_void,enum cckpd_lv lv)190 void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv)
191 {
192 struct dm_struct *dm = (struct dm_struct *)dm_void;
193 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
194 u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
195 u8 cck_n_rx = 1;
196
197 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
198 PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
199
200 /*@r_mrx & r_cca_mrc*/
201 cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
202 odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
203
204 if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) {
205 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
206 return;
207 }
208
209 cckpd_t->cck_n_rx = cck_n_rx;
210 cckpd_t->cck_pd_lv = lv;
211 cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
212
213 if (lv == CCK_PD_LV_4) {
214 cs_ratio = cckpd_t->aaa_default + 8;
215 cs_2r_offset = 5;
216 pd_th = 0xd;
217 } else if (lv == CCK_PD_LV_3) {
218 cs_ratio = cckpd_t->aaa_default + 6;
219 cs_2r_offset = 4;
220 pd_th = 0xd;
221 } else if (lv == CCK_PD_LV_2) {
222 cs_ratio = cckpd_t->aaa_default + 4;
223 cs_2r_offset = 3;
224 pd_th = 0xd;
225 } else if (lv == CCK_PD_LV_1) {
226 cs_ratio = cckpd_t->aaa_default + 2;
227 cs_2r_offset = 1;
228 pd_th = 0x7;
229 } else if (lv == CCK_PD_LV_0) {
230 cs_ratio = cckpd_t->aaa_default;
231 cs_2r_offset = 0;
232 pd_th = 0x3;
233 }
234
235 if (cckpd_t->cck_n_rx == 2) {
236 if (cs_ratio >= cs_2r_offset)
237 cs_ratio = cs_ratio - cs_2r_offset;
238 else
239 cs_ratio = 0;
240 }
241 phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
242 }
243
244 #if 0
245 void phydm_set_cckpd_lv_type2_bcn(void *dm_void, enum cckpd_lv lv)
246 {
247 struct dm_struct *dm = (struct dm_struct *)dm_void;
248 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
249 u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
250 u8 cck_n_rx = 1;
251 u8 cs_ratio_pre = 0;
252 u8 bcn_cnt = dm->phy_dbg_info.beacon_cnt_in_period; //BCN CNT
253 u8 ofst = 0;
254 u8 ofst_direc = 0; //0:+, 1:-
255
256 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
257 PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
258
259 /*@r_mrx & r_cca_mrc*/
260 cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
261 odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
262 cs_ratio_pre = (u8)((odm_get_bb_reg(dm, R_0xaa8, 0x1f0000)));
263 PHYDM_DBG(dm, DBG_CCKPD, "BCN: %d, pre CS ratio: 0x%x\n", bcn_cnt,
264 cs_ratio_pre);
265
266 if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx &&
267 (bcn_cnt >= 10 && bcn_cnt < 14)) {
268 PHYDM_DBG(dm, DBG_CCKPD, "BCN ok, stay lv=%d, cs ratio=0x%x\n",
269 lv, cs_ratio_pre);
270 return;
271 }
272
273 cckpd_t->cck_n_rx = cck_n_rx;
274 cckpd_t->cck_pd_lv = lv;
275 cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
276
277 if (lv == CCK_PD_LV_4) {
278 cs_ratio = cckpd_t->aaa_default + 8;
279 cs_2r_offset = 5;
280 pd_th = 0xd;
281 } else if (lv == CCK_PD_LV_3) {
282 cs_ratio = cckpd_t->aaa_default + 6;
283 cs_2r_offset = 4;
284 pd_th = 0xd;
285 } else if (lv == CCK_PD_LV_2) {
286 cs_ratio = cckpd_t->aaa_default + 4;
287 cs_2r_offset = 3;
288 pd_th = 0xd;
289 } else if (lv == CCK_PD_LV_1) {
290 cs_ratio = cckpd_t->aaa_default + 2;
291 cs_2r_offset = 1;
292 pd_th = 0x7;
293 } else if (lv == CCK_PD_LV_0) {
294 cs_ratio = cckpd_t->aaa_default;
295 cs_2r_offset = 0;
296 pd_th = 0x3;
297 }
298
299 if (cckpd_t->cck_n_rx == 2) {
300 if (cs_ratio >= cs_2r_offset)
301 cs_ratio = cs_ratio - cs_2r_offset;
302 else
303 cs_ratio = 0;
304 }
305
306 if (bcn_cnt >= 18) {
307 ofst_direc = 0;
308 ofst = 0x2;
309 } else if (bcn_cnt >= 14) {
310 ofst_direc = 0;
311 ofst = 0x1;
312 } else if (bcn_cnt >= 10) {
313 ofst_direc = 0;
314 ofst = 0x0;
315 } else if (bcn_cnt >= 5) {
316 ofst_direc = 1;
317 ofst = 0x3;
318 } else {
319 ofst_direc = 1;
320 ofst = 0x4;
321 }
322 PHYDM_DBG(dm, DBG_CCKPD, "bcn:(%d), ofst:(%s%d)\n", bcn_cnt,
323 ((ofst_direc) ? "-" : "+"), ofst);
324
325 if (ofst_direc == 0)
326 cs_ratio = cs_ratio + ofst;
327 else
328 cs_ratio = cs_ratio - ofst;
329
330 if (cs_ratio == cs_ratio_pre) {
331 PHYDM_DBG(dm, DBG_CCKPD, "Same cs ratio, lv=%d cs_ratio=0x%x\n",
332 lv, cs_ratio);
333 return;
334 }
335 phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
336 }
337 #endif
338
phydm_cckpd_type2(void * dm_void)339 void phydm_cckpd_type2(void *dm_void)
340 {
341 struct dm_struct *dm = (struct dm_struct *)dm_void;
342 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
343 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
344 enum cckpd_lv lv = CCK_PD_LV_INIT;
345 u8 igi = dig_t->cur_ig_value;
346 u8 rssi_min = dm->rssi_min;
347 boolean is_update = true;
348
349 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
350
351 if (dm->is_linked) {
352 if (igi > 0x38 && rssi_min > 32) {
353 lv = CCK_PD_LV_4;
354 } else if (igi > 0x2a && rssi_min > 32) {
355 lv = CCK_PD_LV_3;
356 } else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) {
357 lv = CCK_PD_LV_2;
358 } else if (igi <= 0x24 || rssi_min < 22) {
359 if (cckpd_t->cck_fa_ma > 1000) {
360 lv = CCK_PD_LV_1;
361 } else if (cckpd_t->cck_fa_ma < 500) {
362 lv = CCK_PD_LV_0;
363 } else {
364 is_update = false;
365 }
366 } else {
367 is_update = false;
368 }
369 } else {
370 if (cckpd_t->cck_fa_ma > 1000) {
371 lv = CCK_PD_LV_1;
372 } else if (cckpd_t->cck_fa_ma < 500) {
373 lv = CCK_PD_LV_0;
374 } else {
375 is_update = false;
376 }
377 }
378
379 /*[Abnormal case] =================================================*/
380 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
381 /*@21C Miracast lag issue & [PCIE-3298]*/
382 if (dm->support_ic_type & ODM_RTL8821C && rssi_min > 60) {
383 lv = CCK_PD_LV_4;
384 cckpd_t->cck_pd_lv = lv;
385 phydm_write_cck_pd_type2(dm, 0x1d, (cckpd_t->aaa_default + 8));
386 is_update = false;
387 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
388 }
389 #endif
390 /*=================================================================*/
391
392 if (is_update) {
393 phydm_set_cckpd_lv_type2(dm, lv);
394 }
395
396 PHYDM_DBG(dm, DBG_CCKPD,
397 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
398 dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx,
399 cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres);
400 }
401 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/
402
403 #ifdef PHYDM_COMPILE_CCKPD_TYPE3
phydm_write_cck_pd_type3(void * dm_void,u8 pd_th,u8 cs_ratio,enum cckpd_mode mode)404 void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio,
405 enum cckpd_mode mode)
406 {
407 struct dm_struct *dm = (struct dm_struct *)dm_void;
408 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
409
410 PHYDM_DBG(dm, DBG_CCKPD,
411 "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__,
412 mode, pd_th, cs_ratio);
413
414 switch (mode) {
415 case CCK_BW20_1R: /*RFBW20_1R*/
416 {
417 cckpd_t->cur_cck_pd_20m_1r = pd_th;
418 cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio;
419 odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th);
420 odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio);
421 } break;
422 case CCK_BW20_2R: /*RFBW20_2R*/
423 {
424 cckpd_t->cur_cck_pd_20m_2r = pd_th;
425 cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio;
426 odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th);
427 odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio);
428 } break;
429 case CCK_BW40_1R: /*RFBW40_1R*/
430 {
431 cckpd_t->cur_cck_pd_40m_1r = pd_th;
432 cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio;
433 odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th);
434 odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio);
435 } break;
436 case CCK_BW40_2R: /*RFBW40_2R*/
437 {
438 cckpd_t->cur_cck_pd_40m_2r = pd_th;
439 cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio;
440 odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th);
441 odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio);
442 } break;
443
444 default:
445 /*@pr_debug("[%s] warning!\n", __func__);*/
446 break;
447 }
448 }
449
phydm_set_cckpd_lv_type3(void * dm_void,enum cckpd_lv lv)450 void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv)
451 {
452 struct dm_struct *dm = (struct dm_struct *)dm_void;
453 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
454 enum cckpd_mode cck_mode = CCK_BW20_2R;
455 enum channel_width cck_bw = CHANNEL_WIDTH_20;
456 u8 cck_n_rx = 1;
457 u8 pd_th;
458 u8 cs_ratio;
459
460 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
461 PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
462
463 /*[Check Nrx]*/
464 cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1;
465
466 /*[Check BW]*/
467 if (odm_get_bb_reg(dm, R_0x800, BIT(0)))
468 cck_bw = CHANNEL_WIDTH_40;
469 else
470 cck_bw = CHANNEL_WIDTH_20;
471
472 /*[Check LV]*/
473 if (cckpd_t->cck_pd_lv == lv &&
474 cckpd_t->cck_n_rx == cck_n_rx &&
475 cckpd_t->cck_bw == cck_bw) {
476 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
477 return;
478 }
479
480 cckpd_t->cck_bw = cck_bw;
481 cckpd_t->cck_n_rx = cck_n_rx;
482 cckpd_t->cck_pd_lv = lv;
483 cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
484
485 if (cck_n_rx == 2) {
486 if (cck_bw == CHANNEL_WIDTH_20) {
487 pd_th = cckpd_t->cck_pd_20m_2r;
488 cs_ratio = cckpd_t->cck_cs_ratio_20m_2r;
489 cck_mode = CCK_BW20_2R;
490 } else {
491 pd_th = cckpd_t->cck_pd_40m_2r;
492 cs_ratio = cckpd_t->cck_cs_ratio_40m_2r;
493 cck_mode = CCK_BW40_2R;
494 }
495 } else {
496 if (cck_bw == CHANNEL_WIDTH_20) {
497 pd_th = cckpd_t->cck_pd_20m_1r;
498 cs_ratio = cckpd_t->cck_cs_ratio_20m_1r;
499 cck_mode = CCK_BW20_1R;
500 } else {
501 pd_th = cckpd_t->cck_pd_40m_1r;
502 cs_ratio = cckpd_t->cck_cs_ratio_40m_1r;
503 cck_mode = CCK_BW40_1R;
504 }
505 }
506
507 if (lv == CCK_PD_LV_4) {
508 if (cck_n_rx == 2) {
509 pd_th += 4;
510 cs_ratio += 2;
511 } else {
512 pd_th += 4;
513 cs_ratio += 3;
514 }
515 } else if (lv == CCK_PD_LV_3) {
516 if (cck_n_rx == 2) {
517 pd_th += 3;
518 cs_ratio += 1;
519 } else {
520 pd_th += 3;
521 cs_ratio += 2;
522 }
523 } else if (lv == CCK_PD_LV_2) {
524 pd_th += 2;
525 cs_ratio += 1;
526 } else if (lv == CCK_PD_LV_1) {
527 pd_th += 1;
528 cs_ratio += 1;
529 }
530
531 phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode);
532 }
533
phydm_cckpd_type3(void * dm_void)534 void phydm_cckpd_type3(void *dm_void)
535 {
536 struct dm_struct *dm = (struct dm_struct *)dm_void;
537 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
538 enum cckpd_lv lv = CCK_PD_LV_INIT;
539 u8 igi = dm->dm_dig_table.cur_ig_value;
540 boolean is_update = true;
541 u8 pd_th = 0;
542 u8 cs_ratio = 0;
543
544 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
545
546 if (dm->is_linked) {
547 if (igi > 0x38 && dm->rssi_min > 32) {
548 lv = CCK_PD_LV_4;
549 } else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
550 lv = CCK_PD_LV_3;
551 } else if ((igi > 0x24) ||
552 (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
553 lv = CCK_PD_LV_2;
554 } else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
555 if (cckpd_t->cck_fa_ma > 1000)
556 lv = CCK_PD_LV_1;
557 else if (cckpd_t->cck_fa_ma < 500)
558 lv = CCK_PD_LV_0;
559 else
560 is_update = false;
561 }
562 if ((dm->anti_interference_en != NULL) && (*dm->anti_interference_en == 1)) {
563 if (igi >= 0x20 && dm->rssi_min >= 27 && (igi - dm->rssi_min < 10)) {
564 //printf(">>>>>TUYA CCK FA CNT = %d, RSSI = %d, IGI =%d \n", cckpd_t->cck_fa_ma, dm->rssi_min, igi);
565 is_update = false;
566 odm_set_bb_reg(dm, R_0xa08, BIT(21) | BIT(20), 0x2);
567 //odm_set_bb_reg(dm, R_0xac8, 0xff, 0x18);
568 }
569 else {
570 //printf("CCK FA CNT = %d, RSSI = %d, IGI =%d \n", cckpd_t->cck_fa_ma, dm->rssi_min, igi);
571 odm_set_bb_reg(dm, R_0xa08, BIT(21) | BIT(20), cckpd_t->cck_din_shift_opt);
572 //odm_set_bb_reg(dm, R_0xac8, 0xff, cckpd_t->cck_pd_20m_1r);
573 }
574 }
575 } else {
576 if (cckpd_t->cck_fa_ma > 1000)
577 lv = CCK_PD_LV_1;
578 else if (cckpd_t->cck_fa_ma < 500)
579 lv = CCK_PD_LV_0;
580 else
581 is_update = false;
582 }
583
584 if (is_update)
585 phydm_set_cckpd_lv_type3(dm, lv);
586
587 if (cckpd_t->cck_n_rx == 2) {
588 if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
589 pd_th = cckpd_t->cur_cck_pd_20m_2r;
590 cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r;
591 } else {
592 pd_th = cckpd_t->cur_cck_pd_40m_2r;
593 cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r;
594 }
595 } else {
596 if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
597 pd_th = cckpd_t->cur_cck_pd_20m_1r;
598 cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r;
599 } else {
600 pd_th = cckpd_t->cur_cck_pd_40m_1r;
601 cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r;
602 }
603 }
604 PHYDM_DBG(dm, DBG_CCKPD,
605 "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
606 cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked,
607 cckpd_t->cck_pd_lv, cs_ratio, pd_th);
608 }
609
phydm_cck_pd_init_type3(void * dm_void)610 void phydm_cck_pd_init_type3(void *dm_void)
611 {
612 struct dm_struct *dm = (struct dm_struct *)dm_void;
613 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
614 u32 reg_tmp = 0;
615
616 /*Get Default value*/
617 cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff);
618 cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00);
619 cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff);
620 cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00);
621 cckpd_t->cck_din_shift_opt = (u8)odm_get_bb_reg(dm, R_0xa08, BIT(21) | BIT(20));
622
623 reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD);
624 cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f);
625 cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);
626 cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);
627 cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);
628 }
629 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/
630
631 #ifdef PHYDM_COMPILE_CCKPD_TYPE4
phydm_write_cck_pd_type4(void * dm_void,enum cckpd_lv lv,enum cckpd_mode mode)632 void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv,
633 enum cckpd_mode mode)
634 {
635 struct dm_struct *dm = (struct dm_struct *)dm_void;
636 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
637 u32 val = 0;
638
639 PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
640 switch (mode) {
641 case CCK_BW20_1R: /*RFBW20_1R*/
642 {
643 val = cckpd_t->cckpd_jgr3[0][0][0][lv];
644 odm_set_bb_reg(dm, R_0x1ac8, 0xff, val);
645 val = cckpd_t->cckpd_jgr3[0][0][1][lv];
646 odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val);
647 } break;
648 case CCK_BW40_1R: /*RFBW40_1R*/
649 {
650 val = cckpd_t->cckpd_jgr3[1][0][0][lv];
651 odm_set_bb_reg(dm, R_0x1acc, 0xff, val);
652 val = cckpd_t->cckpd_jgr3[1][0][1][lv];
653 odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val);
654 } break;
655 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
656 case CCK_BW20_2R: /*RFBW20_2R*/
657 {
658 val = cckpd_t->cckpd_jgr3[0][1][0][lv];
659 odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val);
660 val = cckpd_t->cckpd_jgr3[0][1][1][lv];
661 odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val);
662 } break;
663 case CCK_BW40_2R: /*RFBW40_2R*/
664 {
665 val = cckpd_t->cckpd_jgr3[1][1][0][lv];
666 odm_set_bb_reg(dm, R_0x1acc, 0xff00, val);
667 val = cckpd_t->cckpd_jgr3[1][1][1][lv];
668 odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val);
669 } break;
670 #endif
671 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
672 case CCK_BW20_3R: /*RFBW20_3R*/
673 {
674 val = cckpd_t->cckpd_jgr3[0][2][0][lv];
675 odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val);
676 val = cckpd_t->cckpd_jgr3[0][2][1][lv];
677 odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val);
678 } break;
679 case CCK_BW40_3R: /*RFBW40_3R*/
680 {
681 val = cckpd_t->cckpd_jgr3[1][2][0][lv];
682 odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val);
683 val = cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x3;
684 odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val);
685 val = (cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x1c) >> 2;
686 odm_set_bb_reg(dm, R_0x1ad4, 0x7, val);
687 } break;
688 #endif
689 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
690 case CCK_BW20_4R: /*RFBW20_4R*/
691 {
692 val = cckpd_t->cckpd_jgr3[0][3][0][lv];
693 odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val);
694 val = cckpd_t->cckpd_jgr3[0][3][1][lv];
695 odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val);
696 } break;
697 case CCK_BW40_4R: /*RFBW40_4R*/
698 {
699 val = cckpd_t->cckpd_jgr3[1][3][0][lv];
700 odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val);
701 val = cckpd_t->cckpd_jgr3[1][3][1][lv];
702 odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val);
703 } break;
704 #endif
705 default:
706 /*@pr_debug("[%s] warning!\n", __func__);*/
707 break;
708 }
709 }
710
phydm_set_cck_pd_lv_type4(void * dm_void,enum cckpd_lv lv)711 void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)
712 {
713 struct dm_struct *dm = (struct dm_struct *)dm_void;
714 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
715 enum cckpd_mode cck_mode = CCK_BW20_2R;
716 enum channel_width cck_bw = CHANNEL_WIDTH_20;
717 u8 cck_n_rx = 0;
718 u32 val = 0;
719 /*u32 val_dbg = 0;*/
720
721 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
722 PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
723
724 /*[Check Nrx]*/
725 cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
726
727 /*[Check BW]*/
728 val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
729 if (val == 0)
730 cck_bw = CHANNEL_WIDTH_20;
731 else if (val == 1)
732 cck_bw = CHANNEL_WIDTH_40;
733 else
734 cck_bw = CHANNEL_WIDTH_80;
735
736 /*[Check LV]*/
737 if (cckpd_t->cck_pd_lv == lv &&
738 cckpd_t->cck_n_rx == cck_n_rx &&
739 cckpd_t->cck_bw == cck_bw) {
740 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
741 return;
742 }
743
744 cckpd_t->cck_bw = cck_bw;
745 cckpd_t->cck_n_rx = cck_n_rx;
746 cckpd_t->cck_pd_lv = lv;
747 cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
748
749 switch (cck_n_rx) {
750 case 1: /*1R*/
751 {
752 if (cck_bw == CHANNEL_WIDTH_20)
753 cck_mode = CCK_BW20_1R;
754 else if (cck_bw == CHANNEL_WIDTH_40)
755 cck_mode = CCK_BW40_1R;
756 } break;
757 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
758 case 2: /*2R*/
759 {
760 if (cck_bw == CHANNEL_WIDTH_20)
761 cck_mode = CCK_BW20_2R;
762 else if (cck_bw == CHANNEL_WIDTH_40)
763 cck_mode = CCK_BW40_2R;
764 } break;
765 #endif
766 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
767 case 3: /*3R*/
768 {
769 if (cck_bw == CHANNEL_WIDTH_20)
770 cck_mode = CCK_BW20_3R;
771 else if (cck_bw == CHANNEL_WIDTH_40)
772 cck_mode = CCK_BW40_3R;
773 } break;
774 #endif
775 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
776 case 4: /*4R*/
777 {
778 if (cck_bw == CHANNEL_WIDTH_20)
779 cck_mode = CCK_BW20_4R;
780 else if (cck_bw == CHANNEL_WIDTH_40)
781 cck_mode = CCK_BW40_4R;
782 } break;
783 #endif
784 default:
785 /*@pr_debug("[%s] warning!\n", __func__);*/
786 break;
787 }
788 phydm_write_cck_pd_type4(dm, lv, cck_mode);
789 }
790
phydm_read_cckpd_para_type4(void * dm_void)791 void phydm_read_cckpd_para_type4(void *dm_void)
792 {
793 struct dm_struct *dm = (struct dm_struct *)dm_void;
794 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
795 u8 bw = 0; /*r_RX_RF_BW*/
796 u8 n_rx = 0;
797 u8 curr_cck_pd_t[2][4][2];
798 u32 reg0 = 0;
799 u32 reg1 = 0;
800 u32 reg2 = 0;
801 u32 reg3 = 0;
802
803 if (!(dm->debug_components & DBG_CCKPD))
804 return;
805
806 bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
807 n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
808
809 reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
810 reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
811 reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
812 reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
813 curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff);
814 curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff);
815 curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
816 curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20);
817 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
818 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
819 curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8);
820 curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8);
821 curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
822 curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25);
823 }
824 #endif
825 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
826 if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
827 curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16);
828 curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16);
829 curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
830 curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) |
831 (u8)((reg3 & 0x00000007) << 2);
832 }
833 #endif
834 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
835 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
836 curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24);
837 curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24);
838 curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
839 curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3);
840 }
841 #endif
842
843 PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
844 PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n",
845 cckpd_t->cck_pd_lv,
846 curr_cck_pd_t[bw][n_rx - 1][1],
847 curr_cck_pd_t[bw][n_rx - 1][0]);
848 }
849
phydm_cckpd_type4(void * dm_void)850 void phydm_cckpd_type4(void *dm_void)
851 {
852 struct dm_struct *dm = (struct dm_struct *)dm_void;
853 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
854 u8 igi = dm->dm_dig_table.cur_ig_value;
855 enum cckpd_lv lv = 0;
856 boolean is_update = true;
857
858 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
859
860 if (dm->is_linked) {
861 PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
862 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
863 if (dm->rssi_min > 40) {
864 lv = CCK_PD_LV_4;
865 PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
866 } else if (dm->rssi_min > 32) {
867 lv = CCK_PD_LV_3;
868 PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
869 } else if (dm->rssi_min > 24) {
870 lv = CCK_PD_LV_2;
871 PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
872 } else {
873 if (cckpd_t->cck_fa_ma > 1000) {
874 lv = CCK_PD_LV_1;
875 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
876 } else if (cckpd_t->cck_fa_ma < 500) {
877 lv = CCK_PD_LV_0;
878 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
879 } else {
880 is_update = false;
881 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
882 }
883 }
884 #else /*ODM_AP*/
885 if (igi > 0x38 && dm->rssi_min > 32) {
886 lv = CCK_PD_LV_4;
887 PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
888 } else if (igi > 0x2a && dm->rssi_min > 32) {
889 lv = CCK_PD_LV_3;
890 PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
891 } else if (igi > 0x24 || dm->rssi_min > 24) {
892 lv = CCK_PD_LV_2;
893 PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
894 } else {
895 if (cckpd_t->cck_fa_ma > 1000) {
896 lv = CCK_PD_LV_1;
897 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
898 } else if (cckpd_t->cck_fa_ma < 500) {
899 lv = CCK_PD_LV_0;
900 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
901 } else {
902 is_update = false;
903 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
904 }
905 }
906 #endif
907 } else {
908 PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
909 if (cckpd_t->cck_fa_ma > 1000) {
910 lv = CCK_PD_LV_1;
911 PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
912 } else if (cckpd_t->cck_fa_ma < 500) {
913 lv = CCK_PD_LV_0;
914 PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
915 } else {
916 is_update = false;
917 PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
918 }
919 }
920
921 if (is_update) {
922 phydm_set_cck_pd_lv_type4(dm, lv);
923
924 PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
925 cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
926 [cckpd_t->cck_n_rx - 1][1][lv],
927 cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
928 [cckpd_t->cck_n_rx - 1][0][lv]);
929 }
930 phydm_read_cckpd_para_type4(dm);
931 }
932
phydm_cck_pd_init_type4(void * dm_void)933 void phydm_cck_pd_init_type4(void *dm_void)
934 {
935 struct dm_struct *dm = (struct dm_struct *)dm_void;
936 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
937 u32 reg0 = 0;
938 u32 reg1 = 0;
939 u32 reg2 = 0;
940 u32 reg3 = 0;
941 u8 pw_step = 0;
942 u8 cs_step = 0;
943 u8 cck_bw = 0; /*r_RX_RF_BW*/
944 u8 cck_n_rx = 0;
945 u8 val = 0;
946 u8 i = 0;
947
948 PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
949
950 #if 0
951 /*@
952 *cckpd_t[0][0][0][0] = 1ac8[7:0] r_PD_lim_RFBW20_1R
953 *cckpd_t[0][1][0][0] = 1ac8[15:8] r_PD_lim_RFBW20_2R
954 *cckpd_t[0][2][0][0] = 1ac8[23:16] r_PD_lim_RFBW20_3R
955 *cckpd_t[0][3][0][0] = 1ac8[31:24] r_PD_lim_RFBW20_4R
956 *cckpd_t[1][0][0][0] = 1acc[7:0] r_PD_lim_RFBW40_1R
957 *cckpd_t[1][1][0][0] = 1acc[15:8] r_PD_lim_RFBW40_2R
958 *cckpd_t[1][2][0][0] = 1acc[23:16] r_PD_lim_RFBW40_3R
959 *cckpd_t[1][3][0][0] = 1acc[31:24] r_PD_lim_RFBW40_4R
960 *
961 *
962 *cckpd_t[0][0][1][0] = 1ad0[4:0] r_CS_ratio_RFBW20_1R[4:0]
963 *cckpd_t[0][1][1][0] = 1ad0[9:5] r_CS_ratio_RFBW20_2R[4:0]
964 *cckpd_t[0][2][1][0] = 1ad0[14:10] r_CS_ratio_RFBW20_3R[4:0]
965 *cckpd_t[0][3][1][0] = 1ad0[19:15] r_CS_ratio_RFBW20_4R[4:0]
966 *cckpd_t[1][0][1][0] = 1ad0[24:20] r_CS_ratio_RFBW40_1R[4:0]
967 *cckpd_t[1][1][1][0] = 1ad0[29:25] r_CS_ratio_RFBW40_2R[4:0]
968 *cckpd_t[1][2][1][0] = 1ad0[31:30] r_CS_ratio_RFBW40_3R[1:0]
969 * 1ad4[2:0] r_CS_ratio_RFBW40_3R[4:2]
970 *cckpd_t[1][3][1][0] = 1ad4[7:3] r_CS_ratio_RFBW40_4R[4:0]
971 */
972 #endif
973 /*[Check Nrx]*/
974 cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
975
976 /*[Check BW]*/
977 val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
978 if (val == 0)
979 cck_bw = CHANNEL_WIDTH_20;
980 else if (val == 1)
981 cck_bw = CHANNEL_WIDTH_40;
982 else
983 cck_bw = CHANNEL_WIDTH_80;
984
985 cckpd_t->cck_bw = cck_bw;
986 cckpd_t->cck_n_rx = cck_n_rx;
987 reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
988 reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
989 reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
990 reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
991
992 for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
993 pw_step = i * 2;
994 cs_step = i * 2;
995
996 #if (RTL8197G_SUPPORT)
997 if (dm->support_ic_type & ODM_RTL8197G) {
998 pw_step = i;
999 cs_step = i;
1000 if (i > CCK_PD_LV_3) {
1001 pw_step = 3;
1002 cs_step = 3;
1003 }
1004 }
1005 #endif
1006
1007 #if (RTL8822C_SUPPORT)
1008 if (dm->support_ic_type & ODM_RTL8822C) {
1009 if (i == CCK_PD_LV_1) {
1010 pw_step = 9; /*IGI-19.2:0x11=d'17*/
1011 cs_step = 0;
1012 } else if (i == CCK_PD_LV_2) {
1013 pw_step = 12; /*IGI-15.5:0x14=d'20*/
1014 cs_step = 1;
1015 } else if (i == CCK_PD_LV_3) {
1016 pw_step = 14; /*IGI-14:0x16=d'22*/
1017 cs_step = 1;
1018 } else if (i == CCK_PD_LV_4) {
1019 pw_step = 17; /*IGI-12:0x19=d'25*/
1020 cs_step = 1;
1021 }
1022 }
1023 #endif
1024
1025 val = (u8)(reg0 & 0x000000ff) + pw_step;
1026 PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
1027 cckpd_t->cckpd_jgr3[0][0][0][i] = val;
1028
1029 val = (u8)(reg1 & 0x000000ff) + pw_step;
1030 cckpd_t->cckpd_jgr3[1][0][0][i] = val;
1031
1032 val = (u8)(reg2 & 0x0000001f) + cs_step;
1033 cckpd_t->cckpd_jgr3[0][0][1][i] = val;
1034
1035 val = (u8)((reg2 & 0x01f00000) >> 20) + cs_step;
1036 cckpd_t->cckpd_jgr3[1][0][1][i] = val;
1037
1038 #ifdef PHYDM_COMPILE_ABOVE_2SS
1039 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
1040 val = (u8)((reg0 & 0x0000ff00) >> 8) + pw_step;
1041 cckpd_t->cckpd_jgr3[0][1][0][i] = val;
1042
1043 val = (u8)((reg1 & 0x0000ff00) >> 8) + pw_step;
1044 cckpd_t->cckpd_jgr3[1][1][0][i] = val;
1045
1046 val = (u8)((reg2 & 0x000003e0) >> 5) + cs_step;
1047 cckpd_t->cckpd_jgr3[0][1][1][i] = val;
1048
1049 val = (u8)((reg2 & 0x3e000000) >> 25) + cs_step;
1050 cckpd_t->cckpd_jgr3[1][1][1][i] = val;
1051 }
1052 #endif
1053
1054 #ifdef PHYDM_COMPILE_ABOVE_3SS
1055 if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
1056 val = (u8)((reg0 & 0x00ff0000) >> 16) + pw_step;
1057 cckpd_t->cckpd_jgr3[0][2][0][i] = val;
1058
1059 val = (u8)((reg1 & 0x00ff0000) >> 16) + pw_step;
1060 cckpd_t->cckpd_jgr3[1][2][0][i] = val;
1061 val = (u8)((reg2 & 0x00007c00) >> 10) + cs_step;
1062 cckpd_t->cckpd_jgr3[0][2][1][i] = val;
1063 val = (u8)(((reg2 & 0xc0000000) >> 30) |
1064 ((reg3 & 0x7) << 3)) + cs_step;
1065 cckpd_t->cckpd_jgr3[1][2][1][i] = val;
1066 }
1067 #endif
1068
1069 #ifdef PHYDM_COMPILE_ABOVE_4SS
1070 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
1071 val = (u8)((reg0 & 0xff000000) >> 24) + pw_step;
1072 cckpd_t->cckpd_jgr3[0][3][0][i] = val;
1073
1074 val = (u8)((reg1 & 0xff000000) >> 24) + pw_step;
1075 cckpd_t->cckpd_jgr3[1][3][0][i] = val;
1076
1077 val = (u8)((reg2 & 0x000f8000) >> 15) + cs_step;
1078 cckpd_t->cckpd_jgr3[0][3][1][i] = val;
1079
1080 val = (u8)((reg3 & 0x000000f8) >> 3) + cs_step;
1081 cckpd_t->cckpd_jgr3[1][3][1][i] = val;
1082 }
1083 #endif
1084 }
1085 }
1086
phydm_invalid_cckpd_type4(void * dm_void)1087 void phydm_invalid_cckpd_type4(void *dm_void)
1088 {
1089 struct dm_struct *dm = (struct dm_struct *)dm_void;
1090 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1091 u8 val = 0;
1092 u8 i = 0;
1093 u8 j = 0;
1094 u8 k = 0;
1095
1096 PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
1097
1098 for (i = 0; i < CCK_PD_LV_MAX; i++) {
1099 for (j = 0; j < 2; j++) {
1100 for (k = 0; k < dm->num_rf_path; k++) {
1101 val = cckpd_t->cckpd_jgr3[j][k][1][i];
1102 if (val == INVALID_CS_RATIO_0)
1103 cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1c;
1104 else if (val == INVALID_CS_RATIO_1)
1105 cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1e;
1106 else if (val > MAXVALID_CS_RATIO)
1107 cckpd_t->cckpd_jgr3[j][k][1][i] =
1108 MAXVALID_CS_RATIO;
1109 }
1110 }
1111
1112 #if (RTL8198F_SUPPORT)
1113 if (dm->support_ic_type & ODM_RTL8198F) {
1114 val = cckpd_t->cckpd_jgr3[0][3][1][i];
1115 if (i == CCK_PD_LV_1 && val > 0x10)
1116 cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
1117 else if (i == CCK_PD_LV_2 && val > 0x10)
1118 cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
1119 else if (i == CCK_PD_LV_3 && val > 0x10)
1120 cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
1121 else if (i == CCK_PD_LV_4 && val > 0x10)
1122 cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
1123 val = cckpd_t->cckpd_jgr3[1][3][1][i];
1124 if (i == CCK_PD_LV_1 && val > 0xF)
1125 cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
1126 else if (i == CCK_PD_LV_2 && val > 0xF)
1127 cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
1128 else if (i == CCK_PD_LV_3 && val > 0xF)
1129 cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
1130 else if (i == CCK_PD_LV_4 && val > 0xF)
1131 cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
1132 }
1133 #endif
1134 }
1135 }
1136
1137 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/
1138
1139
1140 #ifdef PHYDM_COMPILE_CCKPD_TYPE5
phydm_write_cck_pd_type5(void * dm_void,enum cckpd_lv lv,enum cckpd_mode mode)1141 void phydm_write_cck_pd_type5(void *dm_void, enum cckpd_lv lv,
1142 enum cckpd_mode mode)
1143 {
1144 struct dm_struct *dm = (struct dm_struct *)dm_void;
1145 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1146 u32 val = 0;
1147
1148 PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
1149 switch (mode) {
1150 case CCK_BW20_1R: /*RFBW20_1R*/
1151 {
1152 val = cckpd_t->cck_pd_table_jgr3[0][0][0][lv];
1153 odm_set_bb_reg(dm, R_0x1a30, 0x1f, val);
1154 val = cckpd_t->cck_pd_table_jgr3[0][0][1][lv];
1155 odm_set_bb_reg(dm, R_0x1a20, 0x1f, val);
1156 } break;
1157 case CCK_BW40_1R: /*RFBW40_1R*/
1158 {
1159 val = cckpd_t->cck_pd_table_jgr3[1][0][0][lv];
1160 odm_set_bb_reg(dm, R_0x1a34, 0x1f, val);
1161 val = cckpd_t->cck_pd_table_jgr3[1][0][1][lv];
1162 odm_set_bb_reg(dm, R_0x1a24, 0x1f, val);
1163 } break;
1164 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1165 case CCK_BW20_2R: /*RFBW20_2R*/
1166 {
1167 val = cckpd_t->cck_pd_table_jgr3[0][1][0][lv];
1168 odm_set_bb_reg(dm, R_0x1a30, 0x3e0, val);
1169 val = cckpd_t->cck_pd_table_jgr3[0][1][1][lv];
1170 odm_set_bb_reg(dm, R_0x1a20, 0x3e0, val);
1171 } break;
1172 case CCK_BW40_2R: /*RFBW40_2R*/
1173 {
1174 val = cckpd_t->cck_pd_table_jgr3[1][1][0][lv];
1175 odm_set_bb_reg(dm, R_0x1a34, 0x3e0, val);
1176 val = cckpd_t->cck_pd_table_jgr3[1][1][1][lv];
1177 odm_set_bb_reg(dm, R_0x1a24, 0x3e0, val);
1178 } break;
1179 #endif
1180 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1181 case CCK_BW20_3R: /*RFBW20_3R*/
1182 {
1183 val = cckpd_t->cck_pd_table_jgr3[0][2][0][lv];
1184 odm_set_bb_reg(dm, R_0x1a30, 0x7c00, val);
1185 val = cckpd_t->cck_pd_table_jgr3[0][2][1][lv];
1186 odm_set_bb_reg(dm, R_0x1a20, 0x7c00, val);
1187 } break;
1188 case CCK_BW40_3R: /*RFBW40_3R*/
1189 {
1190 val = cckpd_t->cck_pd_table_jgr3[1][2][0][lv];
1191 odm_set_bb_reg(dm, R_0x1a34, 0x7c00, val);
1192 val = cckpd_t->cck_pd_table_jgr3[1][2][1][lv];
1193 odm_set_bb_reg(dm, R_0x1a24, 0x7c00, val);
1194 } break;
1195 #endif
1196 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1197 case CCK_BW20_4R: /*RFBW20_4R*/
1198 {
1199 val = cckpd_t->cck_pd_table_jgr3[0][3][0][lv];
1200 odm_set_bb_reg(dm, R_0x1a30, 0xF8000, val);
1201 val = cckpd_t->cck_pd_table_jgr3[0][3][1][lv];
1202 odm_set_bb_reg(dm, R_0x1a20, 0xF8000, val);
1203 } break;
1204 case CCK_BW40_4R: /*RFBW40_4R*/
1205 {
1206 val = cckpd_t->cck_pd_table_jgr3[1][3][0][lv];
1207 odm_set_bb_reg(dm, R_0x1a34, 0xF8000, val);
1208 val = cckpd_t->cck_pd_table_jgr3[1][3][1][lv];
1209 odm_set_bb_reg(dm, R_0x1a24, 0xF8000, val);
1210 } break;
1211 #endif
1212 default:
1213 /*@pr_debug("[%s] warning!\n", __func__);*/
1214 break;
1215 }
1216 }
1217
1218
phydm_set_cck_pd_lv_type5(void * dm_void,enum cckpd_lv lv)1219 void phydm_set_cck_pd_lv_type5(void *dm_void, enum cckpd_lv lv)
1220 {
1221 struct dm_struct *dm = (struct dm_struct *)dm_void;
1222 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1223 enum cckpd_mode cck_mode = CCK_BW20_1R;
1224 enum channel_width cck_bw = CHANNEL_WIDTH_20;
1225 u8 cck_n_rx = 0;
1226 u32 val = 0;
1227 /*u32 val_dbg = 0;*/
1228
1229 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
1230 PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
1231
1232 /*[Check Nrx] for 8723F*/
1233 cck_n_rx = 1;
1234
1235 /*[Check BW]*/
1236 val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
1237 if (val == 0)
1238 cck_bw = CHANNEL_WIDTH_20;
1239 else if (val == 1)
1240 cck_bw = CHANNEL_WIDTH_40;
1241 else
1242 cck_bw = CHANNEL_WIDTH_80;
1243
1244 /*[Check LV]*/
1245 if (cckpd_t->cck_pd_lv == lv &&
1246 cckpd_t->cck_n_rx == cck_n_rx &&
1247 cckpd_t->cck_bw == cck_bw) {
1248 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
1249 return;
1250 }
1251 cckpd_t->cck_bw = cck_bw;
1252 cckpd_t->cck_n_rx = cck_n_rx;
1253 cckpd_t->cck_pd_lv = lv;
1254 cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
1255
1256 switch (cck_n_rx) {
1257 case 1: /*1R*/
1258 {
1259 if (cck_bw == CHANNEL_WIDTH_20)
1260 cck_mode = CCK_BW20_1R;
1261 else if (cck_bw == CHANNEL_WIDTH_40)
1262 cck_mode = CCK_BW40_1R;
1263 } break;
1264 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1265 case 2: /*2R*/
1266 {
1267 if (cck_bw == CHANNEL_WIDTH_20)
1268 cck_mode = CCK_BW20_2R;
1269 else if (cck_bw == CHANNEL_WIDTH_40)
1270 cck_mode = CCK_BW40_2R;
1271 } break;
1272 #endif
1273 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1274 case 3: /*3R*/
1275 {
1276 if (cck_bw == CHANNEL_WIDTH_20)
1277 cck_mode = CCK_BW20_3R;
1278 else if (cck_bw == CHANNEL_WIDTH_40)
1279 cck_mode = CCK_BW40_3R;
1280 } break;
1281 #endif
1282 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1283 case 4: /*4R*/
1284 {
1285 if (cck_bw == CHANNEL_WIDTH_20)
1286 cck_mode = CCK_BW20_4R;
1287 else if (cck_bw == CHANNEL_WIDTH_40)
1288 cck_mode = CCK_BW40_4R;
1289 } break;
1290 #endif
1291 default:
1292 /*@pr_debug("[%s] warning!\n", __func__);*/
1293 break;
1294 }
1295
1296
1297
1298 phydm_write_cck_pd_type5(dm, lv, cck_mode);
1299 }
1300
phydm_read_cckpd_para_type5(void * dm_void)1301 void phydm_read_cckpd_para_type5(void *dm_void)
1302 {
1303 struct dm_struct *dm = (struct dm_struct *)dm_void;
1304 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1305 u8 bw = 0; /*r_RX_RF_BW*/
1306 u8 n_rx = 0;
1307 u8 curr_cck_pd_t[2][4][2];
1308 u32 reg0 = 0;
1309 u32 reg1 = 0;
1310 u32 reg2 = 0;
1311 u32 reg3 = 0;
1312
1313 bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
1314
1315 reg0 = odm_get_bb_reg(dm, R_0x1a30, MASKDWORD);
1316 reg1 = odm_get_bb_reg(dm, R_0x1a34, MASKDWORD);
1317 reg2 = odm_get_bb_reg(dm, R_0x1a20, MASKDWORD);
1318 reg3 = odm_get_bb_reg(dm, R_0x1a24, MASKDWORD);
1319 curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x0000001f);
1320 curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x0000001f);
1321 curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
1322 curr_cck_pd_t[1][0][1] = (u8)(reg3 & 0x0000001f);
1323 n_rx = 1;
1324 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1325 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
1326 curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x000003E0) >> 5);
1327 curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x000003E0) >> 5);
1328 curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
1329 curr_cck_pd_t[1][1][1] = (u8)((reg3 & 0x000003E0) >> 5);
1330 n_rx = 2;
1331 }
1332 #endif
1333 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1334 if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
1335 curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00007C00) >> 10);
1336 curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00007C00) >> 10);
1337 curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
1338 curr_cck_pd_t[1][2][1] = (u8)((reg3 & 0x00007C00) >> 10);
1339 n_rx = 3;
1340 }
1341 #endif
1342 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1343 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
1344 curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0x000F8000) >> 15);
1345 curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0x000F8000) >> 15);
1346 curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
1347 curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000F8000) >> 15);
1348 n_rx = 4;
1349 }
1350 #endif
1351
1352 PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
1353 PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n",
1354 cckpd_t->cck_pd_lv,
1355 curr_cck_pd_t[bw][n_rx - 1][1],
1356 curr_cck_pd_t[bw][n_rx - 1][0]);
1357 }
1358
phydm_cckpd_type5(void * dm_void)1359 void phydm_cckpd_type5(void *dm_void)
1360 {
1361 struct dm_struct *dm = (struct dm_struct *)dm_void;
1362 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1363 u8 igi = dm->dm_dig_table.cur_ig_value;
1364 enum cckpd_lv lv = 0;
1365 boolean is_update = true;
1366
1367 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
1368
1369 if (dm->is_linked) {
1370 PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
1371 if (dm->rssi_min > 40) {
1372 lv = CCK_PD_LV_4;
1373 PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
1374 } else if (dm->rssi_min > 32) {
1375 lv = CCK_PD_LV_3;
1376 PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
1377 } else if (dm->rssi_min > 24) {
1378 lv = CCK_PD_LV_2;
1379 PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
1380 } else {
1381 if (cckpd_t->cck_fa_ma > 1000) {
1382 lv = CCK_PD_LV_1;
1383 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
1384 } else if (cckpd_t->cck_fa_ma < 500) {
1385 lv = CCK_PD_LV_0;
1386 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
1387 } else {
1388 is_update = false;
1389 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
1390 }
1391 }
1392 } else {
1393 PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
1394 if (cckpd_t->cck_fa_ma > 1000) {
1395 lv = CCK_PD_LV_1;
1396 PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
1397 } else if (cckpd_t->cck_fa_ma < 500) {
1398 lv = CCK_PD_LV_0;
1399 PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
1400 } else {
1401 is_update = false;
1402 PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
1403 }
1404 }
1405
1406 if (is_update) {
1407 phydm_set_cck_pd_lv_type5(dm, lv);
1408
1409 PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
1410 cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
1411 [cckpd_t->cck_n_rx - 1][1][lv],
1412 cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
1413 [cckpd_t->cck_n_rx - 1][0][lv]);
1414 }
1415
1416 phydm_read_cckpd_para_type5(dm);
1417 }
1418
phydm_cck_pd_init_type5(void * dm_void)1419 void phydm_cck_pd_init_type5(void *dm_void)
1420 {
1421 struct dm_struct *dm = (struct dm_struct *)dm_void;
1422 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1423 u32 reg0 = 0;
1424 u32 reg1 = 0;
1425 u32 reg2 = 0;
1426 u32 reg3 = 0;
1427 u8 pw_step = 0;
1428 u8 cs_step = 0;
1429 u8 cck_bw = 0; /*r_RX_RF_BW*/
1430 u8 cck_n_rx = 0;
1431 u8 val = 0;
1432 u8 i = 0;
1433
1434 PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
1435 #if 0
1436 /*@
1437 *cckpd_t[0][0][0][0] = 1a30[4:0] r_PD_lim_RFBW20_1R
1438 *cckpd_t[0][1][0][0] = 1a30[9:5] r_PD_lim_RFBW20_2R
1439 *cckpd_t[0][2][0][0] = 1a30[14:10] r_PD_lim_RFBW20_3R
1440 *cckpd_t[0][3][0][0] = 1a30[19:15] r_PD_lim_RFBW20_4R
1441 *cckpd_t[1][0][0][0] = 1a34[4:0] r_PD_lim_RFBW40_1R
1442 *cckpd_t[1][1][0][0] = 1a34[9:5] r_PD_lim_RFBW40_2R
1443 *cckpd_t[1][2][0][0] = 1a34[14:10] r_PD_lim_RFBW40_3R
1444 *cckpd_t[1][3][0][0] = 1a34[19:15] r_PD_lim_RFBW40_4R
1445 *
1446 *
1447 *cckpd_t[0][0][1][0] = 1a20[4:0] r_CS_ratio_RFBW20_1R
1448 *cckpd_t[0][1][1][0] = 1a20[9:5] r_CS_ratio_RFBW20_2R
1449 *cckpd_t[0][2][1][0] = 1a20[14:10] r_CS_ratio_RFBW20_3R
1450 *cckpd_t[0][3][1][0] = 1a20[19:15] r_CS_ratio_RFBW20_4R
1451 *cckpd_t[1][0][1][0] = 1a24[4:0] r_CS_ratio_RFBW40_1R
1452 *cckpd_t[1][1][1][0] = 1a24[9:5] r_CS_ratio_RFBW40_2R
1453 *cckpd_t[1][2][1][0] = 1a24[14:10] r_CS_ratio_RFBW40_3R
1454 *cckpd_t[1][3][1][0] = 1a24[19:15] r_CS_ratio_RFBW40_4R
1455 */
1456 #endif
1457 /*[Check Nrx]*/
1458 cck_n_rx = 1;
1459
1460 /*[Check BW]*/
1461 val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
1462 if (val == 0)
1463 cck_bw = CHANNEL_WIDTH_20;
1464 else if (val == 1)
1465 cck_bw = CHANNEL_WIDTH_40;
1466 else
1467 cck_bw = CHANNEL_WIDTH_80;
1468
1469 cckpd_t->cck_bw = cck_bw;
1470 reg0 = odm_get_bb_reg(dm, R_0x1a30, MASKDWORD);
1471 reg1 = odm_get_bb_reg(dm, R_0x1a34, MASKDWORD);
1472 reg2 = odm_get_bb_reg(dm, R_0x1a20, MASKDWORD);
1473 reg3 = odm_get_bb_reg(dm, R_0x1a24, MASKDWORD);
1474
1475 for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
1476 pw_step = i * 2;
1477 cs_step = i * 2;
1478
1479 #if (RTL8723F_SUPPORT)
1480 if (dm->support_ic_type & ODM_RTL8723F) {
1481 if (i == CCK_PD_LV_1) {
1482 pw_step = 9; /*IGI-19.2:0x11=d'17*/
1483 cs_step = 0;
1484 } else if (i == CCK_PD_LV_2) {
1485 pw_step = 12; /*IGI-15.5:0x14=d'20*/
1486 cs_step = 1;
1487 } else if (i == CCK_PD_LV_3) {
1488 pw_step = 14; /*IGI-14:0x16=d'22*/
1489 cs_step = 1;
1490 } else if (i == CCK_PD_LV_4) {
1491 pw_step = 17; /*IGI-12:0x19=d'25*/
1492 cs_step = 1;
1493 }
1494 }
1495 #endif
1496 val = (u8)(reg0 & 0x0000001F) + pw_step;
1497 PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
1498 cckpd_t->cck_pd_table_jgr3[0][0][0][i] = val;
1499
1500 val = (u8)(reg1 & 0x0000001F) + pw_step;
1501 cckpd_t->cck_pd_table_jgr3[1][0][0][i] = val;
1502
1503 val = (u8)(reg2 & 0x0000001F) + cs_step;
1504 cckpd_t->cck_pd_table_jgr3[0][0][1][i] = val;
1505
1506 val = (u8)(reg3 & 0x0000001F) + cs_step;
1507 cckpd_t->cck_pd_table_jgr3[1][0][1][i] = val;
1508
1509 #ifdef PHYDM_COMPILE_ABOVE_2SS
1510 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
1511 val = (u8)((reg0 & 0x000003E0) >> 5) + pw_step;
1512 cckpd_t->cck_pd_table_jgr3[0][1][0][i] = val;
1513
1514 val = (u8)((reg1 & 0x000003E0) >> 5) + pw_step;
1515 cckpd_t->cck_pd_table_jgr3[1][1][0][i] = val;
1516
1517 val = (u8)((reg2 & 0x000003E0) >> 5) + cs_step;
1518 cckpd_t->cck_pd_table_jgr3[0][1][1][i] = val;
1519
1520 val = (u8)((reg3 & 0x000003E0) >> 5) + cs_step;
1521 cckpd_t->cck_pd_table_jgr3[1][1][1][i] = val;
1522
1523 cck_n_rx = 2;
1524 }
1525 #endif
1526 #ifdef PHYDM_COMPILE_ABOVE_3SS
1527 if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
1528 val = (u8)((reg0 & 0x00007C00) >> 10) + pw_step;
1529 cckpd_t->cck_pd_table_jgr3[0][2][0][i] = val;
1530
1531 val = (u8)((reg1 & 0x00007C00) >> 10) + pw_step;
1532 cckpd_t->cck_pd_table_jgr3[1][2][0][i] = val;
1533
1534 val = (u8)((reg2 & 0x00007C00) >> 10) + cs_step;
1535 cckpd_t->cck_pd_table_jgr3[0][2][1][i] = val;
1536
1537 val = (u8)((reg3 & 0x00007C00) >> 10) + cs_step;
1538 cckpd_t->cck_pd_table_jgr3[1][2][1][i] = val;
1539
1540 cck_n_rx = 3;
1541 }
1542 #endif
1543
1544 #ifdef PHYDM_COMPILE_ABOVE_4SS
1545 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
1546 val = (u8)((reg0 & 0x000F8000) >> 15) + pw_step;
1547 cckpd_t->cck_pd_table_jgr3[0][3][0][i] = val;
1548
1549 val = (u8)((reg1 & 0x000F8000) >> 15) + pw_step;
1550 cckpd_t->cck_pd_table_jgr3[1][3][0][i] = val;
1551
1552 val = (u8)((reg2 & 0x000F8000) >> 15) + cs_step;
1553 cckpd_t->cck_pd_table_jgr3[0][3][1][i] = val;
1554
1555 val = (u8)((reg3 & 0x000F8000) >> 15) + cs_step;
1556 cckpd_t->cck_pd_table_jgr3[1][3][1][i] = val;
1557
1558 cck_n_rx = 4;
1559 }
1560 #endif
1561 }
1562 cckpd_t->cck_n_rx = cck_n_rx;
1563 }
1564
1565
1566
1567
1568 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE5*/
1569
1570
1571
1572
phydm_set_cckpd_val(void * dm_void,u32 * val_buf,u8 val_len)1573 void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)
1574 {
1575 struct dm_struct *dm = (struct dm_struct *)dm_void;
1576 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1577 enum cckpd_lv lv;
1578
1579 if (val_len != 1) {
1580 PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n");
1581 return;
1582 }
1583
1584 lv = (enum cckpd_lv)val_buf[0];
1585
1586 if (lv > CCK_PD_LV_4) {
1587 pr_debug("[%s] warning! lv=%d\n", __func__, lv);
1588 return;
1589 }
1590
1591 switch (cckpd_t->cckpd_hw_type) {
1592 #ifdef PHYDM_COMPILE_CCKPD_TYPE1
1593 case 1:
1594 phydm_set_cckpd_lv_type1(dm, lv);
1595 break;
1596 #endif
1597 #ifdef PHYDM_COMPILE_CCKPD_TYPE2
1598 case 2:
1599 phydm_set_cckpd_lv_type2(dm, lv);
1600 break;
1601 #endif
1602 #ifdef PHYDM_COMPILE_CCKPD_TYPE3
1603 case 3:
1604 phydm_set_cckpd_lv_type3(dm, lv);
1605 break;
1606 #endif
1607 #ifdef PHYDM_COMPILE_CCKPD_TYPE4
1608 case 4:
1609 phydm_set_cck_pd_lv_type4(dm, lv);
1610 break;
1611 #endif
1612 #ifdef PHYDM_COMPILE_CCKPD_TYPE5
1613 case 5:
1614 phydm_set_cck_pd_lv_type5(dm, lv);
1615 break;
1616 #endif
1617 default:
1618 pr_debug("[%s]warning\n", __func__);
1619 break;
1620 }
1621 }
1622
1623 boolean
phydm_stop_cck_pd_th(void * dm_void)1624 phydm_stop_cck_pd_th(void *dm_void)
1625 {
1626 struct dm_struct *dm = (struct dm_struct *)dm_void;
1627
1628 if (!(dm->support_ability & ODM_BB_FA_CNT)) {
1629 PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_FA_CNT disable\n");
1630 return true;
1631 }
1632
1633 if (!(dm->support_ability & ODM_BB_CCK_PD)) {
1634 PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_CCK_PD disable\n");
1635 return true;
1636 }
1637
1638 if (dm->pause_ability & ODM_BB_CCK_PD) {
1639 PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n",
1640 dm->pause_lv_table.lv_cckpd);
1641 return true;
1642 }
1643
1644 if (dm->is_linked && (*dm->channel > 36)) {
1645 PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel);
1646 return true;
1647 }
1648 return false;
1649 }
1650
phydm_cck_pd_th(void * dm_void)1651 void phydm_cck_pd_th(void *dm_void)
1652 {
1653 struct dm_struct *dm = (struct dm_struct *)dm_void;
1654 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1655 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1656 u32 cck_fa = fa_t->cnt_cck_fail;
1657 #ifdef PHYDM_TDMA_DIG_SUPPORT
1658 struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
1659 #endif
1660
1661 PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__);
1662
1663 if (phydm_stop_cck_pd_th(dm))
1664 return;
1665
1666 #ifdef PHYDM_TDMA_DIG_SUPPORT
1667 if (dm->original_dig_restore)
1668 cck_fa = fa_t->cnt_cck_fail;
1669 else
1670 cck_fa = fa_acc_t->cnt_cck_fail_1sec;
1671 #endif
1672
1673 if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
1674 cckpd_t->cck_fa_ma = cck_fa;
1675 else
1676 cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2;
1677
1678 PHYDM_DBG(dm, DBG_CCKPD,
1679 "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n",
1680 dm->dm_dig_table.cur_ig_value, dm->rssi_min,
1681 cck_fa, cckpd_t->cck_fa_ma);
1682
1683 switch (cckpd_t->cckpd_hw_type) {
1684 #ifdef PHYDM_COMPILE_CCKPD_TYPE1
1685 case 1:
1686 phydm_cckpd_type1(dm);
1687 break;
1688 #endif
1689 #ifdef PHYDM_COMPILE_CCKPD_TYPE2
1690 case 2:
1691 phydm_cckpd_type2(dm);
1692 break;
1693 #endif
1694 #ifdef PHYDM_COMPILE_CCKPD_TYPE3
1695 case 3:
1696 phydm_cckpd_type3(dm);
1697 break;
1698 #endif
1699 #ifdef PHYDM_COMPILE_CCKPD_TYPE4
1700 case 4:
1701 #ifdef PHYDM_DCC_ENHANCE
1702 if (dm->dm_dcc_info.dcc_en)
1703 phydm_cckpd_type4_dcc(dm);
1704 else
1705 #endif
1706 phydm_cckpd_type4(dm);
1707 break;
1708 #endif
1709 #ifdef PHYDM_COMPILE_CCKPD_TYPE5
1710 case 5:
1711 phydm_cckpd_type5(dm);
1712 break;
1713 #endif
1714 default:
1715 pr_debug("[%s]warning\n", __func__);
1716 break;
1717 }
1718 }
1719
phydm_cck_pd_init(void * dm_void)1720 void phydm_cck_pd_init(void *dm_void)
1721 {
1722 struct dm_struct *dm = (struct dm_struct *)dm_void;
1723 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1724
1725 if (*dm->mp_mode)
1726 return;
1727
1728 if (dm->support_ic_type & CCK_PD_IC_TYPE1)
1729 cckpd_t->cckpd_hw_type = 1;
1730 else if (dm->support_ic_type & CCK_PD_IC_TYPE2)
1731 cckpd_t->cckpd_hw_type = 2;
1732 else if (dm->support_ic_type & CCK_PD_IC_TYPE3)
1733 cckpd_t->cckpd_hw_type = 3;
1734 else if (dm->support_ic_type & CCK_PD_IC_TYPE4)
1735 cckpd_t->cckpd_hw_type = 4;
1736
1737 if (dm->support_ic_type & CCK_PD_IC_TYPE5)
1738 cckpd_t->cckpd_hw_type = 5;
1739
1740 PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n",
1741 __func__, cckpd_t->cckpd_hw_type);
1742
1743 cckpd_t->cck_pd_lv = CCK_PD_LV_INIT;
1744 cckpd_t->cck_n_rx = 0xff;
1745 cckpd_t->cck_bw = CHANNEL_WIDTH_MAX;
1746 cckpd_t->cck_fa_th[1] = 400;
1747 cckpd_t->cck_fa_th[0] = 200;
1748
1749 switch (cckpd_t->cckpd_hw_type) {
1750 #ifdef PHYDM_COMPILE_CCKPD_TYPE1
1751 case 1:
1752 phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_1);
1753 break;
1754 #endif
1755 #ifdef PHYDM_COMPILE_CCKPD_TYPE2
1756 case 2:
1757 cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
1758 phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_1);
1759 break;
1760 #endif
1761 #ifdef PHYDM_COMPILE_CCKPD_TYPE3
1762 case 3:
1763 phydm_cck_pd_init_type3(dm);
1764 phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_1);
1765 break;
1766 #endif
1767 #ifdef PHYDM_COMPILE_CCKPD_TYPE4
1768 case 4:
1769 phydm_cck_pd_init_type4(dm);
1770 phydm_invalid_cckpd_type4(dm);
1771 phydm_set_cck_pd_lv_type4(dm, CCK_PD_LV_1);
1772 break;
1773 #endif
1774 #ifdef PHYDM_COMPILE_CCKPD_TYPE5
1775 case 5:
1776 phydm_cck_pd_init_type5(dm);
1777 break;
1778 #endif
1779 default:
1780 pr_debug("[%s]warning\n", __func__);
1781 break;
1782 }
1783 }
1784
1785 #ifdef PHYDM_DCC_ENHANCE
1786
phydm_cckpd_type4_dcc(void * dm_void)1787 void phydm_cckpd_type4_dcc(void *dm_void)
1788 {
1789 struct dm_struct *dm = (struct dm_struct *)dm_void;
1790 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1791 enum cckpd_lv lv_curr = cckpd_t->cck_pd_lv;
1792 enum phydm_cck_pd_trend trend = CCKPD_STABLE;
1793 u8 th_ofst = 0;
1794 u16 lv_up_th, lv_down_th;
1795
1796 PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
1797
1798 if (!dm->is_linked)
1799 th_ofst = 1;
1800
1801 lv_up_th = (cckpd_t->cck_fa_th[1]) << th_ofst;
1802 lv_down_th = (cckpd_t->cck_fa_th[0]) << th_ofst;
1803
1804 PHYDM_DBG(dm, DBG_CCKPD, "th{Up, Down}: {%d, %d}\n",
1805 lv_up_th, lv_down_th);
1806
1807 if (cckpd_t->cck_fa_ma > lv_up_th) {
1808 if (lv_curr <= CCK_PD_LV_3) {
1809 lv_curr++;
1810 trend = CCKPD_INCREASING;
1811 } else {
1812 lv_curr = CCK_PD_LV_4;
1813 }
1814 } else if (cckpd_t->cck_fa_ma < lv_down_th) {
1815 if (lv_curr >= CCK_PD_LV_1) {
1816 lv_curr--;
1817 trend = CCKPD_DECREASING;
1818 } else {
1819 lv_curr = CCK_PD_LV_0;
1820 }
1821 }
1822
1823 PHYDM_DBG(dm, DBG_CCKPD, "lv: %d->%d\n", cckpd_t->cck_pd_lv, lv_curr);
1824 #if 1
1825 if (trend != CCKPD_STABLE) {
1826 phydm_set_cck_pd_lv_type4(dm, lv_curr);
1827
1828 PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
1829 cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
1830 [cckpd_t->cck_n_rx - 1][1][lv_curr],
1831 cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
1832 [cckpd_t->cck_n_rx - 1][0][lv_curr]);
1833 }
1834 phydm_read_cckpd_para_type4(dm);
1835 #endif
1836 }
1837
phydm_do_cckpd(void * dm_void)1838 boolean phydm_do_cckpd(void *dm_void)
1839 {
1840 struct dm_struct *dm = (struct dm_struct *)dm_void;
1841 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1842
1843 if (dig_t->igi_trend == DIG_INCREASING)
1844 return false;
1845
1846 return true;
1847 }
1848
phydm_dig_cckpd_coex(void * dm_void)1849 void phydm_dig_cckpd_coex(void *dm_void)
1850 {
1851 struct dm_struct *dm = (struct dm_struct *)dm_void;
1852 struct phydm_dcc_struct *dcc = &dm->dm_dcc_info;
1853
1854 if (*dm->channel > 36) {
1855 phydm_dig(dm);
1856 return;
1857 } else if (!dcc->dcc_en) {
1858 phydm_dig(dm);
1859 phydm_cck_pd_th(dm);
1860 return;
1861 }
1862
1863 dcc->dig_execute_cnt++;
1864 PHYDM_DBG(dm, DBG_CCKPD, "DCC_cnt: %d\n", dcc->dig_execute_cnt);
1865
1866 if (dcc->dig_execute_cnt % dcc->dcc_ratio) {
1867 PHYDM_DBG(dm, DBG_CCKPD, "DCC: DIG\n");
1868 phydm_dig(dm);
1869 } else {
1870 if (phydm_do_cckpd(dm)) {
1871 PHYDM_DBG(dm, DBG_CCKPD, "DCC: CCKPD\n");
1872 dcc->dcc_mode = DCC_CCK_PD;
1873 phydm_cck_pd_th(dm);
1874 } else {
1875 PHYDM_DBG(dm, DBG_CCKPD, "DCC: Boost_DIG\n");
1876 dcc->dcc_mode = DCC_DIG;
1877 phydm_dig(dm);
1878 }
1879 }
1880 }
1881
phydm_dig_cckpd_coex_init(void * dm_void)1882 void phydm_dig_cckpd_coex_init(void *dm_void)
1883 {
1884 struct dm_struct *dm = (struct dm_struct *)dm_void;
1885 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1886 struct phydm_dcc_struct *dcc = &dm->dm_dcc_info;
1887
1888 dcc->dcc_mode = DCC_DIG;
1889 dcc->dcc_en = false;
1890 dcc->dig_execute_cnt = 0;
1891 dcc->dcc_ratio = 2;
1892 }
1893
phydm_dig_cckpd_coex_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1894 void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
1895 char *output, u32 *_out_len)
1896 {
1897 struct dm_struct *dm = (struct dm_struct *)dm_void;
1898 struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1899 struct phydm_dcc_struct *dcc = &dm->dm_dcc_info;
1900 char help[] = "-h";
1901 u32 var[10] = {0};
1902 u32 used = *_used;
1903 u32 out_len = *_out_len;
1904 u8 i = 0;
1905
1906 for (i = 0; i < 3; i++) {
1907 if (input[i + 1])
1908 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
1909 }
1910
1911 if ((strcmp(input[1], help) == 0)) {
1912 PDM_SNPF(out_len, used, output + used, out_len - used,
1913 "Enable: en {0/1}\n");
1914 PDM_SNPF(out_len, used, output + used, out_len - used,
1915 "DCC_ratio: ratio {x}\n");
1916 PDM_SNPF(out_len, used, output + used, out_len - used,
1917 "threshold: th {Down_th} {Up_th}\n");
1918 } else if ((strcmp(input[1], "en") == 0)) {
1919 dcc->dcc_en = (var[1]) ? true : false;
1920 PDM_SNPF(out_len, used, output + used, out_len - used,
1921 "en=%d\n", dcc->dcc_en);
1922 } else if ((strcmp(input[1], "ratio") == 0)) {
1923 dcc->dcc_ratio = (u8)var[1];
1924 PDM_SNPF(out_len, used, output + used, out_len - used,
1925 "Ratio=%d\n", dcc->dcc_ratio);
1926 } else if ((strcmp(input[1], "th") == 0)) {
1927 cckpd_t->cck_fa_th[1] = (u16)var[2];
1928 cckpd_t->cck_fa_th[0] = (u16)var[1];
1929 PDM_SNPF(out_len, used, output + used, out_len - used,
1930 "th{Down, Up}: {%d, %d}\n",
1931 cckpd_t->cck_fa_th[0], cckpd_t->cck_fa_th[1]);
1932 }
1933
1934 *_used = used;
1935 *_out_len = out_len;
1936 }
1937
1938 #endif
1939 #endif /*#ifdef PHYDM_SUPPORT_CCKPD*/
1940
1941