1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
18 #if RT_PLATFORM == PLATFORM_MACOSX
19 #include "phydm_precomp.h"
20 #else
21 #include "../phydm_precomp.h"
22 #endif
23 #else
24 #include "../../phydm_precomp.h"
25 #endif
26
27 #if (RTL8821C_SUPPORT == 1)
halrf_rf_lna_setting_8821c(struct dm_struct * dm_void,enum halrf_lna_set type)28 void halrf_rf_lna_setting_8821c(struct dm_struct *dm_void,
29 enum halrf_lna_set type)
30 {
31 struct dm_struct *dm = (struct dm_struct *)dm_void;
32 u8 path = 0x0;
33
34 if (type == HALRF_LNA_DISABLE) {
35 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
36 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
37 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
38 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0afce);
39 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
40 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x1);
41 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
42 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
43 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0280d);
44 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x0);
45 } else if (type == HALRF_LNA_ENABLE) {
46 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
47 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
48 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
49 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x1afce);
50 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
51 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x1);
52 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
53 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
54 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0281d);
55 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x0);
56 }
57 }
58
59 boolean
get_mix_mode_tx_agc_bbs_wing_offset_8821c(void * dm_void,enum pwrtrack_method method,u8 rf_path,u8 tx_power_index_offest_upper_bound,s8 tx_power_index_offest_lower_bound)60 get_mix_mode_tx_agc_bbs_wing_offset_8821c(void *dm_void,
61 enum pwrtrack_method method,
62 u8 rf_path,
63 u8 tx_power_index_offest_upper_bound,
64 s8 tx_power_index_offest_lower_bound)
65 {
66 struct dm_struct *dm = (struct dm_struct *)dm_void;
67 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
68
69 u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
70 u8 bb_swing_lower_bound = 0;
71
72 s8 tx_agc_index = 0;
73 u8 tx_bb_swing_index = cali_info->default_ofdm_index;
74
75 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
76 "Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest_upper_bound=%d, tx_power_index_offest_lower_bound=%d\n",
77 rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
78 tx_power_index_offest_upper_bound,
79 tx_power_index_offest_lower_bound);
80
81 if (tx_power_index_offest_upper_bound > 0XF)
82 tx_power_index_offest_upper_bound = 0XF;
83
84 if (tx_power_index_offest_lower_bound < -15)
85 tx_power_index_offest_lower_bound = -15;
86
87 if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest_upper_bound) {
88 tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
89 tx_bb_swing_index = cali_info->default_ofdm_index;
90 } else if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest_upper_bound)) {
91 tx_agc_index = tx_power_index_offest_upper_bound;
92 cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_upper_bound;
93 tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
94
95 if (tx_bb_swing_index > bb_swing_upper_bound)
96 tx_bb_swing_index = bb_swing_upper_bound;
97 } else if (cali_info->absolute_ofdm_swing_idx[rf_path] < 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] >= tx_power_index_offest_lower_bound)) {
98 tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
99 tx_bb_swing_index = cali_info->default_ofdm_index;
100 } else if (cali_info->absolute_ofdm_swing_idx[rf_path] < 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] < tx_power_index_offest_lower_bound)) {
101 tx_agc_index = tx_power_index_offest_lower_bound;
102 cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_lower_bound;
103
104 if (cali_info->default_ofdm_index > (cali_info->remnant_ofdm_swing_idx[rf_path] * (-1)))
105 tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
106 else
107 tx_bb_swing_index = bb_swing_lower_bound;
108 }
109
110 cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
111 cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
112
113 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
114 "MixMode Offset Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d pRF->bb_swing_idx_ofdm[rf_path]=%d TxPwrIdxOffestUpper=%d TxPwrIdxOffestLower=%d\n",
115 rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
116 cali_info->bb_swing_idx_ofdm[rf_path],
117 tx_power_index_offest_upper_bound,
118 tx_power_index_offest_lower_bound);
119
120 return true;
121 }
122
odm_tx_pwr_track_set_pwr8821c(void * dm_void,enum pwrtrack_method method,u8 rf_path,u8 channel_mapped_index)123 void odm_tx_pwr_track_set_pwr8821c(void *dm_void, enum pwrtrack_method method,
124 u8 rf_path, u8 channel_mapped_index)
125 {
126 struct dm_struct *dm = (struct dm_struct *)dm_void;
127 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
128 struct _ADAPTER *adapter = dm->adapter;
129 u8 channel = *dm->channel;
130 u8 band_width = *dm->band_width;
131 #endif
132 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
133 struct _hal_rf_ *rf = &dm->rf_table;
134 u8 tx_power_index_offest_upper_bound = 0;
135 s8 tx_power_index_offest_lower_bound = 0;
136 u8 tx_power_index = 0;
137 u8 tx_rate = 0xFF;
138
139 if (*dm->mp_mode) {
140 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
141 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
142 #if (MP_DRIVER == 1)
143 PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
144
145 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
146 #endif
147 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
148 #ifdef CONFIG_MP_INCLUDED
149 PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
150
151 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
152 #endif
153 #endif
154 #endif
155 } else {
156 u16 rate = *dm->forced_data_rate;
157
158 if (!rate) { /*auto rate*/
159 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
160 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
161 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
162 tx_rate = dm->tx_rate;
163 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
164 if (dm->number_linked_client != 0)
165 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
166 else
167 tx_rate = rf->p_rate_index;
168 #endif
169 } else { /*force rate*/
170 tx_rate = (u8)rate;
171 }
172 }
173
174 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
175 tx_rate);
176
177 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
178 "pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n",
179 cali_info->default_ofdm_index, cali_info->default_cck_index);
180
181 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
182 "pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
183 cali_info->absolute_ofdm_swing_idx[rf_path],
184 cali_info->remnant_ofdm_swing_idx[rf_path],
185 cali_info->absolute_cck_swing_idx[rf_path],
186 cali_info->remnant_cck_swing_idx, rf_path);
187
188 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
189 tx_power_index = odm_get_tx_power_index(dm, (enum rf_path)rf_path, tx_rate, band_width, channel);
190 #else
191 tx_power_index = config_phydm_read_txagc_8821c(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/
192 #endif
193
194 if (tx_power_index >= 63)
195 tx_power_index = 63;
196
197 tx_power_index_offest_upper_bound = 63 - tx_power_index;
198
199 tx_power_index_offest_lower_bound = 0 - tx_power_index;
200
201 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
202 "tx_power_index=%d tx_power_index_offest_upper_bound=%d tx_power_index_offest_lower_bound=%d rf_path=%d\n",
203 tx_power_index, tx_power_index_offest_upper_bound,
204 tx_power_index_offest_lower_bound, rf_path);
205
206 if (method == BBSWING) { /*use for mp driver clean power tracking status*/
207 switch (rf_path) {
208 case RF_PATH_A:
209 odm_set_bb_reg(dm, R_0xc94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((cali_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f));
210 odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
211 break;
212
213 default:
214 break;
215 }
216
217 } else if (method == MIX_MODE) {
218 switch (rf_path) {
219 case RF_PATH_A:
220 get_mix_mode_tx_agc_bbs_wing_offset_8821c(dm, method, rf_path, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound);
221 odm_set_bb_reg(dm, R_0xc94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((cali_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f));
222 odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
223
224 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
225 "TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
226 odm_get_bb_reg(dm, R_0xc94,
227 (BIT(6) | BIT(5) | BIT(4) |
228 BIT(3) | BIT(2) | BIT(1))),
229 odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000),
230 cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
231 break;
232
233 default:
234 break;
235 }
236 }
237 }
238
get_delta_swing_table_8821c(void * dm_void,u8 ** temperature_up_a,u8 ** temperature_down_a,u8 ** temperature_up_b,u8 ** temperature_down_b,u8 ** temperature_up_cck_a,u8 ** temperature_down_cck_a,u8 ** temperature_up_cck_b,u8 ** temperature_down_cck_b)239 void get_delta_swing_table_8821c(void *dm_void,
240 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
241 u8 **temperature_up_a, u8 **temperature_down_a,
242 u8 **temperature_up_b, u8 **temperature_down_b,
243 u8 **temperature_up_cck_a,
244 u8 **temperature_down_cck_a,
245 u8 **temperature_up_cck_b,
246 u8 **temperature_down_cck_b
247 #else
248 u8 **temperature_up_a, u8 **temperature_down_a,
249 u8 **temperature_up_b,
250 u8 **temperature_down_b
251 #endif
252 )
253 {
254 struct dm_struct *dm = (struct dm_struct *)dm_void;
255 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
256
257 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
258 u8 channel = *(dm->channel);
259 #else
260 u8 channel = *dm->channel;
261 #endif
262
263 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
264 *temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
265 *temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
266 *temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
267 *temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
268 #endif
269
270 *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
271 *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
272 *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
273 *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
274
275 if (channel >= 36 && channel <= 64) {
276 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
277 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
278 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
279 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
280 } else if (channel >= 100 && channel <= 144) {
281 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
282 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
283 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
284 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
285 } else if (channel >= 149 && channel <= 177) {
286 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
287 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
288 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
289 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
290 }
291 }
292
aac_check_8821c(struct dm_struct * dm)293 void aac_check_8821c(struct dm_struct *dm)
294 {
295 struct _hal_rf_ *rf = &dm->rf_table;
296 u32 temp;
297
298 if (!rf->aac_checked) {
299 RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8821c\n");
300 temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8);
301 if (temp < 4 || temp > 7) {
302 odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0);
303 odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6);
304 }
305 rf->aac_checked = true;
306 }
307 }
308
_phy_aac_calibrate_8821c(struct dm_struct * dm)309 void _phy_aac_calibrate_8821c(struct dm_struct *dm)
310 {
311 #if 0
312 u32 cnt = 0;
313
314 RF_DBG(dm, DBG_RF_LCK, "[AACK]AACK start!!!!!!!\n");
315 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, RFREGOFFSETMASK, 0x80a00);
316 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xff0fa);
317 ODM_delay_ms(10);
318 odm_set_rf_reg(dm, RF_PATH_A, RF_0xca, RFREGOFFSETMASK, 0x80000);
319 odm_set_rf_reg(dm, RF_PATH_A, RF_0xc9, RFREGOFFSETMASK, 0x1c141);
320 for (cnt = 0; cnt < 100; cnt++) {
321 ODM_delay_ms(1);
322 if (odm_get_rf_reg(dm, RF_PATH_A, RF_0xca, 0x1000) != 0x1)
323 break;
324 }
325
326 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xff0f8);
327
328 RF_DBG(dm, DBG_RF_IQK, "[AACK]AACK end!!!!!!!\n");
329 #endif
330 }
331
phy_lck_done_8821c(struct dm_struct * dm)332 boolean phy_lck_done_8821c(struct dm_struct *dm)
333 {
334 boolean lck_ok = false;
335
336 if (odm_get_rf_reg(dm, RF_PATH_A, 0xc6, BIT(19)) == 0x0)
337 lck_ok = true;
338 return lck_ok;
339 }
340
_phy_lc_calibrate_8821c(struct dm_struct * dm)341 void _phy_lc_calibrate_8821c(struct dm_struct *dm)
342 {
343 #if 0
344 aac_check_8821c(dm);
345 RF_DBG(dm, DBG_RF_LCK, "[LCK]real-time LCK!!!!!!!\n");
346 odm_set_rf_reg(dm, RF_PATH_A, RF_0xcc, RFREGOFFSETMASK, 0x2018);
347 odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x8f602);
348 odm_set_rf_reg(dm, RF_PATH_A, RF_0xcc, RFREGOFFSETMASK, 0x201c);
349 #endif
350 #if 1
351 u32 lc_cal = 0, cnt = 0, tmp0xc00;
352 /*RF to standby mode*/
353 tmp0xc00 = odm_read_4byte(dm, 0xc00);
354 odm_write_4byte(dm, 0xc00, 0x4);
355 odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
356
357 _phy_aac_calibrate_8821c(dm);
358
359 /*backup RF0x18*/
360 lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
361 /*Start LCK*/
362 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
363 ODM_delay_ms(50);
364
365 for (cnt = 0; cnt < 100; cnt++) {
366 if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
367 break;
368 ODM_delay_ms(10);
369 }
370
371 /*Recover channel number*/
372 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
373 /**restore*/
374 odm_write_4byte(dm, 0xc00, tmp0xc00);
375 odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x3ffff);
376 RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK end!!!!!!!\n");
377 #endif
378 }
379
380 /*LCK:0x3*/
381 /*1. full LCK*/
phy_lc_calibrate_8821c(void * dm_void)382 void phy_lc_calibrate_8821c(void *dm_void)
383 {
384 struct dm_struct *dm = (struct dm_struct *)dm_void;
385
386 _phy_lc_calibrate_8821c(dm);
387 }
388
configure_txpower_track_8821c(struct txpwrtrack_cfg * config)389 void configure_txpower_track_8821c(struct txpwrtrack_cfg *config)
390 {
391 config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
392 config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
393 config->threshold_iqk = IQK_THRESHOLD;
394 config->threshold_dpk = DPK_THRESHOLD;
395 config->average_thermal_num = AVG_THERMAL_NUM_8821C;
396 config->rf_path_count = MAX_PATH_NUM_8821C;
397 config->thermal_reg_addr = RF_T_METER_8821C;
398
399 config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821c;
400 config->do_iqk = do_iqk_8821c;
401 config->phy_lc_calibrate = halrf_lck_trigger;
402
403 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
404 config->get_delta_all_swing_table = get_delta_swing_table_8821c;
405 #else
406 config->get_delta_swing_table = get_delta_swing_table_8821c;
407 #endif
408 }
409
410 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
phy_set_rf_path_switch_8821c(struct dm_struct * dm,boolean is_main)411 void phy_set_rf_path_switch_8821c(struct dm_struct *dm,
412 #else
413 void phy_set_rf_path_switch_8821c(void *adapter,
414 #endif
415 boolean is_main)
416 {
417 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
418 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
419 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
420 struct dm_struct *dm = &hal_data->DM_OutSrc;
421 #endif
422 #endif
423 u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/
424
425 if (is_main)
426 ant_num = SWITCH_TO_ANT1; /*Main = ANT_1*/
427 else
428 ant_num = SWITCH_TO_ANT2; /*Aux = ANT_2*/
429
430 config_phydm_set_ant_path(dm, dm->current_rf_set_8821c, ant_num);
431 }
432
433
434 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_query_rf_path_switch_8821c(struct dm_struct * dm)435 boolean _phy_query_rf_path_switch_8821c(struct dm_struct *dm
436 #else
437 boolean _phy_query_rf_path_switch_8821c(void *adapter
438 #endif
439 )
440 {
441 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
442 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
443 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
444 struct dm_struct *dm = &hal_data->odmpriv;
445 #endif
446 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
447 struct dm_struct *dm = &hal_data->DM_OutSrc;
448 #endif
449 #endif
450 u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/
451
452 ODM_delay_ms(300);
453
454 ant_num = query_phydm_current_ant_num_8821c(dm);
455
456 if (ant_num == SWITCH_TO_ANT1)
457 return true; /*Main = ANT_1*/
458 else
459 return false; /*Aux = ANT_2*/
460 }
461
462 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
phy_query_rf_path_switch_8821c(struct dm_struct * dm)463 boolean phy_query_rf_path_switch_8821c(struct dm_struct *dm
464 #else
465 boolean phy_query_rf_path_switch_8821c(void *adapter
466 #endif
467 )
468 {
469 #if DISABLE_BB_RF
470 return true;
471 #endif
472
473 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
474 return _phy_query_rf_path_switch_8821c(dm);
475 #else
476 return _phy_query_rf_path_switch_8821c(adapter);
477 #endif
478 }
479
480 #endif /* (RTL8821C_SUPPORT == 0)*/
481