1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 #ifndef HALMAC_POWER_SEQUENCE_CMD 17 #define HALMAC_POWER_SEQUENCE_CMD 18 19 #include "halmac_2_platform.h" 20 21 #define HALMAC_PWR_POLLING_CNT 20000 22 23 /* The value of cmd : 4 bits */ 24 25 /* offset : the read register offset 26 * msk : the mask of the read value 27 * value : N/A, left by 0 28 * Note : dirver shall implement this function by read & msk 29 */ 30 #define HALMAC_PWR_CMD_READ 0x00 31 /* offset: the read register offset 32 * msk: the mask of the write bits 33 * value: write value 34 * Note: driver shall implement this cmd by read & msk after write 35 */ 36 #define HALMAC_PWR_CMD_WRITE 0x01 37 /* offset: the read register offset 38 * msk: the mask of the polled value 39 * value: the value to be polled, masked by the msd field. 40 * Note: driver shall implement this cmd by 41 * do{ 42 * if( (Read(offset) & msk) == (value & msk) ) 43 * break; 44 * } while(not timeout); 45 */ 46 #define HALMAC_PWR_CMD_POLLING 0x02 47 /* offset: the value to delay 48 * msk: N/A 49 * value: the unit of delay, 0: us, 1: ms 50 */ 51 #define HALMAC_PWR_CMD_DELAY 0x03 52 /* offset: N/A 53 * msk: N/A 54 * value: N/A 55 */ 56 #define HALMAC_PWR_CMD_END 0x04 57 58 /* The value of base : 4 bits */ 59 60 /* define the base address of each block */ 61 #define HALMAC_PWR_ADDR_MAC 0x00 62 #define HALMAC_PWR_ADDR_USB 0x01 63 #define HALMAC_PWR_ADDR_PCIE 0x02 64 #define HALMAC_PWR_ADDR_SDIO 0x03 65 66 /* The value of interface_msk : 4 bits */ 67 #define HALMAC_PWR_INTF_SDIO_MSK BIT(0) 68 #define HALMAC_PWR_INTF_USB_MSK BIT(1) 69 #define HALMAC_PWR_INTF_PCI_MSK BIT(2) 70 #define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 71 72 /* The value of cut_msk : 8 bits */ 73 #define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0) 74 #define HALMAC_PWR_CUT_A_MSK BIT(1) 75 #define HALMAC_PWR_CUT_B_MSK BIT(2) 76 #define HALMAC_PWR_CUT_C_MSK BIT(3) 77 #define HALMAC_PWR_CUT_D_MSK BIT(4) 78 #define HALMAC_PWR_CUT_E_MSK BIT(5) 79 #define HALMAC_PWR_CUT_F_MSK BIT(6) 80 #define HALMAC_PWR_CUT_G_MSK BIT(7) 81 #define HALMAC_PWR_CUT_ALL_MSK 0xFF 82 83 enum halmac_pwrseq_cmd_delay_unit { 84 HALMAC_PWR_DELAY_US, 85 HALMAC_PWR_DELAY_MS, 86 }; 87 88 struct halmac_wlan_pwr_cfg { 89 u16 offset; 90 u8 cut_msk; 91 u8 interface_msk; 92 u8 base:4; 93 u8 cmd:4; 94 u8 msk; 95 u8 value; 96 }; 97 98 #endif 99