1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_MP_C_
16
17 #include <drv_types.h>
18
19 #ifdef CONFIG_MP_INCLUDED
20
21 #ifdef RTW_HALMAC
22 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
23 #else /* !RTW_HALMAC */
24 #ifdef CONFIG_RTL8188E
25 #include <rtl8188e_hal.h>
26 #endif
27 #ifdef CONFIG_RTL8723B
28 #include <rtl8723b_hal.h>
29 #endif
30 #ifdef CONFIG_RTL8192E
31 #include <rtl8192e_hal.h>
32 #endif
33 #ifdef CONFIG_RTL8814A
34 #include <rtl8814a_hal.h>
35 #endif
36 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
37 #include <rtl8812a_hal.h>
38 #endif
39 #ifdef CONFIG_RTL8703B
40 #include <rtl8703b_hal.h>
41 #endif
42 #ifdef CONFIG_RTL8723D
43 #include <rtl8723d_hal.h>
44 #endif
45 #ifdef CONFIG_RTL8710B
46 #include <rtl8710b_hal.h>
47 #endif
48 #ifdef CONFIG_RTL8188F
49 #include <rtl8188f_hal.h>
50 #endif
51 #ifdef CONFIG_RTL8188GTV
52 #include <rtl8188gtv_hal.h>
53 #endif
54 #ifdef CONFIG_RTL8192F
55 #include <rtl8192f_hal.h>
56 #endif
57 #endif /* !RTW_HALMAC */
58
59
MgntQuery_NssTxRate(u16 Rate)60 u8 MgntQuery_NssTxRate(u16 Rate)
61 {
62 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
63
64 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
65 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
66 NssNum = RF_2TX;
67 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
68 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
69 NssNum = RF_3TX;
70 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
71 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
72 NssNum = RF_4TX;
73 else
74 NssNum = RF_1TX;
75
76 return NssNum;
77 }
78
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)79 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
80 {
81 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
82 u8 ChannelToSw = pMptCtx->MptChannelToSw;
83 u32 ulRateIdx = pMptCtx->mpt_rate_index;
84 u32 ulbandwidth = pMptCtx->MptBandWidth;
85
86 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
87 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
88 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
89 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
90 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
91
92 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
93 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
94 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
95 } else {
96 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
97 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
98 }
99 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
100 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
101 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
102 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
103 } else {
104 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
105 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
106 }
107 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
108 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
109 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
110 }
111 }
112
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)113 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
114 {
115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
116 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
117
118
119 if (!netif_running(padapter->pnetdev)) {
120 return _FAIL;
121 }
122
123 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
124 return _FAIL;
125 }
126 if (enable)
127 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
128 else
129 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
130
131 return _SUCCESS;
132 }
133
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)134 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
137 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
138
139
140 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
141 }
142
143
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)144 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
145 {
146 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
147 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
148 u8 i;
149 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
150 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
151 u8 u1Channel = pHalData->current_channel;
152 u32 ulRateIdx = pMptCtx->mpt_rate_index;
153 u8 DataRate = 0xFF;
154
155 /* Do not modify CCK TX filter parameters for 8822B*/
156 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
157 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
158 return;
159
160 DataRate = mpt_to_mgnt_rate(ulRateIdx);
161
162 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
163 pHalData->bCCKinCH14 = TRUE;
164 else
165 pHalData->bCCKinCH14 = FALSE;
166
167 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
168 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
169 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
170 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
171 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
172
173 } else {
174 /* Normal setting for 8703B, just recover to the default setting. */
175 /* This hardcore values reference from the parameter which BB team gave. */
176 for (i = 0 ; i < 2 ; ++i)
177 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
178
179 }
180 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
181 /* 2.4G CCK TX DFIR */
182 /* 2016.01.20 Suggest from RS BB mingzhi*/
183 if ((u1Channel == 14)) {
184 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
185 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
186 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
187 } else {
188 for (i = 0 ; i < 3 ; ++i) {
189 phy_set_bb_reg(Adapter,
190 pHalData->RegForRecover[i].offset,
191 bMaskDWord,
192 pHalData->RegForRecover[i].value);
193 }
194 }
195 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
196 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
197 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
198 CCKSwingIndex = 20; /* default index */
199
200 if (!pHalData->bCCKinCH14) {
201 /* Readback the current bb cck swing value and compare with the table to */
202 /* get the current swing index */
203 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
204 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
205 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
206 CCKSwingIndex = i;
207 break;
208 }
209 }
210 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
211 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
212 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
213 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
214 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
215 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
216 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
217 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
218 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
219 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
220 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
221 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
222 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
223 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
224 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
225 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
226 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
227 } else {
228 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
229 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
230 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
231 CCKSwingIndex = i;
232 break;
233 }
234 }
235 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
236 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
237 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
238 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
239 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
240 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
241 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
242 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
243 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
244 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
245 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
246 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
247 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
248 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
249 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
250 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
251 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
252 }
253 } else {
254
255 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
256 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
257
258 if (!pHalData->bCCKinCH14) {
259 /* Readback the current bb cck swing value and compare with the table to */
260 /* get the current swing index */
261 for (i = 0; i < CCK_TABLE_SIZE; i++) {
262 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
263 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
264 CCKSwingIndex = i;
265 break;
266 }
267 }
268
269 /*Write 0xa22 0xa23*/
270 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
271 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
272
273
274 /*Write 0xa24 ~ 0xa27*/
275 TempVal2 = 0;
276 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
277 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
278 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
280
281 /*Write 0xa28 0xa29*/
282 TempVal3 = 0;
283 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
284 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
285 } else {
286 for (i = 0; i < CCK_TABLE_SIZE; i++) {
287 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
288 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
289 CCKSwingIndex = i;
290 break;
291 }
292 }
293
294 /*Write 0xa22 0xa23*/
295 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
296 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
297
298 /*Write 0xa24 ~ 0xa27*/
299 TempVal2 = 0;
300 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
301 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
302 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
303 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
304
305 /*Write 0xa28 0xa29*/
306 TempVal3 = 0;
307 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
308 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
309 }
310
311 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
312 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
313 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
314 }
315
316 }
317
hal_mpt_SetChannel(PADAPTER pAdapter)318 void hal_mpt_SetChannel(PADAPTER pAdapter)
319 {
320 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
321 struct mp_priv *pmp = &pAdapter->mppriv;
322 u8 channel = pmp->channel;
323 u8 bandwidth = pmp->bandwidth;
324
325 hal_mpt_SwitchRfSetting(pAdapter);
326
327 pHalData->bSwChnl = _TRUE;
328 pHalData->bSetChnlBW = _TRUE;
329
330 if (bandwidth == 2) {
331 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
332 } else if (bandwidth == 1) {
333 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
334 } else
335 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
336
337 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
338 rtw_btcoex_wifionly_scan_notify(pAdapter);
339
340 }
341
342 /*
343 * Notice
344 * Switch bandwitdth may change center frequency(channel)
345 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)346 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
347 {
348 struct mp_priv *pmp = &pAdapter->mppriv;
349 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
350
351 u8 channel = pmp->channel;
352 u8 bandwidth = pmp->bandwidth;
353
354 pHalData->bSwChnl = _TRUE;
355 pHalData->bSetChnlBW = _TRUE;
356
357 if (bandwidth == 2) {
358 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
359 } else if (bandwidth == 1) {
360 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
361 } else
362 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
363
364 hal_mpt_SwitchRfSetting(pAdapter);
365 rtw_btcoex_wifionly_scan_notify(pAdapter);
366
367 }
368
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)369 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
370 {
371 switch (Rate) {
372 case MPT_CCK: {
373 u32 TxAGC = 0, pwr = 0;
374
375 pwr = pTxPower[RF_PATH_A];
376 if (pwr < 0x3f) {
377 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
378 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
379 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
380 }
381 pwr = pTxPower[RF_PATH_B];
382 if (pwr < 0x3f) {
383 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
384 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
385 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
386 }
387 }
388 break;
389
390 case MPT_OFDM_AND_HT: {
391 u32 TxAGC = 0;
392 u8 pwr = 0;
393
394 pwr = pTxPower[0];
395 if (pwr < 0x3f) {
396 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
397 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
398 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
399 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
400 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
401 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
402 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
404 }
405 TxAGC = 0;
406 pwr = pTxPower[1];
407 if (pwr < 0x3f) {
408 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
409 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
410 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
411 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
412 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
413 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
414 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
416 }
417 }
418 break;
419
420 default:
421 break;
422 }
423 RTW_INFO("<===mpt_SetTxPower_Old()\n");
424 }
425
426 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)427 mpt_SetTxPower(
428 PADAPTER pAdapter,
429 MPT_TXPWR_DEF Rate,
430 u8 *pTxPower
431 )
432 {
433 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
434
435 u8 path = 0 , i = 0, MaxRate = MGN_6M;
436 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
437 u8 tx_nss = 2;
438
439 if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter)) {
440 EndPath = RF_PATH_D;
441 tx_nss = 4;
442 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
443 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8723F(pAdapter)) {
444 EndPath = RF_PATH_A;
445 tx_nss = 1;
446 }
447
448 switch (Rate) {
449 case MPT_CCK: {
450 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
451
452 for (path = StartPath; path <= EndPath; path++)
453 for (i = 0; i < sizeof(rate); ++i)
454 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
455 }
456 break;
457 case MPT_OFDM: {
458 u8 rate[] = {
459 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
460 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
461 };
462
463 for (path = StartPath; path <= EndPath; path++)
464 for (i = 0; i < sizeof(rate); ++i)
465 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
466 }
467 break;
468 case MPT_HT: {
469 u8 rate[] = {
470 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
471 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
472 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
473 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
474 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
475 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
476 MGN_MCS30, MGN_MCS31,
477 };
478 if (tx_nss == 4)
479 MaxRate = MGN_MCS31;
480 else if (tx_nss == 3)
481 MaxRate = MGN_MCS23;
482 else if (tx_nss == 2)
483 MaxRate = MGN_MCS15;
484 else
485 MaxRate = MGN_MCS7;
486
487 for (path = StartPath; path <= EndPath; path++) {
488 for (i = 0; i < sizeof(rate); ++i) {
489 if (rate[i] > MaxRate)
490 break;
491 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
492 }
493 }
494 }
495 break;
496 case MPT_VHT: {
497 u8 rate[] = {
498 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
499 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
500 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
501 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
502 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
503 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
504 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
505 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
506 };
507 if (tx_nss == 4)
508 MaxRate = MGN_VHT4SS_MCS9;
509 else if (tx_nss == 3)
510 MaxRate = MGN_VHT3SS_MCS9;
511 else if (tx_nss == 2)
512 MaxRate = MGN_VHT2SS_MCS9;
513 else
514 MaxRate = MGN_VHT1SS_MCS9;
515
516 for (path = StartPath; path <= EndPath; path++) {
517 for (i = 0; i < sizeof(rate); ++i) {
518 if (rate[i] > MaxRate)
519 break;
520 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
521 }
522 }
523 }
524 break;
525 default:
526 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
527 break;
528 }
529 }
530
hal_mpt_SetTxPower(PADAPTER pAdapter)531 void hal_mpt_SetTxPower(PADAPTER pAdapter)
532 {
533 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
534 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
535 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
536
537 if (pHalData->rf_chip < RF_CHIP_MAX) {
538 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
539 IS_HARDWARE_TYPE_8723B(pAdapter) ||
540 IS_HARDWARE_TYPE_8192E(pAdapter) ||
541 IS_HARDWARE_TYPE_8703B(pAdapter) ||
542 IS_HARDWARE_TYPE_8188F(pAdapter) ||
543 IS_HARDWARE_TYPE_8188GTV(pAdapter)
544 ) {
545
546 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
547
548 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
549 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
550
551 } else {
552
553 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
554 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
555 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
556 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
557 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
558 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
559 }
560 }
561
562 rtw_hal_set_txpwr_done(pAdapter);
563 } else
564 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
565
566 odm_clear_txpowertracking_state(pDM_Odm);
567 }
568
hal_mpt_SetDataRate(PADAPTER pAdapter)569 void hal_mpt_SetDataRate(PADAPTER pAdapter)
570 {
571 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
572 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
573 u32 DataRate;
574
575 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
576
577 hal_mpt_SwitchRfSetting(pAdapter);
578
579 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
580 #ifdef CONFIG_RTL8723B
581 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
582 if (IS_CCK_RATE(DataRate)) {
583 if (pMptCtx->mpt_rf_path == RF_PATH_A)
584 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
585 else
586 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
587 } else {
588 if (pMptCtx->mpt_rf_path == RF_PATH_A)
589 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
590 else
591 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
592 }
593 }
594
595 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
596 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
597 if (pMptCtx->mpt_rf_path == RF_PATH_A)
598 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
599 else
600 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
601 }
602 #endif
603 }
604
hal_mpt_tssi_turn_target_power(PADAPTER padapter,s16 power_offset,u8 path)605 u32 hal_mpt_tssi_turn_target_power(PADAPTER padapter, s16 power_offset, u8 path)
606 {
607 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
608 struct dm_struct *pdm = &pHalData->odmpriv;
609 u32 pout = 0;
610
611 #ifdef CONFIG_RTL8723F
612 pout = halrf_tssi_turn_target_power(pdm, power_offset, path);
613 #endif
614 RTW_INFO("%s()===> pout %d\n", __func__, pout);
615
616 return pout;
617 }
618
hal_mpt_tssi_set_power_offset(PADAPTER padapter,s16 power_offset,u8 path)619 void hal_mpt_tssi_set_power_offset(PADAPTER padapter, s16 power_offset, u8 path)
620 {
621 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
622 struct dm_struct *pdm = &pHalData->odmpriv;
623
624 #ifdef CONFIG_RTL8723F
625 halrf_tssi_set_power_offset(pdm, power_offset, path);
626 #endif
627 RTW_INFO("%s()===> path%d = %d\n", __func__, path, power_offset);
628
629 return;
630 }
631
632 #define RF_PATH_AB 22
633
634 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)635 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
636 {
637 u8 Path;
638 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
639
640 for (Path = 0; Path <= RF_PATH_D; Path++) {
641 switch (Path) {
642 case RF_PATH_B:
643 IGReg = rB_IGI_Jaguar;
644 break;
645 case RF_PATH_C:
646 IGReg = rC_IGI_Jaguar2;
647 break;
648 case RF_PATH_D:
649 IGReg = rD_IGI_Jaguar2;
650 break;
651 default:
652 IGReg = rA_IGI_Jaguar;
653 break;
654 }
655
656 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
657 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
658 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
659 }
660 }
661
mpt_SetRFPath_8814A(PADAPTER pAdapter)662 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
663 {
664
665 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
666 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
667 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
668 R_ANTENNA_SELECT_CCK *p_cck_txrx;
669 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
670 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
671 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
672
673 u32 ulAntennaTx = pHalData->antenna_tx_path;
674 u32 ulAntennaRx = pHalData->AntennaRxPath;
675 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
676
677 if (NssforRate == RF_3TX) {
678 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
679
680 switch (ulAntennaTx) {
681 case ANTENNA_BCD:
682 pMptCtx->mpt_rf_path = RF_PATH_BCD;
683 /*pHalData->ValidTxPath = 0x0e;*/
684 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
685 break;
686
687 case ANTENNA_ABC:
688 default:
689 pMptCtx->mpt_rf_path = RF_PATH_ABC;
690 /*pHalData->ValidTxPath = 0x0d;*/
691 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
692 break;
693 }
694
695 } else { /*/if(NssforRate == RF_1TX)*/
696 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
697 switch (ulAntennaTx) {
698 case ANTENNA_BCD:
699 pMptCtx->mpt_rf_path = RF_PATH_BCD;
700 /*pHalData->ValidTxPath = 0x0e;*/
701 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
702 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
703 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
704 break;
705
706 case ANTENNA_BC:
707 pMptCtx->mpt_rf_path = RF_PATH_BC;
708 /*pHalData->ValidTxPath = 0x06;*/
709 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
710 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
711 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
712 break;
713 case ANTENNA_B:
714 pMptCtx->mpt_rf_path = RF_PATH_B;
715 /*pHalData->ValidTxPath = 0x02;*/
716 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
717 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
718 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
719 break;
720
721 case ANTENNA_C:
722 pMptCtx->mpt_rf_path = RF_PATH_C;
723 /*pHalData->ValidTxPath = 0x04;*/
724 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
725 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
726 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
727 break;
728
729 case ANTENNA_D:
730 pMptCtx->mpt_rf_path = RF_PATH_D;
731 /*pHalData->ValidTxPath = 0x08;*/
732 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
733 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
734 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
735 break;
736
737 case ANTENNA_A:
738 default:
739 pMptCtx->mpt_rf_path = RF_PATH_A;
740 /*pHalData->ValidTxPath = 0x01;*/
741 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
742 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
743 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
744 break;
745 }
746 }
747
748 switch (ulAntennaRx) {
749 case ANTENNA_A:
750 /*pHalData->ValidRxPath = 0x01;*/
751 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
752 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
753 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
754 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
755 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
756 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
757 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
758 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
759 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
760 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
761 /*/ CCA related PD_delay_th*/
762 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
763 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
764 break;
765
766 case ANTENNA_B:
767 /*pHalData->ValidRxPath = 0x02;*/
768 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
769 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
770 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
771 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
772 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
773 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
774 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
775 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
776 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
777 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
778 /*/ CCA related PD_delay_th*/
779 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
780 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
781 break;
782
783 case ANTENNA_C:
784 /*pHalData->ValidRxPath = 0x04;*/
785 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
786 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
787 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
788 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
789 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
790 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
791 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
792 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
793 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
794 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
795 /*/ CCA related PD_delay_th*/
796 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
797 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
798 break;
799
800 case ANTENNA_D:
801 /*pHalData->ValidRxPath = 0x08;*/
802 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
803 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
804 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
805 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
806 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
807 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
808 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
809 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
810 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
811 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
812 /*/ CCA related PD_delay_th*/
813 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
814 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
815 break;
816
817 case ANTENNA_BC:
818 /*pHalData->ValidRxPath = 0x06;*/
819 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
820 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
821 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
822 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
823 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
824 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
825 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
826 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
827 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
828 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
829 /*/ CCA related PD_delay_th*/
830 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
831 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
832 break;
833
834 case ANTENNA_CD:
835 /*pHalData->ValidRxPath = 0x0C;*/
836 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
837 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
838 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
839 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
840 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
841 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
842 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
843 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
844 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
845 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
846 /*/ CCA related PD_delay_th*/
847 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
848 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
849 break;
850
851 case ANTENNA_BCD:
852 /*pHalData->ValidRxPath = 0x0e;*/
853 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
854 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
855 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
856 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
857 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
858 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
859 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
860 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
861 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
862 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
863 /*/ CCA related PD_delay_th*/
864 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
865 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
866 break;
867
868 case ANTENNA_ABCD:
869 /*pHalData->ValidRxPath = 0x0f;*/
870 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
871 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
872 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
873 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
874 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
875 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
876 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
877 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
878 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
879 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
880 /*/ CCA related PD_delay_th*/
881 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
882 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
883 break;
884
885 default:
886 break;
887 }
888
889 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
890
891 mpt_ToggleIG_8814A(pAdapter);
892 }
893
894 #endif /* CONFIG_RTL8814A */
895 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) \
896 || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F)
897 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)898 mpt_SetSingleTone_8814A(
899 PADAPTER pAdapter,
900 BOOLEAN bSingleTone,
901 BOOLEAN bEnPMacTx)
902 {
903
904 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
905 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
906 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
907
908 if (bSingleTone) {
909 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
910 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
911 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
912 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
913
914 switch (pMptCtx->mpt_rf_path) {
915 case RF_PATH_A:
916 case RF_PATH_B:
917 case RF_PATH_C:
918 case RF_PATH_D:
919 StartPath = pMptCtx->mpt_rf_path;
920 EndPath = pMptCtx->mpt_rf_path;
921 break;
922 case RF_PATH_AB:
923 EndPath = RF_PATH_B;
924 break;
925 case RF_PATH_BC:
926 StartPath = RF_PATH_B;
927 EndPath = RF_PATH_C;
928 break;
929 case RF_PATH_ABC:
930 EndPath = RF_PATH_C;
931 break;
932 case RF_PATH_BCD:
933 StartPath = RF_PATH_B;
934 EndPath = RF_PATH_D;
935 break;
936 case RF_PATH_ABCD:
937 EndPath = RF_PATH_D;
938 break;
939 }
940
941 if (bEnPMacTx == FALSE) {
942 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
943 issue_nulldata(pAdapter, NULL, 1, 3, 500);
944 }
945
946 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
947
948 for (path = StartPath; path <= EndPath; path++) {
949 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
950 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
951
952 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
953 }
954
955 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
956 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
957 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
958 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
959 } else {
960 switch (pMptCtx->mpt_rf_path) {
961 case RF_PATH_A:
962 case RF_PATH_B:
963 case RF_PATH_C:
964 case RF_PATH_D:
965 StartPath = pMptCtx->mpt_rf_path;
966 EndPath = pMptCtx->mpt_rf_path;
967 break;
968 case RF_PATH_AB:
969 EndPath = RF_PATH_B;
970 break;
971 case RF_PATH_BC:
972 StartPath = RF_PATH_B;
973 EndPath = RF_PATH_C;
974 break;
975 case RF_PATH_ABC:
976 EndPath = RF_PATH_C;
977 break;
978 case RF_PATH_BCD:
979 StartPath = RF_PATH_B;
980 EndPath = RF_PATH_D;
981 break;
982 case RF_PATH_ABCD:
983 EndPath = RF_PATH_D;
984 break;
985 }
986 for (path = StartPath; path <= EndPath; path++)
987 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
988
989 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
990
991 if (bEnPMacTx == FALSE) {
992 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
993 #ifdef PHYDM_MP_SUPPORT
994 phydm_stop_ofdm_cont_tx(pAdapter);
995 pMptCtx->bCckContTx = FALSE;
996 pMptCtx->bOfdmContTx = FALSE;
997 #endif
998 } else
999 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
1000 }
1001
1002 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
1003 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
1004 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
1005 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
1006 }
1007 }
1008
1009 #endif
1010
1011 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)1012 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
1013 {
1014 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1015 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
1016 struct mp_priv *pmp = &pAdapter->mppriv;
1017 u8 channel = pmp->channel;
1018 u8 bandwidth = pmp->bandwidth;
1019 u8 eLNA_2g = pHalData->ExternalLNA_2G;
1020 u32 ulAntennaTx, ulAntennaRx;
1021 u32 reg0xC50 = 0;
1022
1023 ulAntennaTx = pHalData->antenna_tx_path;
1024 ulAntennaRx = pHalData->AntennaRxPath;
1025
1026 switch (ulAntennaTx) {
1027 case ANTENNA_A:
1028 pMptCtx->mpt_rf_path = RF_PATH_A;
1029 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
1030 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1031 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1032 break;
1033 case ANTENNA_B:
1034 pMptCtx->mpt_rf_path = RF_PATH_B;
1035 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
1036 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1037 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
1038 break;
1039 case ANTENNA_AB:
1040 pMptCtx->mpt_rf_path = RF_PATH_AB;
1041 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1042 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1043 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1044 break;
1045 default:
1046 pMptCtx->mpt_rf_path = RF_PATH_AB;
1047 RTW_INFO("Unknown Tx antenna.\n");
1048 break;
1049 }
1050
1051 switch (ulAntennaRx) {
1052 case ANTENNA_A:
1053 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1054 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1055 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1056 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1057
1058 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1059 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1060 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1061 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1062
1063 /* set PWED_TH for BB Yn user guide R29 */
1064 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1065 if (channel <= 14) { /* 2.4G */
1066 if (bandwidth == CHANNEL_WIDTH_20
1067 && eLNA_2g == 0) {
1068 /* 0x830[3:1]=3'b010 */
1069 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1070 } else
1071 /* 0x830[3:1]=3'b100 */
1072 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1073 } else
1074 /* 0x830[3:1]=3'b100 for 5G */
1075 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1076 }
1077 break;
1078 case ANTENNA_B:
1079 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1080 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1081 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1082 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1083
1084 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1085 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1086 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1087 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1088
1089 /* set PWED_TH for BB Yn user guide R29 */
1090 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1091 if (channel <= 14) {
1092 if (bandwidth == CHANNEL_WIDTH_20
1093 && eLNA_2g == 0) {
1094 /* 0x830[3:1]=3'b010 */
1095 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1096 } else
1097 /* 0x830[3:1]=3'b100 */
1098 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1099 } else
1100 /* 0x830[3:1]=3'b100 for 5G */
1101 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1102 }
1103 break;
1104 case ANTENNA_AB:
1105 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1106 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1107 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1108 /* set PWED_TH for BB Yn user guide R29 */
1109 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1110 break;
1111 default:
1112 RTW_INFO("Unknown Rx antenna.\n");
1113 break;
1114 }
1115
1116 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1117 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1118 /* WiFi */
1119 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1120 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1121 } else {
1122 /* BT */
1123 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1124 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1125 }
1126 }
1127 }
1128 #endif
1129
1130 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1131 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1132 {
1133 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1134 u32 ulAntennaTx, ulAntennaRx;
1135 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1136 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1137 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1138 u8 i;
1139
1140 ulAntennaTx = pHalData->antenna_tx_path;
1141 ulAntennaRx = pHalData->AntennaRxPath;
1142
1143 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1144 RTW_INFO("This RF chip ID is not supported\n");
1145 return;
1146 }
1147
1148 switch (pAdapter->mppriv.antenna_tx) {
1149 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1150 pMptCtx->mpt_rf_path = RF_PATH_A;
1151 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1152 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1153
1154 for (i = 0; i < 3; ++i) {
1155 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1156 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1157
1158 if (offset != 0) {
1159 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1160 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1161 }
1162 }
1163 for (i = 0; i < 2; ++i) {
1164 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1165 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1166
1167 if (offset != 0) {
1168 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1169 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1170 }
1171 }
1172 }
1173 break;
1174 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1175 u32 offset;
1176 u32 data;
1177
1178 pMptCtx->mpt_rf_path = RF_PATH_B;
1179 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1180 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1181
1182 for (i = 0; i < 3; ++i) {
1183 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1184 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1185 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1186 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1187 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1188 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1189 }
1190 }
1191 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1192 for (i = 0; i < 2; ++i) {
1193 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1194 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1195 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1196 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1197 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1198 }
1199 }
1200 }
1201 break;
1202 default:
1203 pMptCtx->mpt_rf_path = RF_PATH_AB;
1204 break;
1205 }
1206 }
1207 #endif
1208
1209 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1210 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1211 {
1212 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1213 u32 ulAntennaTx, ulAntennaRx;
1214 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1215 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1216 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1217 u8 i;
1218
1219 ulAntennaTx = pHalData->antenna_tx_path;
1220 ulAntennaRx = pHalData->AntennaRxPath;
1221
1222 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1223 RTW_INFO("This RF chip ID is not supported\n");
1224 return;
1225 }
1226
1227 switch (pAdapter->mppriv.antenna_tx) {
1228 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1229 pMptCtx->mpt_rf_path = RF_PATH_A;
1230 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1231 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1232
1233 for (i = 0; i < 3; ++i) {
1234 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1235 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1236
1237 if (offset != 0) {
1238 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1239 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1240 }
1241
1242 }
1243 for (i = 0; i < 2; ++i) {
1244 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1245 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1246
1247 if (offset != 0) {
1248 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1249 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1250 }
1251 }
1252 }
1253 break;
1254 case ANTENNA_B: { /* Actually path S0 (BT)*/
1255 pMptCtx->mpt_rf_path = RF_PATH_B;
1256 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1257 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1258
1259 for (i = 0; i < 3; ++i) {
1260 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1261 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1262
1263 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1264 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1265 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1266 }
1267 }
1268 for (i = 0; i < 2; ++i) {
1269 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1270 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1271
1272 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1273 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1274 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1275 }
1276 }
1277 }
1278 break;
1279 default:
1280 pMptCtx->mpt_rf_path = RF_PATH_AB;
1281 break;
1282 }
1283
1284 }
1285 #endif
1286
1287 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1288 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1289 {
1290 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1291 u8 p = 0, i = 0;
1292 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1293 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1294 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1295 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1296
1297 ulAntennaTx = pHalData->antenna_tx_path;
1298 ulAntennaRx = pHalData->AntennaRxPath;
1299
1300 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1301 RTW_INFO("This RF chip ID is not supported\n");
1302 return;
1303 }
1304
1305 switch (pAdapter->mppriv.antenna_tx) {
1306 /* Actually path S1 (Wi-Fi) */
1307 case ANTENNA_A: {
1308 pMptCtx->mpt_rf_path = RF_PATH_A;
1309 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1310 }
1311 break;
1312 /* Actually path S0 (BT) */
1313 case ANTENNA_B: {
1314 pMptCtx->mpt_rf_path = RF_PATH_B;
1315 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1316
1317 }
1318 break;
1319 default:
1320 pMptCtx->mpt_rf_path = RF_PATH_AB;
1321 break;
1322 }
1323 }
1324 #endif
1325
mpt_SetRFPath_819X(PADAPTER pAdapter)1326 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1327 {
1328 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1329 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1330 u32 ulAntennaTx, ulAntennaRx;
1331 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1332 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1333 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1334 u8 chgTx = 0, chgRx = 0;
1335 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1336
1337 ulAntennaTx = pHalData->antenna_tx_path;
1338 ulAntennaRx = pHalData->AntennaRxPath;
1339
1340 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1341 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1342
1343 p_ofdm_tx->r_ant_ht1 = 0x1;
1344 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1345 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1346
1347 switch (ulAntennaTx) {
1348 case ANTENNA_A:
1349 p_ofdm_tx->r_tx_antenna = 0x1;
1350 r_ofdm_tx_en_val = 0x1;
1351 p_ofdm_tx->r_ant_l = 0x1;
1352 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1353 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1354 p_cck_txrx->r_ccktx_enable = 0x8;
1355 chgTx = 1;
1356 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1357 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1358 {
1359 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1360 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1361 r_ofdm_tx_en_val = 0x3;
1362 /*/ Power save*/
1363 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1364 /*/ We need to close RFB by SW control*/
1365 if (pHalData->rf_type == RF_2T2R) {
1366 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1367 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1368 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1369 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1370 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1371 }
1372 }
1373 pMptCtx->mpt_rf_path = RF_PATH_A;
1374 break;
1375 case ANTENNA_B:
1376 p_ofdm_tx->r_tx_antenna = 0x2;
1377 r_ofdm_tx_en_val = 0x2;
1378 p_ofdm_tx->r_ant_l = 0x2;
1379 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1380 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1381 p_cck_txrx->r_ccktx_enable = 0x4;
1382 chgTx = 1;
1383 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1384 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1385 {
1386 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1387 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1388
1389 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1390 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1391 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1392 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1393 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1394 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1395 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1396 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1397 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1398 }
1399 }
1400 pMptCtx->mpt_rf_path = RF_PATH_B;
1401 break;
1402 case ANTENNA_AB:/*/ For 8192S*/
1403 p_ofdm_tx->r_tx_antenna = 0x3;
1404 r_ofdm_tx_en_val = 0x3;
1405 p_ofdm_tx->r_ant_l = 0x3;
1406 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1407 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1408 p_cck_txrx->r_ccktx_enable = 0xC;
1409 chgTx = 1;
1410 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1411 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1412 {
1413 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1414 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1415 /* Disable Power save*/
1416 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1417 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1418 if (pHalData->rf_type == RF_2T2R) {
1419 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1420
1421 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1422 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1423 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1424 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1425 }
1426 }
1427 pMptCtx->mpt_rf_path = RF_PATH_AB;
1428 break;
1429 default:
1430 break;
1431 }
1432 #if 0
1433 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1434 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1435 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1436 #endif
1437 switch (ulAntennaRx) {
1438 case ANTENNA_A:
1439 r_rx_antenna_ofdm = 0x1; /* A*/
1440 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1441 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1442 chgRx = 1;
1443 break;
1444 case ANTENNA_B:
1445 r_rx_antenna_ofdm = 0x2; /*/ B*/
1446 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1447 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1448 chgRx = 1;
1449 break;
1450 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1451 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1452 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1453 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1454 chgRx = 1;
1455 break;
1456 default:
1457 break;
1458 }
1459
1460
1461 if (chgTx && chgRx) {
1462 switch (pHalData->rf_chip) {
1463 case RF_8225:
1464 case RF_8256:
1465 case RF_6052:
1466 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1467 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1468 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1469 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1470 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1471 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1472 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1473 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1474 }
1475 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1476 break;
1477
1478 default:
1479 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1480 break;
1481 }
1482 }
1483 } /* MPT_ProSetRFPath */
1484
1485 #ifdef CONFIG_RTL8192F
1486
mpt_set_rfpath_8192f(PADAPTER pAdapter)1487 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1488 {
1489 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1490 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1491
1492 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1493 u8 NssforRate, odmNssforRate;
1494 u32 ulAntennaTx, ulAntennaRx;
1495 enum bb_path RxAntToPhyDm;
1496 enum bb_path TxAntToPhyDm;
1497
1498 ulAntennaTx = pHalData->antenna_tx_path;
1499 ulAntennaRx = pHalData->AntennaRxPath;
1500 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1501
1502 if (pHalData->rf_chip >= RF_TYPE_MAX)
1503 RTW_INFO("This RF chip ID is not supported\n");
1504
1505 switch (ulAntennaTx) {
1506 case ANTENNA_A:
1507 pMptCtx->mpt_rf_path = RF_PATH_A;
1508 TxAntToPhyDm = BB_PATH_A;
1509 break;
1510 case ANTENNA_B:
1511 pMptCtx->mpt_rf_path = RF_PATH_B;
1512 TxAntToPhyDm = BB_PATH_B;
1513 break;
1514 case ANTENNA_AB:
1515 pMptCtx->mpt_rf_path = RF_PATH_AB;
1516 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1517 break;
1518 default:
1519 pMptCtx->mpt_rf_path = RF_PATH_AB;
1520 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1521 break;
1522 }
1523
1524 switch (ulAntennaRx) {
1525 case ANTENNA_A:
1526 RxAntToPhyDm = BB_PATH_A;
1527 break;
1528 case ANTENNA_B:
1529 RxAntToPhyDm = BB_PATH_B;
1530 break;
1531 case ANTENNA_AB:
1532 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1533 break;
1534 default:
1535 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1536 break;
1537 }
1538
1539 phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1540
1541 }
1542
1543 #endif
1544
hal_mpt_SetAntenna(PADAPTER pAdapter)1545 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1546 {
1547 PHAL_DATA_TYPE hal;
1548 ANTENNA_PATH anttx;
1549 enum bb_path bb_tx = 0;
1550
1551
1552 hal = GET_HAL_DATA(pAdapter);
1553 anttx = hal->antenna_tx_path;
1554
1555 switch (anttx) {
1556 case ANTENNA_A:
1557 bb_tx = BB_PATH_A;
1558 break;
1559 case ANTENNA_B:
1560 bb_tx = BB_PATH_B;
1561 break;
1562 case ANTENNA_C:
1563 bb_tx = BB_PATH_C;
1564 break;
1565 case ANTENNA_D:
1566 bb_tx = BB_PATH_D;
1567 break;
1568 case ANTENNA_AB:
1569 bb_tx = BB_PATH_AB;
1570 break;
1571 case ANTENNA_AC:
1572 bb_tx = BB_PATH_AC;
1573 break;
1574 case ANTENNA_AD:
1575 bb_tx = BB_PATH_AD;
1576 break;
1577 case ANTENNA_BC:
1578 bb_tx = BB_PATH_BC;
1579 break;
1580 case ANTENNA_BD:
1581 bb_tx = BB_PATH_BD;
1582 break;
1583 case ANTENNA_CD:
1584 bb_tx = BB_PATH_CD;
1585 break;
1586 case ANTENNA_ABC:
1587 bb_tx = BB_PATH_ABC;
1588 break;
1589 case ANTENNA_BCD:
1590 bb_tx = BB_PATH_BCD;
1591 break;
1592 case ANTENNA_ABD:
1593 bb_tx = BB_PATH_ABD;
1594 break;
1595 case ANTENNA_ACD:
1596 bb_tx = BB_PATH_ACD;
1597 break;
1598 case ANTENNA_ABCD:
1599 bb_tx = BB_PATH_ABCD;
1600 break;
1601 default:
1602 bb_tx = BB_PATH_A;
1603 break;
1604 }
1605 tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
1606 RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
1607
1608 #ifdef CONFIG_RTL8723F
1609 if (IS_HARDWARE_TYPE_8723F(pAdapter)) {
1610 rtl8723f_mp_config_rfpath(pAdapter);
1611 return;
1612 }
1613 #endif
1614 #ifdef CONFIG_RTL8822C
1615 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1616 rtl8822c_mp_config_rfpath(pAdapter);
1617 return;
1618 }
1619 #endif
1620 #ifdef CONFIG_RTL8814A
1621 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1622 mpt_SetRFPath_8814A(pAdapter);
1623 return;
1624 }
1625 #endif
1626 #ifdef CONFIG_RTL8822B
1627 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1628 rtl8822b_mp_config_rfpath(pAdapter);
1629 return;
1630 }
1631 #endif
1632 #ifdef CONFIG_RTL8821C
1633 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1634 rtl8821c_mp_config_rfpath(pAdapter);
1635 return;
1636 }
1637 #endif
1638 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1639 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1640 mpt_SetRFPath_8812A(pAdapter);
1641 return;
1642 }
1643 #endif
1644 #ifdef CONFIG_RTL8723B
1645 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1646 mpt_SetRFPath_8723B(pAdapter);
1647 return;
1648 }
1649 #endif
1650
1651 #ifdef CONFIG_RTL8703B
1652 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1653 mpt_SetRFPath_8703B(pAdapter);
1654 return;
1655 }
1656 #endif
1657
1658 #ifdef CONFIG_RTL8723D
1659 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1660 mpt_SetRFPath_8723D(pAdapter);
1661 return;
1662 }
1663 #endif
1664
1665 #ifdef CONFIG_RTL8192F
1666 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1667 mpt_set_rfpath_8192f(pAdapter);
1668 return;
1669 }
1670 #endif
1671
1672 #ifdef CONFIG_RTL8814B
1673 if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1674 rtl8814b_mp_config_rfpath(pAdapter);
1675 return;
1676 }
1677 #endif
1678
1679 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1680 mpt_SetRFPath_8821B(pAdapter);
1681 Prepare for 8822B
1682 else if (IS_HARDWARE_TYPE_8822B(Context))
1683 mpt_SetRFPath_8822B(Context);
1684 */
1685 mpt_SetRFPath_819X(pAdapter);
1686 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1687 }
1688
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1689 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1690 {
1691 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1692
1693 if (!netif_running(pAdapter->pnetdev)) {
1694 return _FAIL;
1695 }
1696
1697
1698 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1699 return _FAIL;
1700 }
1701
1702 target_ther &= 0xff;
1703
1704 pHalData->eeprom_thermal_meter = target_ther;
1705
1706 return _SUCCESS;
1707 }
1708
1709
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1710 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1711 {
1712 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
1713 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1714 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1715 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1716 } else
1717 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1718
1719 }
1720
1721
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1722 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1723
1724 {
1725 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1726
1727 u32 ThermalValue = 0;
1728 s32 thermal_value_temp = 0;
1729 s8 thermal_offset = 0;
1730 u32 thermal_reg_mask = 0;
1731
1732 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id) || IS_8723F_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1733 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1734 else
1735 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1736
1737 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1738
1739 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1740
1741 thermal_value_temp = ThermalValue + thermal_offset;
1742
1743 if (thermal_value_temp > 63)
1744 ThermalValue = 63;
1745 else if (thermal_value_temp < 0)
1746 ThermalValue = 0;
1747 else
1748 ThermalValue = thermal_value_temp;
1749
1750 return (u8)ThermalValue;
1751 }
1752
1753
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1754 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1755 {
1756 #if 0
1757 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1758 rtw_msleep_os(1000);
1759 fw_cmd_data(pAdapter, value, 1);
1760 *value &= 0xFF;
1761 #else
1762 hal_mpt_TriggerRFThermalMeter(pAdapter);
1763 rtw_msleep_os(1000);
1764 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1765 #endif
1766
1767 }
1768
1769
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1770 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1771 {
1772 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1773
1774 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1775
1776 if (bStart) {/*/ Start Single Carrier.*/
1777 /*/ Start Single Carrier.*/
1778 /*/ 1. if OFDM block on?*/
1779 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1780 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1781
1782 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1783 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1784
1785 /*/ 3. turn on scramble setting*/
1786 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1787
1788 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1789 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\
1790 || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8723F)
1791 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
1792 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1793 else
1794 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1795 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1796
1797 } else {
1798 /*/ Stop Single Carrier.*/
1799 /*/ Stop Single Carrier.*/
1800 /*/ Turn off all test modes.*/
1801 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)\
1802 || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8723F)
1803 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)|| IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
1804 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1805 else
1806 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1807 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1808
1809 rtw_msleep_os(10);
1810 /*/BB Reset*/
1811 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1812 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1813 }
1814 }
1815
1816
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1817 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1818 {
1819 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1820 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1821 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1822 u32 ulAntennaTx = pHalData->antenna_tx_path;
1823 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1824 u8 rfPath;
1825
1826 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
1827 #ifdef PHYDM_MP_SUPPORT
1828 #ifdef CONFIG_RTL8814B
1829 if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
1830 {
1831 /* @Tx mode: RF0x00[19:16]=4'b0010 */
1832 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
1833 /* @Lowest RF gain index: RF_0x0[4:0] = 0*/
1834 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
1835 /* @RF LO enabled */
1836 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
1837 /* @SYN1 */
1838 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
1839 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
1840 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
1841 }
1842 #endif
1843 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1844 #endif
1845 return;
1846 }
1847
1848 switch (ulAntennaTx) {
1849 case ANTENNA_B:
1850 rfPath = RF_PATH_B;
1851 break;
1852 case ANTENNA_C:
1853 rfPath = RF_PATH_C;
1854 break;
1855 case ANTENNA_D:
1856 rfPath = RF_PATH_D;
1857 break;
1858 case ANTENNA_A:
1859 default:
1860 rfPath = RF_PATH_A;
1861 break;
1862 }
1863
1864 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1865 if (bStart) {
1866 /*/ Start Single Tone.*/
1867 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1868 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1869 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1870 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1871 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1872 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1873 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1874 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1875 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1876 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1877 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1878 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1879 #ifdef CONFIG_RTL8192F
1880 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1881 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1882 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1883 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1884 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1885 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1886 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1887 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1888 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1889 #endif
1890 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1891 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1892 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1893 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1894 } else {
1895 /*/ S0/S1 both use PATH A to configure*/
1896 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1897 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1898 }
1899 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1900 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1901 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1902 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1903 }
1904 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1905 /*Set BB REG 88C: Prevent SingleTone Fail*/
1906 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1907 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1908 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1909
1910 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1911 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1912 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1913 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1914 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1915 } else {/* S0/S1 both use PATH A to configure */
1916 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1917 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1918 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1919 }
1920 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1921 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1922 u8 p = RF_PATH_A;
1923
1924 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1925 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1926 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1927 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1928 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1929
1930 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1931
1932 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1933 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1934 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1935 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1936 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1937 }
1938 } else {
1939 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1940 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1941 #ifdef CONFIG_RTL8821C
1942 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1943 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1944 else
1945 #endif
1946 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1947 }
1948 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1949 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1950 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1951 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1952 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1953 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1954 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1955 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1956 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1957
1958 if (pHalData->external_pa_5g)
1959 {
1960 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1961 }
1962 else if (pHalData->ExternalPA_2G)
1963 {
1964 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1965 }
1966 } else {
1967 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1968 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1969
1970 if (pHalData->external_pa_5g) {
1971 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1972 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1973 } else if (pHalData->ExternalPA_2G) {
1974 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1975 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1976 }
1977 }
1978 #endif
1979 }
1980 #if defined(CONFIG_RTL8814A)
1981 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1982 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1983 #endif
1984 else /*/ Turn On SingleTone and turn off the other test modes.*/
1985 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1986
1987 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1988 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1989
1990 } else {/*/ Stop Single Ton e.*/
1991
1992 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1993 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1994 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1995 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1996 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1997 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1998 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1999 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
2000 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
2001 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
2002 #ifdef CONFIG_RTL8192F
2003 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
2004 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
2005 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
2006 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
2007 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
2008 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
2009 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
2010 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
2011 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
2012 #endif
2013 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
2014 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
2015 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
2016 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
2017 } else {
2018 /*/ S0/S1 both use PATH A to configure*/
2019 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
2020 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
2021 }
2022 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
2023 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
2024 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
2025 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
2026 }
2027 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2028 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
2029 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
2030 /*Set BB REG 88C: Prevent SingleTone Fail*/
2031 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
2032 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
2033 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
2034 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
2035 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2036 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
2037 } else { /* S0/S1 both use PATH A to configure */
2038 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
2039 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2040 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
2041 }
2042 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
2043 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2044 u8 p = RF_PATH_A;
2045
2046 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
2047
2048 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
2049 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
2050 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2051 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2052 }
2053 } else {
2054 p = pMptCtx->mpt_rf_path;
2055 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2056
2057 if (IS_HARDWARE_TYPE_8821C(pAdapter))
2058 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
2059
2060 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2061 }
2062
2063 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
2064 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
2065 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
2066 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
2067
2068 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
2069 RTW_INFO("Restore RFE control Pin cbc\n");
2070 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
2071 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
2072 }
2073 #endif
2074 }
2075 #if defined(CONFIG_RTL8814A)
2076 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
2077 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
2078
2079 else/*/ Turn off all test modes.*/
2080 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2081 #endif
2082 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2083 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2084
2085 }
2086 }
2087
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)2088 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
2089 {
2090 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2091 struct dm_struct *pdm_odm = &pHalData->odmpriv;
2092 u8 Rate;
2093
2094 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
2095
2096 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2097 #ifdef PHYDM_MP_SUPPORT
2098 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
2099 #endif
2100 return;
2101 }
2102
2103 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2104 if (bStart) {/* Start Carrier Suppression.*/
2105 if (Rate <= MPT_RATE_11M) {
2106 /*/ 1. if CCK block on?*/
2107 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2108 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
2109
2110 /*/Turn Off All Test Mode*/
2111 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2112 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
2113 else
2114 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2115
2116 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
2117 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
2118
2119 /*/Set CCK Tx Test Rate*/
2120 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
2121 }
2122
2123 /*Set for dynamic set Power index*/
2124 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2125 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2126
2127 } else {/* Stop Carrier Suppression.*/
2128
2129 if (Rate <= MPT_RATE_11M) {
2130 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2131 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2132
2133 /*BB Reset*/
2134 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2135 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2136 }
2137 /*Stop for dynamic set Power index*/
2138 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2139 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2140 }
2141 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2142 }
2143
hal_mpt_query_phytxok(PADAPTER pAdapter)2144 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2145 {
2146 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2147 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2148 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2149 u16 count = 0;
2150
2151 #ifdef PHYDM_MP_SUPPORT
2152 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2153 struct phydm_mp *mp = &dm->dm_mp_table;
2154
2155 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2156 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2157 count = mp->tx_phy_ok_cnt;
2158
2159 } else
2160 #endif
2161 {
2162
2163 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2164 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2165 else
2166 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2167 }
2168
2169 if (count > 50000) {
2170 rtw_reset_phy_trx_ok_counters(pAdapter);
2171 pAdapter->mppriv.tx.sended += count;
2172 count = 0;
2173 }
2174
2175 return pAdapter->mppriv.tx.sended + count;
2176
2177 }
2178
mpt_StopCckContTx(PADAPTER pAdapter)2179 static void mpt_StopCckContTx(
2180 PADAPTER pAdapter
2181 )
2182 {
2183 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2184 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2185 u8 u1bReg;
2186
2187 pMptCtx->bCckContTx = FALSE;
2188 pMptCtx->bOfdmContTx = FALSE;
2189
2190 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2191 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2192
2193 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2194 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2195 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2196
2197 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2198 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2199 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2200 }
2201
2202 /*BB Reset*/
2203 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2204 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2205
2206 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2207 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2208 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2209 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2210 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2211 }
2212
2213 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2214 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2215 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2216 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2217 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2218 }
2219
2220 } /* mpt_StopCckContTx */
2221
2222
mpt_StopOfdmContTx(PADAPTER pAdapter)2223 static void mpt_StopOfdmContTx(
2224 PADAPTER pAdapter
2225 )
2226 {
2227 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2228 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2229 u8 u1bReg;
2230 u32 data;
2231
2232 pMptCtx->bCckContTx = FALSE;
2233 pMptCtx->bOfdmContTx = FALSE;
2234
2235 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2236 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2237 else
2238 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2239
2240 rtw_mdelay_os(10);
2241
2242 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)){
2243 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2244 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2245 }
2246
2247 /*BB Reset*/
2248 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2249 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2250
2251 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2252 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2253 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2254 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2255 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2256 }
2257 } /* mpt_StopOfdmContTx */
2258
2259
mpt_StartCckContTx(PADAPTER pAdapter)2260 static void mpt_StartCckContTx(
2261 PADAPTER pAdapter
2262 )
2263 {
2264 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2265 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2266 u32 cckrate;
2267
2268 /* 1. if CCK block on */
2269 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2270 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2271
2272 /*Turn Off All Test Mode*/
2273 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2274 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2275 else
2276 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2277
2278 cckrate = pAdapter->mppriv.rateidx;
2279
2280 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2281
2282 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2283 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2284
2285 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2286 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2287 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2288 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2289 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2290 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2291 }
2292
2293 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2294 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2295 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2296 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2297 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2298 }
2299
2300 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2301 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2302 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2303 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2304 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2305 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2306 else
2307 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2308 }
2309
2310 pMptCtx->bCckContTx = TRUE;
2311 pMptCtx->bOfdmContTx = FALSE;
2312
2313 } /* mpt_StartCckContTx */
2314
2315
mpt_StartOfdmContTx(PADAPTER pAdapter)2316 static void mpt_StartOfdmContTx(
2317 PADAPTER pAdapter
2318 )
2319 {
2320 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2321 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2322
2323 /* 1. if OFDM block on?*/
2324 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2325 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2326
2327 /* 2. set CCK test mode off, set to CCK normal mode*/
2328 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2329
2330 /* 3. turn on scramble setting*/
2331 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2332
2333 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2334 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2335 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2336 }
2337
2338 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2339 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2340 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2341 else
2342 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2343
2344 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2345 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2346 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2347 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2348 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2349 }
2350
2351 pMptCtx->bCckContTx = FALSE;
2352 pMptCtx->bOfdmContTx = TRUE;
2353 } /* mpt_StartOfdmContTx */
2354
2355 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) \
2356 || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
2357 || defined(CONFIG_RTL8723F)
2358 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO * pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2359 static void mpt_convert_phydm_txinfo_for_jaguar3(
2360 RT_PMAC_TX_INFO *pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2361 {
2362 phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
2363 phydmtxinfo->mode = pMacTxInfo->Mode;
2364 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
2365 phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
2366 phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
2367 phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
2368 phydmtxinfo->bw = pMacTxInfo->BandWidth;
2369 phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
2370 phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
2371 phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
2372 phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
2373 phydmtxinfo->sfd = pMacTxInfo->SFD;
2374 phydmtxinfo->signal_field = pMacTxInfo->SignalField;
2375 phydmtxinfo->service_field = pMacTxInfo->ServiceField;
2376 phydmtxinfo->length = pMacTxInfo->LENGTH;
2377 #if defined(CONFIG_RTL8723F)
2378 if (IS_MPT_CCK_RATE(pMacTxInfo->TX_RATE))
2379 phydmtxinfo->service_field_bit2= 0x1;
2380 phydmtxinfo->packet_length = pMacTxInfo->PacketLength;
2381 #endif
2382 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
2383 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
2384 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
2385 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
2386 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
2387 phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
2388 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
2389 }
2390 #endif
2391
2392 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2393 u8 mpt_ProSetPMacTx(PADAPTER Adapter)
2394 {
2395 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2396 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2397 struct mp_priv *pmppriv = &Adapter->mppriv;
2398 struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
2399 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2400 struct dm_struct *p_dm_odm;
2401 u32 u4bTmp;
2402 u8 status = _TRUE;
2403
2404 p_dm_odm = &pHalData->odmpriv;
2405
2406 #if 0
2407 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2408 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2409 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2410 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2411 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2412 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2413
2414 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2415 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2416 #endif
2417 if (pmppriv->pktInterval != 0)
2418 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2419
2420 if (pmppriv->tx.count != 0)
2421 PMacTxInfo.PacketCount = pmppriv->tx.count;
2422
2423 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2424 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2425 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2426
2427 if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
2428 return _FALSE;
2429 if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
2430 return _FALSE;
2431 if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
2432 return _FALSE;
2433 if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
2434 return _FALSE;
2435 if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
2436 return _FALSE;
2437
2438 if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
2439 PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
2440 else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
2441 PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
2442 else
2443 PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
2444
2445 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(Adapter)) {
2446 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2447 struct phydm_pmac_info phydm_mactxinfo;
2448
2449 if (PMacTxInfo.bEnPMacTx == TRUE) {
2450 pMptCtx->HWTxmode = PMacTxInfo.Mode;
2451 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2452 if (PMacTxInfo.Mode != PACKETS_TX)
2453 hal_mpt_SetTxPower(Adapter);
2454 } else {
2455 PMacTxInfo.Mode = pMptCtx->HWTxmode;
2456 PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
2457 pMptCtx->HWTxmode = TEST_NONE;
2458 }
2459 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2460 phydm_mp_set_single_tone(p_dm_odm, PMacTxInfo.bEnPMacTx ,pMptCtx->mpt_rf_path);
2461 RTW_INFO("To set Tx mode OFDM_Single_Tone_TX\n");
2462 return status;
2463 }
2464
2465 if (PMacTxInfo.Mode == CCK_Carrier_Suppression_TX) {
2466 phydm_mp_set_carrier_supp(p_dm_odm, PMacTxInfo.bEnPMacTx ,PMacTxInfo.TX_RATE);
2467
2468 RTW_INFO("To set Tx mode CCK_Carrier_Suppression_TX\n");
2469 return status;
2470 }
2471
2472 mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
2473 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2474 #endif
2475 return status;
2476 }
2477
2478 if (PMacTxInfo.bEnPMacTx == FALSE) {
2479 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2480 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2481 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2482 mpt_StopCckContTx(Adapter);
2483 else
2484 mpt_StopOfdmContTx(Adapter);
2485 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2486 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2487 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2488 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2489 } else
2490 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2491
2492 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2493 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2494 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2495 mpt_StopCckContTx(Adapter);
2496 else
2497 mpt_StopOfdmContTx(Adapter);
2498
2499 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2500 }
2501 pMptCtx->HWTxmode = TEST_NONE;
2502 return status;
2503 }
2504
2505 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2506
2507 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2508 pMptCtx->HWTxmode = CONTINUOUS_TX;
2509 PMacTxInfo.PacketCount = 1;
2510
2511 hal_mpt_SetTxPower(Adapter);
2512
2513 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2514 mpt_StartCckContTx(Adapter);
2515 else
2516 mpt_StartOfdmContTx(Adapter);
2517 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2518 /* Continuous TX -> HW TX -> RF Setting */
2519 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2520 PMacTxInfo.PacketCount = 1;
2521
2522 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2523 mpt_StartCckContTx(Adapter);
2524 else
2525 mpt_StartOfdmContTx(Adapter);
2526 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2527 pMptCtx->HWTxmode = PACKETS_TX;
2528 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2529 PMacTxInfo.PacketCount = 0xffff;
2530 }
2531
2532 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2533 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2534 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2535 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2536 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2537 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2538 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2539 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2540 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2541
2542 if (PMacTxInfo.bSPreamble)
2543 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2544 else
2545 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2546 } else {
2547 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2548
2549 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2550 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2551
2552 if (PMacTxInfo.PacketPattern == 0x12)
2553 u4bTmp = 0x3000000;
2554 else
2555 u4bTmp = 0;
2556 }
2557
2558 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2559 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2560 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2561 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2562 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2563 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2564 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2565 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2566 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2567 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2568
2569 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2570 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2571 }
2572
2573 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2574 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2575 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2576
2577 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2578 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2579
2580 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2581 /*& Duration & Frame control*/
2582 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2583
2584 /* Address1 [0:3]*/
2585 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2586 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2587
2588 /* Address3 [3:0]*/
2589 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2590
2591 /* Address2[0:1] & Address1 [5:4]*/
2592 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2593 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2594
2595 /* Address2 [5:2]*/
2596 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2597 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2598
2599 /* Sequence Control & Address3 [5:4]*/
2600 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2601 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2602 } else {
2603 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2604 /* & Duration & Frame control */
2605 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2606
2607 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2608 /* Address1 [0:3]*/
2609 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2610 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2611
2612 /* Address3 [3:0]*/
2613 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2614
2615 /* Address2[0:1] & Address1 [5:4]*/
2616 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2617 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2618
2619 /* Address2 [5:2] */
2620 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2621 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2622
2623 /* Sequence Control & Address3 [5:4]*/
2624 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2625 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2626 }
2627
2628 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2629
2630 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2631 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2632 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2633
2634 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2635 u32 offset = 0xb44;
2636
2637 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2638 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2639 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2640 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2641 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2642 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2643
2644 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2645 u32 offset = 0xb4c;
2646
2647 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2648 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2649 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2650 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2651 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2652 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2653 }
2654
2655 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2656 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2657 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2658 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2659 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2660 } else
2661 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2662
2663 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2664 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2665
2666 return status;
2667 }
2668
2669 #endif
2670
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2671 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2672 {
2673 u8 Rate;
2674
2675 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2676 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2677 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2678
2679 if (Rate <= MPT_RATE_11M) {
2680 if (bStart)
2681 mpt_StartCckContTx(pAdapter);
2682 else
2683 mpt_StopCckContTx(pAdapter);
2684
2685 } else if (Rate >= MPT_RATE_6M) {
2686 if (bStart)
2687 mpt_StartOfdmContTx(pAdapter);
2688 else
2689 mpt_StopOfdmContTx(pAdapter);
2690 }
2691 }
2692
mpt_trigger_tssi_tracking(PADAPTER pAdapter,u8 rf_path)2693 void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
2694 {
2695 #ifdef CONFIG_RTL8814B
2696 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2697 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2698
2699 halrf_do_tssi_8814b(pDM_Odm, rf_path);
2700 #endif
2701 }
2702
2703 #endif /* CONFIG_MP_INCLUDE*/
2704