1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2019 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _RTW_XMIT_H_ 16*4882a593Smuzhiyun #define _RTW_XMIT_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 20*4882a593Smuzhiyun #ifdef CONFIG_TX_AGGREGATION 21*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C 22*4882a593Smuzhiyun #ifdef CONFIG_SDIO_TX_FORMAT_DUMMY_AUTO 23*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (51200) 24*4882a593Smuzhiyun #else 25*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (32764) 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (20480) /* 20k */ 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun /* #define SDIO_TX_AGG_MAX 5 */ 31*4882a593Smuzhiyun #else 32*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (1664) 33*4882a593Smuzhiyun #define SDIO_TX_AGG_MAX 1 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #if defined CONFIG_SDIO_HCI 37*4882a593Smuzhiyun #define NR_XMITBUFF (16) 38*4882a593Smuzhiyun #define SDIO_TX_DIV_NUM (2) 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun #if defined(CONFIG_GSPI_HCI) 41*4882a593Smuzhiyun #define NR_XMITBUFF (128) 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #elif defined (CONFIG_USB_HCI) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_AGGREGATION 47*4882a593Smuzhiyun #if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1) 48*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (12288) /* 12k 1536*8 */ 49*4882a593Smuzhiyun #elif defined (CONFIG_PLATFORM_MSTAR) 50*4882a593Smuzhiyun #define MAX_XMITBUF_SZ 7680 /* 7.5k */ 51*4882a593Smuzhiyun #else 52*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (20480) /* 20k */ 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun #else 55*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (2048) 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef CONFIG_SINGLE_XMIT_BUF 59*4882a593Smuzhiyun #define NR_XMITBUFF (1) 60*4882a593Smuzhiyun #else 61*4882a593Smuzhiyun #define NR_XMITBUFF (4) 62*4882a593Smuzhiyun #endif /* CONFIG_SINGLE_XMIT_BUF */ 63*4882a593Smuzhiyun #elif defined (CONFIG_PCI_HCI) 64*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU 65*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (3500) 66*4882a593Smuzhiyun #else 67*4882a593Smuzhiyun #define MAX_XMITBUF_SZ (1664) 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING 70*4882a593Smuzhiyun #define NR_XMITBUFF (256) 71*4882a593Smuzhiyun #else 72*4882a593Smuzhiyun #define NR_XMITBUFF (128) 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 78*4882a593Smuzhiyun #define XMITBUF_ALIGN_SZ 4 79*4882a593Smuzhiyun #else 80*4882a593Smuzhiyun #ifdef USB_XMITBUF_ALIGN_SZ 81*4882a593Smuzhiyun #define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ) 82*4882a593Smuzhiyun #else 83*4882a593Smuzhiyun #define XMITBUF_ALIGN_SZ 512 84*4882a593Smuzhiyun #endif 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* xmit extension buff defination */ 89*4882a593Smuzhiyun #define MAX_XMIT_EXTBUF_SZ (1536) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #ifdef CONFIG_SINGLE_XMIT_BUF 92*4882a593Smuzhiyun #define NR_XMIT_EXTBUFF (1) 93*4882a593Smuzhiyun #else 94*4882a593Smuzhiyun #define NR_XMIT_EXTBUFF (32) 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifdef CONFIG_RTL8812A 98*4882a593Smuzhiyun #define MAX_CMDBUF_SZ (512 * 18) 99*4882a593Smuzhiyun #elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF) 100*4882a593Smuzhiyun #define MAX_CMDBUF_SZ (128*70) /*(8960)*/ 101*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822C) && defined(CONFIG_WAR_OFFLOAD) 102*4882a593Smuzhiyun #define MAX_CMDBUF_SZ (128*128) /*(16k) */ 103*4882a593Smuzhiyun #else 104*4882a593Smuzhiyun #define MAX_CMDBUF_SZ (5120) /* (4096) */ 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define MAX_BEACON_LEN 512 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define MAX_NUMBLKS (1) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define XMIT_VO_QUEUE (0) 112*4882a593Smuzhiyun #define XMIT_VI_QUEUE (1) 113*4882a593Smuzhiyun #define XMIT_BE_QUEUE (2) 114*4882a593Smuzhiyun #define XMIT_BK_QUEUE (3) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define VO_QUEUE_INX 0 117*4882a593Smuzhiyun #define VI_QUEUE_INX 1 118*4882a593Smuzhiyun #define BE_QUEUE_INX 2 119*4882a593Smuzhiyun #define BK_QUEUE_INX 3 120*4882a593Smuzhiyun #define BCN_QUEUE_INX 4 121*4882a593Smuzhiyun #define MGT_QUEUE_INX 5 122*4882a593Smuzhiyun #define TXCMD_QUEUE_INX 6 123*4882a593Smuzhiyun #define HIGH_QUEUE_INX 7 124*4882a593Smuzhiyun /* keep high queue to be the last one, so we can extend HIQ to port 1, 2, ... */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #ifndef CONFIG_PORT_BASED_HIQ 127*4882a593Smuzhiyun #define HW_QUEUE_ENTRY 8 128*4882a593Smuzhiyun #else 129*4882a593Smuzhiyun #define HI_QUEUE_INX(n) (HIGH_QUEUE_INX + (n)) 130*4882a593Smuzhiyun #define HW_QUEUE_ENTRY (8 + CONFIG_IFACE_NUMBER - 1) 131*4882a593Smuzhiyun #endif 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 134*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH 135*4882a593Smuzhiyun #define TX_BD_NUM (128+1) /* +1 result from ring buffer */ 136*4882a593Smuzhiyun #else 137*4882a593Smuzhiyun #define TXDESC_NUM 128 138*4882a593Smuzhiyun #endif 139*4882a593Smuzhiyun #endif 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ 142*4882a593Smuzhiyun do {\ 143*4882a593Smuzhiyun dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\ 144*4882a593Smuzhiyun pattrib_iv[0] = dot11txpn._byte_.TSC0;\ 145*4882a593Smuzhiyun pattrib_iv[1] = dot11txpn._byte_.TSC1;\ 146*4882a593Smuzhiyun pattrib_iv[2] = dot11txpn._byte_.TSC2;\ 147*4882a593Smuzhiyun pattrib_iv[3] = ((keyidx & 0x3)<<6);\ 148*4882a593Smuzhiyun } while (0) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ 152*4882a593Smuzhiyun do {\ 153*4882a593Smuzhiyun dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ 154*4882a593Smuzhiyun pattrib_iv[0] = dot11txpn._byte_.TSC1;\ 155*4882a593Smuzhiyun pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ 156*4882a593Smuzhiyun pattrib_iv[2] = dot11txpn._byte_.TSC0;\ 157*4882a593Smuzhiyun pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ 158*4882a593Smuzhiyun pattrib_iv[4] = dot11txpn._byte_.TSC2;\ 159*4882a593Smuzhiyun pattrib_iv[5] = dot11txpn._byte_.TSC3;\ 160*4882a593Smuzhiyun pattrib_iv[6] = dot11txpn._byte_.TSC4;\ 161*4882a593Smuzhiyun pattrib_iv[7] = dot11txpn._byte_.TSC5;\ 162*4882a593Smuzhiyun } while (0) 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define AES_IV(pattrib_iv, dot11txpn, keyidx)\ 165*4882a593Smuzhiyun do {\ 166*4882a593Smuzhiyun dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ 167*4882a593Smuzhiyun pattrib_iv[0] = dot11txpn._byte_.TSC0;\ 168*4882a593Smuzhiyun pattrib_iv[1] = dot11txpn._byte_.TSC1;\ 169*4882a593Smuzhiyun pattrib_iv[2] = 0;\ 170*4882a593Smuzhiyun pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ 171*4882a593Smuzhiyun pattrib_iv[4] = dot11txpn._byte_.TSC2;\ 172*4882a593Smuzhiyun pattrib_iv[5] = dot11txpn._byte_.TSC3;\ 173*4882a593Smuzhiyun pattrib_iv[6] = dot11txpn._byte_.TSC4;\ 174*4882a593Smuzhiyun pattrib_iv[7] = dot11txpn._byte_.TSC5;\ 175*4882a593Smuzhiyun } while (0) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define GCMP_IV(a, b, c) AES_IV(a, b, c) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* Check if AMPDU Tx is supported or not. If it is supported, 180*4882a593Smuzhiyun * it need to check "amsdu in ampdu" is supported or not. 181*4882a593Smuzhiyun * (ampdu_en, amsdu_ampdu_en) = 182*4882a593Smuzhiyun * (0, x) : AMPDU is not enable, but AMSDU is valid to send. 183*4882a593Smuzhiyun * (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send. 184*4882a593Smuzhiyun * (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send. 185*4882a593Smuzhiyun */ 186*4882a593Smuzhiyun #define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\ 187*4882a593Smuzhiyun ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define IS_AMSDU_AMPDU_VALID(pattrib)\ 190*4882a593Smuzhiyun !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 193*4882a593Smuzhiyun #define HWXMIT_ENTRY 5 194*4882a593Smuzhiyun #else 195*4882a593Smuzhiyun #define HWXMIT_ENTRY 4 196*4882a593Smuzhiyun #endif 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* For Buffer Descriptor ring architecture */ 199*4882a593Smuzhiyun #if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH) 200*4882a593Smuzhiyun #if defined(CONFIG_RTL8192E) 201*4882a593Smuzhiyun #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ 202*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814A) 203*4882a593Smuzhiyun #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ 204*4882a593Smuzhiyun #else 205*4882a593Smuzhiyun #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ 206*4882a593Smuzhiyun #endif 207*4882a593Smuzhiyun #endif 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\ 210*4882a593Smuzhiyun defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\ 211*4882a593Smuzhiyun defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\ 212*4882a593Smuzhiyun defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\ 213*4882a593Smuzhiyun defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F) ||\ 214*4882a593Smuzhiyun defined(CONFIG_RTL8723F) 215*4882a593Smuzhiyun #define TXDESC_SIZE 40 216*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) 217*4882a593Smuzhiyun #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8822B */ 218*4882a593Smuzhiyun #elif defined(CONFIG_RTL8821C) 219*4882a593Smuzhiyun #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8821C */ 220*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814B) 221*4882a593Smuzhiyun #define TXDESC_SIZE (16 + 32) 222*4882a593Smuzhiyun #else 223*4882a593Smuzhiyun #define TXDESC_SIZE 32 /* old IC (ex: 8188E) */ 224*4882a593Smuzhiyun #endif 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE 227*4882a593Smuzhiyun #define EARLY_MODE_INFO_SIZE 8 228*4882a593Smuzhiyun #endif 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 232*4882a593Smuzhiyun #define TXDESC_OFFSET TXDESC_SIZE 233*4882a593Smuzhiyun #endif 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 236*4882a593Smuzhiyun #ifdef USB_PACKET_OFFSET_SZ 237*4882a593Smuzhiyun #define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ) 238*4882a593Smuzhiyun #else 239*4882a593Smuzhiyun #define PACKET_OFFSET_SZ (8) 240*4882a593Smuzhiyun #endif 241*4882a593Smuzhiyun #define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) 242*4882a593Smuzhiyun #endif 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 245*4882a593Smuzhiyun #if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH) 246*4882a593Smuzhiyun /* this section is defined for buffer descriptor ring architecture */ 247*4882a593Smuzhiyun #define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */ 248*4882a593Smuzhiyun /* tx desc and payload are in the same buf */ 249*4882a593Smuzhiyun #define TXDESC_OFFSET (TX_WIFI_INFO_SIZE) 250*4882a593Smuzhiyun #else 251*4882a593Smuzhiyun /* tx desc and payload are NOT in the same buf */ 252*4882a593Smuzhiyun #define TXDESC_OFFSET (0) 253*4882a593Smuzhiyun /* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */ 254*4882a593Smuzhiyun #define TX_DESC_NEXT_DESC_OFFSET (TXDESC_SIZE + 8) 255*4882a593Smuzhiyun #endif 256*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */ 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun enum TXDESC_SC { 259*4882a593Smuzhiyun SC_DONT_CARE = 0x00, 260*4882a593Smuzhiyun SC_UPPER = 0x01, 261*4882a593Smuzhiyun SC_LOWER = 0x02, 262*4882a593Smuzhiyun SC_DUPLICATE = 0x03 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 266*4882a593Smuzhiyun #ifndef CONFIG_TRX_BD_ARCH /* CONFIG_TRX_BD_ARCH doesn't need this */ 267*4882a593Smuzhiyun #define TXDESC_64_BYTES 268*4882a593Smuzhiyun #endif 269*4882a593Smuzhiyun #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \ 270*4882a593Smuzhiyun || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \ 271*4882a593Smuzhiyun || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723F) 272*4882a593Smuzhiyun #define TXDESC_40_BYTES 273*4882a593Smuzhiyun #endif 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH 276*4882a593Smuzhiyun struct tx_buf_desc { 277*4882a593Smuzhiyun #ifdef CONFIG_64BIT_DMA 278*4882a593Smuzhiyun #define TX_BUFFER_SEG_SIZE 4 /* in unit of DWORD */ 279*4882a593Smuzhiyun #else 280*4882a593Smuzhiyun #define TX_BUFFER_SEG_SIZE 2 /* in unit of DWORD */ 281*4882a593Smuzhiyun #endif 282*4882a593Smuzhiyun unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)]; 283*4882a593Smuzhiyun } __packed; 284*4882a593Smuzhiyun #elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */ 285*4882a593Smuzhiyun /* 8192EE_TODO */ 286*4882a593Smuzhiyun struct tx_desc { 287*4882a593Smuzhiyun unsigned int txdw0; 288*4882a593Smuzhiyun unsigned int txdw1; 289*4882a593Smuzhiyun unsigned int txdw2; 290*4882a593Smuzhiyun unsigned int txdw3; 291*4882a593Smuzhiyun unsigned int txdw4; 292*4882a593Smuzhiyun unsigned int txdw5; 293*4882a593Smuzhiyun unsigned int txdw6; 294*4882a593Smuzhiyun unsigned int txdw7; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun #else 297*4882a593Smuzhiyun struct tx_desc { 298*4882a593Smuzhiyun unsigned int txdw0; 299*4882a593Smuzhiyun unsigned int txdw1; 300*4882a593Smuzhiyun unsigned int txdw2; 301*4882a593Smuzhiyun unsigned int txdw3; 302*4882a593Smuzhiyun unsigned int txdw4; 303*4882a593Smuzhiyun unsigned int txdw5; 304*4882a593Smuzhiyun unsigned int txdw6; 305*4882a593Smuzhiyun unsigned int txdw7; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES) 308*4882a593Smuzhiyun unsigned int txdw8; 309*4882a593Smuzhiyun unsigned int txdw9; 310*4882a593Smuzhiyun #endif /* TXDESC_40_BYTES */ 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun #ifdef TXDESC_64_BYTES 313*4882a593Smuzhiyun unsigned int txdw10; 314*4882a593Smuzhiyun unsigned int txdw11; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now, our descriptor */ 317*4882a593Smuzhiyun /* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */ 318*4882a593Smuzhiyun /* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */ 319*4882a593Smuzhiyun /* number or enlarge descriptor size as 64 bytes. */ 320*4882a593Smuzhiyun unsigned int txdw12; 321*4882a593Smuzhiyun unsigned int txdw13; 322*4882a593Smuzhiyun unsigned int txdw14; 323*4882a593Smuzhiyun unsigned int txdw15; 324*4882a593Smuzhiyun #endif 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun #endif 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun #ifndef CONFIG_TRX_BD_ARCH 329*4882a593Smuzhiyun union txdesc { 330*4882a593Smuzhiyun struct tx_desc txdesc; 331*4882a593Smuzhiyun unsigned int value[TXDESC_SIZE >> 2]; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun #endif 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 336*4882a593Smuzhiyun #define PCI_MAX_TX_QUEUE_COUNT HW_QUEUE_ENTRY 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun struct rtw_tx_ring { 339*4882a593Smuzhiyun unsigned char qid; 340*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH 341*4882a593Smuzhiyun struct tx_buf_desc *buf_desc; 342*4882a593Smuzhiyun #else 343*4882a593Smuzhiyun struct tx_desc *desc; 344*4882a593Smuzhiyun #endif 345*4882a593Smuzhiyun dma_addr_t dma; 346*4882a593Smuzhiyun unsigned int idx; 347*4882a593Smuzhiyun unsigned int entries; 348*4882a593Smuzhiyun _queue queue; 349*4882a593Smuzhiyun u32 qlen; 350*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH 351*4882a593Smuzhiyun u16 hw_rp_cache; 352*4882a593Smuzhiyun #endif 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun #ifdef DBG_TXBD_DESC_DUMP 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun #define TX_BAK_FRMAE_CNT 10 358*4882a593Smuzhiyun #define TX_BAK_DESC_LEN 48 /* byte */ 359*4882a593Smuzhiyun #define TX_BAK_DATA_LEN 30 /* byte */ 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun struct rtw_tx_desc_backup { 362*4882a593Smuzhiyun int tx_bak_rp; 363*4882a593Smuzhiyun int tx_bak_wp; 364*4882a593Smuzhiyun u8 tx_bak_desc[TX_BAK_DESC_LEN]; 365*4882a593Smuzhiyun u8 tx_bak_data_hdr[TX_BAK_DATA_LEN]; 366*4882a593Smuzhiyun u8 tx_desc_size; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun #endif 369*4882a593Smuzhiyun #endif 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun struct hw_xmit { 372*4882a593Smuzhiyun /* _lock xmit_lock; */ 373*4882a593Smuzhiyun /* _list pending; */ 374*4882a593Smuzhiyun _queue *sta_queue; 375*4882a593Smuzhiyun /* struct hw_txqueue *phwtxqueue; */ 376*4882a593Smuzhiyun /* sint txcmdcnt; */ 377*4882a593Smuzhiyun int accnt; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun struct pkt_attrib { 381*4882a593Smuzhiyun u8 type; 382*4882a593Smuzhiyun u8 subtype; 383*4882a593Smuzhiyun u8 bswenc; 384*4882a593Smuzhiyun u8 dhcp_pkt; 385*4882a593Smuzhiyun u16 ether_type; 386*4882a593Smuzhiyun u16 seqnum; 387*4882a593Smuzhiyun u8 hw_ssn_sel; /* for HW_SEQ0,1,2,3 */ 388*4882a593Smuzhiyun u16 pkt_hdrlen; /* the original 802.3 pkt header len */ 389*4882a593Smuzhiyun u16 hdrlen; /* the WLAN Header Len */ 390*4882a593Smuzhiyun u32 pktlen; /* the original 802.3 pkt raw_data len (not include ether_hdr data) */ 391*4882a593Smuzhiyun u32 last_txcmdsz; 392*4882a593Smuzhiyun u8 nr_frags; 393*4882a593Smuzhiyun u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ 394*4882a593Smuzhiyun u8 bmc_camid; 395*4882a593Smuzhiyun u8 iv_len; 396*4882a593Smuzhiyun u8 icv_len; 397*4882a593Smuzhiyun u8 iv[18]; 398*4882a593Smuzhiyun u8 icv[16]; 399*4882a593Smuzhiyun u8 priority; 400*4882a593Smuzhiyun u8 ack_policy; 401*4882a593Smuzhiyun u8 mac_id; 402*4882a593Smuzhiyun u8 vcs_mode; /* virtual carrier sense method */ 403*4882a593Smuzhiyun u8 dst[ETH_ALEN]; 404*4882a593Smuzhiyun u8 src[ETH_ALEN]; 405*4882a593Smuzhiyun u8 ta[ETH_ALEN]; 406*4882a593Smuzhiyun u8 ra[ETH_ALEN]; 407*4882a593Smuzhiyun #ifdef CONFIG_RTW_WDS 408*4882a593Smuzhiyun u8 wds; 409*4882a593Smuzhiyun #endif 410*4882a593Smuzhiyun #ifdef CONFIG_RTW_MESH 411*4882a593Smuzhiyun u8 mda[ETH_ALEN]; /* mesh da */ 412*4882a593Smuzhiyun u8 msa[ETH_ALEN]; /* mesh sa */ 413*4882a593Smuzhiyun u8 meshctrl_len; /* Length of Mesh Control field */ 414*4882a593Smuzhiyun u8 mesh_frame_mode; 415*4882a593Smuzhiyun #if CONFIG_RTW_MESH_DATA_BMC_TO_UC 416*4882a593Smuzhiyun u8 mb2u; 417*4882a593Smuzhiyun #endif 418*4882a593Smuzhiyun u8 mfwd_ttl; 419*4882a593Smuzhiyun u32 mseq; 420*4882a593Smuzhiyun #endif 421*4882a593Smuzhiyun #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX 422*4882a593Smuzhiyun u8 hw_csum; 423*4882a593Smuzhiyun #endif 424*4882a593Smuzhiyun u8 key_idx; 425*4882a593Smuzhiyun u8 qos_en; 426*4882a593Smuzhiyun u8 ht_en; 427*4882a593Smuzhiyun u8 raid;/* rate adpative id */ 428*4882a593Smuzhiyun u8 bwmode; 429*4882a593Smuzhiyun u8 ch_offset;/* PRIME_CHNL_OFFSET */ 430*4882a593Smuzhiyun u8 sgi;/* short GI */ 431*4882a593Smuzhiyun u8 ampdu_en;/* tx ampdu enable */ 432*4882a593Smuzhiyun u8 ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */ 433*4882a593Smuzhiyun u8 amsdu; 434*4882a593Smuzhiyun u8 amsdu_ampdu_en;/* tx amsdu in ampdu enable */ 435*4882a593Smuzhiyun u8 mdata;/* more data bit */ 436*4882a593Smuzhiyun u8 pctrl;/* per packet txdesc control enable */ 437*4882a593Smuzhiyun u8 triggered;/* for ap mode handling Power Saving sta */ 438*4882a593Smuzhiyun u8 qsel; 439*4882a593Smuzhiyun u8 order;/* order bit */ 440*4882a593Smuzhiyun u8 eosp; 441*4882a593Smuzhiyun u8 rate; 442*4882a593Smuzhiyun u8 intel_proxim; 443*4882a593Smuzhiyun u8 retry_ctrl; 444*4882a593Smuzhiyun u8 mbssid; 445*4882a593Smuzhiyun u8 ldpc; 446*4882a593Smuzhiyun u8 stbc; 447*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA 448*4882a593Smuzhiyun u8 trigger_frame; 449*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */ 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun struct sta_info *psta; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun u8 rtsen; 454*4882a593Smuzhiyun u8 cts2self; 455*4882a593Smuzhiyun union Keytype dot11tkiptxmickey; 456*4882a593Smuzhiyun /* union Keytype dot11tkiprxmickey; */ 457*4882a593Smuzhiyun union Keytype dot118021x_UncstKey; 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun #ifdef CONFIG_TDLS 460*4882a593Smuzhiyun u8 direct_link; 461*4882a593Smuzhiyun struct sta_info *ptdls_sta; 462*4882a593Smuzhiyun #endif /* CONFIG_TDLS */ 463*4882a593Smuzhiyun u8 key_type; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun u8 icmp_pkt; 466*4882a593Smuzhiyun u8 hipriority_pkt; /* high priority packet */ 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 469*4882a593Smuzhiyun u16 txbf_p_aid;/*beamforming Partial_AID*/ 470*4882a593Smuzhiyun u16 txbf_g_id;/*beamforming Group ID*/ 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* 473*4882a593Smuzhiyun * 2'b00: Unicast NDPA 474*4882a593Smuzhiyun * 2'b01: Broadcast NDPA 475*4882a593Smuzhiyun * 2'b10: Beamforming Report Poll 476*4882a593Smuzhiyun * 2'b11: Final Beamforming Report Poll 477*4882a593Smuzhiyun */ 478*4882a593Smuzhiyun u8 bf_pkt_type; 479*4882a593Smuzhiyun #endif 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 482*4882a593Smuzhiyun u8 ps_dontq; /* 1: this frame can't be queued at PS state */ 483*4882a593Smuzhiyun #endif 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun #ifdef CONFIG_RTW_WDS 487*4882a593Smuzhiyun #define XATTRIB_GET_WDS(xattrib) ((xattrib)->wds) 488*4882a593Smuzhiyun #else 489*4882a593Smuzhiyun #define XATTRIB_GET_WDS(xattrib) 0 490*4882a593Smuzhiyun #endif 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun #ifdef CONFIG_RTW_MESH 493*4882a593Smuzhiyun #define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len) 494*4882a593Smuzhiyun #else 495*4882a593Smuzhiyun #define XATTRIB_GET_MCTRL_LEN(xattrib) 0 496*4882a593Smuzhiyun #endif 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU 499*4882a593Smuzhiyun enum { 500*4882a593Smuzhiyun RTW_AMSDU_TIMER_UNSET = 0, 501*4882a593Smuzhiyun RTW_AMSDU_TIMER_SETTING, 502*4882a593Smuzhiyun RTW_AMSDU_TIMER_TIMEOUT, 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun #endif 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun #define WLANHDR_OFFSET 64 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun #define NULL_FRAMETAG (0x0) 509*4882a593Smuzhiyun #define DATA_FRAMETAG 0x01 510*4882a593Smuzhiyun #define L2_FRAMETAG 0x02 511*4882a593Smuzhiyun #define MGNT_FRAMETAG 0x03 512*4882a593Smuzhiyun #define AMSDU_FRAMETAG 0x04 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #define EII_FRAMETAG 0x05 515*4882a593Smuzhiyun #define IEEE8023_FRAMETAG 0x06 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun #define MP_FRAMETAG 0x07 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun #define TXAGG_FRAMETAG 0x08 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun enum { 522*4882a593Smuzhiyun XMITBUF_DATA = 0, 523*4882a593Smuzhiyun XMITBUF_MGNT = 1, 524*4882a593Smuzhiyun XMITBUF_CMD = 2, 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun bool rtw_xmit_ac_blocked(_adapter *adapter); 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun struct submit_ctx { 530*4882a593Smuzhiyun systime submit_time; /* */ 531*4882a593Smuzhiyun u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ 532*4882a593Smuzhiyun int status; /* status for operation */ 533*4882a593Smuzhiyun #ifdef PLATFORM_LINUX 534*4882a593Smuzhiyun struct completion done; 535*4882a593Smuzhiyun #endif 536*4882a593Smuzhiyun }; 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun enum { 539*4882a593Smuzhiyun RTW_SCTX_SUBMITTED = -1, 540*4882a593Smuzhiyun RTW_SCTX_DONE_SUCCESS = 0, 541*4882a593Smuzhiyun RTW_SCTX_DONE_UNKNOWN, 542*4882a593Smuzhiyun RTW_SCTX_DONE_TIMEOUT, 543*4882a593Smuzhiyun RTW_SCTX_DONE_BUF_ALLOC, 544*4882a593Smuzhiyun RTW_SCTX_DONE_BUF_FREE, 545*4882a593Smuzhiyun RTW_SCTX_DONE_WRITE_PORT_ERR, 546*4882a593Smuzhiyun RTW_SCTX_DONE_TX_DESC_NA, 547*4882a593Smuzhiyun RTW_SCTX_DONE_TX_DENY, 548*4882a593Smuzhiyun RTW_SCTX_DONE_CCX_PKT_FAIL, 549*4882a593Smuzhiyun RTW_SCTX_DONE_DRV_STOP, 550*4882a593Smuzhiyun RTW_SCTX_DONE_DEV_REMOVE, 551*4882a593Smuzhiyun RTW_SCTX_DONE_CMD_ERROR, 552*4882a593Smuzhiyun RTW_SCTX_DONE_CMD_DROP, 553*4882a593Smuzhiyun RTX_SCTX_CSTR_WAIT_RPT2, 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); 558*4882a593Smuzhiyun int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg); 559*4882a593Smuzhiyun void rtw_sctx_done_err(struct submit_ctx **sctx, int status); 560*4882a593Smuzhiyun void rtw_sctx_done(struct submit_ctx **sctx); 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun struct xmit_buf { 563*4882a593Smuzhiyun _list list; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun _adapter *padapter; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun u8 *pallocated_buf; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun u8 *pbuf; 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun void *priv_data; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */ 574*4882a593Smuzhiyun u16 flags; 575*4882a593Smuzhiyun u32 alloc_sz; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun u32 len; 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun struct submit_ctx *sctx; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun /* u32 sz[8]; */ 584*4882a593Smuzhiyun u32 ff_hwaddr; 585*4882a593Smuzhiyun #ifdef RTW_HALMAC 586*4882a593Smuzhiyun u8 bulkout_id; /* for halmac */ 587*4882a593Smuzhiyun #endif /* RTW_HALMAC */ 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun PURB pxmit_urb[8]; 590*4882a593Smuzhiyun dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun u8 bpending[8]; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun sint last[8]; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #endif 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 599*4882a593Smuzhiyun u8 *phead; 600*4882a593Smuzhiyun u8 *pdata; 601*4882a593Smuzhiyun u8 *ptail; 602*4882a593Smuzhiyun u8 *pend; 603*4882a593Smuzhiyun u32 ff_hwaddr; 604*4882a593Smuzhiyun u8 pg_num; 605*4882a593Smuzhiyun u8 agg_num; 606*4882a593Smuzhiyun #endif 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 609*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH 610*4882a593Smuzhiyun /*struct tx_buf_desc *buf_desc;*/ 611*4882a593Smuzhiyun #else 612*4882a593Smuzhiyun struct tx_desc *desc; 613*4882a593Smuzhiyun #endif 614*4882a593Smuzhiyun #endif 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun #if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT) 617*4882a593Smuzhiyun u8 no; 618*4882a593Smuzhiyun #endif 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun struct xmit_frame { 624*4882a593Smuzhiyun _list list; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun struct pkt_attrib attrib; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun u16 os_qid; 629*4882a593Smuzhiyun _pkt *pkt; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun int frame_tag; 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun _adapter *padapter; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun u8 *buf_addr; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun struct xmit_buf *pxmitbuf; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 640*4882a593Smuzhiyun u8 pg_num; 641*4882a593Smuzhiyun u8 agg_num; 642*4882a593Smuzhiyun #endif 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 645*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_AGGREGATION 646*4882a593Smuzhiyun u8 agg_num; 647*4882a593Smuzhiyun #endif 648*4882a593Smuzhiyun s8 pkt_offset; 649*4882a593Smuzhiyun #endif 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK 652*4882a593Smuzhiyun u8 ack_report; 653*4882a593Smuzhiyun #endif 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun u8 *alloc_addr; /* the actual address this xmitframe allocated */ 656*4882a593Smuzhiyun u8 ext_tag; /* 0:data, 1:mgmt */ 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun struct tx_servq { 661*4882a593Smuzhiyun _list tx_pending; 662*4882a593Smuzhiyun _queue sta_pending; 663*4882a593Smuzhiyun int qcnt; 664*4882a593Smuzhiyun }; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun struct sta_xmit_priv { 668*4882a593Smuzhiyun _lock lock; 669*4882a593Smuzhiyun sint option; 670*4882a593Smuzhiyun sint apsd_setting; /* When bit mask is on, the associated edca queue supports APSD. */ 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun /* struct tx_servq blk_q[MAX_NUMBLKS]; */ 674*4882a593Smuzhiyun struct tx_servq be_q; /* priority == 0,3 */ 675*4882a593Smuzhiyun struct tx_servq bk_q; /* priority == 1,2 */ 676*4882a593Smuzhiyun struct tx_servq vi_q; /* priority == 4,5 */ 677*4882a593Smuzhiyun struct tx_servq vo_q; /* priority == 6,7 */ 678*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 679*4882a593Smuzhiyun struct tx_servq mgmt_q; 680*4882a593Smuzhiyun #endif 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun _list legacy_dz; 683*4882a593Smuzhiyun _list apsd; 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun u16 txseq_tid[16]; 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun /* uint sta_tx_bytes; */ 688*4882a593Smuzhiyun /* u64 sta_tx_pkts; */ 689*4882a593Smuzhiyun /* uint sta_tx_fail; */ 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun }; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun struct hw_txqueue { 696*4882a593Smuzhiyun volatile sint head; 697*4882a593Smuzhiyun volatile sint tail; 698*4882a593Smuzhiyun volatile sint free_sz; /* in units of 64 bytes */ 699*4882a593Smuzhiyun volatile sint free_cmdsz; 700*4882a593Smuzhiyun volatile sint txsz[8]; 701*4882a593Smuzhiyun uint ff_hwaddr; 702*4882a593Smuzhiyun uint cmd_hwaddr; 703*4882a593Smuzhiyun sint ac_tag; 704*4882a593Smuzhiyun }; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun struct agg_pkt_info { 707*4882a593Smuzhiyun u16 offset; 708*4882a593Smuzhiyun u16 pkt_len; 709*4882a593Smuzhiyun }; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun enum cmdbuf_type { 712*4882a593Smuzhiyun CMDBUF_BEACON = 0x00, 713*4882a593Smuzhiyun CMDBUF_RSVD, 714*4882a593Smuzhiyun CMDBUF_MAX 715*4882a593Smuzhiyun }; 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun u8 rtw_get_hwseq_no(_adapter *padapter); 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun struct xmit_priv { 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun _lock lock; 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun _sema xmit_sema; 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun /* _queue blk_strms[MAX_NUMBLKS]; */ 726*4882a593Smuzhiyun _queue be_pending; 727*4882a593Smuzhiyun _queue bk_pending; 728*4882a593Smuzhiyun _queue vi_pending; 729*4882a593Smuzhiyun _queue vo_pending; 730*4882a593Smuzhiyun _queue mgmt_pending; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun /* _queue legacy_dz_queue; */ 733*4882a593Smuzhiyun /* _queue apsd_queue; */ 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun u8 *pallocated_frame_buf; 736*4882a593Smuzhiyun u8 *pxmit_frame_buf; 737*4882a593Smuzhiyun uint free_xmitframe_cnt; 738*4882a593Smuzhiyun _queue free_xmit_queue; 739*4882a593Smuzhiyun 740*4882a593Smuzhiyun /* uint mapping_addr; */ 741*4882a593Smuzhiyun /* uint pkt_sz; */ 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun u8 *xframe_ext_alloc_addr; 744*4882a593Smuzhiyun u8 *xframe_ext; 745*4882a593Smuzhiyun uint free_xframe_ext_cnt; 746*4882a593Smuzhiyun _queue free_xframe_ext_queue; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun /* struct hw_txqueue be_txqueue; */ 749*4882a593Smuzhiyun /* struct hw_txqueue bk_txqueue; */ 750*4882a593Smuzhiyun /* struct hw_txqueue vi_txqueue; */ 751*4882a593Smuzhiyun /* struct hw_txqueue vo_txqueue; */ 752*4882a593Smuzhiyun /* struct hw_txqueue bmc_txqueue; */ 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun uint frag_len; 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun _adapter *adapter; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun u8 vcs_setting; 759*4882a593Smuzhiyun u8 vcs; 760*4882a593Smuzhiyun u8 vcs_type; 761*4882a593Smuzhiyun /* u16 rts_thresh; */ 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun u64 tx_bytes; 764*4882a593Smuzhiyun u64 tx_pkts; 765*4882a593Smuzhiyun u64 tx_drop; 766*4882a593Smuzhiyun u64 last_tx_pkts; 767*4882a593Smuzhiyun 768*4882a593Smuzhiyun struct hw_xmit *hwxmits; 769*4882a593Smuzhiyun u8 hwxmit_entry; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */ 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 774*4882a593Smuzhiyun _sema tx_retevt;/* all tx return event; */ 775*4882a593Smuzhiyun u8 txirp_cnt; 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun _tasklet xmit_tasklet; 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun /* per AC pending irp */ 780*4882a593Smuzhiyun int beq_cnt; 781*4882a593Smuzhiyun int bkq_cnt; 782*4882a593Smuzhiyun int viq_cnt; 783*4882a593Smuzhiyun int voq_cnt; 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun #endif 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 788*4882a593Smuzhiyun /* Tx */ 789*4882a593Smuzhiyun struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; 790*4882a593Smuzhiyun int txringcount[PCI_MAX_TX_QUEUE_COUNT]; 791*4882a593Smuzhiyun u8 beaconDMAing; /* flag of indicating beacon is transmiting to HW by DMA */ 792*4882a593Smuzhiyun _tasklet xmit_tasklet; 793*4882a593Smuzhiyun #endif 794*4882a593Smuzhiyun 795*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 796*4882a593Smuzhiyun #ifdef CONFIG_SDIO_TX_TASKLET 797*4882a593Smuzhiyun _tasklet xmit_tasklet; 798*4882a593Smuzhiyun #else 799*4882a593Smuzhiyun _thread_hdl_ SdioXmitThread; 800*4882a593Smuzhiyun _sema SdioXmitSema; 801*4882a593Smuzhiyun #ifdef SDIO_FREE_XMIT_BUF_SEMA 802*4882a593Smuzhiyun _sema sdio_free_xmitbuf_sema; 803*4882a593Smuzhiyun #endif 804*4882a593Smuzhiyun #endif /* CONFIG_SDIO_TX_TASKLET */ 805*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */ 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun _queue free_xmitbuf_queue; 808*4882a593Smuzhiyun _queue pending_xmitbuf_queue; 809*4882a593Smuzhiyun u8 *pallocated_xmitbuf; 810*4882a593Smuzhiyun u8 *pxmitbuf; 811*4882a593Smuzhiyun uint free_xmitbuf_cnt; 812*4882a593Smuzhiyun 813*4882a593Smuzhiyun _queue free_xmit_extbuf_queue; 814*4882a593Smuzhiyun u8 *pallocated_xmit_extbuf; 815*4882a593Smuzhiyun u8 *pxmit_extbuf; 816*4882a593Smuzhiyun uint free_xmit_extbuf_cnt; 817*4882a593Smuzhiyun 818*4882a593Smuzhiyun struct xmit_buf pcmd_xmitbuf[CMDBUF_MAX]; 819*4882a593Smuzhiyun u8 hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */ 820*4882a593Smuzhiyun u16 nqos_ssn; 821*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI 824*4882a593Smuzhiyun #define MAX_AGG_PKT_NUM 20 825*4882a593Smuzhiyun #else 826*4882a593Smuzhiyun #define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts */ 827*4882a593Smuzhiyun #endif 828*4882a593Smuzhiyun 829*4882a593Smuzhiyun struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM]; 830*4882a593Smuzhiyun #endif 831*4882a593Smuzhiyun 832*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK 833*4882a593Smuzhiyun int ack_tx; 834*4882a593Smuzhiyun _mutex ack_tx_mutex; 835*4882a593Smuzhiyun struct submit_ctx ack_tx_ops; 836*4882a593Smuzhiyun u8 seq_no; 837*4882a593Smuzhiyun #ifdef CONFIG_REMOVE_DUP_TX_STATE 838*4882a593Smuzhiyun u8 retry_count; 839*4882a593Smuzhiyun #endif 840*4882a593Smuzhiyun #endif 841*4882a593Smuzhiyun 842*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU 843*4882a593Smuzhiyun _timer amsdu_vo_timer; 844*4882a593Smuzhiyun u8 amsdu_vo_timeout; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun _timer amsdu_vi_timer; 847*4882a593Smuzhiyun u8 amsdu_vi_timeout; 848*4882a593Smuzhiyun 849*4882a593Smuzhiyun _timer amsdu_be_timer; 850*4882a593Smuzhiyun u8 amsdu_be_timeout; 851*4882a593Smuzhiyun 852*4882a593Smuzhiyun _timer amsdu_bk_timer; 853*4882a593Smuzhiyun u8 amsdu_bk_timeout; 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun u32 amsdu_debug_set_timer; 856*4882a593Smuzhiyun u32 amsdu_debug_timeout; 857*4882a593Smuzhiyun u32 amsdu_debug_coalesce_one; 858*4882a593Smuzhiyun u32 amsdu_debug_coalesce_two; 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun #endif 861*4882a593Smuzhiyun #ifdef DBG_TXBD_DESC_DUMP 862*4882a593Smuzhiyun BOOLEAN dump_txbd_desc; 863*4882a593Smuzhiyun #endif 864*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING 865*4882a593Smuzhiyun _timer tx_poll_timer; 866*4882a593Smuzhiyun #endif 867*4882a593Smuzhiyun #ifdef CONFIG_LAYER2_ROAMING 868*4882a593Smuzhiyun _queue rpkt_queue; 869*4882a593Smuzhiyun #endif 870*4882a593Smuzhiyun _lock lock_sctx; 871*4882a593Smuzhiyun 872*4882a593Smuzhiyun }; 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, 875*4882a593Smuzhiyun enum cmdbuf_type buf_type); 876*4882a593Smuzhiyun #define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD) 877*4882a593Smuzhiyun #if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI) 878*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv, 879*4882a593Smuzhiyun enum cmdbuf_type buf_type); 880*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON) 881*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI) 882*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv, 883*4882a593Smuzhiyun enum cmdbuf_type buf_type); 884*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON) 885*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822C) && defined(CONFIG_PCI_HCI) 886*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv, 887*4882a593Smuzhiyun enum cmdbuf_type buf_type); 888*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822ce(p, CMDBUF_BEACON) 889*4882a593Smuzhiyun #elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI) 890*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv, 891*4882a593Smuzhiyun enum cmdbuf_type buf_type); 892*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON) 893*4882a593Smuzhiyun #elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI) 894*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv, 895*4882a593Smuzhiyun enum cmdbuf_type buf_type); 896*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON) 897*4882a593Smuzhiyun #elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI) 898*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv, 899*4882a593Smuzhiyun enum cmdbuf_type buf_type); 900*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON) 901*4882a593Smuzhiyun #elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI) 902*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv, 903*4882a593Smuzhiyun enum cmdbuf_type buf_type); 904*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON) 905*4882a593Smuzhiyun #elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI) 906*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv, 907*4882a593Smuzhiyun enum cmdbuf_type buf_type); 908*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON) 909*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI) 910*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv, 911*4882a593Smuzhiyun enum cmdbuf_type buf_type); 912*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON) 913*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814B) && defined(CONFIG_PCI_HCI) 914*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814be(struct xmit_priv *pxmitpriv, 915*4882a593Smuzhiyun enum cmdbuf_type buf_type); 916*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814be(p, CMDBUF_BEACON) 917*4882a593Smuzhiyun #else 918*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON) 919*4882a593Smuzhiyun #endif 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); 922*4882a593Smuzhiyun extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 923*4882a593Smuzhiyun 924*4882a593Smuzhiyun extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); 925*4882a593Smuzhiyun extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); 928*4882a593Smuzhiyun extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); 929*4882a593Smuzhiyun 930*4882a593Smuzhiyun extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); 931*4882a593Smuzhiyun extern s32 rtw_put_snap(u8 *data, u16 h_proto); 932*4882a593Smuzhiyun 933*4882a593Smuzhiyun extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid); 934*4882a593Smuzhiyun struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv); 935*4882a593Smuzhiyun struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv); 936*4882a593Smuzhiyun extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); 937*4882a593Smuzhiyun extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); 938*4882a593Smuzhiyun struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); 939*4882a593Smuzhiyun extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 942*4882a593Smuzhiyun void rtw_free_mgmt_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *mgmt_queue); 943*4882a593Smuzhiyun u8 rtw_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 944*4882a593Smuzhiyun struct xmit_frame *rtw_dequeue_mgmt_xframe(struct xmit_priv *pxmitpriv); 945*4882a593Smuzhiyun #endif /* CONFIG_RTW_MGMT_QUEUE */ 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); 948*4882a593Smuzhiyun 949*4882a593Smuzhiyun extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); 950*4882a593Smuzhiyun extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); 951*4882a593Smuzhiyun #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) 952*4882a593Smuzhiyun extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); 953*4882a593Smuzhiyun #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) 954*4882a593Smuzhiyun extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); 955*4882a593Smuzhiyun #endif 956*4882a593Smuzhiyun #ifdef CONFIG_TDLS 957*4882a593Smuzhiyun extern struct tdls_txmgmt *ptxmgmt; 958*4882a593Smuzhiyun s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); 959*4882a593Smuzhiyun s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib); 960*4882a593Smuzhiyun #endif 961*4882a593Smuzhiyun s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag); 962*4882a593Smuzhiyun void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun s32 rtw_txframes_pending(_adapter *padapter); 966*4882a593Smuzhiyun s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); 967*4882a593Smuzhiyun void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); 971*4882a593Smuzhiyun void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun 974*4882a593Smuzhiyun void rtw_alloc_hwxmits(_adapter *padapter); 975*4882a593Smuzhiyun void rtw_free_hwxmits(_adapter *padapter); 976*4882a593Smuzhiyun #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) 977*4882a593Smuzhiyun s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); 978*4882a593Smuzhiyun #endif 979*4882a593Smuzhiyun void rtw_xmit_dequeue_callback(_workitem *work); 980*4882a593Smuzhiyun void rtw_xmit_queue_set(struct sta_info *sta); 981*4882a593Smuzhiyun void rtw_xmit_queue_clear(struct sta_info *sta); 982*4882a593Smuzhiyun s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt); 983*4882a593Smuzhiyun s32 rtw_xmit(_adapter *padapter, _pkt **pkt, u16 os_qid); 984*4882a593Smuzhiyun bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); 985*4882a593Smuzhiyun #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) 986*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 987*4882a593Smuzhiyun u8 mgmt_xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); 988*4882a593Smuzhiyun #endif 989*4882a593Smuzhiyun sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); 990*4882a593Smuzhiyun void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); 991*4882a593Smuzhiyun void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); 992*4882a593Smuzhiyun void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); 993*4882a593Smuzhiyun #endif 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta); 996*4882a593Smuzhiyun 997*4882a593Smuzhiyun void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj); 998*4882a593Smuzhiyun u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); 999*4882a593Smuzhiyun u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); 1000*4882a593Smuzhiyun s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter, bool eirp); 1001*4882a593Smuzhiyun s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp); 1002*4882a593Smuzhiyun s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj, bool erip); 1003*4882a593Smuzhiyun s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp); 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun u8 query_ra_short_GI(struct sta_info *psta, u8 bw); 1006*4882a593Smuzhiyun 1007*4882a593Smuzhiyun u8 qos_acm(u8 acm_mask, u8 priority); 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE 1010*4882a593Smuzhiyun void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 1011*4882a593Smuzhiyun void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 1012*4882a593Smuzhiyun struct xmit_buf *dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); 1013*4882a593Smuzhiyun struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter); 1014*4882a593Smuzhiyun sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); 1015*4882a593Smuzhiyun thread_return rtw_xmit_thread(thread_context context); 1016*4882a593Smuzhiyun #endif 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU 1019*4882a593Smuzhiyun extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext); 1020*4882a593Smuzhiyun extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext); 1021*4882a593Smuzhiyun extern void rtw_amsdu_be_timeout_handler(void *FunctionContext); 1022*4882a593Smuzhiyun extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext); 1023*4882a593Smuzhiyun 1024*4882a593Smuzhiyun extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority); 1025*4882a593Smuzhiyun extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status); 1026*4882a593Smuzhiyun extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority); 1027*4882a593Smuzhiyun extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority); 1028*4882a593Smuzhiyun 1029*4882a593Smuzhiyun extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue); 1030*4882a593Smuzhiyun extern s32 check_amsdu(struct xmit_frame *pxmitframe); 1031*4882a593Smuzhiyun extern s32 check_amsdu_tx_support(_adapter *padapter); 1032*4882a593Smuzhiyun extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); 1033*4882a593Smuzhiyun #endif 1034*4882a593Smuzhiyun 1035*4882a593Smuzhiyun #ifdef DBG_TXBD_DESC_DUMP 1036*4882a593Smuzhiyun void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq); 1037*4882a593Smuzhiyun void rtw_tx_desc_backup_reset(void); 1038*4882a593Smuzhiyun u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak); 1039*4882a593Smuzhiyun #endif 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING 1042*4882a593Smuzhiyun void rtw_tx_poll_init(_adapter *padapter); 1043*4882a593Smuzhiyun void rtw_tx_poll_timeout_handler(void *FunctionContext); 1044*4882a593Smuzhiyun void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay); 1045*4882a593Smuzhiyun void rtw_tx_poll_timer_cancel(_adapter *padapter); 1046*4882a593Smuzhiyun #endif 1047*4882a593Smuzhiyun 1048*4882a593Smuzhiyun u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); 1049*4882a593Smuzhiyun 1050*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK 1051*4882a593Smuzhiyun int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); 1052*4882a593Smuzhiyun void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); 1053*4882a593Smuzhiyun #endif /* CONFIG_XMIT_ACK */ 1054*4882a593Smuzhiyun 1055*4882a593Smuzhiyun enum XMIT_BLOCK_REASON { 1056*4882a593Smuzhiyun XMIT_BLOCK_NONE = 0, 1057*4882a593Smuzhiyun XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/ 1058*4882a593Smuzhiyun XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/ 1059*4882a593Smuzhiyun XMIT_BLOCK_MAX = 0xFF, 1060*4882a593Smuzhiyun }; 1061*4882a593Smuzhiyun void rtw_init_xmit_block(_adapter *padapter); 1062*4882a593Smuzhiyun void rtw_deinit_xmit_block(_adapter *padapter); 1063*4882a593Smuzhiyun 1064*4882a593Smuzhiyun #ifdef DBG_XMIT_BLOCK 1065*4882a593Smuzhiyun void dump_xmit_block(void *sel, _adapter *padapter); 1066*4882a593Smuzhiyun #endif 1067*4882a593Smuzhiyun void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); 1068*4882a593Smuzhiyun void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); 1069*4882a593Smuzhiyun bool rtw_is_xmit_blocked(_adapter *padapter); 1070*4882a593Smuzhiyun 1071*4882a593Smuzhiyun /* include after declaring struct xmit_buf, in order to avoid warning */ 1072*4882a593Smuzhiyun #include <xmit_osdep.h> 1073*4882a593Smuzhiyun 1074*4882a593Smuzhiyun #endif /* _RTL871X_XMIT_H_ */ 1075