1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8192F_CMD_H__ 16 #define __RTL8192F_CMD_H__ 17 18 /* --------------------------------------------------------------------------------------------------------- 19 * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ 20 * --------------------------------------------------------------------------------------------------------- */ 21 22 enum h2c_cmd_8192F { 23 /* Common Class: 000 */ 24 H2C_8192F_RSVD_PAGE = 0x00, 25 H2C_8192F_MEDIA_STATUS_RPT = 0x01, 26 H2C_8192F_SCAN_ENABLE = 0x02, 27 H2C_8192F_KEEP_ALIVE = 0x03, 28 H2C_8192F_DISCON_DECISION = 0x04, 29 H2C_8192F_PSD_OFFLOAD = 0x05, 30 H2C_8192F_AP_OFFLOAD = 0x08, 31 H2C_8192F_BCN_RSVDPAGE = 0x09, 32 H2C_8192F_PROBERSP_RSVDPAGE = 0x0A, 33 H2C_8192F_FCS_RSVDPAGE = 0x10, 34 H2C_8192F_FCS_INFO = 0x11, 35 H2C_8192F_AP_WOW_GPIO_CTRL = 0x13, 36 37 /* PoweSave Class: 001 */ 38 H2C_8192F_SET_PWR_MODE = 0x20, 39 H2C_8192F_PS_TUNING_PARA = 0x21, 40 H2C_8192F_PS_TUNING_PARA2 = 0x22, 41 H2C_8192F_P2P_LPS_PARAM = 0x23, 42 H2C_8192F_P2P_PS_OFFLOAD = 0x24, 43 H2C_8192F_PS_SCAN_ENABLE = 0x25, 44 H2C_8192F_SAP_PS_ = 0x26, 45 H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */ 46 H2C_8192F_FWLPS_IN_IPS_ = 0x28, 47 48 /* Dynamic Mechanism Class: 010 */ 49 H2C_8192F_MACID_CFG = 0x40, 50 H2C_8192F_TXBF = 0x41, 51 H2C_8192F_RSSI_SETTING = 0x42, 52 H2C_8192F_AP_REQ_TXRPT = 0x43, 53 H2C_8192F_INIT_RATE_COLLECT = 0x44, 54 H2C_8192F_RA_PARA_ADJUST = 0x46, 55 56 /* BT Class: 011 */ 57 H2C_8192F_B_TYPE_TDMA = 0x60, 58 H2C_8192F_BT_INFO = 0x61, 59 H2C_8192F_FORCE_BT_TXPWR = 0x62, 60 H2C_8192F_BT_IGNORE_WLANACT = 0x63, 61 H2C_8192F_DAC_SWING_VALUE = 0x64, 62 H2C_8192F_ANT_SEL_RSV = 0x65, 63 H2C_8192F_WL_OPMODE = 0x66, 64 H2C_8192F_BT_MP_OPER = 0x67, 65 H2C_8192F_BT_CONTROL = 0x68, 66 H2C_8192F_BT_WIFI_CTRL = 0x69, 67 H2C_8192F_BT_FW_PATCH = 0x6A, 68 H2C_8192F_BT_WLAN_CALIBRATION = 0x6D, 69 70 /* WOWLAN Class: 100 */ 71 H2C_8192F_WOWLAN = 0x80, 72 H2C_8192F_REMOTE_WAKE_CTRL = 0x81, 73 H2C_8192F_AOAC_GLOBAL_INFO = 0x82, 74 H2C_8192F_AOAC_RSVD_PAGE = 0x83, 75 H2C_8192F_AOAC_RSVD_PAGE2 = 0x84, 76 H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85, 77 H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86, 78 H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87, 79 H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A, 80 H2C_8192F_P2P_OFFLOAD = 0x8B, 81 82 H2C_8192F_RESET_TSF = 0xC0, 83 H2C_8192F_MAXID, 84 }; 85 86 /* --------------------------------------------------------------------------------------------------------- 87 * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- 88 * --------------------------------------------------------------------------------------------------------- 89 * _RSVDPAGE_LOC_CMD_0x00 */ 90 #define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 91 #define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) 92 #define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) 93 #define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) 94 #define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) 95 96 /*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/ 97 #define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) 98 #define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) 99 #define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) 100 #define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) 101 /* _PWR_MOD_CMD_0x20 */ 102 #define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 103 #define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) 104 #define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) 105 #define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) 106 #define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) 107 #define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) 108 #define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) 109 110 #define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) 111 112 /* _PS_TUNE_PARAM_CMD_0x21 */ 113 #define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 114 #define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) 115 #define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) 116 #define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) 117 #define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) 118 119 /* _MACID_CFG_CMD_0x40 */ 120 #define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 121 #define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) 122 #define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) 123 #define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) 124 #define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) 125 #define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) 126 #define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) 127 #define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) 128 #define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) 129 #define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) 130 #define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) 131 #define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) 132 133 /* _RSSI_SETTING_CMD_0x42 */ 134 #define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 135 #define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) 136 #define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) 137 138 /* _AP_REQ_TXRPT_CMD_0x43 */ 139 #define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 140 #define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) 141 142 /* _FORCE_BT_TXPWR_CMD_0x62 */ 143 #define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 144 145 /* _FORCE_BT_MP_OPER_CMD_0x67 */ 146 #define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) 147 #define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) 148 #define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) 149 #define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) 150 #define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) 151 #define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) 152 153 /* _BT_FW_PATCH_0x6A */ 154 #define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value) 155 #define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) 156 #define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) 157 #define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) 158 #define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) 159 160 /* --------------------------------------------------------------------------------------------------------- 161 * ------------------------------------------- Structure -------------------------------------------------- 162 * --------------------------------------------------------------------------------------------------------- */ 163 164 165 /* --------------------------------------------------------------------------------------------------------- 166 * ---------------------------------- Function Statement -------------------------------------------------- 167 * --------------------------------------------------------------------------------------------------------- */ 168 169 /* host message to firmware cmd */ 170 void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); 171 void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); 172 /* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ 173 void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter); 174 void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus); 175 #ifdef CONFIG_BT_COEXIST 176 void rtl8192f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); 177 #endif /* CONFIG_BT_COEXIST */ 178 #ifdef CONFIG_P2P 179 void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); 180 #endif /* CONFIG_P2P */ 181 182 #ifdef CONFIG_P2P_WOWLAN 183 void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); 184 #endif 185 186 /* AP_REQ_TXREP_CMD 0x43 */ 187 #define SET_8192F_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) 188 #define SET_8192F_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) 189 #define SET_8192F_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) 190 191 /* C2H_AP_REQ_TXRPT */ 192 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_MACID1(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) 193 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16) 194 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) 195 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) 196 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_MACID2(_Header) LE_BITS_TO_1BYTE((_Header + 6), 0, 8) 197 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16) 198 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header) LE_BITS_TO_2BYTE((_Header + 9), 0, 16) 199 #define GET_8192F_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header) LE_BITS_TO_1BYTE((_Header + 11), 0, 8) 200 201 /* C2H_SPC_STAT */ 202 #define GET_8192F_C2H_SPC_STAT_IDX(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) 203 /* Tip :TYPE_A data3 is msb and data0 is lsb */ 204 #define GET_8192F_C2H_SPC_STAT_TYPEA_RETRY(_Header) LE_BITS_TO_4BYTE((_Header + 1), 0, 32) 205 #define GET_8192F_C2H_SPC_STAT_TYPEB_PKT1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16) 206 #define GET_8192F_C2H_SPC_STAT_TYPEB_RETRY1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) 207 #define GET_8192F_C2H_SPC_STAT_TYPEB_PKT2(_Header) LE_BITS_TO_2BYTE((_Header + 5), 0, 16) 208 #define GET_8192F_C2H_SPC_STAT_TYPEB_RETRY2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16) 209 210 void rtl8192f_req_txrpt_cmd(PADAPTER, u8 macid); 211 s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); 212 u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan); 213 #endif 214