1 /****************************************************************************** 2 * 3 * Copyright(c) 2012 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8192E_SPEC_H__ 16 #define __RTL8192E_SPEC_H__ 17 18 #include <drv_conf.h> 19 20 #define HAL_NAV_UPPER_UNIT_8192E 128 /* micro-second */ 21 22 /* ************************************************************ 23 * 8192E Regsiter offset definition 24 * ************************************************************ */ 25 26 /* ************************************************************ 27 * 28 * ************************************************************ */ 29 30 /* ----------------------------------------------------- 31 * 32 * 0x0000h ~ 0x00FFh System Configuration 33 * 34 * ----------------------------------------------------- */ 35 #define REG_SYS_SWR_CTRL1_8192E 0x0010 /* 1 Byte */ 36 #define REG_SYS_SWR_CTRL2_8192E 0x0014 /* 1 Byte */ 37 #define REG_AFE_CTRL1_8192E 0x0024 38 #define REG_AFE_CTRL2_8192E 0x0028 39 #define REG_AFE_CTRL3_8192E 0x002c 40 41 #define REG_PAD_CTRL1_8192E 0x0064 42 #define REG_SDIO_CTRL_8192E 0x0070 43 #define REG_OPT_CTRL_8192E 0x0074 44 #define REG_RF_B_CTRL_8192E 0x0076 45 #define REG_AFE_CTRL4_8192E 0x0078 46 #define REG_LDO_SWR_CTRL 0x007C 47 #define REG_FW_DRV_MSG_8192E 0x0088 48 #define REG_HMEBOX_E2_E3_8192E 0x008C 49 #define REG_HIMR0_8192E 0x00B0 50 #define REG_HISR0_8192E 0x00B4 51 #define REG_HIMR1_8192E 0x00B8 52 #define REG_HISR1_8192E 0x00BC 53 54 #define REG_SYS_CFG1_8192E 0x00F0 55 #define REG_SYS_CFG2_8192E 0x00FC 56 /* ----------------------------------------------------- 57 * 58 * 0x0100h ~ 0x01FFh MACTOP General Configuration 59 * 60 * ----------------------------------------------------- */ 61 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 62 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 63 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 64 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 65 66 #define REG_RSVD3_8192E 0x0168 67 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 68 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 69 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 70 71 #define REG_HMEBOX_EXT0_8192E 0x01F0 72 #define REG_HMEBOX_EXT1_8192E 0x01F4 73 #define REG_HMEBOX_EXT2_8192E 0x01F8 74 #define REG_HMEBOX_EXT3_8192E 0x01FC 75 76 /* ----------------------------------------------------- 77 * 78 * 0x0200h ~ 0x027Fh TXDMA Configuration 79 * 80 * ----------------------------------------------------- */ 81 #define REG_DWBCN0_CTRL 0x0208 82 #define REG_DWBCN1_CTRL 0x0228 83 84 /* ----------------------------------------------------- 85 * 86 * 0x0280h ~ 0x02FFh RXDMA Configuration 87 * 88 * ----------------------------------------------------- */ 89 #define REG_RXDMA_8192E 0x0290 90 #define REG_EARLY_MODE_CONTROL_8192E 0x02BC 91 92 #define REG_RSVD5_8192E 0x02F0 93 #define REG_RSVD6_8192E 0x02F4 94 #define REG_RSVD7_8192E 0x02F8 95 #define REG_RSVD8_8192E 0x02FC 96 97 /* ----------------------------------------------------- 98 * 99 * 0x0300h ~ 0x03FFh PCIe 100 * 101 * ----------------------------------------------------- */ 102 #define REG_PCIE_CTRL_REG_8192E 0x0300 103 #define REG_INT_MIG_8192E 0x0304 /* Interrupt Migration */ 104 #define REG_BCNQ_TXBD_DESA_8192E 0x0308 /* TX Beacon Descriptor Address */ 105 #define REG_MGQ_TXBD_DESA_8192E 0x0310 /* TX Manage Queue Descriptor Address */ 106 #define REG_VOQ_TXBD_DESA_8192E 0x0318 /* TX VO Queue Descriptor Address */ 107 #define REG_VIQ_TXBD_DESA_8192E 0x0320 /* TX VI Queue Descriptor Address */ 108 #define REG_BEQ_TXBD_DESA_8192E 0x0328 /* TX BE Queue Descriptor Address */ 109 #define REG_BKQ_TXBD_DESA_8192E 0x0330 /* TX BK Queue Descriptor Address */ 110 #define REG_RXQ_RXBD_DESA_8192E 0x0338 /* RX Queue Descriptor Address */ 111 #define REG_HI0Q_TXBD_DESA_8192E 0x0340 112 #define REG_HI1Q_TXBD_DESA_8192E 0x0348 113 #define REG_HI2Q_TXBD_DESA_8192E 0x0350 114 #define REG_HI3Q_TXBD_DESA_8192E 0x0358 115 #define REG_HI4Q_TXBD_DESA_8192E 0x0360 116 #define REG_HI5Q_TXBD_DESA_8192E 0x0368 117 #define REG_HI6Q_TXBD_DESA_8192E 0x0370 118 #define REG_HI7Q_TXBD_DESA_8192E 0x0378 119 #define REG_MGQ_TXBD_NUM_8192E 0x0380 120 #define REG_RX_RXBD_NUM_8192E 0x0382 121 #define REG_VOQ_TXBD_NUM_8192E 0x0384 122 #define REG_VIQ_TXBD_NUM_8192E 0x0386 123 #define REG_BEQ_TXBD_NUM_8192E 0x0388 124 #define REG_BKQ_TXBD_NUM_8192E 0x038A 125 #define REG_HI0Q_TXBD_NUM_8192E 0x038C 126 #define REG_HI1Q_TXBD_NUM_8192E 0x038E 127 #define REG_HI2Q_TXBD_NUM_8192E 0x0390 128 #define REG_HI3Q_TXBD_NUM_8192E 0x0392 129 #define REG_HI4Q_TXBD_NUM_8192E 0x0394 130 #define REG_HI5Q_TXBD_NUM_8192E 0x0396 131 #define REG_HI6Q_TXBD_NUM_8192E 0x0398 132 #define REG_HI7Q_TXBD_NUM_8192E 0x039A 133 #define REG_TSFTIMER_HCI_8192E 0x039C 134 135 /* Read Write Point */ 136 #define REG_VOQ_TXBD_IDX_8192E 0x03A0 137 #define REG_VIQ_TXBD_IDX_8192E 0x03A4 138 #define REG_BEQ_TXBD_IDX_8192E 0x03A8 139 #define REG_BKQ_TXBD_IDX_8192E 0x03AC 140 #define REG_MGQ_TXBD_IDX_8192E 0x03B0 141 #define REG_RXQ_TXBD_IDX_8192E 0x03B4 142 #define REG_HI0Q_TXBD_IDX_8192E 0x03B8 143 #define REG_HI1Q_TXBD_IDX_8192E 0x03BC 144 #define REG_HI2Q_TXBD_IDX_8192E 0x03C0 145 #define REG_HI3Q_TXBD_IDX_8192E 0x03C4 146 #define REG_HI4Q_TXBD_IDX_8192E 0x03C8 147 #define REG_HI5Q_TXBD_IDX_8192E 0x03CC 148 #define REG_HI6Q_TXBD_IDX_8192E 0x03D0 149 #define REG_HI7Q_TXBD_IDX_8192E 0x03D4 150 151 #define REG_PCIE_HCPWM_8192EE 0x03D8 /* ?????? */ 152 #define REG_PCIE_HRPWM_8192EE 0x03DC /* PCIe RPWM */ /* ?????? */ 153 #define REG_DBI_WDATA_V1_8192E 0x03E8 154 #define REG_DBI_RDATA_V1_8192E 0x03EC 155 #define REG_DBI_FLAG_V1_8192E 0x03F0 156 #define REG_MDIO_V1_8192E 0x3F4 157 #define REG_PCIE_MIX_CFG_8192E 0x3F8 158 159 /* ----------------------------------------------------- 160 * 161 * 0x0400h ~ 0x047Fh Protocol Configuration 162 * 163 * ----------------------------------------------------- */ 164 #define REG_TXBF_CTRL_8192E 0x042C 165 #define REG_ARFR0_8192E 0x0444 166 #define REG_ARFR1_8192E 0x044C 167 #define REG_CCK_CHECK_8192E 0x0454 168 #define REG_AMPDU_MAX_TIME_8192E 0x0456 169 #define REG_BCNQ1_BDNY_8192E 0x0457 170 171 #define REG_AMPDU_MAX_LENGTH_8192E 0x0458 172 #define REG_WMAC_LBK_BUF_HD_8192E 0x045D 173 #define REG_NDPA_OPT_CTRL_8192E 0x045F 174 #define REG_DATA_SC_8192E 0x0483 175 #ifdef CONFIG_WOWLAN 176 #define REG_TXPKTBUF_IV_LOW 0x0484 177 #define REG_TXPKTBUF_IV_HIGH 0x0488 178 #endif 179 #define REG_ARFR2_8192E 0x048C 180 #define REG_ARFR3_8192E 0x0494 181 #define REG_TXRPT_START_OFFSET 0x04AC 182 #define REG_AMPDU_BURST_MODE_8192E 0x04BC 183 #define REG_HT_SINGLE_AMPDU_8192E 0x04C7 184 #define REG_MACID_PKT_DROP0_8192E 0x04D0 185 186 /* ----------------------------------------------------- 187 * 188 * 0x0500h ~ 0x05FFh EDCA Configuration 189 * 190 * ----------------------------------------------------- */ 191 #define REG_CTWND_8192E 0x0572 192 #define REG_SECONDARY_CCA_CTRL_8192E 0x0577 193 #define REG_SCH_TXCMD_8192E 0x05F8 194 195 /* ----------------------------------------------------- 196 * 197 * 0x0600h ~ 0x07FFh WMAC Configuration 198 * 199 * ----------------------------------------------------- */ 200 #define REG_MAC_CR_8192E 0x0600 201 202 #define REG_MAC_TX_SM_STATE_8192E 0x06B4 203 204 /* Power */ 205 #define REG_BFMER0_INFO_8192E 0x06E4 206 #define REG_BFMER1_INFO_8192E 0x06EC 207 #define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4 208 #define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8 209 #define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC 210 211 /* Hardware Port 2 */ 212 #define REG_BFMEE_SEL_8192E 0x0714 213 #define REG_SND_PTCL_CTRL_8192E 0x0718 214 215 216 /* ----------------------------------------------------- 217 * 218 * Redifine register definition for compatibility 219 * 220 * ----------------------------------------------------- */ 221 222 /* TODO: use these definition when using REG_xxx naming rule. 223 * NOTE: DO NOT Remove these definition. Use later. */ 224 #define ISR_8192E REG_HISR0_8192E 225 226 /* ---------------------------------------------------------------------------- 227 * 8192E IMR/ISR bits (offset 0xB0, 8bits) 228 * ---------------------------------------------------------------------------- */ 229 #define IMR_DISABLED_8192E 0 230 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 231 #define IMR_TIMER2_8192E BIT(31) /* Timeout interrupt 2 */ 232 #define IMR_TIMER1_8192E BIT(30) /* Timeout interrupt 1 */ 233 #define IMR_PSTIMEOUT_8192E BIT(29) /* Power Save Time Out Interrupt */ 234 #define IMR_GTINT4_8192E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 235 #define IMR_GTINT3_8192E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 236 #define IMR_TXBCN0ERR_8192E BIT(26) /* Transmit Beacon0 Error */ 237 #define IMR_TXBCN0OK_8192E BIT(25) /* Transmit Beacon0 OK */ 238 #define IMR_TSF_BIT32_TOGGLE_8192E BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ 239 #define IMR_BCNDMAINT0_8192E BIT(20) /* Beacon DMA Interrupt 0 */ 240 #define IMR_BCNDERR0_8192E BIT(16) /* Beacon Queue DMA OK0 */ 241 #define IMR_HSISR_IND_ON_INT_8192E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 242 #define IMR_BCNDMAINT_E_8192E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 243 #define IMR_ATIMEND_8192E BIT(12) /* CTWidnow End or ATIM Window End */ 244 #define IMR_C2HCMD_8192E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ 245 #define IMR_CPWM2_8192E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ 246 #define IMR_CPWM_8192E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ 247 #define IMR_HIGHDOK_8192E BIT(7) /* High Queue DMA OK */ 248 #define IMR_MGNTDOK_8192E BIT(6) /* Management Queue DMA OK */ 249 #define IMR_BKDOK_8192E BIT(5) /* AC_BK DMA OK */ 250 #define IMR_BEDOK_8192E BIT(4) /* AC_BE DMA OK */ 251 #define IMR_VIDOK_8192E BIT(3) /* AC_VI DMA OK */ 252 #define IMR_VODOK_8192E BIT(2) /* AC_VO DMA OK */ 253 #define IMR_RDU_8192E BIT(1) /* Rx Descriptor Unavailable */ 254 #define IMR_ROK_8192E BIT(0) /* Receive DMA OK */ 255 256 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 257 #define IMR_BCNDMAINT7_8192E BIT(27) /* Beacon DMA Interrupt 7 */ 258 #define IMR_BCNDMAINT6_8192E BIT(26) /* Beacon DMA Interrupt 6 */ 259 #define IMR_BCNDMAINT5_8192E BIT(25) /* Beacon DMA Interrupt 5 */ 260 #define IMR_BCNDMAINT4_8192E BIT(24) /* Beacon DMA Interrupt 4 */ 261 #define IMR_BCNDMAINT3_8192E BIT(23) /* Beacon DMA Interrupt 3 */ 262 #define IMR_BCNDMAINT2_8192E BIT(22) /* Beacon DMA Interrupt 2 */ 263 #define IMR_BCNDMAINT1_8192E BIT(21) /* Beacon DMA Interrupt 1 */ 264 #define IMR_BCNDOK7_8192E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ 265 #define IMR_BCNDOK6_8192E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ 266 #define IMR_BCNDOK5_8192E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ 267 #define IMR_BCNDOK4_8192E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ 268 #define IMR_BCNDOK3_8192E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ 269 #define IMR_BCNDOK2_8192E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ 270 #define IMR_BCNDOK1_8192E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ 271 #define IMR_ATIMEND_E_8192E BIT(13) /* ATIM Window End Extension for Win7 */ 272 #define IMR_TXERR_8192E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ 273 #define IMR_RXERR_8192E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ 274 #define IMR_TXFOVW_8192E BIT(9) /* Transmit FIFO Overflow */ 275 #define IMR_RXFOVW_8192E BIT(8) /* Receive FIFO Overflow */ 276 277 /* ---------------------------------------------------------------------------- 278 * 8192E Auto LLT bits (offset 0x224, 8bits) 279 * ---------------------------------------------------------------------------- 280 * 224 REG_AUTO_LLT 281 * move to hal_com_reg.h */ 282 283 /* ---------------------------------------------------------------------------- 284 * 8192E Auto LLT bits (offset 0x290, 32bits) 285 * ---------------------------------------------------------------------------- */ 286 #define BIT_DMA_MODE BIT(1) 287 #define BIT_USB_RXDMA_AGG_EN BIT(31) 288 289 /* ---------------------------------------------------------------------------- 290 * 8192E REG_SYS_CFG1 (offset 0xF0, 32bits) 291 * ---------------------------------------------------------------------------- */ 292 #define BIT_SPSLDO_SEL BIT(24) 293 294 295 /* ---------------------------------------------------------------------------- 296 * 8192E REG_CCK_CHECK (offset 0x454, 8bits) 297 * ---------------------------------------------------------------------------- */ 298 #define BIT_BCN_PORT_SEL BIT(5) 299 300 /* **************************************************************************** 301 * Regsiter Bit and Content definition 302 * **************************************************************************** */ 303 304 /* 2 ACMHWCTRL 0x05C0 */ 305 #define AcmHw_HwEn_8192E BIT(0) 306 #define AcmHw_VoqEn_8192E BIT(1) 307 #define AcmHw_ViqEn_8192E BIT(2) 308 #define AcmHw_BeqEn_8192E BIT(3) 309 #define AcmHw_VoqStatus_8192E BIT(5) 310 #define AcmHw_ViqStatus_8192E BIT(6) 311 #define AcmHw_BeqStatus_8192E BIT(7) 312 313 #endif /* __RTL8192E_SPEC_H__ */ 314