1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8188E_XMIT_H__ 16 #define __RTL8188E_XMIT_H__ 17 18 19 20 21 /* For 88e early mode */ 22 #define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) 23 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) 24 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) 25 #define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) 26 #define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) 27 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) 28 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) 29 30 /* 31 * defined for TX DESC Operation 32 * */ 33 34 #define MAX_TID (15) 35 36 /* OFFSET 0 */ 37 #define OFFSET_SZ 0 38 #define OFFSET_SHT 16 39 #define BMC BIT(24) 40 #define LSG BIT(26) 41 #define FSG BIT(27) 42 #define OWN BIT(31) 43 44 45 /* OFFSET 4 */ 46 #define PKT_OFFSET_SZ 0 47 #define QSEL_SHT 8 48 #define RATE_ID_SHT 16 49 #define NAVUSEHDR BIT(20) 50 #define SEC_TYPE_SHT 22 51 #define PKT_OFFSET_SHT 26 52 53 /* OFFSET 8 */ 54 #define AGG_EN BIT(12) 55 #define AGG_BK BIT(16) 56 #define AMPDU_DENSITY_SHT 20 57 #define ANTSEL_A BIT(24) 58 #define ANTSEL_B BIT(25) 59 #define TX_ANT_CCK_SHT 26 60 #define TX_ANTL_SHT 28 61 #define TX_ANT_HT_SHT 30 62 63 /* OFFSET 12 */ 64 #define SEQ_SHT 16 65 #define EN_HWSEQ BIT(31) 66 67 /* OFFSET 16 */ 68 #define QOS BIT(6) 69 #define HW_SSN BIT(7) 70 #define USERATE BIT(8) 71 #define DISDATAFB BIT(10) 72 #define CTS_2_SELF BIT(11) 73 #define RTS_EN BIT(12) 74 #define HW_RTS_EN BIT(13) 75 #define DATA_SHORT BIT(24) 76 #define PWR_STATUS_SHT 15 77 #define DATA_SC_SHT 20 78 #define DATA_BW BIT(25) 79 80 /* OFFSET 20 */ 81 #define RTY_LMT_EN BIT(17) 82 83 84 /* OFFSET 20 */ 85 #define SGI BIT(6) 86 #define USB_TXAGG_NUM_SHT 24 87 88 typedef struct txdesc_88e { 89 /* Offset 0 */ 90 u32 pktlen:16; 91 u32 offset:8; 92 u32 bmc:1; 93 u32 htc:1; 94 u32 ls:1; 95 u32 fs:1; 96 u32 linip:1; 97 u32 noacm:1; 98 u32 gf:1; 99 u32 own:1; 100 101 /* Offset 4 */ 102 u32 macid:6; 103 u32 rsvd0406:2; 104 u32 qsel:5; 105 u32 rd_nav_ext:1; 106 u32 lsig_txop_en:1; 107 u32 pifs:1; 108 u32 rate_id:4; 109 u32 navusehdr:1; 110 u32 en_desc_id:1; 111 u32 sectype:2; 112 u32 rsvd0424:2; 113 u32 pkt_offset:5; /* unit: 8 bytes */ 114 u32 rsvd0431:1; 115 116 /* Offset 8 */ 117 u32 rts_rc:6; 118 u32 data_rc:6; 119 u32 agg_en:1; 120 u32 rd_en:1; 121 u32 bar_rty_th:2; 122 u32 bk:1; 123 u32 morefrag:1; 124 u32 raw:1; 125 u32 ccx:1; 126 u32 ampdu_density:3; 127 u32 bt_null:1; 128 u32 ant_sel_a:1; 129 u32 ant_sel_b:1; 130 u32 tx_ant_cck:2; 131 u32 tx_antl:2; 132 u32 tx_ant_ht:2; 133 134 /* Offset 12 */ 135 u32 nextheadpage:8; 136 u32 tailpage:8; 137 u32 seq:12; 138 u32 cpu_handle:1; 139 u32 tag1:1; 140 u32 trigger_int:1; 141 u32 hwseq_en:1; 142 143 /* Offset 16 */ 144 u32 rtsrate:5; 145 u32 ap_dcfe:1; 146 u32 hwseq_sel:2; 147 u32 userate:1; 148 u32 disrtsfb:1; 149 u32 disdatafb:1; 150 u32 cts2self:1; 151 u32 rtsen:1; 152 u32 hw_rts_en:1; 153 u32 port_id:1; 154 u32 pwr_status:3; 155 u32 wait_dcts:1; 156 u32 cts2ap_en:1; 157 u32 data_sc:2; 158 u32 data_stbc:2; 159 u32 data_short:1; 160 u32 data_bw:1; 161 u32 rts_short:1; 162 u32 rts_bw:1; 163 u32 rts_sc:2; 164 u32 vcs_stbc:2; 165 166 /* Offset 20 */ 167 u32 datarate:6; 168 u32 sgi:1; 169 u32 try_rate:1; 170 u32 data_ratefb_lmt:5; 171 u32 rts_ratefb_lmt:4; 172 u32 rty_lmt_en:1; 173 u32 data_rt_lmt:6; 174 u32 usb_txagg_num:8; 175 176 /* Offset 24 */ 177 u32 txagg_a:5; 178 u32 txagg_b:5; 179 u32 use_max_len:1; 180 u32 max_agg_num:5; 181 u32 mcsg1_max_len:4; 182 u32 mcsg2_max_len:4; 183 u32 mcsg3_max_len:4; 184 u32 mcs7_sgi_max_len:4; 185 186 /* Offset 28 */ 187 u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */ 188 u32 sw0:8; /* offset 30 */ 189 u32 sw1:4; 190 u32 mcs15_sgi_max_len:4; 191 } TXDESC_8188E, *PTXDESC_8188E; 192 193 #define txdesc_set_ccx_sw_88e(txdesc, value) \ 194 do { \ 195 ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \ 196 ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \ 197 } while (0) 198 199 struct txrpt_ccx_88e { 200 /* offset 0 */ 201 u8 tag1:1; 202 u8 pkt_num:3; 203 u8 txdma_underflow:1; 204 u8 int_bt:1; 205 u8 int_tri:1; 206 u8 int_ccx:1; 207 208 /* offset 1 */ 209 u8 mac_id:6; 210 u8 pkt_ok:1; 211 u8 bmc:1; 212 213 /* offset 2 */ 214 u8 retry_cnt:6; 215 u8 lifetime_over:1; 216 u8 retry_over:1; 217 218 /* offset 3 */ 219 u8 ccx_qtime0; 220 u8 ccx_qtime1; 221 222 /* offset 5 */ 223 u8 final_data_rate; 224 225 /* offset 6 */ 226 u8 sw1:4; 227 u8 qsel:4; 228 229 /* offset 7 */ 230 u8 sw0; 231 }; 232 233 #define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) 234 #define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) 235 236 #define SET_TX_DESC_SEC_TYPE_8188E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) 237 238 void rtl8188e_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, 239 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); 240 void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc); 241 void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); 242 243 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 244 s32 rtl8188es_init_xmit_priv(PADAPTER padapter); 245 void rtl8188es_free_xmit_priv(PADAPTER padapter); 246 s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 247 s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 248 #ifdef CONFIG_RTW_MGMT_QUEUE 249 s32 rtl8188es_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 250 #endif 251 s32 rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 252 thread_return rtl8188es_xmit_thread(thread_context context); 253 s32 rtl8188es_xmit_buf_handler(PADAPTER padapter); 254 255 #ifdef CONFIG_SDIO_TX_TASKLET 256 void rtl8188es_xmit_tasklet(void *priv); 257 #endif 258 #endif 259 260 #ifdef CONFIG_USB_HCI 261 s32 rtl8188eu_init_xmit_priv(PADAPTER padapter); 262 void rtl8188eu_free_xmit_priv(PADAPTER padapter); 263 s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 264 s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 265 #ifdef CONFIG_RTW_MGMT_QUEUE 266 s32 rtl8188eu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 267 #endif 268 s32 rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 269 s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter); 270 void rtl8188eu_xmit_tasklet(void *priv); 271 s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 272 #endif 273 274 #ifdef CONFIG_PCI_HCI 275 s32 rtl8188ee_init_xmit_priv(PADAPTER padapter); 276 void rtl8188ee_free_xmit_priv(PADAPTER padapter); 277 void rtl8188ee_xmitframe_resume(_adapter *padapter); 278 s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 279 s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 280 #ifdef CONFIG_RTW_MGMT_QUEUE 281 s32 rtl8188ee_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 282 #endif 283 s32 rtl8188ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 284 void rtl8188ee_xmit_tasklet(void *priv); 285 #endif 286 287 288 289 #ifdef CONFIG_TX_EARLY_MODE 290 void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 291 #endif 292 293 #ifdef CONFIG_XMIT_ACK 294 void dump_txrpt_ccx_88e(void *buf); 295 void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf); 296 #else 297 #define dump_txrpt_ccx_88e(buf) do {} while (0) 298 #define handle_txrpt_ccx_88e(adapter, buf) do {} while (0) 299 #endif /* CONFIG_XMIT_ACK */ 300 301 void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); 302 #endif /* __RTL8188E_XMIT_H__ */ 303