1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8814PHYREG_H__ 16 #define __INC_HAL8814PHYREG_H__ 17 /*--------------------------Define Parameters-------------------------------*/ 18 /* 19 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 20 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 21 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 22 * 3. RF register 0x00-2E 23 * 4. Bit Mask for BB/RF register 24 * 5. Other defintion for BB/RF R/W 25 * */ 26 27 28 /* BB Register Definition */ 29 30 #define rCCAonSec_Jaguar 0x838 31 #define rPwed_TH_Jaguar 0x830 32 #define rL1_Weight_Jaguar 0x840 33 #define r_L1_SBD_start_time 0x844 34 35 /* BW and sideband setting */ 36 #define rBWIndication_Jaguar 0x834 37 #define rL1PeakTH_Jaguar 0x848 38 #define rRFMOD_Jaguar 0x8ac /* RF mode */ 39 #define rADC_Buf_Clk_Jaguar 0x8c4 40 #define rADC_Buf_40_Clk_Jaguar2 0x8c8 41 #define rRFECTRL_Jaguar 0x900 42 #define bRFMOD_Jaguar 0xc3 43 #define rCCK_System_Jaguar 0xa00 /* for cck sideband */ 44 #define bCCK_System_Jaguar 0x10 45 46 /* Block & Path enable */ 47 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ 48 #define bOFDMEN_Jaguar 0x20000000 49 #define bCCKEN_Jaguar 0x10000000 50 #define rRxPath_Jaguar 0x808 /* Rx antenna */ 51 #define bRxPath_Jaguar 0xff 52 #define rTxPath_Jaguar 0x80c /* Tx antenna */ 53 #define bTxPath_Jaguar 0x0fffffff 54 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ 55 #define bCCK_RX_Jaguar 0x0c000000 56 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ 57 58 #define rRxPath_Jaguar2 0xa04 /* Rx antenna */ 59 #define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */ 60 #define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */ 61 62 63 /* RF read/write-related */ 64 #define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ 65 #define bHSSIRead_addr_Jaguar 0xff 66 #define bHSSIRead_trigger_Jaguar 0x100 67 #define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ 68 #define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ 69 #define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ 70 #define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ 71 #define rRead_data_Jaguar 0xfffff 72 #define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ 73 #define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ 74 #define bLSSIWrite_data_Jaguar 0x000fffff 75 #define bLSSIWrite_addr_Jaguar 0x0ff00000 76 77 #define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */ 78 #define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */ 79 #define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */ 80 #define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */ 81 #define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */ 82 #define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */ 83 84 85 /* YN: mask the following register definition temporarily */ 86 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 87 #define rFPGA0_XB_RFInterfaceOE 0x864 88 89 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 90 #define rFPGA0_XCD_RFInterfaceSW 0x874 91 92 /* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter 93 * #define rFPGA0_XCD_RFParameter 0x87c */ 94 95 /* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? 96 * #define rFPGA0_AnalogParameter2 0x884 97 * #define rFPGA0_AnalogParameter3 0x888 98 * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy 99 * #define rFPGA0_AnalogParameter4 0x88c */ 100 101 102 /* CCK TX scaling */ 103 #define rCCK_TxFilter1_Jaguar 0xa20 104 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 105 #define bCCK_TxFilter1_C1_Jaguar 0xff000000 106 #define rCCK_TxFilter2_Jaguar 0xa24 107 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff 108 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 109 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 110 #define bCCK_TxFilter2_C5_Jaguar 0xff000000 111 #define rCCK_TxFilter3_Jaguar 0xa28 112 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff 113 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 114 /* NBI & CSI Mask setting */ 115 #define rCSI_Mask_Setting1_Jaguar 0x874 116 #define rCSI_Fix_Mask0_Jaguar 0x880 117 #define rCSI_Fix_Mask1_Jaguar 0x884 118 #define rCSI_Fix_Mask2_Jaguar 0x888 119 #define rCSI_Fix_Mask3_Jaguar 0x88c 120 #define rCSI_Fix_Mask4_Jaguar 0x890 121 #define rCSI_Fix_Mask5_Jaguar 0x894 122 #define rCSI_Fix_Mask6_Jaguar 0x898 123 #define rCSI_Fix_Mask7_Jaguar 0x89c 124 #define rNBI_Setting_Jaguar 0x87c 125 126 127 /* YN: mask the following register definition temporarily 128 * #define rPdp_AntA 0xb00 129 * #define rPdp_AntA_4 0xb04 130 * #define rConfig_Pmpd_AntA 0xb28 131 * #define rConfig_AntA 0xb68 132 * #define rConfig_AntB 0xb6c 133 * #define rPdp_AntB 0xb70 134 * #define rPdp_AntB_4 0xb74 135 * #define rConfig_Pmpd_AntB 0xb98 136 * #define rAPK 0xbd8 */ 137 138 /* RXIQC */ 139 #define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ 140 #define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ 141 #define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ 142 #define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ 143 #define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ 144 #define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ 145 #define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ 146 #define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ 147 148 #define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */ 149 #define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */ 150 #define rRF_TxGainOffset 0x55 151 152 /* DIG-related */ 153 #define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ 154 #define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ 155 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */ 156 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */ 157 158 #define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ 159 #define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ 160 #define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ 161 #define b_FalseAlarm_Jaguar 0xffff 162 #define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ 163 #define bCCK_CCA_Jaguar 0x00ff0000 164 165 /* Tx Power Ttraining-related */ 166 #define rA_TxPwrTraing_Jaguar 0xc54 167 #define rB_TxPwrTraing_Jaguar 0xe54 168 169 /* Report-related */ 170 #define rOFDM_ShortCFOAB_Jaguar 0xf60 171 #define rOFDM_LongCFOAB_Jaguar 0xf64 172 #define rOFDM_EndCFOAB_Jaguar 0xf70 173 #define rOFDM_AGCReport_Jaguar 0xf84 174 #define rOFDM_RxSNR_Jaguar 0xf88 175 #define rOFDM_RxEVMCSI_Jaguar 0xf8c 176 #define rOFDM_SIGReport_Jaguar 0xf90 177 178 /* Misc functions */ 179 #define rEDCCA_Jaguar 0x8a4 /* EDCCA */ 180 #define bEDCCA_Jaguar 0xffff 181 #define rAGC_table_Jaguar 0x82c /* AGC tabel select */ 182 #define bAGC_table_Jaguar 0x3 183 #define b_sel5g_Jaguar 0x1000 /* sel5g */ 184 #define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ 185 #define rFc_area_Jaguar 0x860 /* fc_area */ 186 #define bFc_area_Jaguar 0x1ffe000 187 #define rSingleTone_ContTx_Jaguar 0x914 188 189 #define rAGC_table_Jaguar2 0x958 /* AGC tabel select */ 190 #define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */ 191 192 193 /* RFE */ 194 #define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ 195 #define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ 196 #define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ 197 #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ 198 #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ 199 #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ 200 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 201 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 202 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 203 #define bMask_RFEInv_Jaguar 0x3ff00000 204 #define bMask_AntselPathFollow_Jaguar 0x00030000 205 206 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */ 207 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */ 208 #define rA_RFE_Sel_Jaguar2 0x1990 209 210 211 212 /* TX AGC */ 213 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 214 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 215 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 216 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c 217 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 218 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 219 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 220 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c 221 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 222 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 223 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 224 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c 225 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 226 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 227 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 228 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c 229 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 230 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 231 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 232 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c 233 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 234 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 235 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 236 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c 237 #define bTxAGC_byte0_Jaguar 0xff 238 #define bTxAGC_byte1_Jaguar 0xff00 239 #define bTxAGC_byte2_Jaguar 0xff0000 240 #define bTxAGC_byte3_Jaguar 0xff000000 241 242 243 /* TX AGC */ 244 #define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20 245 #define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24 246 #define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28 247 #define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c 248 #define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30 249 #define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34 250 #define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38 251 #define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8 252 #define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc 253 #define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c 254 #define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40 255 #define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44 256 #define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48 257 #define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c 258 #define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0 259 #define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4 260 #define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8 261 #define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20 262 #define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24 263 #define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28 264 #define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c 265 #define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30 266 #define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34 267 #define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38 268 #define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8 269 #define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc 270 #define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c 271 #define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40 272 #define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44 273 #define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48 274 #define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c 275 #define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0 276 #define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4 277 #define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8 278 #define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820 279 #define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824 280 #define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828 281 #define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c 282 #define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830 283 #define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834 284 #define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838 285 #define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8 286 #define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc 287 #define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c 288 #define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840 289 #define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844 290 #define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848 291 #define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c 292 #define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0 293 #define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4 294 #define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8 295 #define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20 296 #define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24 297 #define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28 298 #define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c 299 #define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30 300 #define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34 301 #define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38 302 #define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8 303 #define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc 304 #define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c 305 #define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40 306 #define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44 307 #define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48 308 #define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c 309 #define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0 310 #define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4 311 #define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8 312 /* IQK YN: temporaily mask this part 313 * #define rFPGA0_IQK 0xe28 314 * #define rTx_IQK_Tone_A 0xe30 315 * #define rRx_IQK_Tone_A 0xe34 316 * #define rTx_IQK_PI_A 0xe38 317 * #define rRx_IQK_PI_A 0xe3c */ 318 319 /* #define rTx_IQK 0xe40 */ 320 /* #define rRx_IQK 0xe44 */ 321 /* #define rIQK_AGC_Pts 0xe48 */ 322 /* #define rIQK_AGC_Rsp 0xe4c */ 323 /* #define rTx_IQK_Tone_B 0xe50 */ 324 /* #define rRx_IQK_Tone_B 0xe54 */ 325 /* #define rTx_IQK_PI_B 0xe58 */ 326 /* #define rRx_IQK_PI_B 0xe5c */ 327 /* #define rIQK_AGC_Cont 0xe60 */ 328 329 330 /* AFE-related */ 331 #define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ 332 #define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ 333 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 334 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c 335 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 336 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74 337 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 338 #define rA_Rx2Rx_BT_Jaguar 0xc7c 339 #define rA_sleep_nav_Jaguar 0xc80 340 #define rA_pmpd_Jaguar 0xc84 341 #define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ 342 #define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ 343 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 344 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c 345 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 346 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74 347 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 348 #define rB_Rx2Rx_BT_Jaguar 0xe7c 349 #define rB_sleep_nav_Jaguar 0xe80 350 #define rB_pmpd_Jaguar 0xe84 351 352 353 /* YN: mask these registers temporaily 354 * #define rTx_Power_Before_IQK_A 0xe94 355 * #define rTx_Power_After_IQK_A 0xe9c */ 356 357 /* #define rRx_Power_Before_IQK_A 0xea0 */ 358 /* #define rRx_Power_Before_IQK_A_2 0xea4 */ 359 /* #define rRx_Power_After_IQK_A 0xea8 */ 360 /* #define rRx_Power_After_IQK_A_2 0xeac */ 361 362 /* #define rTx_Power_Before_IQK_B 0xeb4 */ 363 /* #define rTx_Power_After_IQK_B 0xebc */ 364 365 /* #define rRx_Power_Before_IQK_B 0xec0 */ 366 /* #define rRx_Power_Before_IQK_B_2 0xec4 */ 367 /* #define rRx_Power_After_IQK_B 0xec8 */ 368 /* #define rRx_Power_After_IQK_B_2 0xecc */ 369 370 371 /* RSSI Dump */ 372 #define rA_RSSIDump_Jaguar 0xBF0 373 #define rB_RSSIDump_Jaguar 0xBF1 374 #define rS1_RXevmDump_Jaguar 0xBF4 375 #define rS2_RXevmDump_Jaguar 0xBF5 376 #define rA_RXsnrDump_Jaguar 0xBF6 377 #define rB_RXsnrDump_Jaguar 0xBF7 378 #define rA_CfoShortDump_Jaguar 0xBF8 379 #define rB_CfoShortDump_Jaguar 0xBFA 380 #define rA_CfoLongDump_Jaguar 0xBEC 381 #define rB_CfoLongDump_Jaguar 0xBEE 382 383 384 /* RF Register 385 * */ 386 #define RF_AC_Jaguar 0x00 /* */ 387 #define RF_RF_Top_Jaguar 0x07 /* */ 388 #define RF_TXLOK_Jaguar 0x08 /* */ 389 #define RF_TXAPK_Jaguar 0x0B 390 #define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ 391 #define RF_RCK1_Jaguar 0x1c /* */ 392 #define RF_RCK2_Jaguar 0x1d 393 #define RF_RCK3_Jaguar 0x1e 394 #define RF_ModeTableAddr 0x30 395 #define RF_ModeTableData0 0x31 396 #define RF_ModeTableData1 0x32 397 #define RF_TxLCTank_Jaguar 0x54 398 #define RF_APK_Jaguar 0x63 399 #define RF_LCK 0xB4 400 #define RF_WeLut_Jaguar 0xEF 401 402 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 403 #define bRF_CHNLBW_BW 0xc00 404 405 406 /* 407 * RL6052 Register definition 408 * */ 409 #define RF_AC 0x00 /* */ 410 #define RF_IPA_A 0x0C /* */ 411 #define RF_TXBIAS_A 0x0D 412 #define RF_BS_PA_APSET_G9_G11 0x0E 413 #define RF_MODE1 0x10 /* */ 414 #define RF_MODE2 0x11 /* */ 415 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 416 #define RF_RCK_OS 0x30 /* RF TX PA control */ 417 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 418 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 419 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 420 #define RF_0x52 0x52 421 #define RF_WE_LUT 0xEF 422 423 /* 424 * Bit Mask 425 * 426 * 1. Page1(0x100) */ 427 #define bBBResetB 0x100 /* Useless now? */ 428 #define bGlobalResetB 0x200 429 #define bOFDMTxStart 0x4 430 #define bCCKTxStart 0x8 431 #define bCRC32Debug 0x100 432 #define bPMACLoopback 0x10 433 #define bTxLSIG 0xffffff 434 #define bOFDMTxRate 0xf 435 #define bOFDMTxReserved 0x10 436 #define bOFDMTxLength 0x1ffe0 437 #define bOFDMTxParity 0x20000 438 #define bTxHTSIG1 0xffffff 439 #define bTxHTMCSRate 0x7f 440 #define bTxHTBW 0x80 441 #define bTxHTLength 0xffff00 442 #define bTxHTSIG2 0xffffff 443 #define bTxHTSmoothing 0x1 444 #define bTxHTSounding 0x2 445 #define bTxHTReserved 0x4 446 #define bTxHTAggreation 0x8 447 #define bTxHTSTBC 0x30 448 #define bTxHTAdvanceCoding 0x40 449 #define bTxHTShortGI 0x80 450 #define bTxHTNumberHT_LTF 0x300 451 #define bTxHTCRC8 0x3fc00 452 #define bCounterReset 0x10000 453 #define bNumOfOFDMTx 0xffff 454 #define bNumOfCCKTx 0xffff0000 455 #define bTxIdleInterval 0xffff 456 #define bOFDMService 0xffff0000 457 #define bTxMACHeader 0xffffffff 458 #define bTxDataInit 0xff 459 #define bTxHTMode 0x100 460 #define bTxDataType 0x30000 461 #define bTxRandomSeed 0xffffffff 462 #define bCCKTxPreamble 0x1 463 #define bCCKTxSFD 0xffff0000 464 #define bCCKTxSIG 0xff 465 #define bCCKTxService 0xff00 466 #define bCCKLengthExt 0x8000 467 #define bCCKTxLength 0xffff0000 468 #define bCCKTxCRC16 0xffff 469 #define bCCKTxStatus 0x1 470 #define bOFDMTxStatus 0x2 471 472 473 /* 474 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 475 * 1. Page1(0x100) 476 * */ 477 #define rPMAC_Reset 0x100 478 #define rPMAC_TxStart 0x104 479 #define rPMAC_TxLegacySIG 0x108 480 #define rPMAC_TxHTSIG1 0x10c 481 #define rPMAC_TxHTSIG2 0x110 482 #define rPMAC_PHYDebug 0x114 483 #define rPMAC_TxPacketNum 0x118 484 #define rPMAC_TxIdle 0x11c 485 #define rPMAC_TxMACHeader0 0x120 486 #define rPMAC_TxMACHeader1 0x124 487 #define rPMAC_TxMACHeader2 0x128 488 #define rPMAC_TxMACHeader3 0x12c 489 #define rPMAC_TxMACHeader4 0x130 490 #define rPMAC_TxMACHeader5 0x134 491 #define rPMAC_TxDataType 0x138 492 #define rPMAC_TxRandomSeed 0x13c 493 #define rPMAC_CCKPLCPPreamble 0x140 494 #define rPMAC_CCKPLCPHeader 0x144 495 #define rPMAC_CCKCRC16 0x148 496 #define rPMAC_OFDMRxCRC32OK 0x170 497 #define rPMAC_OFDMRxCRC32Er 0x174 498 #define rPMAC_OFDMRxParityEr 0x178 499 #define rPMAC_OFDMRxCRC8Er 0x17c 500 #define rPMAC_CCKCRxRC16Er 0x180 501 #define rPMAC_CCKCRxRC32Er 0x184 502 #define rPMAC_CCKCRxRC32OK 0x188 503 #define rPMAC_TxStatus 0x18c 504 505 /* 506 * 3. Page8(0x800) 507 * */ 508 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 509 510 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 511 #define rFPGA0_PSDFunction 0x808 512 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 513 514 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 515 #define rFPGA0_XA_HSSIParameter2 0x824 516 #define rFPGA0_XB_HSSIParameter1 0x828 517 #define rFPGA0_XB_HSSIParameter2 0x82c 518 519 #define rFPGA0_XA_LSSIParameter 0x840 520 #define rFPGA0_XB_LSSIParameter 0x844 521 522 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 523 #define rFPGA0_XCD_SwitchControl 0x85c 524 525 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 526 #define rFPGA0_XCD_RFParameter 0x87c 527 528 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 529 #define rFPGA0_AnalogParameter2 0x884 530 #define rFPGA0_AnalogParameter3 0x888 531 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 532 #define rFPGA0_AnalogParameter4 0x88c 533 534 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 535 #define rFPGA0_XB_LSSIReadBack 0x8a4 536 #define rFPGA0_XC_LSSIReadBack 0x8a8 537 #define rFPGA0_XD_LSSIReadBack 0x8ac 538 539 #define rFPGA0_XCD_RFPara 0x8b4 540 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 541 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 542 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 543 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 544 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 545 546 /* 547 * 4. Page9(0x900) 548 * */ 549 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 550 #define REG_BB_TX_PATH_SEL_1_8814A 0x93c 551 #define REG_BB_TX_PATH_SEL_2_8814A 0x940 552 #define rFPGA1_TxBlock 0x904 /* Useless now */ 553 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 554 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 555 /*Page 19 for TxBF*/ 556 #define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac 557 #define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4 558 /* 559 * PageA(0xA00) 560 * */ 561 #define rCCK0_System 0xa00 562 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 563 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 564 #define rCCK0_TxFilter1 0xa20 565 #define rCCK0_TxFilter2 0xa24 566 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 567 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 568 569 /* 570 * PageB(0xB00) 571 * */ 572 #define rPdp_AntA 0xb00 573 #define rPdp_AntA_4 0xb04 574 #define rConfig_Pmpd_AntA 0xb28 575 #define rConfig_AntA 0xb68 576 #define rConfig_AntB 0xb6c 577 #define rPdp_AntB 0xb70 578 #define rPdp_AntB_4 0xb74 579 #define rConfig_Pmpd_AntB 0xb98 580 #define rAPK 0xbd8 581 582 /* 583 * 6. PageC(0xC00) 584 * */ 585 #define rOFDM0_LSTF 0xc00 586 587 #define rOFDM0_TRxPathEnable 0xc04 588 #define rOFDM0_TRMuxPar 0xc08 589 #define rOFDM0_TRSWIsolation 0xc0c 590 591 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 592 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 593 #define rOFDM0_XBRxAFE 0xc18 594 #define rOFDM0_XBRxIQImbalance 0xc1c 595 #define rOFDM0_XCRxAFE 0xc20 596 #define rOFDM0_XCRxIQImbalance 0xc24 597 #define rOFDM0_XDRxAFE 0xc28 598 #define rOFDM0_XDRxIQImbalance 0xc2c 599 600 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 601 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 602 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 603 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 604 605 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 606 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 607 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 608 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 609 610 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 611 #define rOFDM0_XAAGCCore2 0xc54 612 #define rOFDM0_XBAGCCore1 0xc58 613 #define rOFDM0_XBAGCCore2 0xc5c 614 #define rOFDM0_XCAGCCore1 0xc60 615 #define rOFDM0_XCAGCCore2 0xc64 616 #define rOFDM0_XDAGCCore1 0xc68 617 #define rOFDM0_XDAGCCore2 0xc6c 618 619 #define rOFDM0_AGCParameter1 0xc70 620 #define rOFDM0_AGCParameter2 0xc74 621 #define rOFDM0_AGCRSSITable 0xc78 622 #define rOFDM0_HTSTFAGC 0xc7c 623 624 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 625 #define rOFDM0_XATxAFE 0xc84 626 #define rOFDM0_XBTxIQImbalance 0xc88 627 #define rOFDM0_XBTxAFE 0xc8c 628 #define rOFDM0_XCTxIQImbalance 0xc90 629 #define rOFDM0_XCTxAFE 0xc94 630 #define rOFDM0_XDTxIQImbalance 0xc98 631 #define rOFDM0_XDTxAFE 0xc9c 632 633 #define rOFDM0_RxIQExtAnta 0xca0 634 #define rOFDM0_TxCoeff1 0xca4 635 #define rOFDM0_TxCoeff2 0xca8 636 #define rOFDM0_TxCoeff3 0xcac 637 #define rOFDM0_TxCoeff4 0xcb0 638 #define rOFDM0_TxCoeff5 0xcb4 639 #define rOFDM0_TxCoeff6 0xcb8 640 #define rOFDM0_RxHPParameter 0xce0 641 #define rOFDM0_TxPseudoNoiseWgt 0xce4 642 #define rOFDM0_FrameSync 0xcf0 643 #define rOFDM0_DFSReport 0xcf4 644 645 /* 646 * 7. PageD(0xD00) 647 * */ 648 #define rOFDM1_LSTF 0xd00 649 #define rOFDM1_TRxPathEnable 0xd04 650 651 /* 652 * 8. PageE(0xE00) 653 * */ 654 #define rTxAGC_A_Rate18_06 0xe00 655 #define rTxAGC_A_Rate54_24 0xe04 656 #define rTxAGC_A_CCK1_Mcs32 0xe08 657 #define rTxAGC_A_Mcs03_Mcs00 0xe10 658 #define rTxAGC_A_Mcs07_Mcs04 0xe14 659 #define rTxAGC_A_Mcs11_Mcs08 0xe18 660 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 661 662 #define rTxAGC_B_Rate18_06 0x830 663 #define rTxAGC_B_Rate54_24 0x834 664 #define rTxAGC_B_CCK1_55_Mcs32 0x838 665 #define rTxAGC_B_Mcs03_Mcs00 0x83c 666 #define rTxAGC_B_Mcs07_Mcs04 0x848 667 #define rTxAGC_B_Mcs11_Mcs08 0x84c 668 #define rTxAGC_B_Mcs15_Mcs12 0x868 669 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 670 671 #define rFPGA0_IQK 0xe28 672 #define rTx_IQK_Tone_A 0xe30 673 #define rRx_IQK_Tone_A 0xe34 674 #define rTx_IQK_PI_A 0xe38 675 #define rRx_IQK_PI_A 0xe3c 676 677 #define rTx_IQK 0xe40 678 #define rRx_IQK 0xe44 679 #define rIQK_AGC_Pts 0xe48 680 #define rIQK_AGC_Rsp 0xe4c 681 #define rTx_IQK_Tone_B 0xe50 682 #define rRx_IQK_Tone_B 0xe54 683 #define rTx_IQK_PI_B 0xe58 684 #define rRx_IQK_PI_B 0xe5c 685 #define rIQK_AGC_Cont 0xe60 686 687 #define rBlue_Tooth 0xe6c 688 #define rRx_Wait_CCA 0xe70 689 #define rTx_CCK_RFON 0xe74 690 #define rTx_CCK_BBON 0xe78 691 #define rTx_OFDM_RFON 0xe7c 692 #define rTx_OFDM_BBON 0xe80 693 #define rTx_To_Rx 0xe84 694 #define rTx_To_Tx 0xe88 695 #define rRx_CCK 0xe8c 696 697 #define rTx_Power_Before_IQK_A 0xe94 698 #define rTx_Power_After_IQK_A 0xe9c 699 700 #define rRx_Power_Before_IQK_A 0xea0 701 #define rRx_Power_Before_IQK_A_2 0xea4 702 #define rRx_Power_After_IQK_A 0xea8 703 #define rRx_Power_After_IQK_A_2 0xeac 704 705 #define rTx_Power_Before_IQK_B 0xeb4 706 #define rTx_Power_After_IQK_B 0xebc 707 708 #define rRx_Power_Before_IQK_B 0xec0 709 #define rRx_Power_Before_IQK_B_2 0xec4 710 #define rRx_Power_After_IQK_B 0xec8 711 #define rRx_Power_After_IQK_B_2 0xecc 712 713 #define rRx_OFDM 0xed0 714 #define rRx_Wait_RIFS 0xed4 715 #define rRx_TO_Rx 0xed8 716 #define rStandby 0xedc 717 #define rSleep 0xee0 718 #define rPMPD_ANAEN 0xeec 719 720 721 /* 2. Page8(0x800) */ 722 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 723 #define bJapanMode 0x2 724 #define bCCKTxSC 0x30 725 #define bCCKEn 0x1000000 726 #define bOFDMEn 0x2000000 727 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 728 #define bXCTxAGC 0xf000 729 #define bXDTxAGC 0xf0000 730 731 /* 4. PageA(0xA00) */ 732 #define bCCKBBMode 0x3 /* Useless */ 733 #define bCCKTxPowerSaving 0x80 734 #define bCCKRxPowerSaving 0x40 735 736 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 737 738 #define bCCKScramble 0x8 /* Useless */ 739 #define bCCKAntDiversity 0x8000 740 #define bCCKCarrierRecovery 0x4000 741 #define bCCKTxRate 0x3000 742 #define bCCKDCCancel 0x0800 743 #define bCCKISICancel 0x0400 744 #define bCCKMatchFilter 0x0200 745 #define bCCKEqualizer 0x0100 746 #define bCCKPreambleDetect 0x800000 747 #define bCCKFastFalseCCA 0x400000 748 #define bCCKChEstStart 0x300000 749 #define bCCKCCACount 0x080000 750 #define bCCKcs_lim 0x070000 751 #define bCCKBistMode 0x80000000 752 #define bCCKCCAMask 0x40000000 753 #define bCCKTxDACPhase 0x4 754 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 755 #define bCCKr_cp_mode0 0x0100 756 #define bCCKTxDCOffset 0xf0 757 #define bCCKRxDCOffset 0xf 758 #define bCCKCCAMode 0xc000 759 #define bCCKFalseCS_lim 0x3f00 760 #define bCCKCS_ratio 0xc00000 761 #define bCCKCorgBit_sel 0x300000 762 #define bCCKPD_lim 0x0f0000 763 #define bCCKNewCCA 0x80000000 764 #define bCCKRxHPofIG 0x8000 765 #define bCCKRxIG 0x7f00 766 #define bCCKLNAPolarity 0x800000 767 #define bCCKRx1stGain 0x7f0000 768 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 769 #define bCCKRxAGCSatLevel 0x1f000000 770 #define bCCKRxAGCSatCount 0xe0 771 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 772 #define bCCKFixedRxAGC 0x8000 773 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 774 #define bCCKAntennaPolarity 0x2000 775 #define bCCKTxFilterType 0x0c00 776 #define bCCKRxAGCReportType 0x0300 777 #define bCCKRxDAGCEn 0x80000000 778 #define bCCKRxDAGCPeriod 0x20000000 779 #define bCCKRxDAGCSatLevel 0x1f000000 780 #define bCCKTimingRecovery 0x800000 781 #define bCCKTxC0 0x3f0000 782 #define bCCKTxC1 0x3f000000 783 #define bCCKTxC2 0x3f 784 #define bCCKTxC3 0x3f00 785 #define bCCKTxC4 0x3f0000 786 #define bCCKTxC5 0x3f000000 787 #define bCCKTxC6 0x3f 788 #define bCCKTxC7 0x3f00 789 #define bCCKDebugPort 0xff0000 790 #define bCCKDACDebug 0x0f000000 791 #define bCCKFalseAlarmEnable 0x8000 792 #define bCCKFalseAlarmRead 0x4000 793 #define bCCKTRSSI 0x7f 794 #define bCCKRxAGCReport 0xfe 795 #define bCCKRxReport_AntSel 0x80000000 796 #define bCCKRxReport_MFOff 0x40000000 797 #define bCCKRxRxReport_SQLoss 0x20000000 798 #define bCCKRxReport_Pktloss 0x10000000 799 #define bCCKRxReport_Lockedbit 0x08000000 800 #define bCCKRxReport_RateError 0x04000000 801 #define bCCKRxReport_RxRate 0x03000000 802 #define bCCKRxFACounterLower 0xff 803 #define bCCKRxFACounterUpper 0xff000000 804 #define bCCKRxHPAGCStart 0xe000 805 #define bCCKRxHPAGCFinal 0x1c00 806 #define bCCKRxFalseAlarmEnable 0x8000 807 #define bCCKFACounterFreeze 0x4000 808 #define bCCKTxPathSel 0x10000000 809 #define bCCKDefaultRxPath 0xc000000 810 #define bCCKOptionRxPath 0x3000000 811 812 #define RF_T_METER_88E 0x42 813 814 /* 6. PageE(0xE00) */ 815 #define bSTBCEn 0x4 /* Useless */ 816 #define bAntennaMapping 0x10 817 #define bNss 0x20 818 #define bCFOAntSumD 0x200 819 #define bPHYCounterReset 0x8000000 820 #define bCFOReportGet 0x4000000 821 #define bOFDMContinueTx 0x10000000 822 #define bOFDMSingleCarrier 0x20000000 823 #define bOFDMSingleTone 0x40000000 824 825 826 /* 827 * Other Definition 828 * */ 829 830 #define bEnable 0x1 /* Useless */ 831 #define bDisable 0x0 832 833 /* byte endable for srwrite */ 834 #define bByte0 0x1 /* Useless */ 835 #define bByte1 0x2 836 #define bByte2 0x4 837 #define bByte3 0x8 838 #define bWord0 0x3 839 #define bWord1 0xc 840 #define bDWord 0xf 841 842 /* for PutRegsetting & GetRegSetting BitMask */ 843 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 844 #define bMaskByte1 0xff00 845 #define bMaskByte2 0xff0000 846 #define bMaskByte3 0xff000000 847 #define bMaskHWord 0xffff0000 848 #define bMaskLWord 0x0000ffff 849 #define bMaskDWord 0xffffffff 850 #define bMaskH3Bytes 0xffffff00 851 #define bMask12Bits 0xfff 852 #define bMaskH4Bits 0xf0000000 853 #define bMaskOFDM_D 0xffc00000 854 #define bMaskCCK 0x3f3f3f3f 855 #define bMask7bits 0x7f 856 #define bMaskByte2HighNibble 0x00f00000 857 #define bMaskByte3LowNibble 0x0f000000 858 #define bMaskL3Bytes 0x00ffffff 859 860 /*--------------------------Define Parameters-------------------------------*/ 861 862 863 #endif 864