1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8188EPHYCFG_H__ 16 #define __INC_HAL8188EPHYCFG_H__ 17 18 19 /*--------------------------Define Parameters-------------------------------*/ 20 #define LOOP_LIMIT 5 21 #define MAX_STALL_TIME 50 /* us */ 22 #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ 23 #define MAX_TXPWR_IDX_NMODE_92S 63 24 #define Reset_Cnt_Limit 3 25 26 #ifdef CONFIG_PCI_HCI 27 #define MAX_AGGR_NUM 0x0B 28 #else 29 #define MAX_AGGR_NUM 0x07 30 #endif /* CONFIG_PCI_HCI */ 31 32 33 /*--------------------------Define Parameters-------------------------------*/ 34 35 36 /*------------------------------Define structure----------------------------*/ 37 38 #define MAX_TX_COUNT_8188E 1 39 40 /* BB/RF related */ 41 42 43 /*------------------------------Define structure----------------------------*/ 44 45 46 /*------------------------Export global variable----------------------------*/ 47 /*------------------------Export global variable----------------------------*/ 48 49 50 /*------------------------Export Marco Definition---------------------------*/ 51 /*------------------------Export Marco Definition---------------------------*/ 52 53 54 /*--------------------------Exported Function prototype---------------------*/ 55 /* 56 * BB and RF register read/write 57 * */ 58 u32 PHY_QueryBBReg8188E(PADAPTER Adapter, 59 u32 RegAddr, 60 u32 BitMask); 61 void PHY_SetBBReg8188E(PADAPTER Adapter, 62 u32 RegAddr, 63 u32 BitMask, 64 u32 Data); 65 u32 PHY_QueryRFReg8188E(PADAPTER Adapter, 66 enum rf_path eRFPath, 67 u32 RegAddr, 68 u32 BitMask); 69 void PHY_SetRFReg8188E(PADAPTER Adapter, 70 enum rf_path eRFPath, 71 u32 RegAddr, 72 u32 BitMask, 73 u32 Data); 74 75 /* 76 * Initialization related function 77 */ 78 /* MAC/BB/RF HAL config */ 79 int PHY_MACConfig8188E(PADAPTER Adapter); 80 int PHY_BBConfig8188E(PADAPTER Adapter); 81 int PHY_RFConfig8188E(PADAPTER Adapter); 82 83 /* RF config */ 84 int rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath); 85 86 /* 87 * RF Power setting 88 */ 89 /* extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter, 90 * RT_RF_POWER_STATE eRFPowerState); */ 91 92 /* 93 * BB TX Power R/W 94 * */ 95 void PHY_SetTxPowerLevel8188E(PADAPTER Adapter, 96 u8 channel); 97 98 void 99 PHY_SetTxPowerIndex_8188E( 100 PADAPTER Adapter, 101 u32 PowerIndex, 102 enum rf_path RFPath, 103 u8 Rate 104 ); 105 106 s8 phy_get_txpwr_target_extra_bias_8188e(_adapter *adapter, enum rf_path rfpath 107 , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch); 108 109 /* 110 * Switch bandwidth for 8192S 111 */ 112 /* extern void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer ); */ 113 void PHY_SetBWMode8188E(PADAPTER pAdapter, 114 enum channel_width ChnlWidth, 115 unsigned char Offset); 116 117 /* 118 * Set FW CMD IO for 8192S. 119 */ 120 /* extern BOOLEAN HalSetIO8192C(PADAPTER Adapter, 121 * IO_TYPE IOType); */ 122 123 /* 124 * Set A2 entry to fw for 8192S 125 * */ 126 extern void FillA2Entry8192C(PADAPTER Adapter, 127 u8 index, 128 u8 *val); 129 130 131 /* 132 * channel switch related funciton 133 */ 134 /* extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer ); */ 135 void PHY_SwChnl8188E(PADAPTER pAdapter, 136 u8 channel); 137 138 void 139 PHY_SetSwChnlBWMode8188E( 140 PADAPTER Adapter, 141 u8 channel, 142 enum channel_width Bandwidth, 143 u8 Offset40, 144 u8 Offset80 145 ); 146 147 void 148 PHY_SetRFEReg_8188E( 149 PADAPTER Adapter 150 ); 151 /* 152 * BB/MAC/RF other monitor API 153 * */ 154 void phy_set_rf_path_switch_8188e(struct dm_struct *phydm, bool bMain); 155 156 extern void 157 PHY_SwitchEphyParameter( 158 PADAPTER Adapter 159 ); 160 161 extern void 162 PHY_EnableHostClkReq( 163 PADAPTER Adapter 164 ); 165 166 BOOLEAN 167 SetAntennaConfig92C( 168 PADAPTER Adapter, 169 u8 DefaultAnt 170 ); 171 172 /*--------------------------Exported Function prototype---------------------*/ 173 174 /* 175 * Initialization related function 176 * 177 * MAC/BB/RF HAL config */ 178 /* extern s32 PHY_MACConfig8723(PADAPTER padapter); 179 * s32 PHY_BBConfig8723(PADAPTER padapter); 180 * s32 PHY_RFConfig8723(PADAPTER padapter); */ 181 182 183 184 /* ****************************************************************** 185 * Note: If SIC_ENABLE under PCIE, because of the slow operation 186 * you should 187 * 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows 188 * 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed. 189 * */ 190 #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1) 191 #define SIC_ENABLE 1 192 #define SIC_HW_SUPPORT 1 193 #else 194 #define SIC_ENABLE 0 195 #define SIC_HW_SUPPORT 0 196 #endif 197 /* ****************************************************************** */ 198 199 200 #define SIC_MAX_POLL_CNT 5 201 202 #if (SIC_HW_SUPPORT == 1) 203 #define SIC_CMD_READY 0 204 #define SIC_CMD_PREWRITE 0x1 205 #if (RTL8188E_SUPPORT == 1) 206 #define SIC_CMD_WRITE 0x40 207 #define SIC_CMD_PREREAD 0x2 208 #define SIC_CMD_READ 0x80 209 #define SIC_CMD_INIT 0xf0 210 #define SIC_INIT_VAL 0xff 211 212 #define SIC_INIT_REG 0x1b7 213 #define SIC_CMD_REG 0x1EB /* 1byte */ 214 #define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */ 215 #define SIC_DATA_REG 0x1EC /* 1b0~1b3 */ 216 #else 217 #define SIC_CMD_WRITE 0x11 218 #define SIC_CMD_PREREAD 0x2 219 #define SIC_CMD_READ 0x12 220 #define SIC_CMD_INIT 0x1f 221 #define SIC_INIT_VAL 0xff 222 223 #define SIC_INIT_REG 0x1b7 224 #define SIC_CMD_REG 0x1b6 /* 1byte */ 225 #define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */ 226 #define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */ 227 #endif 228 #else 229 #define SIC_CMD_READY 0 230 #define SIC_CMD_WRITE 1 231 #define SIC_CMD_READ 2 232 233 #if (RTL8188E_SUPPORT == 1) 234 #define SIC_CMD_REG 0x1EB /* 1byte */ 235 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ 236 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */ 237 #else 238 #define SIC_CMD_REG 0x1b8 /* 1byte */ 239 #define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */ 240 #define SIC_DATA_REG 0x1bc /* 1bc~1bf */ 241 #endif 242 #endif 243 244 #if (SIC_ENABLE == 1) 245 void SIC_Init( PADAPTER Adapter); 246 #endif 247 248 249 #endif /* __INC_HAL8192CPHYCFG_H */ 250