1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _SDIO_HALINIT_C_
16
17 #include <rtl8723d_hal.h>
18 #include "hal_com_h2c.h"
19
20 /*
21 * Description:
22 * Call power on sequence to enable card
23 *
24 * Return:
25 * _SUCCESS enable success
26 * _FAIL enable fail
27 */
CardEnable(PADAPTER padapter)28 static u8 CardEnable(PADAPTER padapter)
29 {
30 u8 val8 = 0;
31 u8 bMacPwrCtrlOn;
32 u8 ret = _FAIL;
33
34 bMacPwrCtrlOn = _FALSE;
35 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
36 if (bMacPwrCtrlOn == _FALSE) {
37 /* RSV_CTRL 0x1C[7:0] = 0x00 */
38 /* unlock ISO/CLK/Power control register */
39 val8 = rtw_read8(padapter, REG_WLLPS_CTRL + 3);
40
41 if (val8 & BIT(1))
42 RTW_INFO("%s: LP-LPS: %02x\n", __func__, val8);
43
44 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
45
46 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_card_enable_flow);
47 if (ret == _SUCCESS) {
48 u8 bMacPwrCtrlOn = _TRUE;
49
50 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
51 }
52 } else
53 ret = _SUCCESS;
54
55 return ret;
56 }
57
58 /* static */
_InitPowerOn_8723DS(PADAPTER padapter)59 u32 _InitPowerOn_8723DS(PADAPTER padapter)
60 {
61 u8 value8;
62 u16 value16;
63 u32 value32;
64 u8 ret;
65 u8 pwron_chk_cnt = 0;
66 /* u8 bMacPwrCtrlOn; */
67
68 _init_power_on:
69
70 #if 1
71 /* all of these MUST be configured before power on */
72 #ifdef CONFIG_XTAL_26M
73 /* Config PLL Reference CLK, */
74 /* Change crystal to 26M, APLL_FREF_SEL = 4b'0101 */
75 /* APLL_FREF_SEL[0]=1b'1 */
76 value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
77 value8 |= BIT(2);
78 rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
79 /* APLL_FREF_SEL[2:1]=2b'10 */
80 value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723D + 1);
81 value8 &= ~(BIT(1) | BIT(0));
82 value8 |= BIT(1);
83 rtw_write16(padapter, REG_AFE_CTRL_4_8723D + 1, value8);
84 /* APLL_FREF_SEL[3]=1b'0 */
85 value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723D);
86 value8 &= ~BIT(7);
87 rtw_write16(padapter, REG_AFE_CTRL_4_8723D, value8);
88 #endif /* CONFIG_XTAL_26M */
89
90 #ifdef CONFIG_EXT_CLK
91 /* Use external crystal(XTAL) */
92 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723D + 2);
93 value8 |= BIT(7);
94 rtw_write8(padapter, REG_PAD_CTRL1_8723D + 2, value8);
95
96 /* CLK_REQ High active or Low Active */
97 /* Request GPIO polarity: */
98 /* 0: low active */
99 /* 1: high active */
100 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
101 value8 |= BIT(5);
102 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
103 #endif /* CONFIG_EXT_CLK */
104 #endif /* all of these MUST be configured before power on */
105
106 /* only cmd52 can be used before power on(card enable) */
107 ret = CardEnable(padapter);
108 if (ret == _FALSE) {
109 return _FAIL;
110 }
111
112 /* Radio-Off Pin Trigger */
113 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
114 value8 |= BIT(1); /* Enable falling edge triggering interrupt */
115 rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
116 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
117 value8 |= BIT(1);
118 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
119
120 /* Enable power down and GPIO interrupt */
121 value16 = rtw_read16(padapter, REG_APS_FSMCO);
122 value16 |= EnPDN; /* Enable HW power down and RF on */
123 rtw_write16(padapter, REG_APS_FSMCO, value16);
124
125 /* Enable CMD53 R/W Operation
126 * bMacPwrCtrlOn = _TRUE;
127 * rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
128
129 rtw_write8(padapter, REG_CR, 0x00);
130 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
131 value16 = rtw_read16(padapter, REG_CR);
132 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
133 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
134 rtw_write16(padapter, REG_CR, value16);
135
136
137 /* PowerOnCheck() */
138 ret = sdio_power_on_check(padapter);
139 pwron_chk_cnt++;
140 if (_FAIL == ret) {
141 if (pwron_chk_cnt > 1) {
142 RTW_INFO("Failed to init Power On!\n");
143 return _FAIL;
144 }
145 RTW_INFO("Power on Fail! do it again\n");
146 goto _init_power_on;
147 } else {
148 /* MAC team suggest to keep ana clock at 12MHz 0x04[22] = 1 */
149 value8 = rtw_read8(padapter, REG_APS_FSMCO + 2);
150 value8 |= BIT(6);
151 rtw_write8(padapter, REG_APS_FSMCO + 2, value8);
152 }
153
154 value8 = rtw_read8(padapter, REG_SYS_CFG1_8723D + 1);
155 RTW_INFO("%s: %s\n", __func__,
156 (value8 & BIT3) ? "Test Mode" : "Normal Mode");
157
158 value8 = rtw_read8(padapter, REG_SYS_CFG1_8723D + 3);
159 RTW_INFO("%s: %s\n", __func__,
160 (value8 & BIT0) ? "LDO Mode" : "SPS Mode");
161
162 if(!(value8 & BIT0)){
163 /*MAC team suggest to set 0x38[6] = 1 in SPS Mode*/
164 value8 = rtw_read8(padapter, REG_PWR_DATA_8723D);
165 value8 |= BIT(6);
166 rtw_write8(padapter, REG_PWR_DATA_8723D, value8);
167 }
168
169 return _SUCCESS;
170 }
171
172
173
_InitQueueReservedPage(PADAPTER padapter)174 static void _InitQueueReservedPage(PADAPTER padapter)
175 {
176 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
177 struct registry_priv *pregistrypriv = &padapter->registrypriv;
178 u32 outEPNum = (u32)pHalData->OutEpNumber;
179 u32 numHQ = 0;
180 u32 numLQ = 0;
181 u32 numNQ = 0;
182 u32 numPubQ;
183 u32 value32;
184 u8 value8;
185 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
186
187 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
188 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723D : NORMAL_PAGE_NUM_HPQ_8723D;
189
190 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
191 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723D : NORMAL_PAGE_NUM_LPQ_8723D;
192
193 /* NOTE: This step shall be proceed before writing REG_RQPN. */
194 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
195 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723D : NORMAL_PAGE_NUM_NPQ_8723D;
196
197 numPubQ = TX_TOTAL_PAGE_NUMBER_8723D - numHQ - numLQ - numNQ;
198
199 value8 = (u8)_NPQ(numNQ);
200 rtw_write8(padapter, REG_RQPN_NPQ, value8);
201
202 /* TX DMA */
203 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
204 rtw_write32(padapter, REG_RQPN, value32);
205
206 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ, SDIO_TX_DIV_NUM);
207
208 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
209 rtw_hal_sdio_avail_page_threshold_init(padapter);
210 #endif
211 }
_InitTxBufferBoundary(PADAPTER padapter)212 static void _InitTxBufferBoundary(PADAPTER padapter)
213 {
214 struct registry_priv *pregistrypriv = &padapter->registrypriv;
215 #ifdef CONFIG_CONCURRENT_MODE
216 u8 val8;
217 #endif /* CONFIG_CONCURRENT_MODE */
218
219 /* u16 txdmactrl; */
220 u8 txpktbuf_bndy;
221
222 if (!pregistrypriv->wifi_spec)
223 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723D;
224 else {
225 /* for WMM */
226 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723D;
227 }
228
229 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723D, txpktbuf_bndy);
230 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723D, txpktbuf_bndy);
231 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D, txpktbuf_bndy);
232 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
233 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
234
235 #ifdef CONFIG_CONCURRENT_MODE
236 val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8723D + WOWLAN_PAGE_NUM_8723D;
237 rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
238 rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 1, val8); /* BCN1_HEAD */
239
240 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723D + 2);
241 val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
242 rtw_write8(padapter, REG_DWBCN1_CTRL_8723D + 2, val8);
243 #endif /* CONFIG_CONCURRENT_MODE */
244 }
245
246 static void
_InitNormalChipRegPriority(PADAPTER Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)247 _InitNormalChipRegPriority(
248 PADAPTER Adapter,
249 u16 beQ,
250 u16 bkQ,
251 u16 viQ,
252 u16 voQ,
253 u16 mgtQ,
254 u16 hiQ
255 )
256 {
257 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
258
259 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
260 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
261 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
262
263 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
264 }
265
266 static void
_InitNormalChipOneOutEpPriority(PADAPTER Adapter)267 _InitNormalChipOneOutEpPriority(
268 PADAPTER Adapter
269 )
270 {
271 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
272
273 u16 value = 0;
274
275 switch (pHalData->OutEpQueueSel) {
276 case TX_SELE_HQ:
277 value = QUEUE_HIGH;
278 break;
279 case TX_SELE_LQ:
280 value = QUEUE_LOW;
281 break;
282 case TX_SELE_NQ:
283 value = QUEUE_NORMAL;
284 break;
285 default:
286 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
287 break;
288 }
289
290 _InitNormalChipRegPriority(Adapter,
291 value,
292 value,
293 value,
294 value,
295 value,
296 value
297 );
298
299 }
300
301 static void
_InitNormalChipTwoOutEpPriority(PADAPTER Adapter)302 _InitNormalChipTwoOutEpPriority(
303 PADAPTER Adapter
304 )
305 {
306 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
307 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
308 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
309
310
311 u16 valueHi = 0;
312 u16 valueLow = 0;
313
314 switch (pHalData->OutEpQueueSel) {
315 case (TX_SELE_HQ | TX_SELE_LQ):
316 valueHi = QUEUE_HIGH;
317 valueLow = QUEUE_LOW;
318 break;
319 case (TX_SELE_NQ | TX_SELE_LQ):
320 valueHi = QUEUE_NORMAL;
321 valueLow = QUEUE_LOW;
322 break;
323 case (TX_SELE_HQ | TX_SELE_NQ):
324 valueHi = QUEUE_HIGH;
325 valueLow = QUEUE_NORMAL;
326 break;
327 default:
328 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
329 break;
330 }
331
332 if (!pregistrypriv->wifi_spec) {
333 beQ = valueLow;
334 bkQ = valueLow;
335 viQ = valueHi;
336 voQ = valueHi;
337 mgtQ = valueHi;
338 hiQ = valueHi;
339 } else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
340 beQ = valueLow;
341 bkQ = valueHi;
342 viQ = valueHi;
343 voQ = valueLow;
344 mgtQ = valueHi;
345 hiQ = valueHi;
346 }
347
348 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
349
350 }
351
352 static void
_InitNormalChipThreeOutEpPriority(PADAPTER padapter)353 _InitNormalChipThreeOutEpPriority(
354 PADAPTER padapter
355 )
356 {
357 struct registry_priv *pregistrypriv = &padapter->registrypriv;
358 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
359
360 if (!pregistrypriv->wifi_spec) { /* typical setting */
361 beQ = QUEUE_LOW;
362 bkQ = QUEUE_LOW;
363 viQ = QUEUE_NORMAL;
364 voQ = QUEUE_HIGH;
365 mgtQ = QUEUE_HIGH;
366 hiQ = QUEUE_HIGH;
367 } else { /* for WMM */
368 beQ = QUEUE_LOW;
369 bkQ = QUEUE_NORMAL;
370 viQ = QUEUE_NORMAL;
371 voQ = QUEUE_HIGH;
372 mgtQ = QUEUE_HIGH;
373 hiQ = QUEUE_HIGH;
374 }
375 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
376 }
377
378 static void
_InitNormalChipQueuePriority(PADAPTER Adapter)379 _InitNormalChipQueuePriority(
380 PADAPTER Adapter
381 )
382 {
383 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
384
385 switch (pHalData->OutEpNumber) {
386 case 1:
387 _InitNormalChipOneOutEpPriority(Adapter);
388 break;
389 case 2:
390 _InitNormalChipTwoOutEpPriority(Adapter);
391 break;
392 case 3:
393 _InitNormalChipThreeOutEpPriority(Adapter);
394 break;
395 default:
396 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
397 break;
398 }
399
400
401 }
402
_InitQueuePriority(PADAPTER padapter)403 static void _InitQueuePriority(PADAPTER padapter)
404 {
405 _InitNormalChipQueuePriority(padapter);
406 }
407
_InitPageBoundary(PADAPTER padapter)408 static void _InitPageBoundary(PADAPTER padapter)
409 {
410 /* RX Page Boundary */
411 u16 rxff_bndy = RX_DMA_BOUNDARY_8723D;
412
413 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
414 }
415
_InitTransferPageSize(PADAPTER padapter)416 static void _InitTransferPageSize(PADAPTER padapter)
417 {
418 /* Tx page size is always 128. */
419
420 u8 value8;
421
422 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
423 rtw_write8(padapter, REG_PBP, value8);
424 }
425
_InitDriverInfoSize(PADAPTER padapter,u8 drvInfoSize)426 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
427 {
428 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
429 }
430
_InitNetworkType(PADAPTER padapter)431 void _InitNetworkType(PADAPTER padapter)
432 {
433 u32 value32;
434
435 value32 = rtw_read32(padapter, REG_CR);
436
437 /* TODO: use the other function to set network type
438 * value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
439 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
440
441 rtw_write32(padapter, REG_CR, value32);
442 }
443
_InitWMACSetting(PADAPTER padapter)444 void _InitWMACSetting(PADAPTER padapter)
445 {
446 PHAL_DATA_TYPE pHalData;
447 u16 value16;
448 u32 rcr;
449
450 pHalData = GET_HAL_DATA(padapter);
451
452 rcr = 0
453 | RCR_APM | RCR_AM | RCR_AB
454 | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF
455 | RCR_HTC_LOC_CTRL
456 | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC
457 | RCR_APPFCS
458 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
459 | RCR_AAP
460 | RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF
461 #endif
462 ;
463 rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&rcr);
464
465 /* Accept all multicast address */
466 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
467 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
468
469 /* Accept all data frames */
470 value16 = 0xFFFF;
471 rtw_write16(padapter, REG_RXFLTMAP2, value16);
472
473 /* 2010.09.08 hpfan */
474 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
475 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
476 value16 = 0x400;
477 rtw_write16(padapter, REG_RXFLTMAP1, value16);
478
479 /* Accept all management frames */
480 value16 = 0xFFFF;
481 rtw_write16(padapter, REG_RXFLTMAP0, value16);
482 }
483
_InitAdaptiveCtrl(PADAPTER padapter)484 void _InitAdaptiveCtrl(PADAPTER padapter)
485 {
486 u16 value16;
487 u32 value32;
488
489 /* Response Rate Set */
490 value32 = rtw_read32(padapter, REG_RRSR);
491 value32 &= ~RATE_BITMAP_ALL;
492 value32 |= RATE_RRSR_CCK_ONLY_1M;
493
494 rtw_phydm_set_rrsr(padapter, value32, TRUE);
495
496
497 /* CF-END Threshold */
498 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
499
500 /* SIFS (used in NAV) */
501 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
502 rtw_write16(padapter, REG_SPEC_SIFS, value16);
503
504 /* Retry Limit */
505 value16 = BIT_LRL(RL_VAL_STA) | BIT_SRL(RL_VAL_STA);
506 rtw_write16(padapter, REG_RETRY_LIMIT, value16);
507 }
508
_InitEDCA(PADAPTER padapter)509 void _InitEDCA(PADAPTER padapter)
510 {
511 /* Set Spec SIFS (used in NAV) */
512 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
513 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
514
515 /* Set SIFS for CCK */
516 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
517
518 /* Set SIFS for OFDM */
519 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
520
521 /* TXOP */
522 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
523 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
524 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
525 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
526 }
527
_InitRetryFunction(PADAPTER padapter)528 void _InitRetryFunction(PADAPTER padapter)
529 {
530 u8 value8;
531
532 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
533 value8 |= EN_AMPDU_RTY_NEW;
534 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
535
536 /* Set ACK timeout */
537 rtw_write8(padapter, REG_ACKTO, 0x40);
538 }
539
HalRxAggr8723DSdio(PADAPTER padapter)540 static void HalRxAggr8723DSdio(PADAPTER padapter)
541 {
542 u8 dma_time_th;
543 u8 dma_len_th;
544
545 if (padapter->registrypriv.wifi_spec) {
546 dma_time_th = 0x01;
547 dma_len_th = 0x0f;
548 } else {
549 dma_time_th = 0x03;
550 dma_len_th = 0x0a;
551 }
552
553 if (dma_len_th * 1024 > MAX_RECVBUF_SZ) {
554 RTW_PRINT("Reduce RXDMA_AGG_LEN_TH from %u to %u\n"
555 , dma_len_th, MAX_RECVBUF_SZ / 1024);
556 dma_len_th = MAX_RECVBUF_SZ / 1024;
557 }
558
559 rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, (dma_time_th << 8) | dma_len_th);
560
561 }
562
sdio_AggSettingRxUpdate(PADAPTER padapter)563 void sdio_AggSettingRxUpdate(PADAPTER padapter)
564 {
565 HAL_DATA_TYPE *pHalData;
566 u8 val8;
567 u8 valueDMA;
568 u8 valueRxAggCtrl = 0;
569 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
570 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
571
572 pHalData = GET_HAL_DATA(padapter);
573
574 val8 = rtw_read8(padapter, REG_RXDMA_AGG_PG_TH + 3);
575 val8 = val8 | BIT(7) | BIT(5);
576 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 3, val8);
577
578 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
579 valueDMA |= RXDMA_AGG_EN;
580 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
581
582 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
583 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
584 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
585 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723D, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
586 }
587
_initSdioAggregationSetting(PADAPTER padapter)588 void _initSdioAggregationSetting(PADAPTER padapter)
589 {
590 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
591
592 /* Tx aggregation setting
593 * sdio_AggSettingTxUpdate(padapter); */
594
595 /* Rx aggregation setting */
596 HalRxAggr8723DSdio(padapter);
597
598 sdio_AggSettingRxUpdate(padapter);
599 }
600 #if 0
601 static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
602 {
603 PHAL_DATA_TYPE pHalData;
604 u8 valueDMA;
605 u8 valueRxAggCtrl;
606
607
608 pHalData = GET_HAL_DATA(padapter);
609
610 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
611 valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8723D);
612
613 if (_TRUE == enable) {
614 valueDMA |= RXDMA_AGG_EN;
615 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
616 } else {
617 valueDMA &= ~RXDMA_AGG_EN;
618 valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
619 }
620
621 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
622 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723D, valueRxAggCtrl);
623 }
624 #endif
625
_InitInterrupt(PADAPTER padapter)626 void _InitInterrupt(PADAPTER padapter)
627 {
628 /* HISR - turn all off */
629 rtw_write32(padapter, REG_HISR, 0);
630
631 /* HIMR - turn all off */
632 rtw_write32(padapter, REG_HIMR, 0);
633
634 /* */
635 /* Initialize and enable SDIO Host Interrupt. */
636 /* */
637 InitInterrupt8723DSdio(padapter);
638
639 /* */
640 /* Initialize system Host Interrupt. */
641 /* */
642 InitSysInterrupt8723DSdio(padapter);
643 }
644
_InitRDGSetting(PADAPTER padapter)645 void _InitRDGSetting(PADAPTER padapter)
646 {
647 rtw_write8(padapter, REG_RD_CTRL, 0xFF);
648 rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
649 rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
650 }
651
_InitRFType(PADAPTER padapter)652 static void _InitRFType(PADAPTER padapter)
653 {
654 struct registry_priv *pregpriv = &padapter->registrypriv;
655 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
656
657 #if DISABLE_BB_RF
658 pHalData->rf_chip = RF_PSEUDO_11N;
659 return;
660 #endif
661 pHalData->rf_chip = RF_6052;
662
663 RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
664 }
665
666 /* Set CCK and OFDM Block "ON" */
_BBTurnOnBlock(PADAPTER padapter)667 static void _BBTurnOnBlock(PADAPTER padapter)
668 {
669 #if (DISABLE_BB_RF)
670 return;
671 #endif
672
673 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
674 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
675 }
676
_InitBBRegBackup_8723DS(PADAPTER Adapter)677 void _InitBBRegBackup_8723DS(PADAPTER Adapter)
678 {
679 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
680 u8 i;
681
682 /* For Channel 1~11 (Default Value)*/
683 pHalData->RegForRecover[0].offset = rCCK0_TxFilter2;
684 pHalData->RegForRecover[0].value =
685 phy_query_bb_reg(Adapter,
686 pHalData->RegForRecover[0].offset, bMaskDWord);
687
688 pHalData->RegForRecover[1].offset = rCCK0_DebugPort;
689 pHalData->RegForRecover[1].value =
690 phy_query_bb_reg(Adapter,
691 pHalData->RegForRecover[1].offset, bMaskDWord);
692
693 pHalData->RegForRecover[2].offset = 0xAAC;
694 pHalData->RegForRecover[2].value =
695 phy_query_bb_reg(Adapter,
696 pHalData->RegForRecover[2].offset, bMaskDWord);
697 #if 0
698 /* For 20 MHz (Default Value)*/
699 pHalData->RegForRecover[2].offset = rBBrx_DFIR;
700 pHalData->RegForRecover[2].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord);
701
702 pHalData->RegForRecover[3].offset = rOFDM0_XATxAFE;
703 pHalData->RegForRecover[3].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord);
704
705 pHalData->RegForRecover[4].offset = 0x1E;
706 pHalData->RegForRecover[4].value = phy_query_rf_reg(Adapter, RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask);
707 #endif
708 }
709
710 /*
711 * 2010/08/09 MH Add for power down check.
712 * */
HalDetectPwrDownMode(PADAPTER Adapter)713 static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
714 {
715 u8 tmpvalue;
716 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
717 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
718
719
720 EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8723D, (u32 *)&tmpvalue);
721
722 /* 2010/08/25 MH INF priority > PDN Efuse value. */
723 if (tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode)
724 pHalData->pwrdown = _TRUE;
725 else
726 pHalData->pwrdown = _FALSE;
727
728 RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
729
730 return pHalData->pwrdown;
731 } /* HalDetectPwrDownMode */
732
rtl8723ds_init_burst_pkt_len(PADAPTER padapter)733 static void rtl8723ds_init_burst_pkt_len(PADAPTER padapter)
734 {
735 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
736
737 rtw_write8(padapter, 0x4c7, rtw_read8(padapter, 0x4c7) | BIT(7)); /* enable single pkt ampdu */
738 rtw_write8(padapter, REG_RX_PKT_LIMIT_8723D, 0x18); /* for VHT packet length 11K */
739 rtw_write8(padapter, REG_MAX_AGGR_NUM_8723D, 0x1F);
740 rtw_write8(padapter, REG_PIFS_8723D, 0x00);
741 rtw_write8(padapter, REG_FWHW_TXQ_CTRL_8723D, rtw_read8(padapter, REG_FWHW_TXQ_CTRL) & (~BIT(7)));
742 if (pHalData->AMPDUBurstMode)
743 rtw_write8(padapter, REG_AMPDU_BURST_MODE_8723D, 0x5F);
744 rtw_write8(padapter, REG_AMPDU_MAX_TIME_8723D, 0x70);
745
746 /* ARFB table 9 for 11ac 5G 2SS */
747 rtw_write32(padapter, REG_ARFR0_8723D, 0x00000010);
748 if (IS_NORMAL_CHIP(pHalData->version_id))
749 rtw_write32(padapter, REG_ARFR0_8723D + 4, 0xfffff000);
750 else
751 rtw_write32(padapter, REG_ARFR0_8723D + 4, 0x3e0ff000);
752
753 /* ARFB table 10 for 11ac 5G 1SS */
754 rtw_write32(padapter, REG_ARFR1_8723D, 0x00000010);
755 rtw_write32(padapter, REG_ARFR1_8723D + 4, 0x003ff000);
756 }
757
758 #if 0
759 static void rtl8723ds_init_lte_coex(PADAPTER padapter)
760 {
761 /* LTE COEX setting */
762 rtw_write16(padapter, REG_LTECOEX_WRITE_DATA, 0x7700);
763 rtw_write32(padapter, REG_LTECOEX_CTRL, 0xc0020038);
764 rtw_write8(padapter, 0x73, 0x04);
765 }
766 #endif
767
rtl8723ds_hal_init(PADAPTER padapter)768 static u32 rtl8723ds_hal_init(PADAPTER padapter)
769 {
770 s32 ret;
771 PHAL_DATA_TYPE pHalData;
772 struct pwrctrl_priv *pwrctrlpriv;
773 struct registry_priv *pregistrypriv;
774 struct sreset_priv *psrtpriv;
775 struct dvobj_priv *psdpriv = padapter->dvobj;
776 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
777 rt_rf_power_state eRfPowerStateToSet;
778 u32 NavUpper = WiFiNavUpperUs;
779 u8 u1bTmp;
780 u16 value16;
781 u8 typeid;
782 u32 u4Tmp;
783
784 pHalData = GET_HAL_DATA(padapter);
785 psrtpriv = &pHalData->srestpriv;
786 pwrctrlpriv = adapter_to_pwrctl(padapter);
787 pregistrypriv = &padapter->registrypriv;
788
789 #ifdef CONFIG_SWLPS_IN_IPS
790 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
791 u8 val8, bMacPwrCtrlOn = _TRUE;
792
793 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
794
795 /* ser rpwm */
796 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
797 val8 &= 0x80;
798 val8 += 0x80;
799 val8 |= BIT(6);
800 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
801
802 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
803
804 rtw_mdelay_os(5); /* wait set rpwm already */
805
806 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_leave_swlps_flow);
807 if (ret == _FALSE) {
808 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
809 return _FAIL;
810 }
811
812 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
813
814 pHalData->LastHMEBoxNum = 0;
815
816 #ifdef CONFIG_BT_COEXIST
817 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
818 #else
819 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
820 #endif /* CONFIG_BT_COEXIST */
821
822 return _SUCCESS;
823 }
824 #elif defined(CONFIG_FWLPS_IN_IPS)
825 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
826 && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
827 systime start_time;
828 u8 cpwm_orig, cpwm_now;
829 u8 val8, bMacPwrCtrlOn = _TRUE;
830
831 RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
832
833 /* for polling cpwm */
834 cpwm_orig = 0;
835 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
836
837 /* ser rpwm */
838 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
839 val8 &= 0x80;
840 val8 += 0x80;
841 val8 |= BIT(6);
842 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
843 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
844 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
845
846 /* do polling cpwm */
847 start_time = rtw_get_current_time();
848 do {
849
850 rtw_mdelay_os(1);
851
852 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
853 if ((cpwm_orig ^ cpwm_now) & 0x80) {
854 #ifdef DBG_CHECK_FW_PS_STATE
855 RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
856 , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
857 #endif /* DBG_CHECK_FW_PS_STATE */
858 break;
859 }
860
861 if (rtw_get_passing_time_ms(start_time) > 100) {
862 RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
863 break;
864 }
865 } while (1);
866
867 rtw_set_fw_in_ips_mode(padapter, 0);
868
869 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
870
871 #ifdef CONFIG_BT_COEXIST
872 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
873 #else
874 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
875 #endif /* CONFIG_BT_COEXIST */
876
877 #ifdef DBG_CHECK_FW_PS_STATE
878 if (rtw_fw_ps_state(padapter) == _FAIL) {
879 RTW_INFO("after hal init, fw ps state in 32k\n");
880 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
881 }
882 #endif /* DBG_CHECK_FW_PS_STATE */
883 return _SUCCESS;
884 }
885 #endif /* CONFIG_SWLPS_IN_IPS */
886
887 /* Disable Interrupt first.
888 * rtw_hal_disable_interrupt(padapter); */
889
890 if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
891 RTW_INFO("FW exist before power on!!\n");
892 else
893 RTW_INFO("FW does not exist before power on!!\n");
894 #ifdef DBG_CHECK_FW_PS_STATE
895 if (rtw_fw_ps_state(padapter) == _FAIL) {
896 RTW_INFO("check fw_ps_state fail before PowerOn!\n");
897 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
898 }
899 #endif
900 ret = rtw_hal_power_on(padapter);
901 if (_FAIL == ret) {
902 return _FAIL;
903 }
904 RTW_INFO("Power on ok!\n");
905 #ifdef DBG_CHECK_FW_PS_STATE
906 if (rtw_fw_ps_state(padapter) == _FAIL) {
907 RTW_INFO("check fw_ps_state fail after PowerOn!\n");
908 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
909 }
910 #endif
911
912 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
913
914 if (padapter->registrypriv.mp_mode == 0
915 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
916 || padapter->registrypriv.mp_customer_str
917 #endif
918 ) {
919 ret = rtl8723d_FirmwareDownload(padapter, _FALSE);
920 if (ret != _SUCCESS) {
921 pHalData->bFWReady = _FALSE;
922 pHalData->fw_ractrl = _FALSE;
923 return ret;
924 } /*else*/
925 {
926 pHalData->bFWReady = _TRUE;
927 pHalData->fw_ractrl = _TRUE;
928 }
929 }
930
931 /* SIC_Init(padapter); */
932
933 if (pwrctrlpriv->reg_rfoff == _TRUE)
934 pwrctrlpriv->rf_pwrstate = rf_off;
935
936 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
937 /* HW GPIO pin. Before PHY_RFConfig8192C. */
938 HalDetectPwrDownMode(padapter);
939
940 /* Set RF type for BB/RF configuration */
941 _InitRFType(padapter);
942
943 /* Save target channel */
944 /* <Roger_Notes> Current Channel will be updated again later. */
945 pHalData->current_channel = 6;
946
947 #if (HAL_MAC_ENABLE == 1)
948 ret = PHY_MACConfig8723D(padapter);
949 if (ret != _SUCCESS) {
950 return ret;
951 }
952 #endif
953 /* */
954 /* d. Initialize BB related configurations. */
955 /* */
956 #if (HAL_BB_ENABLE == 1)
957 ret = PHY_BBConfig8723D(padapter);
958 if (ret != _SUCCESS) {
959 return ret;
960 }
961
962 #endif
963
964 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
965 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
966 /* if(pHalData->eRFPowerState == eRfOn) */
967 {
968 #if (HAL_RF_ENABLE == 1)
969 ret = PHY_RFConfig8723D(padapter);
970 if (ret != _SUCCESS) {
971 return ret;
972 }
973 #endif
974 }
975
976 _InitBBRegBackup_8723DS(padapter);
977
978 _InitMacAPLLSetting_8723D(padapter);
979
980 /* */
981 /* Joseph Note: Keep RfRegChnlVal for later use. */
982 /* */
983 pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
984 pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask);
985
986 #ifdef CONFIG_DLFW_TXPKT
987 /* Specially add for FWDL by Tx pkt write.
988 Reset Tx/Rx DMA since the Tx boundary setting
989 is changed during FW download */
990 rtw_write8(padapter, REG_CR, 0x00);
991 rtw_write8(padapter, REG_CR, 0xFF);
992 #endif
993
994 /* if (!pHalData->bMACFuncEnable) { */
995 _InitQueueReservedPage(padapter);
996 _InitTxBufferBoundary(padapter);
997 /* init LLT after tx buffer boundary is defined */
998 ret = rtl8723d_InitLLTTable(padapter);
999 if (_SUCCESS != ret) {
1000 RTW_INFO("%s: Failed to init LLT Table!\n", __func__);
1001 return _FAIL;
1002 }
1003 /* } */
1004 _InitQueuePriority(padapter);
1005 _InitPageBoundary(padapter);
1006 _InitTransferPageSize(padapter);
1007
1008 /* Get Rx PHY status in order to report RSSI and others. */
1009 _InitDriverInfoSize(padapter, DRVINFO_SZ);
1010 _InitNetworkType(padapter);
1011 _InitWMACSetting(padapter);
1012 _InitAdaptiveCtrl(padapter);
1013 _InitEDCA(padapter);
1014 _InitRetryFunction(padapter);
1015 _initSdioAggregationSetting(padapter);
1016 rtl8723d_InitBeaconParameters(padapter);
1017 rtl8723d_InitBeaconMaxError(padapter, _TRUE);
1018 _InitInterrupt(padapter);
1019 rtl8723ds_init_burst_pkt_len(padapter);
1020
1021 #if 0
1022 /* 8723D new ADD */
1023 rtl8723ds_init_lte_coex(padapter);
1024 #endif
1025
1026 /* YJ,TODO */
1027 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723D, 0x3); /* CCA */
1028 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
1029
1030 _BBTurnOnBlock(padapter);
1031
1032 invalidate_cam_all(padapter);
1033
1034 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
1035 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
1036
1037 rtl8723d_InitAntenna_Selection(padapter);
1038
1039 /* */
1040 /* Disable BAR, suggested by Scott */
1041 /* 2010.04.09 add by hpfan */
1042 /* */
1043 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1044
1045 /* HW SEQ CTRL */
1046 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1047 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1048
1049
1050 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1051 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
1052 u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1053 rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
1054
1055 rtw_write8(padapter, REG_RD_CTRL, 0x0F);
1056 rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
1057 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
1058 rtw_write32(padapter, REG_CR, 0x0b0202ff);
1059 #endif
1060
1061 /* */
1062 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
1063 /* 2010.02.24. */
1064 /* */
1065 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
1066
1067 rtl8723d_InitHalDm(padapter);
1068
1069 /* dbg_print("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
1070
1071 #if 0
1072 if (pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) /* The lowest Beacon Type that HW can support */
1073 *pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE;
1074 #endif
1075
1076 /* */
1077 /* Update current Tx FIFO page status. */
1078 /* */
1079 HalQueryTxBufferStatus8723DSdio(padapter);
1080 HalQueryTxOQTBufferStatus8723DSdio(padapter);
1081 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
1082
1083 /* Enable MACTXEN/MACRXEN block */
1084 u1bTmp = rtw_read8(padapter, REG_CR);
1085 u1bTmp |= (MACTXEN | MACRXEN);
1086 rtw_write8(padapter, REG_CR, u1bTmp);
1087
1088 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
1089
1090 #ifdef CONFIG_XMIT_ACK
1091 /* ack for xmit mgmt frames. */
1092 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
1093 #endif /* CONFIG_XMIT_ACK */
1094
1095 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
1096
1097 #if (MP_DRIVER == 1)
1098 if (padapter->registrypriv.mp_mode == 1) {
1099 padapter->mppriv.channel = pHalData->current_channel;
1100 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1101 } else
1102 #endif /* #if (MP_DRIVER == 1) */
1103 {
1104 pwrctrlpriv->rf_pwrstate = rf_on;
1105
1106 halrf_lck_trigger(&pHalData->odmpriv);
1107
1108 pHalData->neediqk_24g = _TRUE;
1109
1110 odm_txpowertracking_check(&pHalData->odmpriv);
1111 }
1112
1113 #ifdef CONFIG_BT_COEXIST
1114 /* Init BT hw config.*/
1115 if (padapter->registrypriv.mp_mode == 1)
1116 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1117 else
1118 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1119 #endif
1120
1121 if (padapter->registrypriv.wifi_spec == 1)
1122 phy_set_bb_reg(padapter, rOFDM0_ECCAThreshold,
1123 0x00ff00ff, 0x00250029);
1124
1125 return _SUCCESS;
1126 }
1127
CardDisableRTL8723DSdio(PADAPTER padapter)1128 static void CardDisableRTL8723DSdio(PADAPTER padapter)
1129 {
1130 u8 u1bTmp;
1131 u16 u2bTmp;
1132 u32 u4bTmp;
1133 u8 bMacPwrCtrlOn;
1134 u8 ret = _FAIL;
1135
1136 /* Run LPS WL RFOFF flow */
1137 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_enter_lps_flow);
1138 if (ret == _FAIL)
1139 RTW_INFO(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
1140
1141 /* ==== Reset digital sequence ====== */
1142
1143 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1144 if ((u1bTmp & RAM_DL_SEL) && GET_HAL_DATA(padapter)->bFWReady) /* 8051 RAM code */
1145 rtl8723d_FirmwareSelfReset(padapter);
1146
1147 /* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
1148 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
1149 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
1150 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
1151
1152 /* MCUFWDL 0x80[1:0]=0 */
1153 /* reset MCU ready status */
1154 rtw_write8(padapter, REG_MCUFWDL, 0);
1155
1156 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1157 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1158 u1bTmp &= ~BIT(0);
1159 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1160 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1161 u1bTmp |= BIT(0);
1162 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1163
1164 /* ==== Reset digital sequence end ====== */
1165
1166 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1167 ret = _FALSE;
1168 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1169 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_card_disable_flow);
1170 if (ret == _FALSE)
1171 RTW_INFO(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
1172
1173 GET_HAL_DATA(padapter)->bFWReady = _FALSE;
1174 }
1175
rtl8723ds_hal_deinit(PADAPTER padapter)1176 static u32 rtl8723ds_hal_deinit(PADAPTER padapter)
1177 {
1178 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1179 struct sreset_priv *psrtpriv = &pHalData->srestpriv;
1180 struct dvobj_priv *psdpriv = padapter->dvobj;
1181 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1182
1183 #ifdef CONFIG_MP_INCLUDED
1184 if (padapter->registrypriv.mp_mode == 1)
1185 MPT_DeInitAdapter(padapter);
1186 #endif
1187
1188 if (rtw_is_hw_init_completed(padapter)) {
1189 #ifdef CONFIG_SWLPS_IN_IPS
1190 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
1191 u8 bMacPwrCtrlOn;
1192 u8 ret = _TRUE;
1193
1194 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
1195
1196 rtw_write32(padapter, 0x130, 0x0);
1197 rtw_write32(padapter, 0x138, 0x100);
1198 rtw_write8(padapter, 0x13d, 0x1);
1199
1200
1201 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1202 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1203
1204 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723D_enter_swlps_flow);
1205 if (ret == _FALSE) {
1206 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1207 return _FAIL;
1208 }
1209 } else
1210 #elif defined(CONFIG_FWLPS_IN_IPS)
1211 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
1212 if (padapter->netif_up == _TRUE) {
1213 int cnt = 0;
1214 u8 val8 = 0;
1215
1216 RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
1217
1218 rtw_set_fw_in_ips_mode(padapter, 0x1);
1219 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
1220 do {
1221 val8 = rtw_read8(padapter, REG_HMETFR);
1222 cnt++;
1223 RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1224 rtw_mdelay_os(10);
1225 } while (cnt < 100 && (val8 != 0));
1226 /* H2C done, enter 32k */
1227 if (val8 == 0) {
1228 /* ser rpwm to enter 32k */
1229 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1230 val8 += 0x80;
1231 val8 |= BIT(0);
1232 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1233 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1234 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1235 cnt = val8 = 0;
1236 do {
1237 val8 = rtw_read8(padapter, REG_CR);
1238 cnt++;
1239 RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1240 rtw_mdelay_os(10);
1241 } while (cnt < 100 && (val8 != 0xEA));
1242 #ifdef DBG_CHECK_FW_PS_STATE
1243 if (val8 != 0xEA)
1244 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1245 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1246 #endif /* DBG_CHECK_FW_PS_STATE */
1247 } else {
1248 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1249 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1250 }
1251
1252 RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
1253 , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
1254
1255 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1256
1257 } else {
1258 pdbgpriv->dbg_carddisable_cnt++;
1259 #ifdef DBG_CHECK_FW_PS_STATE
1260 if (rtw_fw_ps_state(padapter) == _FAIL) {
1261 RTW_INFO("card disable should leave 32k\n");
1262 pdbgpriv->dbg_carddisable_error_cnt++;
1263 }
1264 #endif /* DBG_CHECK_FW_PS_STATE */
1265 rtw_hal_power_off(padapter);
1266
1267 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1268 }
1269
1270 } else
1271 #endif /* CONFIG_SWLPS_IN_IPS */
1272 {
1273 pdbgpriv->dbg_carddisable_cnt++;
1274 #ifdef DBG_CHECK_FW_PS_STATE
1275 if (rtw_fw_ps_state(padapter) == _FAIL) {
1276 RTW_INFO("card disable should leave 32k\n");
1277 pdbgpriv->dbg_carddisable_error_cnt++;
1278 }
1279 #endif /* DBG_CHECK_FW_PS_STATE */
1280 rtw_hal_power_off(padapter);
1281 }
1282 } else
1283 pdbgpriv->dbg_deinit_fail_cnt++;
1284
1285 return _SUCCESS;
1286 }
rtl8723ds_init_default_value(PADAPTER padapter)1287 static void rtl8723ds_init_default_value(PADAPTER padapter)
1288 {
1289 PHAL_DATA_TYPE pHalData;
1290
1291
1292 pHalData = GET_HAL_DATA(padapter);
1293
1294 rtl8723d_init_default_value(padapter);
1295
1296 /* interface related variable */
1297 pHalData->SdioRxFIFOCnt = 0;
1298 }
1299
rtl8723ds_interface_configure(PADAPTER padapter)1300 static void rtl8723ds_interface_configure(PADAPTER padapter)
1301 {
1302 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1303 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1304 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1305 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
1306
1307
1308 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1309 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1310 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1311
1312 if (bWiFiConfig)
1313 pHalData->OutEpNumber = 2;
1314 else
1315 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1316
1317 switch (pHalData->OutEpNumber) {
1318 case 3:
1319 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1320 break;
1321 case 2:
1322 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1323 break;
1324 case 1:
1325 pHalData->OutEpQueueSel = TX_SELE_HQ;
1326 break;
1327 default:
1328 break;
1329 }
1330
1331 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1332 }
1333
1334 /*
1335 * Description:
1336 * We should set Efuse cell selection to WiFi cell in default.
1337 *
1338 * Assumption:
1339 * PASSIVE_LEVEL
1340 *
1341 * Added by Roger, 2010.11.23.
1342 * */
1343 static void
_EfuseCellSel(PADAPTER padapter)1344 _EfuseCellSel(
1345 PADAPTER padapter
1346 )
1347 {
1348 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1349
1350 u32 value32;
1351
1352 /* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
1353 {
1354 value32 = rtw_read32(padapter, EFUSE_TEST);
1355 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1356 rtw_write32(padapter, EFUSE_TEST, value32);
1357 }
1358 }
1359
1360 static void
_ReadRFType(PADAPTER Adapter)1361 _ReadRFType(
1362 PADAPTER Adapter
1363 )
1364 {
1365 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1366
1367 #if DISABLE_BB_RF
1368 pHalData->rf_chip = RF_PSEUDO_11N;
1369 #else
1370 pHalData->rf_chip = RF_6052;
1371 #endif
1372 }
1373
1374 static u8
_ReadEfuseInfo8723DS(PADAPTER padapter)1375 _ReadEfuseInfo8723DS(
1376 PADAPTER padapter
1377 )
1378 {
1379 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1380 u8 *hwinfo = NULL;
1381 u8 ret = _FAIL;
1382
1383 /* */
1384 /* This part read and parse the eeprom/efuse content */
1385 /* */
1386
1387 if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8723D)
1388 RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723D!\n");
1389
1390 hwinfo = pHalData->efuse_eeprom_data;
1391
1392 Hal_InitPGData(padapter, hwinfo);
1393
1394 Hal_EfuseParseIDCode(padapter, hwinfo);
1395 Hal_EfuseParseEEPROMVer_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1396 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1397 Hal_EfuseParseTxPowerInfo_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1398 Hal_EfuseParseBoardType_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1399
1400 /* */
1401 /* Read Bluetooth co-exist and initialize */
1402 /* */
1403 Hal_EfuseParseBTCoexistInfo_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1404 Hal_EfuseParseChnlPlan_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1405 Hal_EfuseParseXtal_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1406 Hal_EfuseParseThermalMeter_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1407 Hal_EfuseParseAntennaDiversity_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1408 Hal_EfuseParseCustomerID_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1409
1410 Hal_EfuseParseVoltage_8723D(padapter, hwinfo, pHalData->bautoload_fail_flag);
1411
1412 #ifdef CONFIG_WOWLAN
1413 Hal_DetectWoWMode(padapter);
1414 #endif
1415
1416 #ifdef CONFIG_RF_POWER_TRIM
1417 Hal_ReadRFGainOffset(padapter, hwinfo, pHalData->bautoload_fail_flag);
1418 #endif /* CONFIG_RF_GAIN_OFFSET */
1419
1420 /* set coex. ant info once efuse parsing is done */
1421 rtw_btcoex_set_ant_info(padapter);
1422
1423 if (hal_read_mac_hidden_rpt(padapter) != _SUCCESS)
1424 goto exit;
1425
1426 ret = _SUCCESS;
1427
1428 exit:
1429 return ret;
1430 }
1431
_ReadPROMContent(PADAPTER padapter)1432 static u8 _ReadPROMContent(
1433 PADAPTER padapter
1434 )
1435 {
1436 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1437 u8 eeValue;
1438 u8 ret = _FAIL;
1439
1440 eeValue = rtw_read8(padapter, REG_9346CR);
1441 /* To check system boot selection. */
1442 pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
1443 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1444
1445
1446 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1447
1448 if (_ReadEfuseInfo8723DS(padapter) != _SUCCESS)
1449 goto exit;
1450
1451 ret = _SUCCESS;
1452
1453 exit:
1454 return ret;
1455 }
1456
1457 static void
_InitOtherVariable(PADAPTER Adapter)1458 _InitOtherVariable(
1459 PADAPTER Adapter
1460 )
1461 {
1462 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1463
1464
1465 /* if(Adapter->bInHctTest){ */
1466 /* pMgntInfo->PowerSaveControl.bInactivePs = FALSE; */
1467 /* pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; */
1468 /* pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; */
1469 /* pMgntInfo->keepAliveLevel = 0; */
1470 /* } */
1471
1472
1473
1474 }
1475
1476 /*
1477 * Description:
1478 * Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
1479 *
1480 * Assumption:
1481 * PASSIVE_LEVEL (SDIO interface)
1482 *
1483 * */
ReadAdapterInfo8723DS(PADAPTER padapter)1484 static u8 ReadAdapterInfo8723DS(PADAPTER padapter)
1485 {
1486 u8 val8;
1487 u8 ret = _FAIL;
1488
1489 val8 = rtw_read8(padapter, 0x4e);
1490 RTW_INFO("%s, 0x4e=0x%x\n", __func__, val8);
1491 val8 |= BIT(6);
1492 rtw_write8(padapter, 0x4e, val8);
1493
1494 /* Read EEPROM size before call any EEPROM function */
1495 padapter->EepromAddressSize = GetEEPROMSize8723D(padapter);
1496
1497 _EfuseCellSel(padapter);
1498 _ReadRFType(padapter);
1499 if (_ReadPROMContent(padapter) != _SUCCESS)
1500 goto exit;
1501
1502 _InitOtherVariable(padapter);
1503
1504 #ifdef CONFIG_PLATFORM_INTEL_BYT
1505 { /* for BT, let BT can control ANT when wifi disable */
1506 u32 val32;
1507
1508 RTW_INFO("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
1509 val32 = rtw_read32(padapter, 0x64);
1510 RTW_INFO("%s, 0x64=0x%x\n", __func__, val32);
1511 val32 |= BIT(13);
1512 rtw_write32(padapter, 0x64, val32);
1513 RTW_INFO("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
1514 }
1515 #endif /* CONFIG_PLATFORM_INTEL_BYT */
1516
1517 ret = _SUCCESS;
1518
1519 exit:
1520 return ret;
1521 }
1522
1523 /*
1524 * If variable not handled here,
1525 * some variables will be processed in SetHwReg8723D()
1526 */
SetHwReg8723DS(PADAPTER padapter,u8 variable,u8 * val)1527 u8 SetHwReg8723DS(PADAPTER padapter, u8 variable, u8 *val)
1528 {
1529 PHAL_DATA_TYPE pHalData;
1530 u8 ret = _SUCCESS;
1531 u8 val8;
1532
1533
1534 pHalData = GET_HAL_DATA(padapter);
1535
1536 switch (variable) {
1537 case HW_VAR_SET_RPWM:
1538 /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
1539 /* BIT0 value - 1: 32k, 0:40MHz. */
1540 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1541 /* BIT7 value - Toggle bit change. */
1542 {
1543 val8 = *val;
1544 val8 &= 0xC1;
1545 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1546 }
1547 break;
1548 case HW_VAR_SET_REQ_FW_PS:
1549 /* 1. driver write 0x8f[4]=1 //request fw ps state (only can write bit4) */
1550 {
1551 u8 req_fw_ps = 0;
1552
1553 req_fw_ps = rtw_read8(padapter, 0x8f);
1554 req_fw_ps |= 0x10;
1555 rtw_write8(padapter, 0x8f, req_fw_ps);
1556 }
1557 break;
1558 case HW_VAR_RXDMA_AGG_PG_TH:
1559 #if 0
1560 val8 = *val;
1561
1562 /* TH=1 => invalidate RX DMA aggregation */
1563 /* TH=0 => validate RX DMA aggregation, use init value. */
1564 if (val8 == 0) {
1565 /* enable RXDMA aggregation */
1566 /* _RXAggrSwitch(padapter, _TRUE); */
1567 } else {
1568 /* disable RXDMA aggregation */
1569 /* _RXAggrSwitch(padapter, _FALSE); */
1570 }
1571 #endif
1572 break;
1573 #ifdef CONFIG_GPIO_WAKEUP
1574 case HW_SET_GPIO_WL_CTRL: {
1575 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
1576 u8 enable = *val;
1577 u8 value = 0;
1578
1579 if (pwrpriv->wowlan_gpio_index != 6)
1580 break;
1581
1582 value = rtw_read8(padapter, REG_GPIO_MUXCFG);
1583
1584 if (enable && (value & BIT(3))) {
1585 value &= ~BIT(3);
1586 rtw_write8(padapter, REG_GPIO_MUXCFG, value);
1587 } else if (enable == _FALSE) {
1588 RTW_INFO("%s: keep WLAN ctrl\n", __func__);
1589 }
1590 /*0x66 bit4*/
1591 value = rtw_read8(padapter, REG_PAD_CTRL_1 + 2);
1592 if (enable && (value & BIT(4))) {
1593 value &= ~BIT(4);
1594 rtw_write8(padapter, REG_PAD_CTRL_1 + 2, value);
1595 } else if (enable == _FALSE) {
1596 value |= BIT(4);
1597 rtw_write8(padapter, REG_PAD_CTRL_1 + 2, value);
1598 }
1599
1600 /*0x66 bit8*/
1601 value = rtw_read8(padapter, REG_PAD_CTRL_1 + 3);
1602 if (enable && (value & BIT(0))) {
1603 value &= ~BIT(0);
1604 rtw_write8(padapter, REG_PAD_CTRL_1 + 3, value);
1605 } else if (enable == _FALSE) {
1606 value |= BIT(0);
1607 rtw_write8(padapter, REG_PAD_CTRL_1 + 3, value);
1608 }
1609 RTW_INFO("%s: HW_SET_GPIO_WL_CTRL\n", __func__);
1610 }
1611 break;
1612 #endif
1613 default:
1614 ret = SetHwReg8723D(padapter, variable, val);
1615 break;
1616 }
1617
1618 return ret;
1619 }
1620
1621 /*
1622 * If variable not handled here,
1623 * some variables will be processed in GetHwReg8723D()
1624 */
GetHwReg8723DS(PADAPTER padapter,u8 variable,u8 * val)1625 void GetHwReg8723DS(PADAPTER padapter, u8 variable, u8 *val)
1626 {
1627 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1628
1629
1630 switch (variable) {
1631 case HW_VAR_CPWM:
1632 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723D);
1633 break;
1634
1635 case HW_VAR_FW_PS_STATE: {
1636 /* 3. read dword 0x88 //driver read fw ps state */
1637 *((u16 *)val) = rtw_read16(padapter, 0x88);
1638 }
1639 break;
1640 default:
1641 GetHwReg8723D(padapter, variable, val);
1642 break;
1643 }
1644
1645 }
1646
1647 /*
1648 * Description:
1649 * Query setting of specified variable.
1650 * */
1651 u8
GetHalDefVar8723DSDIO(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)1652 GetHalDefVar8723DSDIO(
1653 PADAPTER Adapter,
1654 HAL_DEF_VARIABLE eVariable,
1655 void *pValue
1656 )
1657 {
1658 struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
1659 PSDIO_DATA psdio_data = NULL;
1660 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1661 u8 bResult = _SUCCESS;
1662
1663 switch (eVariable) {
1664 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1665 #ifdef CONFIG_ANTENNA_DIVERSITY
1666 *((u8 *)pValue) = _FALSE;
1667 #endif
1668 break;
1669
1670 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1671 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1672 /* coding by Lucas@20130730 */
1673 psdio_data = &dvobj->intf_data;
1674 if (psdio_data->clock > RTW_SDIO_CLK_40M)
1675 *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_32K;
1676 else
1677 *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
1678 break;
1679 default:
1680 bResult = GetHalDefVar8723D(Adapter, eVariable, pValue);
1681 break;
1682 }
1683
1684 return bResult;
1685 }
1686
1687 /*
1688 * Description:
1689 * Change default setting of specified variable.
1690 * */
1691 u8
SetHalDefVar8723DSDIO(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)1692 SetHalDefVar8723DSDIO(
1693 PADAPTER Adapter,
1694 HAL_DEF_VARIABLE eVariable,
1695 void *pValue
1696 )
1697 {
1698 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1699 u8 bResult = _SUCCESS;
1700
1701 switch (eVariable) {
1702 default:
1703 bResult = SetHalDefVar8723D(Adapter, eVariable, pValue);
1704 break;
1705 }
1706
1707 return bResult;
1708 }
1709
rtl8723ds_set_hal_ops(PADAPTER padapter)1710 void rtl8723ds_set_hal_ops(PADAPTER padapter)
1711 {
1712 struct hal_ops *pHalFunc = &padapter->hal_func;
1713
1714
1715 rtl8723d_set_hal_ops(pHalFunc);
1716
1717 pHalFunc->hal_power_on = &_InitPowerOn_8723DS;
1718 pHalFunc->hal_power_off = &CardDisableRTL8723DSdio;
1719
1720
1721 pHalFunc->hal_init = &rtl8723ds_hal_init;
1722 pHalFunc->hal_deinit = &rtl8723ds_hal_deinit;
1723
1724 pHalFunc->init_xmit_priv = &rtl8723ds_init_xmit_priv;
1725 pHalFunc->free_xmit_priv = &rtl8723ds_free_xmit_priv;
1726
1727 pHalFunc->init_recv_priv = &rtl8723ds_init_recv_priv;
1728 pHalFunc->free_recv_priv = &rtl8723ds_free_recv_priv;
1729 #ifdef CONFIG_RECV_THREAD_MODE
1730 pHalFunc->recv_hdl = rtl8723ds_recv_hdl;
1731 #endif /* CONFIG_RECV_THREAD_MODE */
1732 #ifdef CONFIG_RTW_SW_LED
1733 pHalFunc->InitSwLeds = &rtl8723ds_InitSwLeds;
1734 pHalFunc->DeInitSwLeds = &rtl8723ds_DeInitSwLeds;
1735 #endif
1736 pHalFunc->init_default_value = &rtl8723ds_init_default_value;
1737 pHalFunc->intf_chip_configure = &rtl8723ds_interface_configure;
1738 pHalFunc->read_adapter_info = &ReadAdapterInfo8723DS;
1739
1740 pHalFunc->enable_interrupt = &EnableInterrupt8723DSdio;
1741 pHalFunc->disable_interrupt = &DisableInterrupt8723DSdio;
1742 pHalFunc->check_ips_status = &CheckIPSStatus;
1743 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1744 pHalFunc->clear_interrupt = &ClearInterrupt8723DSdio;
1745 #endif
1746 pHalFunc->set_hw_reg_handler = &SetHwReg8723DS;
1747 pHalFunc->GetHwRegHandler = &GetHwReg8723DS;
1748 pHalFunc->get_hal_def_var_handler = &GetHalDefVar8723DSDIO;
1749 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723DSDIO;
1750
1751 pHalFunc->hal_xmit = &rtl8723ds_hal_xmit;
1752 pHalFunc->mgnt_xmit = &rtl8723ds_mgnt_xmit;
1753 #ifdef CONFIG_RTW_MGMT_QUEUE
1754 pHalFunc->hal_mgmt_xmitframe_enqueue = &rtl8723ds_hal_mgmt_xmitframe_enqueue;
1755 #endif
1756 pHalFunc->hal_xmitframe_enqueue = &rtl8723ds_hal_xmitframe_enqueue;
1757
1758 #ifdef CONFIG_HOSTAPD_MLME
1759 pHalFunc->hostap_mgnt_xmit_entry = NULL;
1760 #endif
1761
1762 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
1763 pHalFunc->hal_init_checkbthang_workqueue =
1764 &rtl8723ds_init_checkbthang_workqueue;
1765 pHalFunc->hal_free_checkbthang_workqueue =
1766 &rtl8723ds_free_checkbthang_workqueue;
1767 pHalFunc->hal_cancle_checkbthang_workqueue =
1768 &rtl8723ds_cancle_checkbthang_workqueue;
1769 pHalFunc->hal_checke_bt_hang = &rtl8723ds_hal_check_bt_hang;
1770 #endif
1771
1772 }
1773