1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun * more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *****************************************************************************/
15*4882a593Smuzhiyun #define _RTL8723D_CMD_C_
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <rtl8723d_hal.h>
18*4882a593Smuzhiyun #include "hal_com_h2c.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define MAX_H2C_BOX_NUMS 4
21*4882a593Smuzhiyun #define MESSAGE_BOX_SIZE 4
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define RTL8723D_MAX_CMD_LEN 7
24*4882a593Smuzhiyun #define RTL8723D_EX_MESSAGE_BOX_SIZE 4
25*4882a593Smuzhiyun
_is_fw_read_cmd_down(_adapter * padapter,u8 msgbox_num)26*4882a593Smuzhiyun static u8 _is_fw_read_cmd_down(_adapter *padapter, u8 msgbox_num)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun u8 read_down = _FALSE;
29*4882a593Smuzhiyun int retry_cnts = 100;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun u8 valid;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* RTW_INFO(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun do {
36*4882a593Smuzhiyun valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num);
37*4882a593Smuzhiyun if (0 == valid)
38*4882a593Smuzhiyun read_down = _TRUE;
39*4882a593Smuzhiyun else
40*4882a593Smuzhiyun rtw_msleep_os(1);
41*4882a593Smuzhiyun } while ((!read_down) && (retry_cnts--));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return read_down;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*****************************************
49*4882a593Smuzhiyun * H2C Msg format :
50*4882a593Smuzhiyun *| 31 - 8 |7-5 | 4 - 0 |
51*4882a593Smuzhiyun *| h2c_msg |Class |CMD_ID |
52*4882a593Smuzhiyun *| 31-0 |
53*4882a593Smuzhiyun *| Ext msg |
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun ******************************************/
FillH2CCmd8723D(PADAPTER padapter,u8 ElementID,u32 CmdLen,u8 * pCmdBuffer)56*4882a593Smuzhiyun s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun u8 h2c_box_num;
59*4882a593Smuzhiyun u8 h2c[RTL8723D_MAX_CMD_LEN + 1] = {0};
60*4882a593Smuzhiyun u32 msgbox_addr;
61*4882a593Smuzhiyun u32 msgbox_ex_addr = 0;
62*4882a593Smuzhiyun u32 h2c_cmd = 0;
63*4882a593Smuzhiyun u32 h2c_cmd_ex = 0;
64*4882a593Smuzhiyun s32 ret = _FAIL;
65*4882a593Smuzhiyun PHAL_DATA_TYPE pHalData;
66*4882a593Smuzhiyun struct dvobj_priv *psdpriv = padapter->dvobj;
67*4882a593Smuzhiyun struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun padapter = GET_PRIMARY_ADAPTER(padapter);
71*4882a593Smuzhiyun pHalData = GET_HAL_DATA(padapter);
72*4882a593Smuzhiyun #ifdef DBG_CHECK_FW_PS_STATE
73*4882a593Smuzhiyun #ifdef DBG_CHECK_FW_PS_STATE_H2C
74*4882a593Smuzhiyun if (rtw_fw_ps_state(padapter) == _FAIL) {
75*4882a593Smuzhiyun RTW_INFO("%s: h2c doesn't leave 32k ElementID=%02x\n", __FUNCTION__, ElementID);
76*4882a593Smuzhiyun pdbgpriv->dbg_h2c_leave32k_fail_cnt++;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* RTW_INFO("H2C ElementID=%02x , pHalData->LastHMEBoxNum=%02x\n", ElementID, pHalData->LastHMEBoxNum); */
80*4882a593Smuzhiyun #endif /* DBG_CHECK_FW_PS_STATE_H2C */
81*4882a593Smuzhiyun #endif /* DBG_CHECK_FW_PS_STATE */
82*4882a593Smuzhiyun _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun if (!pCmdBuffer)
85*4882a593Smuzhiyun goto exit;
86*4882a593Smuzhiyun if (CmdLen > RTL8723D_MAX_CMD_LEN)
87*4882a593Smuzhiyun goto exit;
88*4882a593Smuzhiyun if (rtw_is_surprise_removed(padapter))
89*4882a593Smuzhiyun goto exit;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun h2c[0] = ElementID;
92*4882a593Smuzhiyun _rtw_memcpy(h2c + 1, pCmdBuffer, CmdLen);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* pay attention to if race condition happened in H2C cmd setting. */
95*4882a593Smuzhiyun do {
96*4882a593Smuzhiyun h2c_box_num = pHalData->LastHMEBoxNum;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) {
99*4882a593Smuzhiyun RTW_INFO(" fw read cmd failed...\n");
100*4882a593Smuzhiyun #ifdef DBG_CHECK_FW_PS_STATE
101*4882a593Smuzhiyun RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
102*4882a593Smuzhiyun , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
103*4882a593Smuzhiyun #endif /* DBG_CHECK_FW_PS_STATE */
104*4882a593Smuzhiyun /* RTW_INFO(" 0x1c0: 0x%8x\n", rtw_read32(padapter, 0x1c0)); */
105*4882a593Smuzhiyun /* RTW_INFO(" 0x1c4: 0x%8x\n", rtw_read32(padapter, 0x1c4)); */
106*4882a593Smuzhiyun goto exit;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Write Ext command (byte 4~7) */
110*4882a593Smuzhiyun msgbox_ex_addr = REG_HMEBOX_EXT0_8723D + (h2c_box_num * RTL8723D_EX_MESSAGE_BOX_SIZE);
111*4882a593Smuzhiyun _rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, RTL8723D_EX_MESSAGE_BOX_SIZE);
112*4882a593Smuzhiyun h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
113*4882a593Smuzhiyun rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
114*4882a593Smuzhiyun /* Write command (byte 0~3) */
115*4882a593Smuzhiyun msgbox_addr = REG_HMEBOX_0_8723D + (h2c_box_num * MESSAGE_BOX_SIZE);
116*4882a593Smuzhiyun _rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
117*4882a593Smuzhiyun h2c_cmd = le32_to_cpu(h2c_cmd);
118*4882a593Smuzhiyun rtw_write32(padapter, msgbox_addr, h2c_cmd);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* RTW_INFO("MSG_BOX:%d, CmdLen(%d), CmdID(0x%x), reg:0x%x =>h2c_cmd:0x%.8x, reg:0x%x =>h2c_cmd_ex:0x%.8x\n" */
121*4882a593Smuzhiyun /* ,pHalData->LastHMEBoxNum , CmdLen, ElementID, msgbox_addr, h2c_cmd, msgbox_ex_addr, h2c_cmd_ex); */
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* update last msg box number */
124*4882a593Smuzhiyun pHalData->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun } while (0);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun ret = _SUCCESS;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun exit:
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return ret;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun * Description: Get the reserved page number in Tx packet buffer.
140*4882a593Smuzhiyun * Retrun value: the page number.
141*4882a593Smuzhiyun * 2012.08.09, by tynli.
142*4882a593Smuzhiyun * */
GetTxBufferRsvdPageNum8723D(_adapter * padapter,bool wowlan)143*4882a593Smuzhiyun u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
146*4882a593Smuzhiyun u8 RsvdPageNum = 0;
147*4882a593Smuzhiyun /* default reseved 1 page for the IC type which is undefined. */
148*4882a593Smuzhiyun u8 TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8723D;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&TxPageBndy);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun RsvdPageNum = LAST_ENTRY_OF_TX_PKT_BUFFER_8723D - TxPageBndy + 1;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return RsvdPageNum;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter,u8 psmode)157*4882a593Smuzhiyun void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 psmode)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun u8 smart_ps = 0;
160*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
161*4882a593Smuzhiyun u8 u1H2CPwrModeParm[H2C_PWRMODE_LEN] = {0};
162*4882a593Smuzhiyun u8 PowerState = 0, awake_intvl = 1, rlbm = 0;
163*4882a593Smuzhiyun #ifdef CONFIG_P2P
164*4882a593Smuzhiyun struct wifidirect_info *wdinfo = &(padapter->wdinfo);
165*4882a593Smuzhiyun #endif /* CONFIG_P2P */
166*4882a593Smuzhiyun u8 allQueueUAPSD = 0;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun #ifdef CONFIG_PLATFORM_INTEL_BYT
169*4882a593Smuzhiyun if (psmode == PS_MODE_DTIM)
170*4882a593Smuzhiyun psmode = PS_MODE_MAX;
171*4882a593Smuzhiyun #endif /* CONFIG_PLATFORM_INTEL_BYT */
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (pwrpriv->dtim > 0)
175*4882a593Smuzhiyun RTW_INFO("%s(): FW LPS mode = %d, SmartPS=%d, dtim=%d\n", __func__, psmode, pwrpriv->smart_ps, pwrpriv->dtim);
176*4882a593Smuzhiyun else
177*4882a593Smuzhiyun RTW_INFO("%s(): FW LPS mode = %d, SmartPS=%d\n", __func__, psmode, pwrpriv->smart_ps);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (psmode == PS_MODE_MIN) {
180*4882a593Smuzhiyun rlbm = 0;
181*4882a593Smuzhiyun awake_intvl = 2;
182*4882a593Smuzhiyun smart_ps = pwrpriv->smart_ps;
183*4882a593Smuzhiyun } else if (psmode == PS_MODE_MAX) {
184*4882a593Smuzhiyun rlbm = 1;
185*4882a593Smuzhiyun awake_intvl = 2;
186*4882a593Smuzhiyun smart_ps = pwrpriv->smart_ps;
187*4882a593Smuzhiyun } else if (psmode == PS_MODE_DTIM) { /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */
188*4882a593Smuzhiyun if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16)
189*4882a593Smuzhiyun awake_intvl = pwrpriv->dtim + 1; /* DTIM = (awake_intvl - 1) */
190*4882a593Smuzhiyun else
191*4882a593Smuzhiyun awake_intvl = 4;/* DTIM=3 */
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun rlbm = 2;
195*4882a593Smuzhiyun smart_ps = pwrpriv->smart_ps;
196*4882a593Smuzhiyun } else {
197*4882a593Smuzhiyun rlbm = 2;
198*4882a593Smuzhiyun awake_intvl = 4;
199*4882a593Smuzhiyun smart_ps = pwrpriv->smart_ps;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun #ifdef CONFIG_P2P
203*4882a593Smuzhiyun if (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) {
204*4882a593Smuzhiyun awake_intvl = 2;
205*4882a593Smuzhiyun rlbm = 1;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun #endif /* CONFIG_P2P */
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun if (padapter->registrypriv.wifi_spec == 1) {
210*4882a593Smuzhiyun awake_intvl = 2;
211*4882a593Smuzhiyun rlbm = 1;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun if (psmode > 0) {
215*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
216*4882a593Smuzhiyun if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
217*4882a593Smuzhiyun PowerState = rtw_btcoex_RpwmVal(padapter);
218*4882a593Smuzhiyun else
219*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
220*4882a593Smuzhiyun PowerState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
221*4882a593Smuzhiyun } else
222*4882a593Smuzhiyun PowerState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun SET_8723D_H2CCMD_PWRMODE_PARM_MODE(u1H2CPwrModeParm, (psmode > 0) ? 1 : 0);
225*4882a593Smuzhiyun SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CPwrModeParm, smart_ps);
226*4882a593Smuzhiyun SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(u1H2CPwrModeParm, rlbm);
227*4882a593Smuzhiyun SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1H2CPwrModeParm, awake_intvl);
228*4882a593Smuzhiyun SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1H2CPwrModeParm, allQueueUAPSD);
229*4882a593Smuzhiyun SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CPwrModeParm, PowerState);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
232*4882a593Smuzhiyun rtw_btcoex_RecordPwrMode(padapter, u1H2CPwrModeParm, H2C_PWRMODE_LEN);
233*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun RTW_DBG_DUMP("u1H2CPwrModeParm:",
236*4882a593Smuzhiyun u1H2CPwrModeParm, H2C_PWRMODE_LEN);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun FillH2CCmd8723D(padapter, H2C_8723D_SET_PWR_MODE, H2C_PWRMODE_LEN, u1H2CPwrModeParm);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter)241*4882a593Smuzhiyun void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
244*4882a593Smuzhiyun u8 u1H2CPsTuneParm[H2C_PSTUNEPARAM_LEN] = {0};
245*4882a593Smuzhiyun u8 bcn_to_limit = 10; /* 10 * 100 * awakeinterval (ms) */
246*4882a593Smuzhiyun u8 dtim_timeout = 5; /* ms //wait broadcast data timer */
247*4882a593Smuzhiyun u8 ps_timeout = 20; /* ms //Keep awake when tx */
248*4882a593Smuzhiyun u8 dtim_period = 3;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* RTW_INFO("%s(): FW LPS mode = %d\n", __func__, psmode); */
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(u1H2CPsTuneParm, bcn_to_limit);
253*4882a593Smuzhiyun SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(u1H2CPsTuneParm, dtim_timeout);
254*4882a593Smuzhiyun SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(u1H2CPsTuneParm, ps_timeout);
255*4882a593Smuzhiyun SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(u1H2CPsTuneParm, 1);
256*4882a593Smuzhiyun SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(u1H2CPsTuneParm, dtim_period);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun RTW_DBG_DUMP("u1H2CPsTuneParm:",
259*4882a593Smuzhiyun u1H2CPsTuneParm, H2C_PSTUNEPARAM_LEN);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun FillH2CCmd8723D(padapter, H2C_8723D_PS_TUNING_PARA, H2C_PSTUNEPARAM_LEN, u1H2CPsTuneParm);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
rtl8723d_download_rsvd_page(PADAPTER padapter,u8 mstatus)264*4882a593Smuzhiyun void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
267*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
268*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
269*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
270*4882a593Smuzhiyun BOOLEAN bcn_valid = _FALSE;
271*4882a593Smuzhiyun u8 DLBcnCount = 0;
272*4882a593Smuzhiyun u32 poll = 0;
273*4882a593Smuzhiyun u8 RegFwHwTxQCtrl;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun RTW_INFO("+" FUNC_ADPT_FMT ": hw_port=%d mstatus(%x)\n",
277*4882a593Smuzhiyun FUNC_ADPT_ARG(padapter), get_hw_port(padapter), mstatus);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (mstatus == RT_MEDIA_CONNECT) {
280*4882a593Smuzhiyun u8 bcn_ctrl = rtw_read8(padapter, REG_BCN_CTRL);
281*4882a593Smuzhiyun BOOLEAN bRecover = _FALSE;
282*4882a593Smuzhiyun u8 v8;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
285*4882a593Smuzhiyun /* Suggested by filen. Added by tynli. */
286*4882a593Smuzhiyun rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid));
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* set REG_CR bit 8 */
289*4882a593Smuzhiyun v8 = rtw_read8(padapter, REG_CR + 1);
290*4882a593Smuzhiyun v8 |= BIT(0); /* ENSWBCN */
291*4882a593Smuzhiyun rtw_write8(padapter, REG_CR + 1, v8);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* Disable Hw protection for a time which revserd for Hw sending beacon. */
294*4882a593Smuzhiyun /* Fix download reserved page packet fail that access collision with the protection time. */
295*4882a593Smuzhiyun /* 2010.05.11. Added by tynli. */
296*4882a593Smuzhiyun rtw_write8(padapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
299*4882a593Smuzhiyun RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2);
300*4882a593Smuzhiyun if (RegFwHwTxQCtrl & BIT(6))
301*4882a593Smuzhiyun bRecover = _TRUE;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* To tell Hw the packet is not a real beacon frame. */
304*4882a593Smuzhiyun RegFwHwTxQCtrl &= ~BIT(6);
305*4882a593Smuzhiyun rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun /* Clear beacon valid check bit. */
308*4882a593Smuzhiyun rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
309*4882a593Smuzhiyun rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun DLBcnCount = 0;
312*4882a593Smuzhiyun poll = 0;
313*4882a593Smuzhiyun do {
314*4882a593Smuzhiyun /* download rsvd page. */
315*4882a593Smuzhiyun rtw_hal_set_fw_rsvd_page(padapter, _FALSE);
316*4882a593Smuzhiyun DLBcnCount++;
317*4882a593Smuzhiyun do {
318*4882a593Smuzhiyun rtw_yield_os();
319*4882a593Smuzhiyun /* rtw_mdelay_os(10); */
320*4882a593Smuzhiyun /* check rsvd page download OK. */
321*4882a593Smuzhiyun rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid));
322*4882a593Smuzhiyun poll++;
323*4882a593Smuzhiyun } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun } while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter));
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (RTW_CANNOT_RUN(padapter))
328*4882a593Smuzhiyun ;
329*4882a593Smuzhiyun else if (!bcn_valid)
330*4882a593Smuzhiyun RTW_ERR(ADPT_FMT": 1 DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
331*4882a593Smuzhiyun ADPT_ARG(padapter) , DLBcnCount, poll);
332*4882a593Smuzhiyun else {
333*4882a593Smuzhiyun struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun pwrctl->fw_psmode_iface_id = padapter->iface_id;
336*4882a593Smuzhiyun rtw_hal_set_fw_rsvd_page(padapter, _TRUE);
337*4882a593Smuzhiyun RTW_INFO(ADPT_FMT": 1 DL RSVD page success! DLBcnCount:%u, poll:%u\n",
338*4882a593Smuzhiyun ADPT_ARG(padapter), DLBcnCount, poll);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /* restore bcn_ctrl */
342*4882a593Smuzhiyun rtw_write8(padapter, REG_BCN_CTRL, bcn_ctrl);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun /* To make sure that if there exists an adapter which would like to send beacon. */
345*4882a593Smuzhiyun /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
346*4882a593Smuzhiyun /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
347*4882a593Smuzhiyun /* the beacon cannot be sent by HW. */
348*4882a593Smuzhiyun /* 2010.06.23. Added by tynli. */
349*4882a593Smuzhiyun if (bRecover) {
350*4882a593Smuzhiyun RegFwHwTxQCtrl |= BIT(6);
351*4882a593Smuzhiyun rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
355*4882a593Smuzhiyun #ifndef CONFIG_PCI_HCI
356*4882a593Smuzhiyun v8 = rtw_read8(padapter, REG_CR + 1);
357*4882a593Smuzhiyun v8 &= ~BIT(0); /* ~ENSWBCN */
358*4882a593Smuzhiyun rtw_write8(padapter, REG_CR + 1, v8);
359*4882a593Smuzhiyun #endif
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter,u8 mstatus)364*4882a593Smuzhiyun void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun if (mstatus == 1)
367*4882a593Smuzhiyun rtl8723d_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter)371*4882a593Smuzhiyun void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun rtl8723d_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun #ifdef CONFIG_P2P
rtl8723d_set_p2p_ps_offload_cmd(_adapter * padapter,u8 p2p_ps_state)378*4882a593Smuzhiyun void rtl8723d_set_p2p_ps_offload_cmd(_adapter *padapter, u8 p2p_ps_state)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
381*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
382*4882a593Smuzhiyun struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
383*4882a593Smuzhiyun struct P2P_PS_Offload_t *p2p_ps_offload = (struct P2P_PS_Offload_t *)(&pHalData->p2p_ps_offload);
384*4882a593Smuzhiyun u8 i;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun #if 1
388*4882a593Smuzhiyun switch (p2p_ps_state) {
389*4882a593Smuzhiyun case P2P_PS_DISABLE:
390*4882a593Smuzhiyun RTW_INFO("P2P_PS_DISABLE\n");
391*4882a593Smuzhiyun _rtw_memset(p2p_ps_offload, 0 , 1);
392*4882a593Smuzhiyun break;
393*4882a593Smuzhiyun case P2P_PS_ENABLE:
394*4882a593Smuzhiyun RTW_INFO("P2P_PS_ENABLE\n");
395*4882a593Smuzhiyun /* update CTWindow value. */
396*4882a593Smuzhiyun if (pwdinfo->ctwindow > 0) {
397*4882a593Smuzhiyun p2p_ps_offload->CTWindow_En = 1;
398*4882a593Smuzhiyun rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* hw only support 2 set of NoA */
402*4882a593Smuzhiyun for (i = 0 ; i < pwdinfo->noa_num ; i++) {
403*4882a593Smuzhiyun /* To control the register setting for which NOA */
404*4882a593Smuzhiyun rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
405*4882a593Smuzhiyun if (i == 0)
406*4882a593Smuzhiyun p2p_ps_offload->NoA0_En = 1;
407*4882a593Smuzhiyun else
408*4882a593Smuzhiyun p2p_ps_offload->NoA1_En = 1;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* config P2P NoA Descriptor Register */
411*4882a593Smuzhiyun /* RTW_INFO("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); */
412*4882a593Smuzhiyun rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /* RTW_INFO("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); */
415*4882a593Smuzhiyun rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* RTW_INFO("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); */
418*4882a593Smuzhiyun rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /* RTW_INFO("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); */
421*4882a593Smuzhiyun rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
425*4882a593Smuzhiyun /* rst p2p circuit */
426*4882a593Smuzhiyun rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun p2p_ps_offload->Offload_En = 1;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (pwdinfo->role == P2P_ROLE_GO) {
431*4882a593Smuzhiyun p2p_ps_offload->role = 1;
432*4882a593Smuzhiyun p2p_ps_offload->AllStaSleep = 0;
433*4882a593Smuzhiyun } else
434*4882a593Smuzhiyun p2p_ps_offload->role = 0;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun p2p_ps_offload->discovery = 0;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun break;
439*4882a593Smuzhiyun case P2P_PS_SCAN:
440*4882a593Smuzhiyun RTW_INFO("P2P_PS_SCAN\n");
441*4882a593Smuzhiyun p2p_ps_offload->discovery = 1;
442*4882a593Smuzhiyun break;
443*4882a593Smuzhiyun case P2P_PS_SCAN_DONE:
444*4882a593Smuzhiyun RTW_INFO("P2P_PS_SCAN_DONE\n");
445*4882a593Smuzhiyun p2p_ps_offload->discovery = 0;
446*4882a593Smuzhiyun pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
447*4882a593Smuzhiyun break;
448*4882a593Smuzhiyun default:
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun FillH2CCmd8723D(padapter, H2C_8723D_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
453*4882a593Smuzhiyun #endif
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun #endif /* CONFIG_P2P */
458*4882a593Smuzhiyun
459