1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #include "../phydm_precomp.h"
18
19 #if (RTL8723D_SUPPORT == 1)
20
odm_config_rf_reg_8723d(struct dm_struct * dm,u32 addr,u32 data,enum rf_path RF_PATH,u32 reg_addr)21 void odm_config_rf_reg_8723d(struct dm_struct *dm, u32 addr, u32 data,
22 enum rf_path RF_PATH, u32 reg_addr)
23 {
24 if (addr == 0xfe || addr == 0xffe) {
25 #ifdef CONFIG_LONG_DELAY_ISSUE
26 ODM_sleep_ms(50);
27 #else
28 ODM_delay_ms(50);
29 #endif
30 } else {
31 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
32 /* Add 1us delay between BB/RF register setting. */
33 ODM_delay_us(1);
34 }
35 }
36
odm_config_rf_radio_a_8723d(struct dm_struct * dm,u32 addr,u32 data)37 void odm_config_rf_radio_a_8723d(struct dm_struct *dm, u32 addr, u32 data)
38 {
39 u32 content = 0x1000; /* RF_Content: radioa_txt */
40 u32 maskfor_phy_set = (u32)(content & 0xE000);
41
42 odm_config_rf_reg_8723d(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
43
44 PHYDM_DBG(dm, ODM_COMP_INIT,
45 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
46 addr, data);
47 }
48
odm_config_rf_radio_b_8723d(struct dm_struct * dm,u32 addr,u32 data)49 void odm_config_rf_radio_b_8723d(struct dm_struct *dm, u32 addr, u32 data)
50 {
51 u32 content = 0x1001; /* RF_Content: radiob_txt */
52 u32 maskfor_phy_set = (u32)(content & 0xE000);
53
54 odm_config_rf_reg_8723d(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
55
56 PHYDM_DBG(dm, ODM_COMP_INIT,
57 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
58 addr, data);
59 }
60
odm_config_mac_8723d(struct dm_struct * dm,u32 addr,u8 data)61 void odm_config_mac_8723d(struct dm_struct *dm, u32 addr, u8 data)
62 {
63 odm_write_1byte(dm, addr, data);
64 PHYDM_DBG(dm, ODM_COMP_INIT,
65 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
66 addr, data);
67 }
68
odm_config_bb_agc_8723d(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)69 void odm_config_bb_agc_8723d(struct dm_struct *dm, u32 addr, u32 bitmask,
70 u32 data)
71 {
72 odm_set_bb_reg(dm, addr, bitmask, data);
73 /* Add 1us delay between BB/RF register setting. */
74 ODM_delay_us(1);
75
76 PHYDM_DBG(dm, ODM_COMP_INIT,
77 "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
78 addr, data);
79 }
80
odm_config_bb_phy_reg_pg_8723d(struct dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)81 void odm_config_bb_phy_reg_pg_8723d(struct dm_struct *dm, u32 band, u32 rf_path,
82 u32 tx_num, u32 addr, u32 bitmask, u32 data)
83 {
84 if (addr == 0xfe || addr == 0xffe)
85 #ifdef CONFIG_LONG_DELAY_ISSUE
86 ODM_sleep_ms(50);
87 #else
88 ODM_delay_ms(50);
89 #endif
90 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
91 else
92 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
93 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
94 else
95 PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
96 #endif
97 PHYDM_DBG(dm, ODM_COMP_INIT,
98 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
99 addr, bitmask, data);
100 }
101
odm_config_bb_phy_8723d(struct dm_struct * dm,u32 addr,u32 bitmask,u32 data)102 void odm_config_bb_phy_8723d(struct dm_struct *dm, u32 addr, u32 bitmask,
103 u32 data)
104 {
105 /*dbg_print("odm_config_bb_phy_8723d(), addr = 0x%x, data = 0x%x\n", addr, data);*/
106 if (addr == 0xfe)
107 #ifdef CONFIG_LONG_DELAY_ISSUE
108 ODM_sleep_ms(50);
109 #else
110 ODM_delay_ms(50);
111 #endif
112 else if (addr == 0xfd)
113 ODM_delay_ms(5);
114 else if (addr == 0xfc)
115 ODM_delay_ms(1);
116 else if (addr == 0xfb)
117 ODM_delay_us(50);
118 else if (addr == 0xfa)
119 ODM_delay_us(5);
120 else if (addr == 0xf9)
121 ODM_delay_us(1);
122 else
123 odm_set_bb_reg(dm, addr, bitmask, data);
124
125 /* Add 1us delay between BB/RF register setting. */
126 ODM_delay_us(1);
127 PHYDM_DBG(dm, ODM_COMP_INIT,
128 "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
129 addr, data);
130 }
131
odm_config_bb_txpwr_lmt_8723d(struct dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)132 void odm_config_bb_txpwr_lmt_8723d(struct dm_struct *dm, u8 *regulation,
133 u8 *band, u8 *bandwidth, u8 *rate_section,
134 u8 *rf_path, u8 *channel, u8 *power_limit)
135 {
136 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
137 phy_set_tx_power_limit(dm, regulation, band,
138 bandwidth, rate_section, rf_path, channel, power_limit);
139 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
140 PHY_SetTxPowerLimit(dm, regulation, band,
141 bandwidth, rate_section, rf_path, channel, power_limit);
142 #endif
143 }
144
145 #endif
146