1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_MP_SUPPORT
34 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
35
phydm_mp_set_single_tone_jgr3(void * dm_void,boolean is_single_tone,u8 path)36 void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
37 u8 path)
38 {
39 struct dm_struct *dm = (struct dm_struct *)dm_void;
40 struct phydm_mp *mp = &dm->dm_mp_table;
41 u8 start = RF_PATH_A, end = RF_PATH_A;
42 u8 i = 0;
43 u8 central_ch = 0;
44 boolean is_2g_ch = false;
45
46 switch (path) {
47 case RF_PATH_A:
48 case RF_PATH_B:
49 case RF_PATH_C:
50 case RF_PATH_D:
51 start = path;
52 end = path;
53 break;
54 case RF_PATH_AB:
55 start = RF_PATH_A;
56 end = RF_PATH_B;
57 break;
58 #if (defined(PHYDM_COMPILE_IC_4SS))
59 case RF_PATH_AC:
60 start = RF_PATH_A;
61 end = RF_PATH_C;
62 break;
63 case RF_PATH_AD:
64 start = RF_PATH_A;
65 end = RF_PATH_D;
66 break;
67 case RF_PATH_BC:
68 start = RF_PATH_B;
69 end = RF_PATH_C;
70 break;
71 case RF_PATH_BD:
72 start = RF_PATH_B;
73 end = RF_PATH_D;
74 break;
75 case RF_PATH_CD:
76 start = RF_PATH_C;
77 end = RF_PATH_D;
78 break;
79 case RF_PATH_ABC:
80 start = RF_PATH_A;
81 end = RF_PATH_C;
82 break;
83 case RF_PATH_ABD:
84 start = RF_PATH_A;
85 end = RF_PATH_D;
86 break;
87 case RF_PATH_ACD:
88 start = RF_PATH_A;
89 end = RF_PATH_D;
90 break;
91 case RF_PATH_BCD:
92 start = RF_PATH_B;
93 end = RF_PATH_D;
94 break;
95 case RF_PATH_ABCD:
96 start = RF_PATH_A;
97 end = RF_PATH_D;
98 break;
99 #endif
100 }
101
102 central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
103 is_2g_ch = (central_ch <= 14) ? true : false;
104
105 if (is_single_tone) {
106 /*Disable CCA*/
107 if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
108 if(dm->support_ic_type & ODM_RTL8723F) {
109 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1); /*CCK*/
110 } else {
111 odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
112 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
113 }
114 }
115 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*OFDM*/
116 if (dm->support_ic_type & ODM_RTL8723F) {
117 odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x0);
118 for (i = start; i <= end; i++) {
119 mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
120 /*Tx mode: RF0x00[19:16]=4'b0010 */
121 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
122 /*Lowest RF gain index: RF_0x1[5:0] TX power*/
123 mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
124 odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
125 /*RF LO enabled */
126 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
127 }
128 } else {
129 for (i = start; i <= end; i++) {
130 mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
131 /*Tx mode: RF0x00[19:16]=4'b0010 */
132 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
133 /*Lowest RF gain index: RF_0x0[4:0] = 0*/
134 odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
135 /*RF LO enabled */
136 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
137 }
138 }
139
140 #if (RTL8814B_SUPPORT)
141 if (dm->support_ic_type & ODM_RTL8814B) {
142 mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
143 dm, RF_SYN0, RF_0x0, RFREG_MASK);
144 /*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
145 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
146 0x1f, 0x0);
147 /*RF LO enabled */
148 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
149 BIT(1), 0x1);
150 /*SYN1*/
151 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
152 mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
153 dm, RF_SYN1, RF_0x0,
154 RFREG_MASK);
155 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
156 RF_0x0, 0x1f,
157 0x0);
158 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
159 RF_0x58, BIT(1),
160 0x1);
161 }
162 }
163 #endif
164 } else {
165 /*Enable CCA*/
166 if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
167 if(dm->support_ic_type & ODM_RTL8723F) {
168 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0); /*CCK*/
169 } else {
170 odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
171 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
172 }
173 }
174 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0); /*OFDM*/
175
176 if(dm->support_ic_type & ODM_RTL8723F) {
177 for (i = start; i <= end; i++) {
178 odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
179 odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
180 /*RF LO disabled */
181 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
182 }
183 odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x1);
184 } else {
185 for (i = start; i <= end; i++) {
186 odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
187 /*RF LO disabled */
188 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
189 }
190 }
191 #if (RTL8814B_SUPPORT)
192 if (dm->support_ic_type & ODM_RTL8814B) {
193 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
194 RFREG_MASK,
195 mp->rf0_syn[RF_SYN0]);
196 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
197 BIT(1), 0x0);
198 /*SYN1*/
199 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
200 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
201 RF_0x0,
202 RFREG_MASK,
203 mp->rf0_syn[RF_SYN1]);
204 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
205 RF_0x58, BIT(1),
206 0x0);
207 }
208 }
209 #endif
210 }
211 }
212
phydm_mp_set_carrier_supp_jgr3(void * dm_void,boolean is_carrier_supp,u32 rate_index)213 void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
214 u32 rate_index)
215 {
216 struct dm_struct *dm = (struct dm_struct *)dm_void;
217 struct phydm_mp *mp = &dm->dm_mp_table;
218
219 if (is_carrier_supp) {
220 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
221 /*if CCK block on? */
222 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
223 odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
224
225 if(dm->support_ic_type & ODM_RTL8723F){
226 /* @Carrier suppress tx */
227 odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
228 /*turn off scramble setting */
229 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
230 /*Set CCK Tx Test Rate, set TxRate to 2Mbps */
231 odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
232 /* BB and PMAC cont tx */
233 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
234 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
235 /* TX CCK ON */
236 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
237 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
238 }
239 else {
240 /*Turn Off All Test mode */
241 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
242
243 /*transmit mode */
244 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
245 /*turn off scramble setting */
246 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
247 /*Set CCK Tx Test Rate, set TxRate to 1Mbps */
248 odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
249 }
250 }
251 } else { /*Stop Carrier Suppression. */
252 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
253 if(dm->support_ic_type & ODM_RTL8723F) {
254 /* TX Stop */
255 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
256 /* Clear BB cont tx */
257 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
258 /* Clear PMAC cont tx */
259 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
260 /* Clear TX Stop */
261 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
262 /* normal mode */
263 odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
264 /* turn on scramble setting */
265 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
266 }
267 else {
268 /*normal mode */
269 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
270 /*turn on scramble setting */
271 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
272 }
273 /*BB Reset */
274 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
275 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
276 }
277 }
278 }
279
phydm_mp_set_single_carrier_jgr3(void * dm_void,boolean is_single_carrier)280 void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
281 {
282 struct dm_struct *dm = (struct dm_struct *)dm_void;
283 struct phydm_mp *mp = &dm->dm_mp_table;
284
285 if (is_single_carrier) {
286 /*1. if OFDM block on? */
287 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
288 odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
289
290 if (dm->support_ic_type & ODM_RTL8723F) {
291 /*3. turn on scramble setting */
292 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
293 /*4. Turn On single carrier. */
294 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
295 }
296 else {
297 /*2. set CCK test mode off, set to CCK normal mode */
298 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
299 /*3. turn on scramble setting */
300 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
301 /*4. Turn On single carrier. */
302 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
303 }
304 } else {
305 /*Turn off all test modes. */
306 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
307
308 /*Delay 10 ms */
309 ODM_delay_ms(10);
310
311 /*BB Reset*/
312 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
313 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
314 }
315 }
316
phydm_mp_get_tx_ok_jgr3(void * dm_void,u32 rate_index)317 void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
318 {
319 struct dm_struct *dm = (struct dm_struct *)dm_void;
320 struct phydm_mp *mp = &dm->dm_mp_table;
321
322 if (phydm_is_cck_rate(dm, (u8)rate_index))
323 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
324 else
325 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
326 }
327
phydm_mp_get_rx_ok_jgr3(void * dm_void)328 void phydm_mp_get_rx_ok_jgr3(void *dm_void)
329 {
330 struct dm_struct *dm = (struct dm_struct *)dm_void;
331 struct phydm_mp *mp = &dm->dm_mp_table;
332
333 u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
334 u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
335 if(dm->support_ic_type & ODM_RTL8723F)
336 cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
337 else
338 cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
339 ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
340 ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
341 vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
342 if(dm->support_ic_type & ODM_RTL8723F)
343 cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
344 else
345 cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
346 ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
347 ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
348 vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
349
350 mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
351 mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
352 mp->io_value = (u32)mp->rx_phy_ok_cnt;
353 }
354 #endif
phydm_mp_set_crystal_cap(void * dm_void,u8 crystal_cap)355 void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
356 {
357 struct dm_struct *dm = (struct dm_struct *)dm_void;
358
359 phydm_set_crystal_cap(dm, crystal_cap);
360 }
361
phydm_mp_set_single_tone(void * dm_void,boolean is_single_tone,u8 path)362 void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
363 {
364 struct dm_struct *dm = (struct dm_struct *)dm_void;
365
366 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
367 phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
368 }
369
phydm_mp_set_carrier_supp(void * dm_void,boolean is_carrier_supp,u32 rate_index)370 void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
371 u32 rate_index)
372 {
373 struct dm_struct *dm = (struct dm_struct *)dm_void;
374
375 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
376 phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
377 }
378
phydm_mp_set_single_carrier(void * dm_void,boolean is_single_carrier)379 void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
380 {
381 struct dm_struct *dm = (struct dm_struct *)dm_void;
382
383 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
384 phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
385 }
phydm_mp_reset_rx_counters_phy(void * dm_void)386 void phydm_mp_reset_rx_counters_phy(void *dm_void)
387 {
388 struct dm_struct *dm = (struct dm_struct *)dm_void;
389
390 phydm_reset_bb_hw_cnt(dm);
391 }
392
phydm_mp_get_tx_ok(void * dm_void,u32 rate_index)393 void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
394 {
395 struct dm_struct *dm = (struct dm_struct *)dm_void;
396
397 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
398 phydm_mp_get_tx_ok_jgr3(dm, rate_index);
399 }
400
phydm_mp_get_rx_ok(void * dm_void)401 void phydm_mp_get_rx_ok(void *dm_void)
402 {
403 struct dm_struct *dm = (struct dm_struct *)dm_void;
404
405 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
406 phydm_mp_get_rx_ok_jgr3(dm);
407 }
408 #endif
409