1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __ODM_INTERFACE_H__ 27 #define __ODM_INTERFACE_H__ 28 29 #define INTERFACE_VERSION "1.2" 30 31 #define pdm_set_reg odm_set_bb_reg 32 33 /*@=========== Constant/Structure/Enum/... Define*/ 34 35 enum phydm_h2c_cmd { 36 PHYDM_H2C_RA_MASK = 0x40, 37 PHYDM_H2C_TXBF = 0x41, 38 ODM_H2C_RSSI_REPORT = 0x42, 39 ODM_H2C_IQ_CALIBRATION = 0x45, 40 PHYDM_RA_MASK_ABOVE_3SS = 0x46, 41 ODM_H2C_RA_PARA_ADJUST = 0x47, 42 PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, 43 PHYDM_H2C_FW_TRACE_EN = 0x49, 44 ODM_H2C_WIFI_CALIBRATION = 0x6d, 45 PHYDM_H2C_MU = 0x4a, 46 PHYDM_H2C_FW_GENERAL_INIT = 0x4c, 47 PHYDM_H2C_FW_CLM_MNTR = 0x4d, 48 PHYDM_H2C_MCC = 0x4f, 49 PHYDM_H2C_RESP_TX_PATH_CTRL = 0x50, 50 PHYDM_H2C_RESP_TX_ANT_CTRL = 0x51, 51 PHYDM_H2C_FW_DM_CTRL = 0x55, 52 ODM_MAX_H2CCMD 53 }; 54 55 enum phydm_c2h_evt { 56 PHYDM_C2H_DBG = 0, 57 PHYDM_C2H_LB = 1, 58 PHYDM_C2H_XBF = 2, 59 PHYDM_C2H_TX_REPORT = 3, 60 PHYDM_C2H_INFO = 9, 61 PHYDM_C2H_BT_MP = 11, 62 PHYDM_C2H_RA_RPT = 12, 63 PHYDM_C2H_RA_PARA_RPT = 14, 64 PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, 65 PHYDM_C2H_IQK_FINISH = 17, /*@0x11*/ 66 PHYDM_C2H_CLM_MONITOR = 0x2a, 67 PHYDM_C2H_DBG_CODE = 0xFE, 68 PHYDM_C2H_EXTEND = 0xFF, 69 }; 70 71 enum phydm_extend_c2h_evt { 72 PHYDM_EXTEND_C2H_DBG_PRINT = 0 73 74 }; 75 76 enum phydm_halmac_param { 77 PHYDM_HALMAC_CMD_MAC_W8 = 0, 78 PHYDM_HALMAC_CMD_MAC_W16 = 1, 79 PHYDM_HALMAC_CMD_MAC_W32 = 2, 80 PHYDM_HALMAC_CMD_BB_W8, 81 PHYDM_HALMAC_CMD_BB_W16, 82 PHYDM_HALMAC_CMD_BB_W32, 83 PHYDM_HALMAC_CMD_RF_W, 84 PHYDM_HALMAC_CMD_DELAY_US, 85 PHYDM_HALMAC_CMD_DELAY_MS, 86 PHYDM_HALMAC_CMD_END = 0XFF, 87 }; 88 89 /*@=========== Macro Define*/ 90 91 #define _reg_all(_name) ODM_##_name 92 #define _reg_ic(_name, _ic) ODM_##_name##_ic 93 #define _bit_all(_name) BIT_##_name 94 #define _bit_ic(_name, _ic) BIT_##_name##_ic 95 96 #if defined(DM_ODM_CE_MAC80211) 97 #define ODM_BIT(name, dm) \ 98 ((dm->support_ic_type & ODM_IC_11N_SERIES) ? \ 99 ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC) 100 101 #define ODM_REG(name, dm) \ 102 ((dm->support_ic_type & ODM_IC_11N_SERIES) ? \ 103 ODM_REG_##name##_11N : ODM_REG_##name##_11AC) 104 #else 105 #define _reg_11N(_name) ODM_REG_##_name##_11N 106 #define _reg_11AC(_name) ODM_REG_##_name##_11AC 107 #define _bit_11N(_name) ODM_BIT_##_name##_11N 108 #define _bit_11AC(_name) ODM_BIT_##_name##_11AC 109 110 #ifdef __ECOS 111 #define _rtk_cat(_name, _ic_type, _func) \ 112 ( \ 113 ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ 114 _func##_11AC(_name)) 115 #else 116 117 #define _cat(_name, _ic_type, _func) \ 118 ( \ 119 ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ 120 _func##_11AC(_name)) 121 #endif 122 /*@ 123 * only sample code 124 *#define _cat(_name, _ic_type, _func) \ 125 * ( \ 126 * ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\ 127 * _func##_ic(_name, _8195) \ 128 * ) 129 */ 130 131 /* @_name: name of register or bit. 132 * Example: "ODM_REG(R_A_AGC_CORE1, dm)" 133 * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", 134 * depends on support_ic_type. 135 */ 136 #ifdef __ECOS 137 #define ODM_REG(_name, _pdm_odm) \ 138 _rtk_cat(_name, _pdm_odm->support_ic_type, _reg) 139 #define ODM_BIT(_name, _pdm_odm) \ 140 _rtk_cat(_name, _pdm_odm->support_ic_type, _bit) 141 #else 142 #define ODM_REG(_name, _pdm_odm) \ 143 _cat(_name, _pdm_odm->support_ic_type, _reg) 144 #define ODM_BIT(_name, _pdm_odm) \ 145 _cat(_name, _pdm_odm->support_ic_type, _bit) 146 #endif 147 148 #endif 149 /*@ 150 * =========== Extern Variable ??? It should be forbidden. 151 */ 152 153 /*@ 154 * =========== EXtern Function Prototype 155 */ 156 157 u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr); 158 159 u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr); 160 161 u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr); 162 163 void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data); 164 165 void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data); 166 167 void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data); 168 169 void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, 170 u32 data); 171 172 u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask); 173 174 void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data); 175 176 u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask); 177 178 void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, 179 u32 bit_mask, u32 data); 180 181 u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, 182 u32 bit_mask); 183 184 /*@ 185 * Memory Relative Function. 186 */ 187 void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length); 188 void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length); 189 190 void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length); 191 192 s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, 193 u32 length); 194 195 void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length); 196 197 /*@ 198 * ODM MISC-spin lock relative API. 199 */ 200 void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type); 201 202 void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type); 203 204 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 205 /*@ 206 * ODM MISC-workitem relative API. 207 */ 208 void odm_initialize_work_item( 209 struct dm_struct *dm, 210 PRT_WORK_ITEM p_rt_work_item, 211 RT_WORKITEM_CALL_BACK rt_work_item_callback, 212 void *context, 213 const char *sz_id); 214 215 void odm_start_work_item( 216 PRT_WORK_ITEM p_rt_work_item); 217 218 void odm_stop_work_item( 219 PRT_WORK_ITEM p_rt_work_item); 220 221 void odm_free_work_item( 222 PRT_WORK_ITEM p_rt_work_item); 223 224 void odm_schedule_work_item( 225 PRT_WORK_ITEM p_rt_work_item); 226 227 boolean 228 odm_is_work_item_scheduled( 229 PRT_WORK_ITEM p_rt_work_item); 230 #endif 231 232 /*@ 233 * ODM Timer relative API. 234 */ 235 void ODM_delay_ms(u32 ms); 236 237 void ODM_delay_us(u32 us); 238 239 void ODM_sleep_ms(u32 ms); 240 241 void ODM_sleep_us(u32 us); 242 243 void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer, 244 u32 ms_delay); 245 246 void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer, 247 void *call_back_func, void *context, 248 const char *sz_id); 249 250 void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer); 251 252 void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer); 253 254 /*ODM FW relative API.*/ 255 256 enum hal_status 257 phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type, 258 u32 offset, u32 data, u32 mask, enum rf_path e_rf_path, 259 u32 delay_time); 260 261 void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len, 262 u8 *cmd_buffer); 263 264 u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, 265 u8 *tmp_buf); 266 267 u64 odm_get_current_time(struct dm_struct *dm); 268 u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time); 269 270 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \ 271 (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) 272 273 void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name, 274 u8 *val); 275 276 void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm, 277 enum _HAL_DEF_VARIABLE e_variable, 278 void *value); 279 280 #endif 281 282 void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm, 283 enum rf_path path, u8 channel, 284 u8 rate_section); 285 286 u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate, 287 u8 band_width, u8 channel); 288 289 u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data, 290 boolean b_pseu_do_test); 291 292 void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset, 293 u32 *data); 294 295 enum hal_status 296 odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment); 297 298 enum hal_status 299 odm_dpk_by_fw(struct dm_struct *dm); 300 301 void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index, 302 struct cmn_sta_info *pcmn_sta_info); 303 304 void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx, 305 struct cmn_sta_info *pcmn_sta_info); 306 307 void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type); 308 309 void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm); 310 311 void phydm_iqk_wait(struct dm_struct *dm, u32 timeout); 312 u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate); 313 314 void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap); 315 void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *), 316 void *context); 317 u8 phydm_get_tx_rate(struct dm_struct *dm); 318 u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path, 319 u8 rate, u8 bandwidth, u8 channel); 320 321 s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path, 322 u8 rate, u8 bandwidth, u8 channel); 323 324 u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num); 325 326 u64 phydm_division64(u64 x, u64 y); 327 328 #endif /* @__ODM_INTERFACE_H__ */ 329