1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMDIG_H__ 27 #define __PHYDMDIG_H__ 28 29 /* 2020.08.13 Add IFS-CLM/FAHM in dig fa source for more accurate fa info*/ 30 #define DIG_VERSION "3.9" 31 32 #define DIG_HW 0 33 #define DIG_LIMIT_PERIOD 60 /*60 sec*/ 34 35 /*@--------------------Define ---------------------------------------*/ 36 37 /*@=== [DIG Boundary] ========================================*/ 38 /*@DIG coverage mode*/ 39 #define DIG_MAX_COVERAGR 0x26 40 #define DIG_MIN_COVERAGE 0x1c 41 #define DIG_MAX_OF_MIN_COVERAGE 0x22 42 43 /*@[DIG Balance mode]*/ 44 #if (DIG_HW == 1) 45 #define DIG_MAX_BALANCE_MODE 0x32 46 #else 47 #define DIG_MAX_BALANCE_MODE 0x3e 48 #endif 49 #define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a 50 51 /*@[DIG Performance mode]*/ 52 #define DIG_MAX_PERFORMANCE_MODE 0x5a 53 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/ 54 #define DIG_MIN_PERFORMANCE 0x20 55 56 /*@DIG DFS function*/ 57 #define DIG_MAX_DFS 0x28 58 #define DIG_MIN_DFS 0x20 59 60 /*@DIG LPS function*/ 61 #define DIG_MAX_LPS 0x3e 62 #define DIG_MIN_LPS 0x20 63 64 #ifdef PHYDM_TDMA_DIG_SUPPORT 65 #define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/ 66 #define DIG_TIMER_MS 250 67 #define ONE_SEC_MS 1000 68 #endif 69 70 /*@=== [DIG FA Threshold] ======================================*/ 71 72 /*Normal*/ 73 #define DM_DIG_FA_TH0 500 74 #define DM_DIG_FA_TH1 750 75 76 /*@LPS*/ 77 #define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */ 78 #define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */ 79 #define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */ 80 81 #define RSSI_OFFSET_DIG_LPS 5 82 #define DIG_RECORD_NUM 4 83 84 /*==== [FA duration] =======================================*/ 85 /*[PHYDM-406]*/ 86 #define OFDM_FA_EXP_DURATION 12 /*us*/ 87 #define CCK_FA_EXP_DURATION 175 /*us*/ 88 89 /*@--------------------Enum-----------------------------------*/ 90 enum phydm_dig_mode { 91 PHYDM_DIG_PERFORAMNCE_MODE = 0, 92 PHYDM_DIG_COVERAGE_MODE = 1, 93 }; 94 95 enum phydm_dig_trend { 96 DIG_STABLE = 0, 97 DIG_INCREASING = 1, 98 DIG_DECREASING = 2 99 }; 100 101 enum phydm_fw_dig_mode_e { 102 DIG_PERFORMANCE_MODE = 0, 103 DIG_COVERAGE_MODE = 1, 104 DIG_LPS_MODE = 2 105 }; 106 107 #ifdef PHYDM_TDMA_DIG_SUPPORT 108 enum upd_type { 109 ENABLE_TDMA, 110 MODE_DECISION 111 }; 112 113 enum tdma_opmode { 114 MODE_PERFORMANCE = 1, 115 MODE_COVERAGE = 2 116 }; 117 118 #ifdef IS_USE_NEW_TDMA 119 enum tdma_dig_timer { 120 INIT_TDMA_DIG_TIMMER, 121 CANCEL_TDMA_DIG_TIMMER, 122 RELEASE_TDMA_DIG_TIMMER 123 }; 124 125 enum tdma_dig_state { 126 TDMA_DIG_LOW_STATE = 0, 127 TDMA_DIG_HIGH_STATE = 1, 128 NORMAL_DIG = 2 129 }; 130 #endif 131 #endif 132 133 /*@--------------------Define Struct-----------------------------------*/ 134 #ifdef CFG_DIG_DAMPING_CHK 135 struct phydm_dig_recorder_strcut { 136 u8 igi_bitmap; /*@Don't add any new parameter before this*/ 137 u8 igi_history[DIG_RECORD_NUM]; 138 u32 fa_history[DIG_RECORD_NUM]; 139 u8 damping_limit_en; 140 u8 damping_limit_val; /*@Limit IGI_dyn_min*/ 141 u32 limit_time; 142 u8 limit_rssi; 143 }; 144 #endif 145 146 struct phydm_mcc_dig { 147 u8 mcc_rssi_A; 148 u8 mcc_rssi_B; 149 }; 150 151 struct phydm_dig_struct { 152 #ifdef CFG_DIG_DAMPING_CHK 153 struct phydm_dig_recorder_strcut dig_recorder_t; 154 u8 dig_dl_en; /*@damping limit function enable*/ 155 #endif 156 boolean fw_dig_enable; 157 boolean is_dbg_fa_th; 158 u8 cur_ig_value; 159 boolean igi_dyn_up_hit; 160 u8 igi_trend; 161 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 162 u8 igi_backup; 163 u8 rx_gain_range_max; /*@dig_dynamic_max*/ 164 u8 rx_gain_range_min; /*@dig_dynamic_min*/ 165 u8 dm_dig_max; /*@Absolutly upper bound*/ 166 u8 dm_dig_min; /*@Absolutly lower bound*/ 167 u8 dig_max_of_min; /*@Absolutly max of min*/ 168 u32 ant_div_rssi_max; 169 u8 *is_p2p_in_process; 170 u32 fa_th[3]; 171 u32 dm_dig_fa_th1; 172 u8 fa_source; 173 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ 174 RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\ 175 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\ 176 RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT ||\ 177 RTL8723F_SUPPORT) 178 u8 rf_gain_idx; 179 u8 agc_table_idx; 180 u8 big_jump_lmt[16]; 181 u8 enable_adjust_big_jump:1; 182 u8 big_jump_step1:3; 183 u8 big_jump_step2:2; 184 u8 big_jump_step3:2; 185 #endif 186 u8 upcheck_init_val; 187 u8 lv0_ratio_reciprocal; 188 u8 lv1_ratio_reciprocal; 189 #ifdef PHYDM_TDMA_DIG_SUPPORT 190 u8 cur_ig_value_tdma; 191 u8 low_ig_value; 192 u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/ 193 u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/ 194 u8 pre_tdma_dig_cnt; 195 u8 sec_factor; 196 u32 cur_timestamp; 197 u32 pre_timestamp; 198 u32 fa_start_timestamp; 199 u32 fa_end_timestamp; 200 u32 fa_acc_1sec_timestamp; 201 #ifdef IS_USE_NEW_TDMA 202 u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/ 203 /*@dynamic upper bound for L/H state*/ 204 u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES]; 205 /*@dynamic lower bound for L/H state*/ 206 u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES]; 207 /*To distinguish current state(L-sate or H-state)*/ 208 #endif 209 u8 tdma_force_l_igi; 210 u8 tdma_force_h_igi; 211 #endif 212 }; 213 214 struct phydm_fa_struct { 215 u32 cnt_parity_fail; 216 u32 cnt_rate_illegal; 217 u32 cnt_crc8_fail; 218 u32 cnt_crc8_fail_vhta; 219 u32 cnt_crc8_fail_vhtb; 220 u32 cnt_mcs_fail; 221 u32 cnt_mcs_fail_vht; 222 u32 cnt_ofdm_fail; 223 u32 cnt_ofdm_fail_pre; /* @For RTL8881A */ 224 u32 cnt_cck_fail; 225 u32 cnt_all; 226 u32 cnt_all_accumulated; 227 u32 cnt_all_pre; 228 u32 cnt_fast_fsync; 229 u32 cnt_sb_search_fail; 230 u32 cnt_ofdm_cca; 231 u32 cnt_cck_cca; 232 u32 cnt_cca_all; 233 u32 cnt_bw_usc; 234 u32 cnt_bw_lsc; 235 u32 cnt_cck_crc32_error; 236 u32 cnt_cck_crc32_ok; 237 u32 cnt_ofdm_crc32_error; 238 u32 cnt_ofdm_crc32_ok; 239 u32 cnt_ht_crc32_error; 240 u32 cnt_ht_crc32_ok; 241 u32 cnt_ht_crc32_error_agg; 242 u32 cnt_ht_crc32_ok_agg; 243 u32 cnt_vht_crc32_error; 244 u32 cnt_vht_crc32_ok; 245 u32 cnt_crc32_error_all; 246 u32 cnt_crc32_ok_all; 247 u32 time_fa_all; 248 u32 time_fa_exp; /*FA duration, [PHYDM-406]*/ 249 u32 time_fa_ifs_clm; /*FA duration, [PHYDM-406]*/ 250 u32 time_fa_fahm; /*FA duration, [PHYDM-406]*/ 251 boolean cck_block_enable; 252 boolean ofdm_block_enable; 253 u32 dbg_port0; 254 boolean edcca_flag; 255 u8 ofdm2_rate_idx; 256 u32 cnt_ofdm2_crc32_error; 257 u32 cnt_ofdm2_crc32_ok; 258 u8 ofdm2_pcr; 259 u8 ht2_rate_idx; 260 u32 cnt_ht2_crc32_error; 261 u32 cnt_ht2_crc32_ok; 262 u8 ht2_pcr; 263 u8 vht2_rate_idx; 264 u32 cnt_vht2_crc32_error; 265 u32 cnt_vht2_crc32_ok; 266 u8 vht2_pcr; 267 u32 cnt_cck_txen; 268 u32 cnt_cck_txon; 269 u32 cnt_ofdm_txen; 270 u32 cnt_ofdm_txon; 271 }; 272 273 #ifdef PHYDM_TDMA_DIG_SUPPORT 274 struct phydm_fa_acc_struct { 275 u32 cnt_parity_fail; 276 u32 cnt_rate_illegal; 277 u32 cnt_crc8_fail; 278 u32 cnt_mcs_fail; 279 u32 cnt_ofdm_fail; 280 u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/ 281 u32 cnt_cck_fail; 282 u32 cnt_all; 283 u32 cnt_all_pre; 284 u32 cnt_fast_fsync; 285 u32 cnt_sb_search_fail; 286 u32 cnt_ofdm_cca; 287 u32 cnt_cck_cca; 288 u32 cnt_cca_all; 289 u32 cnt_cck_crc32_error; 290 u32 cnt_cck_crc32_ok; 291 u32 cnt_ofdm_crc32_error; 292 u32 cnt_ofdm_crc32_ok; 293 u32 cnt_ht_crc32_error; 294 u32 cnt_ht_crc32_ok; 295 u32 cnt_vht_crc32_error; 296 u32 cnt_vht_crc32_ok; 297 u32 cnt_crc32_error_all; 298 u32 cnt_crc32_ok_all; 299 u32 cnt_all_1sec; 300 u32 cnt_cca_all_1sec; 301 u32 cnt_cck_fail_1sec; 302 }; 303 304 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 305 306 /*@--------------------Function declaration-----------------------------*/ 307 void phydm_write_dig_reg(void *dm_void, u8 igi); 308 309 void odm_write_dig(void *dm_void, u8 current_igi); 310 311 u8 phydm_get_igi(void *dm_void, enum bb_path path); 312 313 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len); 314 315 void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type, 316 enum phydm_pause_level pause_level, u8 igi_value); 317 318 #ifdef PHYDM_HW_IGI 319 void phydm_hwigi(void *dm_void); 320 321 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used, 322 char *output, u32 *_out_len); 323 #endif 324 325 void phydm_dig_init(void *dm_void); 326 327 void phydm_dig(void *dm_void); 328 329 void phydm_dig_lps_32k(void *dm_void); 330 331 void phydm_dig_by_rssi_lps(void *dm_void); 332 333 void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min); 334 335 u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi); 336 337 void phydm_false_alarm_counter_statistics(void *dm_void); 338 339 u32 phydm_get_edcca_report(void * dm_void); 340 341 #ifdef PHYDM_TDMA_DIG_SUPPORT 342 void phydm_set_tdma_dig_timer(void *dm_void); 343 344 void phydm_tdma_dig_timer_check(void *dm_void); 345 346 void phydm_tdma_dig(void *dm_void); 347 348 void phydm_tdma_false_alarm_counter_check(void *dm_void); 349 350 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void); 351 352 void phydm_false_alarm_counter_reset(void *dm_void); 353 354 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en); 355 356 void phydm_false_alarm_counter_acc_reset(void *dm_void); 357 358 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input); 359 360 #ifdef IS_USE_NEW_TDMA 361 void phydm_tdma_dig_timers(void *dm_void, u8 state); 362 363 void phydm_tdma_dig_cbk(void *dm_void); 364 365 void phydm_tdma_dig_workitem_callback(void *dm_void); 366 367 void phydm_tdma_fa_cnt_chk(void *dm_void); 368 369 void phydm_tdma_low_dig(void *dm_void); 370 371 void phydm_tdma_high_dig(void *dm_void); 372 373 void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, 374 u8 cur_tdma_dig_state); 375 #endif /*@#ifdef IS_USE_NEW_TDMA*/ 376 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 377 378 void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel); 379 380 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, 381 u32 *_out_len); 382 383 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable, 384 u8 *para4, u8 *para8); 385 386 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used, 387 char *output, u32 *_out_len); 388 389 #ifdef CONFIG_MCC_DM 390 void phydm_mcc_igi_cal(void *dm_void); 391 #endif 392 393 #endif 394