1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef CFG_DIG_DAMPING_CHK
phydm_dig_recorder_reset(void * dm_void)34 void phydm_dig_recorder_reset(void *dm_void)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
38 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
39
40 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
41
42 odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
43 sizeof(struct phydm_dig_recorder_strcut));
44 }
45
phydm_dig_recorder(void * dm_void,u8 igi_curr,u32 fa_metrics)46 void phydm_dig_recorder(void *dm_void, u8 igi_curr,
47 u32 fa_metrics)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
51 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
52 u8 igi_pre = dig_rc->igi_history[0];
53 u8 igi_up = 0;
54
55 if (!dm->is_linked)
56 return;
57
58 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
59
60 if (dm->first_connect) {
61 phydm_dig_recorder_reset(dm);
62 dig_rc->igi_history[0] = igi_curr;
63 dig_rc->fa_history[0] = fa_metrics;
64 return;
65 }
66
67 if (igi_curr % 2)
68 igi_curr--;
69
70 igi_pre = dig_rc->igi_history[0];
71 igi_up = (igi_curr > igi_pre) ? 1 : 0;
72 dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
73
74 dig_rc->igi_history[3] = dig_rc->igi_history[2];
75 dig_rc->igi_history[2] = dig_rc->igi_history[1];
76 dig_rc->igi_history[1] = dig_rc->igi_history[0];
77 dig_rc->igi_history[0] = igi_curr;
78
79 dig_rc->fa_history[3] = dig_rc->fa_history[2];
80 dig_rc->fa_history[2] = dig_rc->fa_history[1];
81 dig_rc->fa_history[1] = dig_rc->fa_history[0];
82 dig_rc->fa_history[0] = fa_metrics;
83
84 PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
85 dig_rc->igi_history[3], dig_rc->igi_history[2],
86 dig_rc->igi_history[1], dig_rc->igi_history[0]);
87 PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
88 dig_rc->fa_history[3], dig_rc->fa_history[2],
89 dig_rc->fa_history[1], dig_rc->fa_history[0]);
90 PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
91 (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
92 (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
93 (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
94 (u8)(dig_rc->igi_bitmap & BIT(0)),
95 dig_rc->igi_bitmap);
96 }
97
phydm_dig_damping_chk(void * dm_void)98 void phydm_dig_damping_chk(void *dm_void)
99 {
100 struct dm_struct *dm = (struct dm_struct *)dm_void;
101 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
102 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
103 u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
104 u8 diff1 = 0, diff2 = 0;
105 u32 fa_low_th = dig_t->fa_th[0];
106 u32 fa_high_th = dig_t->fa_th[1];
107 u32 fa_high_th2 = dig_t->fa_th[2];
108 u8 fa_pattern_match = 0;
109 u32 time_tmp = 0;
110
111 if (!dm->is_linked)
112 return;
113
114 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
115
116 /*@== Release Damping ================================================*/
117 if (dig_rc->damping_limit_en) {
118 PHYDM_DBG(dm, DBG_DIG,
119 "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
120 dig_rc->limit_time, dm->phydm_sys_up_time);
121
122 time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
123
124 if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
125 time_tmp < dm->phydm_sys_up_time) {
126 dig_rc->damping_limit_en = 0;
127 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
128 dm->rssi_min, dig_rc->limit_rssi);
129 }
130 return;
131 }
132
133 /*@== Damping Pattern Check===========================================*/
134 PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
135
136 switch (igi_bitmap_4bit) {
137 case 0x5:
138 /*@ 4b'0101
139 * IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
140 * FA: [3] >high1 ->[2] <low ->[1] >high1 ->[0] <low ->[new] <low
141 *
142 * IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
143 * FA: [3] >high2 ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
144 */
145 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
146 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
147
148 if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
149 diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
150
151 if (dig_rc->fa_history[0] < fa_low_th &&
152 dig_rc->fa_history[1] > fa_high_th &&
153 dig_rc->fa_history[2] < fa_low_th &&
154 dig_rc->fa_history[3] > fa_high_th) {
155 /*@Check each fa element*/
156 fa_pattern_match = 1;
157 }
158 break;
159 case 0x9:
160 /*@ 4b'1001
161 * IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
162 * FA: [3] <low ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
163 */
164 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
165 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
166
167 if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
168 diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
169
170 if (dig_rc->fa_history[0] < fa_low_th &&
171 dig_rc->fa_history[1] > fa_high_th2 &&
172 dig_rc->fa_history[2] < fa_low_th &&
173 dig_rc->fa_history[3] < fa_low_th) {
174 /*@Check each fa element*/
175 fa_pattern_match = 1;
176 }
177 break;
178 default:
179 break;
180 }
181
182 if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
183 dig_rc->damping_limit_en = 1;
184 dig_rc->damping_limit_val = dig_rc->igi_history[0];
185 dig_rc->limit_time = dm->phydm_sys_up_time;
186 dig_rc->limit_rssi = dm->rssi_min;
187
188 PHYDM_DBG(dm, DBG_DIG,
189 "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
190 dig_rc->damping_limit_val,
191 dig_rc->limit_time, dig_rc->limit_rssi);
192 }
193
194 PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
195 }
196 #endif
197
phydm_fa_threshold_check(void * dm_void,boolean is_dfs_band)198 void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
199 {
200 struct dm_struct *dm = (struct dm_struct *)dm_void;
201 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
202 u8 i = 0;
203
204 dig_t->dm_dig_fa_th1 = DM_DIG_FA_TH1;
205
206 if (dig_t->is_dbg_fa_th) {
207 PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
208 } else if (dm->is_linked) {
209 if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
210 dig_t->fa_th[0] = 500;
211 dig_t->fa_th[1] = 750;
212 dig_t->fa_th[2] = 1000;
213 } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
214 (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
215 dig_t->fa_th[0] = 125;
216 dig_t->fa_th[1] = 250;
217 dig_t->fa_th[2] = 500;
218 } else {
219 dig_t->fa_th[0] = 250;
220 dig_t->fa_th[1] = 500;
221 dig_t->fa_th[2] = 750;
222 }
223 } else {
224 if (is_dfs_band) { /* @For DFS band and no link */
225
226 dig_t->fa_th[0] = 250;
227 dig_t->fa_th[1] = 1000;
228 dig_t->fa_th[2] = 2000;
229 } else {
230 dig_t->fa_th[0] = 2000;
231 dig_t->fa_th[1] = 4000;
232 dig_t->fa_th[2] = 5000;
233 }
234 }
235
236 if ((dig_t->fa_source >= 1) && (dig_t->fa_source <= 3)) {
237 for (i = 0; i < 3; i++)
238 dig_t->fa_th[i] *= OFDM_FA_EXP_DURATION;
239
240 dig_t->dm_dig_fa_th1 *= OFDM_FA_EXP_DURATION;
241 }
242
243 PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
244 dig_t->fa_th[1], dig_t->fa_th[2]);
245 }
246
phydm_set_big_jump_step(void * dm_void,u8 curr_igi)247 void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
248 {
249 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
250 struct dm_struct *dm = (struct dm_struct *)dm_void;
251 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
252 u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
253 u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
254 u8 i;
255
256 if (dig_t->enable_adjust_big_jump == 0)
257 return;
258
259 for (i = 0; i <= dig_t->big_jump_step1; i++) {
260 if ((curr_igi + step1[i]) > big_jump_lmt) {
261 if (i != 0)
262 i = i - 1;
263 break;
264 } else if (i == dig_t->big_jump_step1) {
265 break;
266 }
267 }
268 if (dm->support_ic_type & ODM_RTL8822B)
269 odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
270 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
271 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
272
273 PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
274 dig_t->big_jump_step1, big_jump_lmt);
275 #endif
276 }
277
278 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_write_dig_reg_jgr3(void * dm_void,u8 igi)279 void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
280 {
281 struct dm_struct *dm = (struct dm_struct *)dm_void;
282 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
283
284 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
285
286 /* Set IGI value */
287 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
288 return;
289
290 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
291
292 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
293 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
294 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
295 #endif
296
297 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
298 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
299 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
300 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
301 }
302 #endif
303 }
304
phydm_get_igi_reg_val_jgr3(void * dm_void,enum bb_path path)305 u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
306 {
307 struct dm_struct *dm = (struct dm_struct *)dm_void;
308 u32 val = 0;
309
310 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
311
312 /* Set IGI value */
313 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
314 return (u8)val;
315
316 if (path == BB_PATH_A)
317 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
318 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
319 else if (path == BB_PATH_B)
320 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
321 #endif
322
323 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
324 else if (path == BB_PATH_C)
325 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
326 #endif
327
328 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
329 else if (path == BB_PATH_D)
330 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
331 #endif
332 return (u8)val;
333 }
334
phydm_fa_cnt_statistics_jgr3(void * dm_void)335 void phydm_fa_cnt_statistics_jgr3(void *dm_void)
336 {
337 struct dm_struct *dm = (struct dm_struct *)dm_void;
338 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
339 u32 ret_value = 0;
340 u32 cck_enable = 0;
341
342 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
343 return;
344
345 ret_value = odm_get_bb_reg(dm, R_0x2de4, MASKDWORD);
346 fa_t->cnt_cck_txen = (ret_value & 0xffff);
347 fa_t->cnt_cck_txon = ((ret_value & 0xffff0000) >> 16);
348 ret_value = odm_get_bb_reg(dm, R_0x2de0, MASKDWORD);
349 fa_t->cnt_ofdm_txen = (ret_value & 0xffff);
350 fa_t->cnt_ofdm_txon = ((ret_value & 0xffff0000) >> 16);
351
352 ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
353 fa_t->cnt_fast_fsync = ret_value & 0xffff;
354 fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
355
356 ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
357 fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
358
359 ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
360 fa_t->cnt_rate_illegal = ret_value & 0xffff;
361 fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
362
363 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
364 fa_t->cnt_mcs_fail = ret_value & 0xffff;
365
366 /* read CCK CRC32 counter */
367 if (dm->support_ic_type & ODM_RTL8723F)
368 ret_value = odm_get_bb_reg(dm, R_0x2aac, MASKDWORD);
369 else
370 ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
371 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
372 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
373
374 /* read OFDM CRC32 counter */
375 ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
376 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
377 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
378
379 /* read OFDM2 CRC32 counter */
380 ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD);
381 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
382 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
383
384 /* read HT CRC32 counter */
385 ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
386 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
387 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
388
389 /* read HT2 CRC32 counter */
390 ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD);
391 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
392 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
393
394 /*for VHT part */
395 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
396 ODM_RTL8814B)) {
397 /*read VHT CRC32 counter */
398 ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
399 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
400 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
401
402 /*read VHT2 CRC32 counter */
403 ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD);
404 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
405 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
406
407 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
408 fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
409
410 ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
411 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
412 fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
413 } else {
414 fa_t->cnt_vht_crc32_error = 0;
415 fa_t->cnt_vht_crc32_ok = 0;
416 fa_t->cnt_vht2_crc32_error = 0;
417 fa_t->cnt_vht2_crc32_ok = 0;
418 fa_t->cnt_mcs_fail_vht = 0;
419 fa_t->cnt_crc8_fail_vhta = 0;
420 fa_t->cnt_crc8_fail_vhtb = 0;
421 }
422
423 /* @calculate OFDM FA counter instead of reading brk_cnt*/
424 fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
425 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
426 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
427 fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
428
429 /* Read CCK FA counter */
430 if (dm->support_ic_type & ODM_RTL8723F){
431 ret_value= odm_get_bb_reg(dm, R_0x2aa8, MASKLWORD);
432 fa_t->cnt_cck_fail=(ret_value&0xffff)+((ret_value&0xffff0000)>>16);
433 }
434 else
435 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
436
437 /* read CCK/OFDM CCA counter */
438 ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
439 fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
440 if (dm->support_ic_type & ODM_RTL8723F)
441 ret_value = odm_get_bb_reg(dm, R_0x2aa0, MASKDWORD);
442 fa_t->cnt_cck_cca = ret_value & 0xffff;
443
444 /* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
445 if (dm->support_ic_type & ODM_RTL8723F)
446 cck_enable = odm_get_bb_reg(dm, R_0x2a24, BIT(13));
447 else
448 cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
449
450 if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
451 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
452 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
453 } else {
454 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
455 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
456 }
457 }
458
459 #endif
460
phydm_write_dig_reg_c50(void * dm_void,u8 igi)461 void phydm_write_dig_reg_c50(void *dm_void, u8 igi)
462 {
463 struct dm_struct *dm = (struct dm_struct *)dm_void;
464
465 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
466
467 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
468
469 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
470 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
471 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
472 #endif
473
474 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
475 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
476 odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
477 odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
478 }
479 #endif
480 }
481
phydm_write_dig_reg(void * dm_void,u8 igi)482 void phydm_write_dig_reg(void *dm_void, u8 igi)
483 {
484 struct dm_struct *dm = (struct dm_struct *)dm_void;
485 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
486 u8 rf_gain = 0;
487
488 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
489
490 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
491 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
492 phydm_write_dig_reg_jgr3(dm, igi);
493 else
494 #endif
495 phydm_write_dig_reg_c50(dm, igi);
496
497 #if (RTL8721D_SUPPORT)
498 if (dm->invalid_mode) {
499 if (igi <= 0x10)
500 rf_gain = 0xfa;
501 else if (igi <= 0x40)
502 rf_gain = 0xe3 + 0x20 - (igi >> 1);
503 else if (igi <= 0x50)
504 rf_gain = 0xcb - (igi >> 1);
505 else if (igi <= 0x5e)
506 rf_gain = 0x92 - (igi >> 1);
507 else if (igi <= 0x64)
508 rf_gain = 0x74 - (igi >> 1);
509 else
510 rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
511 odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
512 }
513 #endif
514
515 if (igi == dig_t->cur_ig_value)
516 dig_t->igi_trend = DIG_STABLE;
517 else if (igi > dig_t->cur_ig_value)
518 dig_t->igi_trend = DIG_INCREASING;
519 else
520 dig_t->igi_trend = DIG_DECREASING;
521
522 PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n",
523 dig_t->cur_ig_value, igi);
524
525 dig_t->cur_ig_value = igi;
526 }
527
odm_write_dig(void * dm_void,u8 new_igi)528 void odm_write_dig(void *dm_void, u8 new_igi)
529 {
530 struct dm_struct *dm = (struct dm_struct *)dm_void;
531 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
532 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
533
534 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
535
536 /* @1 Check IGI by upper bound */
537 if (adaptivity->igi_lmt_en &&
538 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
539 new_igi = adaptivity->adapt_igi_up;
540
541 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
542 new_igi);
543 }
544
545 #if (RTL8192F_SUPPORT)
546 if ((dm->support_ic_type & ODM_RTL8192F) &&
547 dm->cut_version == ODM_CUT_A &&
548 new_igi > 0x38) {
549 new_igi = 0x38;
550 PHYDM_DBG(dm, DBG_DIG,
551 "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
552 }
553 #endif
554
555 if (dig_t->cur_ig_value != new_igi) {
556 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
557 /* @Modify big jump step for 8822B and 8197F */
558 if (dm->support_ic_type &
559 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
560 phydm_set_big_jump_step(dm, new_igi);
561 #endif
562
563 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
564 /* Set IGI value of CCK for new CCK AGC */
565 if (dm->cck_new_agc &&
566 (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
567 odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
568 #endif
569
570 /*@Add by YuChen for USB IO too slow issue*/
571 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
572 if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
573 if (new_igi < dig_t->cur_ig_value ||
574 dm->is_pause_dig) {
575 dig_t->cur_ig_value = new_igi;
576 phydm_adaptivity(dm);
577 }
578 } else {
579 if (new_igi > dig_t->cur_ig_value) {
580 dig_t->cur_ig_value = new_igi;
581 phydm_adaptivity(dm);
582 }
583 }
584 }
585 phydm_write_dig_reg(dm, new_igi);
586 } else {
587 dig_t->igi_trend = DIG_STABLE;
588 }
589
590 PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n",
591 ((dig_t->igi_trend == DIG_STABLE) ? "=" :
592 ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")),
593 new_igi);
594 }
595
phydm_get_igi_reg_val(void * dm_void,enum bb_path path)596 u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
597 {
598 struct dm_struct *dm = (struct dm_struct *)dm_void;
599 u32 val = 0;
600 u32 bit_map = ODM_BIT(IGI, dm);
601
602 switch (path) {
603 case BB_PATH_A:
604 val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
605 break;
606 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
607 case BB_PATH_B:
608 val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
609 break;
610 #endif
611
612 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
613 case BB_PATH_C:
614 val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
615 break;
616 #endif
617
618 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
619 case BB_PATH_D:
620 val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
621 break;
622 #endif
623
624 default:
625 break;
626 }
627
628 return (u8)val;
629 }
630
phydm_get_igi(void * dm_void,enum bb_path path)631 u8 phydm_get_igi(void *dm_void, enum bb_path path)
632 {
633 struct dm_struct *dm = (struct dm_struct *)dm_void;
634 u8 val = 0;
635
636 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
637 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
638 val = phydm_get_igi_reg_val_jgr3(dm, path);
639 else
640 #endif
641 val = phydm_get_igi_reg_val(dm, path);
642
643 return val;
644 }
645
phydm_set_dig_val(void * dm_void,u32 * val_buf,u8 val_len)646 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
647 {
648 struct dm_struct *dm = (struct dm_struct *)dm_void;
649
650 if (val_len != 1) {
651 PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
652 return;
653 }
654
655 odm_write_dig(dm, (u8)(*val_buf));
656 }
657
odm_pause_dig(void * dm_void,enum phydm_pause_type type,enum phydm_pause_level lv,u8 igi_input)658 void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
659 enum phydm_pause_level lv, u8 igi_input)
660 {
661 struct dm_struct *dm = (struct dm_struct *)dm_void;
662 u8 rpt = false;
663 u32 igi = (u32)igi_input;
664
665 PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
666 lv, igi);
667
668 switch (type) {
669 case PHYDM_PAUSE:
670 case PHYDM_PAUSE_NO_SET: {
671 dm->is_pause_dig = true;
672 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
673 break;
674 }
675
676 case PHYDM_RESUME: {
677 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
678 dm->is_pause_dig = false;
679 break;
680 }
681 default:
682 PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
683 break;
684 }
685
686 PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
687 }
688
689 boolean
phydm_dig_abort(void * dm_void)690 phydm_dig_abort(void *dm_void)
691 {
692 struct dm_struct *dm = (struct dm_struct *)dm_void;
693 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
694 void *adapter = dm->adapter;
695 #endif
696
697 /* support_ability */
698 if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
699 (!(dm->support_ability & ODM_BB_DIG))) {
700 PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
701 return true;
702 }
703
704 if (dm->pause_ability & ODM_BB_DIG) {
705 PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
706 dm->pause_lv_table.lv_dig);
707 return true;
708 }
709
710 if (*dm->is_scan_in_process) {
711 PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
712 return true;
713 }
714
715 if (dm->dm_dig_table.fw_dig_enable) {
716 PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n");
717 return true;
718 }
719
720 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
721 #if OS_WIN_FROM_WIN7(OS_VERSION)
722 if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
723 PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
724 return true;
725 }
726 #endif
727 #endif
728
729 return false;
730 }
731
732 #ifdef PHYDM_HW_IGI
733 #ifdef BB_RAM_SUPPORT
phydm_rd_hwigi_pre_setting(void * dm_void,u32 * _used,char * output,u32 * _out_len)734 void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output,
735 u32 *_out_len)
736 {
737 struct dm_struct *dm = (struct dm_struct *)dm_void;
738 u32 used = *_used;
739 u32 out_len = *_out_len;
740 u8 igi_ofst = 0x0;
741 u32 t1, t2, t3 = 0x0;
742
743 igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0);
744 t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400;
745 t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400;
746 t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400;
747
748 PDM_SNPF(out_len, used, output + used, out_len - used,
749 "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n",
750 igi_ofst, t1, t2, t3);
751 }
752
phydm_set_hwigi_pre_setting(void * dm_void,u8 igi_ofst,u8 t1,u8 t2,u8 t3)753 void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2,
754 u8 t3)
755 {
756 struct dm_struct *dm = (struct dm_struct *)dm_void;
757 u32 reg_0x1e80 = 0;
758
759 reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24);
760 odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80);
761 }
762
phydm_rd_hwigi_table(void * dm_void,u8 macid,u32 * _used,char * output,u32 * _out_len)763 void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output,
764 u32 *_out_len)
765 {
766 struct dm_struct *dm = (struct dm_struct *)dm_void;
767 u32 used = *_used;
768 u32 out_len = *_out_len;
769 boolean hwigi_en = false;
770 u8 hwigi = 0x0;
771 u8 hwigi_rx_offset = 0x0;
772 u32 reg_0x1e84 = 0x0;
773
774 reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/
775 reg_0x1e84 |= BIT(31); /*read_en*/
776 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
777
778 hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15));
779 hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00);
780 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
781
782 PDM_SNPF(out_len, used, output + used, out_len - used,
783 "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en,
784 hwigi);
785
786 *_used = used;
787 *_out_len = out_len;
788 }
789
phydm_wt_hwigi_table(void * dm_void,u8 macid,boolean hwigi_en,u8 hwigi)790 void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi)
791 {
792 struct dm_struct *dm = (struct dm_struct *)dm_void;
793 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
794 u32 reg_0x1e84 = 0;
795
796 if (macid > 63)
797 macid = 63;
798
799 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
800 dm_ram_per_sta->hw_igi_en = hwigi_en;
801 dm_ram_per_sta->hw_igi = hwigi;
802
803 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
804 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
805 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
806 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
807
808 reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f);
809 reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/
810 reg_0x1e84 |= BIT(30); /*write_en*/
811 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
812 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/
813 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/
814 }
815
phydm_rst_hwigi(void * dm_void)816 void phydm_rst_hwigi(void *dm_void)
817 {
818 struct dm_struct *dm = (struct dm_struct *)dm_void;
819 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
820 u32 reg_0x1e84 = 0;
821 u8 i = 0;
822
823 PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n");
824
825 for (i = 0; i < 64; i++) {
826 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
827 dm_ram_per_sta->hw_igi_en = false;
828 dm_ram_per_sta->hw_igi = 0x0;
829
830 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
831 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
832 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
833 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
834
835 reg_0x1e84 |= (i & 0x3f) << 24;
836 reg_0x1e84 |= BIT(30);
837 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
838 }
839
840 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
841 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
842 }
843
phydm_hwigi_init(void * dm_void)844 void phydm_hwigi_init(void *dm_void)
845 {
846 struct dm_struct *dm = (struct dm_struct *)dm_void;
847 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
848 u8 igi_ofst = 0x0;
849 u8 t1 = 0x0;
850 u8 t2 = 0x0;
851 u8 t3 = 0x0;
852
853 t1 = 0x55; /*34 us*/
854 t3 = 0x55; /*34 us*/
855
856 bb_ctrl->hwigi_watchdog_en = false;
857 phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3);
858 }
859
phydm_hwigi(void * dm_void)860 void phydm_hwigi(void *dm_void)
861 {
862 struct dm_struct *dm = (struct dm_struct *)dm_void;
863 struct cmn_sta_info *sta = NULL;
864 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
865 struct rssi_info *rssi = NULL;
866 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
867 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
868 u8 sta_cnt = 0;
869 u8 i = 0;
870 u8 hwigi = 0x0;
871 u8 macid = 0;
872 u8 macid_cnt = 0;
873 u64 macid_cur = 0;
874 u64 macid_diff = 0;
875 u64 macid_mask = 0;
876
877 if (!(bb_ctrl->hwigi_watchdog_en)) {
878 return;
879 }
880
881 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
882 sta = dm->phydm_sta_info[i];
883 if (is_sta_active(sta)) {
884 sta_cnt++;
885
886 if (sta->mac_id > 63)
887 macid = 63;
888 else
889 macid = sta->mac_id;
890
891 dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid];
892 rssi = &sta->rssi_stat;
893 macid_mask = (u64)BIT(sta->mac_id);
894 bb_ctrl->hwigi_macid_is_linked |= macid_mask;
895 macid_cur |= macid_mask;
896 PHYDM_DBG(dm, DBG_DIG,
897 "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n",
898 i, sta->mac_id, rssi->rssi,
899 dm_ram_per_sta->hw_igi_en,
900 dm_ram_per_sta->hw_igi);
901
902 hwigi = MAX_2((u8)(rssi->rssi + 10),
903 dig_t->cur_ig_value);
904
905 if (hwigi > DIG_MAX_PERFORMANCE_MODE)
906 hwigi = DIG_MAX_PERFORMANCE_MODE;
907 else if (hwigi < DIG_MIN_PERFORMANCE)
908 hwigi = DIG_MIN_PERFORMANCE;
909
910 if (dm_ram_per_sta->hw_igi == hwigi) {
911 PHYDM_DBG(dm, DBG_DIG,
912 "hwigi not change!\n");
913 } else {
914
915 PHYDM_DBG(dm, DBG_DIG,
916 "hwigi update: ((0x%x)) -> ((0x%x))\n",
917 dm_ram_per_sta->hw_igi, hwigi);
918
919 phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi);
920 }
921
922 if (sta_cnt == dm->number_linked_client)
923 break;
924 }
925 }
926 macid_diff = bb_ctrl->hwigi_macid_is_linked ^ macid_cur;
927 if (macid_diff)
928 bb_ctrl->hwigi_macid_is_linked &= ~macid_diff;
929 while (macid_diff) {
930 if (macid_diff & 0x1)
931 phydm_wt_hwigi_table(dm, macid_cnt, false, 0x0);
932 macid_cnt++;
933 macid_diff >>= 1;
934 }
935 }
936
phydm_hwigi_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)937 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
938 char *output, u32 *_out_len)
939 {
940 struct dm_struct *dm = (struct dm_struct *)dm_void;
941 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
942 char help[] = "-h";
943 u32 used = *_used;
944 u32 out_len = *_out_len;
945 u32 var1[7] = {0};
946 u8 i = 0;
947
948 if ((strcmp(input[1], help) == 0)) {
949 PDM_SNPF(out_len, used, output + used, out_len - used,
950 "Disable/Enable watchdog : {0/1}\n");
951 PDM_SNPF(out_len, used, output + used, out_len - used,
952 "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n");
953 PDM_SNPF(out_len, used, output + used, out_len - used,
954 "Set hwigi table: {3} {en} {value} {macid}\n");
955 PDM_SNPF(out_len, used, output + used, out_len - used,
956 "Read hwigi : {4} {macid(0~63), 255:all}\n");
957 PDM_SNPF(out_len, used, output + used, out_len - used,
958 "Reset all hwigi : {5}\n");
959 } else {
960 for (i = 0; i < 7; i++) {
961 if (input[i + 1])
962 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
963 &var1[i]);
964 }
965 switch (var1[0]) {
966 case 0:
967 case 1:
968 bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false;
969 break;
970 case 2:
971 phydm_set_hwigi_pre_setting(dm, (u8)var1[1],
972 (u8)var1[2], (u8)var1[3],
973 (u8)var1[4]);
974 break;
975 case 3:
976 phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1],
977 (boolean)var1[2]);
978 break;
979 case 4:
980 phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len);
981 if ((u8)var1[1] == 0xff)
982 for (i = 0; i < 64; i++)
983 phydm_rd_hwigi_table(dm, i, &used,
984 output, &out_len);
985 else
986 phydm_rd_hwigi_table(dm, (u8)var1[1], &used,
987 output, &out_len);
988 break;
989 case 5:
990 phydm_rst_hwigi(dm);
991 break;
992 }
993 }
994 *_used = used;
995 *_out_len = out_len;
996 }
997 #endif
998 #endif
999
phydm_dig_init(void * dm_void)1000 void phydm_dig_init(void *dm_void)
1001 {
1002 struct dm_struct *dm = (struct dm_struct *)dm_void;
1003 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1004 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1005 struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
1006 #endif
1007 u32 ret_value = 0;
1008 u8 i;
1009
1010 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1011 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
1012 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
1013
1014 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1015
1016 dig_t->fa_th[0] = 250;
1017 dig_t->fa_th[1] = 500;
1018 dig_t->fa_th[2] = 750;
1019 dig_t->dm_dig_fa_th1 = DM_DIG_FA_TH1;
1020 dig_t->is_dbg_fa_th = false;
1021 dig_t->igi_dyn_up_hit = false;
1022 dig_t->fw_dig_enable = false;
1023 dig_t->fa_source = 0;
1024
1025 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1026 /* @For RTL8881A */
1027 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1028 #endif
1029
1030 dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
1031 dig_t->rx_gain_range_min = dig_t->cur_ig_value;
1032
1033 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
1034 if (dm->support_ic_type &
1035 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
1036 dig_t->enable_adjust_big_jump = 1;
1037
1038 if (dm->support_ic_type & ODM_RTL8822B)
1039 ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
1040 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1041 ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
1042
1043 dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
1044 dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
1045 dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
1046
1047 for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
1048 if (dig_t->big_jump_lmt[i] == 0)
1049 dig_t->big_jump_lmt[i] = 0x64;
1050 /* Set -10dBm as default value */
1051 }
1052 }
1053 #endif
1054
1055 #ifdef PHYDM_TDMA_DIG_SUPPORT
1056 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1057 dm->original_dig_restore = true;
1058 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
1059 dm->tdma_dig_timer_ms = DIG_TIMER_MS;
1060 #endif
1061 dig_t->tdma_force_l_igi = 0xff;
1062 dig_t->tdma_force_h_igi = 0xff;
1063 #endif
1064 #ifdef CFG_DIG_DAMPING_CHK
1065 phydm_dig_recorder_reset(dm);
1066 dig_t->dig_dl_en = 1;
1067 #endif
1068
1069 #ifdef PHYDM_HW_IGI
1070 phydm_hwigi_init(dm);
1071 #endif
1072 }
phydm_dig_abs_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1073 void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1074 {
1075 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1076 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
1077
1078 if (is_dfs_band) {
1079 if (*dm->band_width == CHANNEL_WIDTH_20){
1080 if (dm->support_ic_type &
1081 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
1082 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
1083 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
1084 else
1085 dig_t->dm_dig_min = DIG_MIN_DFS;
1086 }
1087 else
1088 dig_t->dm_dig_min = DIG_MIN_DFS;
1089 }
1090 else
1091 dig_t->dm_dig_min = DIG_MIN_DFS;
1092
1093 dig_t->dig_max_of_min = DIG_MIN_DFS;
1094 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1095 } else if (!dm->is_linked) {
1096 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
1097 dig_t->dm_dig_min = DIG_MIN_COVERAGE;
1098 } else {
1099 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
1100 /*service > 2 devices*/
1101 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1102 #if (DIG_HW == 1)
1103 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
1104 #else
1105 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
1106 #endif
1107 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
1108 /*service 1 devices*/
1109 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
1110 dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1111 /*dig_max shouldn't be too high because of adaptivity*/
1112 dig_t->dm_dig_max =
1113 MIN_2((adapt->th_l2h + 40),
1114 DIG_MAX_PERFORMANCE_MODE);
1115 else
1116 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
1117
1118 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
1119 }
1120
1121 if (dm->support_ic_type &
1122 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
1123 dig_t->dm_dig_min = 0x1c;
1124 else if (dm->support_ic_type & ODM_RTL8197F)
1125 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
1126 else
1127 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
1128 }
1129
1130 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
1131 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
1132 }
1133
phydm_dig_dym_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1134 void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1135 {
1136 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1137 #ifdef CFG_DIG_DAMPING_CHK
1138 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
1139 #endif
1140 u8 offset = 15, tmp_max = 0;
1141 u8 max_of_rssi_min = 0;
1142
1143 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
1144
1145 if (!dm->is_linked) {
1146 /*@if no link, always stay at lower bound*/
1147 dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
1148 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1149
1150 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
1151 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1152 return;
1153 }
1154
1155 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
1156
1157 /* @DIG lower bound */
1158 if (is_dfs_band)
1159 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1160 else if (dm->rssi_min > dig_t->dig_max_of_min)
1161 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1162 else if (dm->rssi_min < dig_t->dm_dig_min)
1163 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1164 else
1165 dig_t->rx_gain_range_min = dm->rssi_min;
1166
1167 #ifdef CFG_DIG_DAMPING_CHK
1168 /*@Limit Dyn min by damping*/
1169 if (dig_t->dig_dl_en &&
1170 dig_rc->damping_limit_en &&
1171 dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
1172 PHYDM_DBG(dm, DBG_DIG,
1173 "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
1174 dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
1175
1176 dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
1177 }
1178 #endif
1179
1180 /* @DIG upper bound */
1181 tmp_max = dig_t->rx_gain_range_min + offset;
1182 if (dig_t->rx_gain_range_min != dm->rssi_min) {
1183 max_of_rssi_min = dm->rssi_min + offset;
1184 if (tmp_max > max_of_rssi_min)
1185 tmp_max = max_of_rssi_min;
1186 }
1187
1188 if (tmp_max > dig_t->dm_dig_max)
1189 dig_t->rx_gain_range_max = dig_t->dm_dig_max;
1190 else if (tmp_max < dig_t->dm_dig_min)
1191 dig_t->rx_gain_range_max = dig_t->dm_dig_min;
1192 else
1193 dig_t->rx_gain_range_max = tmp_max;
1194
1195 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1196 /* @1 Force Lower Bound for AntDiv */
1197 if (!dm->is_one_entry_only &&
1198 (dm->support_ability & ODM_BB_ANT_DIV) &&
1199 (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
1200 dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
1201 if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
1202 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1203 else
1204 dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
1205
1206 PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
1207 dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
1208 }
1209 #endif
1210
1211 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
1212 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1213 }
1214
phydm_dig_abnormal_case(struct dm_struct * dm)1215 void phydm_dig_abnormal_case(struct dm_struct *dm)
1216 {
1217 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1218
1219 /* @Abnormal lower bound case */
1220 if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
1221 dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
1222
1223 PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
1224 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1225 }
1226
phydm_new_igi_by_fa(struct dm_struct * dm,u8 igi,u32 fa_metrics,u8 * step_size)1227 u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_metrics,
1228 u8 *step_size)
1229 {
1230 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1231
1232 if (fa_metrics > dig_t->fa_th[2])
1233 igi = igi + step_size[0];
1234 else if (fa_metrics > dig_t->fa_th[1])
1235 igi = igi + step_size[1];
1236 else if (fa_metrics < dig_t->fa_th[0])
1237 igi = igi - step_size[2];
1238
1239 return igi;
1240 }
1241
phydm_get_new_igi(struct dm_struct * dm,u8 igi,u32 fa_metrics,boolean is_dfs_band)1242 u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_metrics,
1243 boolean is_dfs_band)
1244 {
1245 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1246 u8 step[3] = {0};
1247
1248 if (dm->is_linked) {
1249 if (dm->pre_rssi_min <= dm->rssi_min) {
1250 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
1251 step[0] = 2;
1252 step[1] = 1;
1253 step[2] = 2;
1254 } else {
1255 step[0] = 4;
1256 step[1] = 2;
1257 step[2] = 2;
1258 }
1259 } else {
1260 step[0] = 2;
1261 step[1] = 1;
1262 step[2] = 2;
1263 }
1264
1265 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
1266 step[0]);
1267
1268 if (dm->first_connect) {
1269 if (is_dfs_band) {
1270 if (dm->rssi_min > DIG_MAX_DFS)
1271 igi = DIG_MAX_DFS;
1272 else
1273 igi = dm->rssi_min;
1274 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
1275 dig_t->rx_gain_range_max);
1276 } else {
1277 igi = dig_t->rx_gain_range_min;
1278 }
1279
1280 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1281 #if (RTL8812A_SUPPORT)
1282 if (dm->support_ic_type == ODM_RTL8812)
1283 odm_config_bb_with_header_file(dm,
1284 CONFIG_BB_AGC_TAB_DIFF);
1285 #endif
1286 #endif
1287 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
1288 } else if (dm->is_linked) {
1289 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
1290 /* @4 Abnormal # beacon case */
1291 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1292 if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
1293 fa_metrics < dig_t->dm_dig_fa_th1 && dm->bsta_state &&
1294 dm->support_ic_type != ODM_RTL8723D &&
1295 dm->support_ic_type != ODM_RTL8822C) {
1296 dig_t->rx_gain_range_min = 0x1c;
1297 igi = dig_t->rx_gain_range_min;
1298 PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
1299 dm->phy_dbg_info.num_qry_beacon_pkt, igi);
1300 } else {
1301 igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step);
1302 }
1303 #else
1304 igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step);
1305 #endif
1306 } else {
1307 /* @2 Before link */
1308 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
1309
1310 if (dm->first_disconnect) {
1311 igi = dig_t->dm_dig_min;
1312 PHYDM_DBG(dm, DBG_DIG,
1313 "First disconnect:foce IGI to lower bound\n");
1314 } else {
1315 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
1316 igi, fa_metrics);
1317
1318 igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step);
1319 }
1320 }
1321
1322 /*@Check IGI by dyn-upper/lower bound */
1323 if (igi < dig_t->rx_gain_range_min)
1324 igi = dig_t->rx_gain_range_min;
1325
1326 if (igi >= dig_t->rx_gain_range_max) {
1327 igi = dig_t->rx_gain_range_max;
1328 dig_t->igi_dyn_up_hit = true;
1329 } else {
1330 dig_t->igi_dyn_up_hit = false;
1331 }
1332 PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n",
1333 dig_t->igi_dyn_up_hit);
1334
1335 PHYDM_DBG(dm, DBG_DIG, "fa_metrics = %d, IGI: 0x%x -> 0x%x\n",
1336 fa_metrics, dig_t->cur_ig_value, igi);
1337
1338 return igi;
1339 }
1340
phydm_dig_dfs_mode_en(void * dm_void)1341 boolean phydm_dig_dfs_mode_en(void *dm_void)
1342 {
1343 struct dm_struct *dm = (struct dm_struct *)dm_void;
1344 boolean dfs_mode_en = false;
1345
1346 /* @Modify lower bound for DFS band */
1347 if (dm->is_dfs_band) {
1348 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1349 dfs_mode_en = true;
1350 #else
1351 if (phydm_dfs_master_enabled(dm))
1352 dfs_mode_en = true;
1353 #endif
1354 PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
1355 }
1356 return dfs_mode_en;
1357 }
1358
phydm_dig_fa_source(void * dm_void,u8 fa_source,u32 * fa_metrics)1359 void phydm_dig_fa_source(void *dm_void, u8 fa_source, u32 *fa_metrics)
1360 {
1361 struct dm_struct *dm = (struct dm_struct *)dm_void;
1362 struct phydm_fa_struct *fa = &dm->false_alm_cnt;
1363
1364 switch (fa_source) {
1365 case 1:
1366 *fa_metrics = fa->time_fa_exp;
1367 break;
1368 #ifdef IFS_CLM_SUPPORT
1369 case 2:
1370 if (fa->time_fa_ifs_clm) {
1371 *fa_metrics = fa->time_fa_ifs_clm;
1372 } else {
1373 fa_source = 1;
1374 *fa_metrics = fa->time_fa_exp;
1375 }
1376 break;
1377 #endif
1378 #ifdef FAHM_SUPPORT
1379 case 3:
1380 if (fa->time_fa_fahm) {
1381 *fa_metrics = fa->time_fa_fahm;
1382 } else {
1383 fa_source = 1;
1384 *fa_metrics = fa->time_fa_exp;
1385 }
1386 break;
1387 #endif
1388 default:
1389 break;
1390 }
1391
1392 PHYDM_DBG(dm, DBG_DIG,
1393 "fa_source:%d, fa_cnt=%d ,time_fa_exp=%d, fa_metrics=%d\n",
1394 fa_source, fa->cnt_all, fa->time_fa_exp, *fa_metrics);
1395 }
1396
phydm_dig(void * dm_void)1397 void phydm_dig(void *dm_void)
1398 {
1399 struct dm_struct *dm = (struct dm_struct *)dm_void;
1400 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1401 struct phydm_fa_struct *fa = &dm->false_alm_cnt;
1402 #ifdef PHYDM_TDMA_DIG_SUPPORT
1403 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1404 #endif
1405 u8 igi = dig_t->cur_ig_value;
1406 u8 new_igi = 0x20;
1407 u32 fa_metrics = fa->cnt_all;
1408 boolean dfs_mode_en = false;
1409
1410 PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
1411
1412 #ifdef PHYDM_DCC_ENHANCE
1413 if (dm->dm_dcc_info.dcc_en) {
1414 fa_metrics = fa->cnt_ofdm_fail; /*OFDM FA only*/
1415 dig_t->fa_source = 0;
1416 }
1417 #endif
1418
1419 #ifdef PHYDM_TDMA_DIG_SUPPORT
1420 if (!(dm->original_dig_restore)) {
1421 if (dig_t->cur_ig_value_tdma == 0)
1422 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1423
1424 igi = dig_t->cur_ig_value_tdma;
1425 fa_metrics = falm_cnt_acc->cnt_all_1sec;
1426 dig_t->fa_source = 0;
1427 }
1428 #endif
1429
1430 if (phydm_dig_abort(dm)) {
1431 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1432 return;
1433 }
1434
1435 if (dig_t->fa_source)
1436 phydm_dig_fa_source(dm, dig_t->fa_source, &fa_metrics);
1437
1438 PHYDM_DBG(dm, DBG_DIG,
1439 "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
1440 dm->is_linked, dm->rssi_min,
1441 dm->first_connect, dm->first_disconnect);
1442
1443 PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
1444 (*dm->bb_op_mode ? "Balance" : "Performance"));
1445
1446 /*@DFS mode enable check*/
1447 dfs_mode_en = phydm_dig_dfs_mode_en(dm);
1448
1449 #ifdef CFG_DIG_DAMPING_CHK
1450 /*Record IGI History*/
1451 phydm_dig_recorder(dm, igi, fa_metrics);
1452
1453 /*@DIG Damping Check*/
1454 phydm_dig_damping_chk(dm);
1455 #endif
1456
1457 /*@Absolute Boundary Decision */
1458 phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
1459
1460 /*@Dynamic Boundary Decision*/
1461 phydm_dig_dym_boundary_decision(dm, dfs_mode_en);
1462
1463 /*@Abnormal case check*/
1464 phydm_dig_abnormal_case(dm);
1465
1466 /*@FA threshold decision */
1467 phydm_fa_threshold_check(dm, dfs_mode_en);
1468
1469 /*Select new IGI by FA */
1470 new_igi = phydm_get_new_igi(dm, igi, fa_metrics, dfs_mode_en);
1471
1472 /* @1 Update status */
1473 #ifdef PHYDM_TDMA_DIG_SUPPORT
1474 if (!(dm->original_dig_restore)) {
1475 dig_t->cur_ig_value_tdma = new_igi;
1476 /*@It is possible fa_acc_1sec_tsf >= */
1477 /*@1sec while tdma_dig_state == 0*/
1478 if (dig_t->tdma_dig_state != 0)
1479 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
1480 } else
1481 #endif
1482 odm_write_dig(dm, new_igi);
1483 }
1484
phydm_dig_lps_32k(void * dm_void)1485 void phydm_dig_lps_32k(void *dm_void)
1486 {
1487 struct dm_struct *dm = (struct dm_struct *)dm_void;
1488 u8 current_igi = dm->rssi_min;
1489
1490 odm_write_dig(dm, current_igi);
1491 }
1492
phydm_dig_by_rssi_lps(void * dm_void)1493 void phydm_dig_by_rssi_lps(void *dm_void)
1494 {
1495 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1496 struct dm_struct *dm = (struct dm_struct *)dm_void;
1497 struct phydm_fa_struct *falm_cnt;
1498
1499 u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
1500 u8 current_igi = dm->rssi_min;
1501
1502 falm_cnt = &dm->false_alm_cnt;
1503 if (phydm_dig_abort(dm))
1504 return;
1505
1506 current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
1507 PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
1508
1509 /* Using FW PS mode to make IGI */
1510 /* @Adjust by FA in LPS MODE */
1511 if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
1512 current_igi = current_igi + 4;
1513 else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
1514 current_igi = current_igi + 2;
1515 else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
1516 current_igi = current_igi - 2;
1517
1518 /* @Lower bound checking */
1519
1520 /* RSSI Lower bound check */
1521 if ((dm->rssi_min - 10) > DIG_MIN_LPS)
1522 rssi_lower = (dm->rssi_min - 10);
1523 else
1524 rssi_lower = DIG_MIN_LPS;
1525
1526 /* Upper and Lower Bound checking */
1527 if (current_igi > DIG_MAX_LPS)
1528 current_igi = DIG_MAX_LPS;
1529 else if (current_igi < rssi_lower)
1530 current_igi = rssi_lower;
1531
1532 PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
1533 falm_cnt->cnt_all, dm->rssi_min, current_igi);
1534 odm_write_dig(dm, current_igi);
1535 #endif
1536 }
1537
phydm_get_dig_coverage(void * dm_void,u8 * max,u8 * min)1538 void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min)
1539 {
1540 *min = DIG_MIN_COVERAGE;
1541 *max = DIG_MAX_PERFORMANCE_MODE;
1542 }
1543
phydm_get_igi_for_target_pin_scan(void * dm_void,u8 rssi)1544 u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi)
1545 {
1546 struct dm_struct *dm = (struct dm_struct *)dm_void;
1547 u8 igi = 0;
1548 u8 max = 0;
1549 u8 min = 0;
1550
1551 igi = rssi + 10;
1552
1553 phydm_get_dig_coverage(dm, &max, &min);
1554
1555 if (igi > max)
1556 igi = max;
1557 else if (igi < min)
1558 igi = min;
1559
1560 return igi;
1561 }
1562
1563 /* @3============================================================
1564 * 3 FASLE ALARM CHECK
1565 * 3============================================================
1566 */
phydm_false_alarm_counter_reg_reset(void * dm_void)1567 void phydm_false_alarm_counter_reg_reset(void *dm_void)
1568 {
1569 struct dm_struct *dm = (struct dm_struct *)dm_void;
1570 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
1571 #ifdef PHYDM_TDMA_DIG_SUPPORT
1572 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1573 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1574 #endif
1575 u32 false_alm_cnt = 0;
1576
1577 #ifdef PHYDM_TDMA_DIG_SUPPORT
1578 if (!(dm->original_dig_restore)) {
1579 if (dig_t->cur_ig_value_tdma == 0)
1580 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1581
1582 false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
1583 } else
1584 #endif
1585 {
1586 false_alm_cnt = falm_cnt->cnt_all;
1587 }
1588
1589 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1590 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1591 if (dm->support_ic_type & ODM_RTL8723F) {
1592 /* @reset CCK FA and CCA counter */
1593 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
1594 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
1595 } else {
1596 /* @reset CCK FA counter */
1597 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
1598 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
1599
1600 /* @reset CCK CCA counter */
1601 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
1602 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
1603 }
1604 /* @Disable common rx clk gating => WLANBB-1106*/
1605 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);
1606 /* @reset OFDM CCA counter, OFDM FA counter*/
1607 phydm_reset_bb_hw_cnt(dm);
1608 /* @Enable common rx clk gating => WLANBB-1106*/
1609 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);
1610 }
1611 #endif
1612 #if (ODM_IC_11N_SERIES_SUPPORT)
1613 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1614 /* @reset false alarm counter registers*/
1615 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
1616 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
1617 odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
1618 odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
1619
1620 /* @update ofdm counter*/
1621 /* @update page C counter*/
1622 odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
1623 /* @update page D counter*/
1624 odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
1625
1626 /* @reset CCK CCA counter*/
1627 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
1628 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
1629
1630 /* @reset CCK FA counter*/
1631 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
1632 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
1633
1634 /* @reset CRC32 counter*/
1635 odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
1636 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
1637 }
1638 #endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
1639
1640 #if (ODM_IC_11AC_SERIES_SUPPORT)
1641 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1642 #if (RTL8881A_SUPPORT)
1643 /* @Reset FA counter by enable/disable OFDM */
1644 if ((dm->support_ic_type == ODM_RTL8881A) &&
1645 false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
1646 /* reset OFDM */
1647 odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
1648 odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
1649 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1650 PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
1651 }
1652 #endif /* @#if (RTL8881A_SUPPORT) */
1653
1654 /* @reset OFDM FA countner */
1655 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
1656 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
1657
1658 /* @reset CCK FA counter */
1659 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
1660 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
1661
1662 /* @reset CCA counter */
1663 phydm_reset_bb_hw_cnt(dm);
1664 }
1665 #endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
1666 }
1667
phydm_false_alarm_counter_reg_hold(void * dm_void)1668 void phydm_false_alarm_counter_reg_hold(void *dm_void)
1669 {
1670 struct dm_struct *dm = (struct dm_struct *)dm_void;
1671
1672 if (dm->support_ic_type & ODM_RTL8723F)
1673 return;
1674
1675 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1676 /* @hold cck counter */
1677 odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
1678 odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
1679 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1680 /*@hold ofdm counter*/
1681 /*@hold page C counter*/
1682 odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
1683 /*@hold page D counter*/
1684 odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
1685
1686 /*@hold cck counter*/
1687 odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
1688 odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
1689 }
1690 }
1691
1692 #if (ODM_IC_11N_SERIES_SUPPORT)
phydm_fa_cnt_statistics_n(void * dm_void)1693 void phydm_fa_cnt_statistics_n(void *dm_void)
1694 {
1695 struct dm_struct *dm = (struct dm_struct *)dm_void;
1696 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1697 u32 reg = 0;
1698
1699 if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
1700 return;
1701
1702 /* @hold ofdm & cck counter */
1703 phydm_false_alarm_counter_reg_hold(dm);
1704
1705 reg = odm_get_bb_reg(dm, R_0x9d0, MASKDWORD);
1706 fa_t->cnt_cck_txon = (reg & 0xffff);
1707 fa_t->cnt_cck_txen = ((reg & 0xffff0000) >> 16);
1708 reg = odm_get_bb_reg(dm, R_0x9cc, MASKDWORD);
1709 fa_t->cnt_ofdm_txon = (reg & 0xffff);
1710 fa_t->cnt_ofdm_txen = ((reg & 0xffff0000) >> 16);
1711
1712 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
1713 fa_t->cnt_fast_fsync = (reg & 0xffff);
1714 fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
1715
1716 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
1717 fa_t->cnt_ofdm_cca = (reg & 0xffff);
1718 fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
1719
1720 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
1721 fa_t->cnt_rate_illegal = (reg & 0xffff);
1722 fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
1723
1724 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
1725 fa_t->cnt_mcs_fail = (reg & 0xffff);
1726
1727 fa_t->cnt_ofdm_fail =
1728 fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
1729 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
1730 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
1731
1732 /* read CCK CRC32 counter */
1733 fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
1734 fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
1735
1736 /* read OFDM CRC32 counter */
1737 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
1738 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1739 fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
1740
1741 /* read OFDM2 CRC32 counter */
1742 reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD);
1743 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1744 fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff;
1745
1746 /* read HT CRC32 counter */
1747 reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1748 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1749 fa_t->cnt_ht_crc32_ok = reg & 0xffff;
1750
1751 /* read HT2 CRC32 counter */
1752 reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
1753 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1754 fa_t->cnt_ht2_crc32_ok = reg & 0xffff;
1755
1756 /* read VHT CRC32 counter */
1757 fa_t->cnt_vht_crc32_error = 0;
1758 fa_t->cnt_vht_crc32_ok = 0;
1759
1760 #if (RTL8723D_SUPPORT)
1761 if (dm->support_ic_type == ODM_RTL8723D) {
1762 /* read HT CRC32 agg counter */
1763 reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
1764 fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
1765 fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
1766 }
1767 #endif
1768
1769 #if (RTL8188E_SUPPORT)
1770 if (dm->support_ic_type == ODM_RTL8188E) {
1771 reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
1772 fa_t->cnt_bw_lsc = (reg & 0xffff);
1773 fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
1774 }
1775 #endif
1776
1777 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
1778 fa_t->cnt_cck_fail = reg;
1779
1780 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
1781 fa_t->cnt_cck_fail += (reg & 0xff) << 8;
1782
1783 reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
1784 fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
1785
1786 fa_t->cnt_all_pre = fa_t->cnt_all;
1787
1788 fa_t->cnt_all = fa_t->cnt_fast_fsync +
1789 fa_t->cnt_sb_search_fail +
1790 fa_t->cnt_parity_fail +
1791 fa_t->cnt_rate_illegal +
1792 fa_t->cnt_crc8_fail +
1793 fa_t->cnt_mcs_fail +
1794 fa_t->cnt_cck_fail;
1795
1796 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
1797 }
1798 #endif
1799
1800 #if (ODM_IC_11AC_SERIES_SUPPORT)
phydm_fa_cnt_statistics_ac(void * dm_void)1801 void phydm_fa_cnt_statistics_ac(void *dm_void)
1802 {
1803 struct dm_struct *dm = (struct dm_struct *)dm_void;
1804 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1805 u32 ret_value = 0;
1806 u32 cck_enable = 0;
1807
1808 if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
1809 return;
1810
1811 ret_value = odm_get_bb_reg(dm, R_0xf50, MASKDWORD);
1812 fa_t->cnt_cck_txen = (ret_value & 0xffff);
1813 fa_t->cnt_ofdm_txen = ((ret_value & 0xffff0000) >> 16);
1814 fa_t->cnt_cck_txon = (u16)odm_get_bb_reg(dm, R_0xfcc, MASKLWORD);
1815 fa_t->cnt_ofdm_txon = (u16)odm_get_bb_reg(dm, R_0xfc8, MASKHWORD);
1816
1817 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
1818 fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
1819
1820 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
1821 fa_t->cnt_sb_search_fail = ret_value & 0xffff;
1822
1823 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
1824 fa_t->cnt_parity_fail = ret_value & 0xffff;
1825 fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
1826
1827 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
1828 fa_t->cnt_crc8_fail = ret_value & 0xffff;
1829 fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
1830
1831 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
1832 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
1833 fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
1834
1835 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
1836 fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
1837
1838 /* read OFDM FA counter */
1839 fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
1840
1841 /* Read CCK FA counter */
1842 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1843
1844 /* read CCK/OFDM CCA counter */
1845 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1846 fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1847 fa_t->cnt_cck_cca = ret_value & 0xffff;
1848
1849 /* read CCK CRC32 counter */
1850 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
1851 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
1852 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
1853
1854 /* read OFDM CRC32 counter */
1855 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
1856 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1857 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1858
1859 /* read OFDM2 CRC32 counter */
1860 ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD);
1861 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
1862 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
1863
1864 /* read HT CRC32 counter */
1865 ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
1866 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1867 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
1868
1869 /* read HT2 CRC32 counter */
1870 ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD);
1871 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
1872 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1873
1874 /* read VHT CRC32 counter */
1875 ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
1876 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
1877 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
1878
1879 /*read VHT2 CRC32 counter */
1880 ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
1881 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
1882 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1883
1884 #if (RTL8881A_SUPPORT)
1885 if (dm->support_ic_type == ODM_RTL8881A) {
1886 u32 tmp = 0;
1887
1888 if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
1889 tmp = fa_t->cnt_ofdm_fail_pre;
1890 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1891 fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
1892 } else {
1893 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1894 }
1895
1896 PHYDM_DBG(dm, DBG_FA_CNT,
1897 "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
1898 fa_t->cnt_ofdm_fail_pre, tmp);
1899 }
1900 #endif
1901
1902 cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1903
1904 if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
1905 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
1906 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
1907 } else {
1908 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
1909 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
1910 }
1911 }
1912 #endif
1913
phydm_get_edcca_report(void * dm_void)1914 u32 phydm_get_edcca_report(void *dm_void)
1915 {
1916 struct dm_struct *dm = (struct dm_struct *)dm_void;
1917 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1918 u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
1919 u32 val = 0;
1920
1921 if (dm->support_ic_type & ODM_RTL8723D) {
1922 val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
1923 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1924 val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
1925 } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
1926 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
1927 val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
1928 else
1929 val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
1930 phydm_release_bb_dbg_port(dm);
1931 }
1932
1933 return val;
1934 }
1935
phydm_get_dbg_port_info(void * dm_void)1936 void phydm_get_dbg_port_info(void *dm_void)
1937 {
1938 struct dm_struct *dm = (struct dm_struct *)dm_void;
1939 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1940
1941 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1942 fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);
1943 } else {
1944 /*set debug port to 0x0*/
1945 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
1946 fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
1947 phydm_release_bb_dbg_port(dm);
1948 }
1949 }
1950
1951 fa_t->edcca_flag = (boolean)phydm_get_edcca_report(dm);
1952
1953 PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n",
1954 fa_t->dbg_port0, fa_t->edcca_flag);
1955 }
1956
phydm_set_crc32_cnt2_rate(void * dm_void,u8 rate_idx)1957 void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx)
1958 {
1959 struct dm_struct *dm = (struct dm_struct *)dm_void;
1960 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1961 boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx);
1962 boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx);
1963 boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx);
1964 u32 reg_addr = 0x0;
1965 u32 ofdm_rate_bitmask = 0x0;
1966 u32 ht_mcs_bitmask = 0x0;
1967 u32 vht_mcs_bitmask = 0x0;
1968 u32 vht_ss_bitmask = 0x0;
1969 u8 rate = 0x0;
1970 u8 ss = 0x0;
1971
1972 if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate)
1973 PHYDM_DBG(dm, DBG_FA_CNT,
1974 "[FA CNT] rate_idx = (0x%x) is not supported !\n",
1975 rate_idx);
1976
1977 switch (dm->ic_ip_series) {
1978 case PHYDM_IC_N:
1979 reg_addr = R_0xf04;
1980 ofdm_rate_bitmask = 0x0000f000;
1981 ht_mcs_bitmask = 0x007f0000;
1982 break;
1983 case PHYDM_IC_AC:
1984 reg_addr = R_0xb04;
1985 ofdm_rate_bitmask = 0x0000f000;
1986 ht_mcs_bitmask = 0x007f0000;
1987 vht_mcs_bitmask = 0x0f000000;
1988 vht_ss_bitmask = 0x30000000;
1989 break;
1990 case PHYDM_IC_JGR3:
1991 reg_addr = R_0x1eb8;
1992 ofdm_rate_bitmask = 0x00000f00;
1993 ht_mcs_bitmask = 0x007f0000;
1994 vht_mcs_bitmask = 0x0000f000;
1995 vht_ss_bitmask = 0x000000c0;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 if (is_ofdm_rate) {
2002 rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx);
2003
2004 odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate);
2005 fa_t->ofdm2_rate_idx = rate_idx;
2006 } else if (is_ht_rate) {
2007 rate = phydm_rate_2_rate_digit(dm, rate_idx);
2008
2009 odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate);
2010 fa_t->ht2_rate_idx = rate_idx;
2011 } else if (is_vht_rate) {
2012 rate = phydm_rate_2_rate_digit(dm, rate_idx);
2013 ss = phydm_rate_to_num_ss(dm, rate_idx);
2014
2015 odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate);
2016 odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1);
2017 fa_t->vht2_rate_idx = rate_idx;
2018 }
2019 }
2020
phydm_fa_cnt_cal_fa_duration(void * dm_void)2021 void phydm_fa_cnt_cal_fa_duration(void *dm_void)
2022 {
2023 struct dm_struct *dm = (struct dm_struct *)dm_void;
2024 struct ccx_info *ccx = &dm->dm_ccx_info;
2025 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2026 u8 norm = 0; /*normalization*/
2027 boolean fahm_chk = false;
2028
2029 fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
2030 fa_t->cnt_sb_search_fail * 12 +
2031 fa_t->cnt_parity_fail * 28 +
2032 fa_t->cnt_rate_illegal * 28 +
2033 fa_t->cnt_crc8_fail * 20 +
2034 fa_t->cnt_crc8_fail_vhta * 28 +
2035 fa_t->cnt_mcs_fail_vht * 36 +
2036 fa_t->cnt_mcs_fail * 32 +
2037 fa_t->cnt_cck_fail * 80;
2038
2039 fa_t->time_fa_exp = fa_t->cnt_ofdm_fail * OFDM_FA_EXP_DURATION +
2040 fa_t->cnt_cck_fail * CCK_FA_EXP_DURATION;
2041
2042 fa_t->time_fa_ifs_clm = 0;
2043 fa_t->time_fa_fahm = 0;
2044
2045 #ifdef IFS_CLM_SUPPORT
2046 if (ccx->ccx_watchdog_result & IFS_CLM_SUCCESS) {
2047 norm = (u8)PHYDM_DIV(PHYDM_WATCH_DOG_PERIOD * S_TO_US,
2048 ccx->ifs_clm_period);
2049 fa_t->time_fa_ifs_clm = (ccx->ifs_clm_cckfa +
2050 ccx->ifs_clm_ofdmfa) * norm;
2051 }
2052 #endif
2053
2054 #ifdef FAHM_SUPPORT
2055 if (ccx->ccx_watchdog_result & FAHM_SUCCESS) {
2056 if (fa_t->cnt_cck_fail) {
2057 if (ccx->fahm_inclu_cck)
2058 fahm_chk = true;
2059 } else {
2060 fahm_chk = true;
2061 }
2062 }
2063
2064 if (fahm_chk) {
2065 norm = (u8)PHYDM_DIV(PHYDM_WATCH_DOG_PERIOD * S_TO_US,
2066 ccx->fahm_period);
2067 fa_t->time_fa_fahm = ccx->fahm_result_sum * norm;
2068 }
2069 #endif
2070 }
2071
phydm_false_alarm_counter_statistics(void * dm_void)2072 void phydm_false_alarm_counter_statistics(void *dm_void)
2073 {
2074 struct dm_struct *dm = (struct dm_struct *)dm_void;
2075 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2076 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
2077 u32 tmp = 0;
2078
2079 if (!(dm->support_ability & ODM_BB_FA_CNT))
2080 return;
2081
2082 PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
2083
2084 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
2085 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2086 phydm_fa_cnt_statistics_jgr3(dm);
2087 #endif
2088 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
2089 #if (ODM_IC_11N_SERIES_SUPPORT)
2090 phydm_fa_cnt_statistics_n(dm);
2091 #endif
2092 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2093 #if (ODM_IC_11AC_SERIES_SUPPORT)
2094 phydm_fa_cnt_statistics_ac(dm);
2095 #endif
2096 }
2097
2098 phydm_get_dbg_port_info(dm);
2099 phydm_false_alarm_counter_reg_reset(dm_void);
2100
2101 phydm_fa_cnt_cal_fa_duration(dm);
2102
2103 fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
2104 fa_t->cnt_ht_crc32_error +
2105 fa_t->cnt_ofdm_crc32_error +
2106 fa_t->cnt_cck_crc32_error;
2107
2108 fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
2109 fa_t->cnt_ht_crc32_ok +
2110 fa_t->cnt_ofdm_crc32_ok +
2111 fa_t->cnt_cck_crc32_ok;
2112
2113 PHYDM_DBG(dm, DBG_FA_CNT,
2114 "[Tx cnt] {CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON} = {%d, %d, %d, %d}\n",
2115 fa_t->cnt_cck_txen, fa_t->cnt_cck_txon, fa_t->cnt_ofdm_txen,
2116 fa_t->cnt_ofdm_txon);
2117 PHYDM_DBG(dm, DBG_FA_CNT,
2118 "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
2119 fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
2120 PHYDM_DBG(dm, DBG_FA_CNT,
2121 "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
2122 fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
2123 PHYDM_DBG(dm, DBG_FA_CNT,
2124 "[FA duration(us)] {exp, ifs_clm, fahm} = {%d, %d, %d}\n",
2125 fa_t->time_fa_exp, fa_t->time_fa_ifs_clm,
2126 fa_t->time_fa_fahm);
2127 PHYDM_DBG(dm, DBG_FA_CNT,
2128 "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
2129 fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
2130 fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
2131 PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
2132 fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
2133 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
2134 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
2135 PHYDM_DBG(dm, DBG_FA_CNT,
2136 "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
2137 fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
2138 fa_t->cnt_mcs_fail_vht);
2139 }
2140 #endif
2141
2142 PHYDM_DBG(dm, DBG_FA_CNT,
2143 "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
2144 fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
2145 fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
2146 fa_t->cnt_crc32_ok_all);
2147 PHYDM_DBG(dm, DBG_FA_CNT,
2148 "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
2149 fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
2150 fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
2151 fa_t->cnt_crc32_error_all);
2152
2153 if (fa_t->ofdm2_rate_idx) {
2154 tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok;
2155 fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100,
2156 tmp);
2157 phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf,
2158 PHYDM_SNPRINT_SIZE);
2159 PHYDM_DBG(dm, DBG_FA_CNT,
2160 "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2161 dbg_buf, fa_t->cnt_ofdm2_crc32_error,
2162 fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
2163 } else {
2164 phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M);
2165 }
2166
2167 if (fa_t->ht2_rate_idx) {
2168 tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok;
2169 fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100,
2170 tmp);
2171 phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
2172 PHYDM_SNPRINT_SIZE);
2173 PHYDM_DBG(dm, DBG_FA_CNT,
2174 "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2175 dbg_buf, fa_t->cnt_ht2_crc32_error,
2176 fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
2177 } else {
2178 phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0);
2179 }
2180
2181 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
2182 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
2183 if (fa_t->vht2_rate_idx) {
2184 tmp = fa_t->cnt_vht2_crc32_error +
2185 fa_t->cnt_vht2_crc32_ok;
2186 fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok *
2187 100, tmp);
2188 phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
2189 dbg_buf, PHYDM_SNPRINT_SIZE);
2190 PHYDM_DBG(dm, DBG_FA_CNT,
2191 "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2192 dbg_buf, fa_t->cnt_vht2_crc32_error,
2193 fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
2194 } else {
2195 phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0);
2196 }
2197 }
2198 #endif
2199 }
2200
phydm_fill_fw_dig_info(void * dm_void,boolean * enable,u8 * para4,u8 * para8)2201 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
2202 u8 *para4, u8 *para8) {
2203 struct dm_struct *dm = (struct dm_struct *)dm_void;
2204 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2205
2206 dig_t->fw_dig_enable = *enable;
2207 para8[0] = dig_t->rx_gain_range_max;
2208 para8[1] = dig_t->rx_gain_range_min;
2209 para8[2] = dm->number_linked_client;
2210 para4[0] = (u8)DIG_LPS_MODE;
2211 }
2212
phydm_crc32_cnt_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2213 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
2214 char *output, u32 *_out_len)
2215 {
2216 struct dm_struct *dm = (struct dm_struct *)dm_void;
2217 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2218 char help[] = "-h";
2219 u32 var1[10] = {0};
2220 u32 used = *_used;
2221 u32 out_len = *_out_len;
2222 u8 i = 0;
2223 u8 rate = 0x0;
2224
2225 if ((strcmp(input[1], help) == 0)) {
2226 PDM_SNPF(out_len, used, output + used, out_len - used,
2227 "[CRC32 Cnt] {rate_idx}\n");
2228 } else {
2229 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2230 rate = (u8)var1[0];
2231
2232 PDM_SNPF(out_len, used, output + used, out_len - used,
2233 "{rate}={0x%x}", rate);
2234
2235 phydm_set_crc32_cnt2_rate(dm, rate);
2236 }
2237 *_used = used;
2238 *_out_len = out_len;
2239 }
2240
2241 #ifdef PHYDM_TDMA_DIG_SUPPORT
phydm_set_tdma_dig_timer(void * dm_void)2242 void phydm_set_tdma_dig_timer(void *dm_void)
2243 {
2244 struct dm_struct *dm = (struct dm_struct *)dm_void;
2245 u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
2246 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2247 u32 timeout = 0;
2248 u32 current_time_stamp, diff_time_stamp, regb0 = 0;
2249
2250 /*some IC has no FREERUN_CUNT register, like 92E*/
2251 if (dm->support_ic_type & ODM_RTL8197F)
2252 current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
2253 else
2254 return;
2255
2256 timeout = current_time_stamp + delta_time_us;
2257
2258 diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
2259 dig_t->pre_timestamp = dig_t->cur_timestamp;
2260 dig_t->cur_timestamp = current_time_stamp;
2261
2262 /*@HIMR0, it shows HW interrupt mask*/
2263 regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
2264
2265 PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
2266 PHYDM_DBG(dm, DBG_DIG,
2267 "curr_time_stamp=%d, delta_time_us=%d\n",
2268 current_time_stamp, delta_time_us);
2269 PHYDM_DBG(dm, DBG_DIG,
2270 "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
2271 timeout, diff_time_stamp, regb0);
2272
2273 if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
2274 odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
2275 else {
2276 PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
2277 return;
2278 }
2279 }
2280
phydm_tdma_dig_timer_check(void * dm_void)2281 void phydm_tdma_dig_timer_check(void *dm_void)
2282 {
2283 struct dm_struct *dm = (struct dm_struct *)dm_void;
2284 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2285
2286 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
2287 dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
2288
2289 if (dig_t->tdma_dig_cnt == 0 ||
2290 dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
2291 if (dm->support_ability & ODM_BB_DIG) {
2292 #ifdef IS_USE_NEW_TDMA
2293 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
2294 ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
2295 ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
2296 ODM_RTL8723D| ODM_RTL8723F)) {
2297 PHYDM_DBG(dm, DBG_DIG,
2298 "Check fail, Restart timer\n\n");
2299 phydm_false_alarm_counter_reset(dm);
2300 odm_set_timer(dm, &dm->tdma_dig_timer,
2301 dm->tdma_dig_timer_ms);
2302 } else {
2303 PHYDM_DBG(dm, DBG_DIG,
2304 "Not support TDMADIG, no SW timer\n");
2305 }
2306 #else
2307 /*@if interrupt mask info is got.*/
2308 /*Reg0xb0 is no longer needed*/
2309 #if 0
2310 /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
2311 #endif
2312 PHYDM_DBG(dm, DBG_DIG,
2313 "Check fail, Mask[0]=0x%x, restart timer\n",
2314 *dm->interrupt_mask);
2315
2316 phydm_tdma_dig_add_interrupt_mask_handler(dm);
2317 phydm_enable_rx_related_interrupt_handler(dm);
2318 phydm_set_tdma_dig_timer(dm);
2319 #endif
2320 }
2321 } else {
2322 PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
2323 }
2324
2325 dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
2326 }
2327
2328 /*@different IC/team may use different timer for tdma-dig*/
phydm_tdma_dig_add_interrupt_mask_handler(void * dm_void)2329 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
2330 {
2331 struct dm_struct *dm = (struct dm_struct *)dm_void;
2332
2333 #if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
2334 if (dm->support_ic_type & ODM_RTL8197F) {
2335 /*@HAL_INT_TYPE_PSTIMEOUT2*/
2336 phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
2337 }
2338 #elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
2339 #elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
2340 #endif
2341 }
2342
2343 /* will be triggered by HW timer*/
phydm_tdma_dig(void * dm_void)2344 void phydm_tdma_dig(void *dm_void)
2345 {
2346 struct dm_struct *dm = (struct dm_struct *)dm_void;
2347 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2348 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2349 u32 reg_c50 = 0;
2350
2351 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
2352 RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
2353 #ifdef IS_USE_NEW_TDMA
2354 if (dm->support_ic_type &
2355 (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |
2356 ODM_RTL8192F | ODM_RTL8821C)) {
2357 PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n");
2358 return;
2359 }
2360 #endif
2361 #endif
2362 reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
2363
2364 dig_t->tdma_dig_state =
2365 dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2366
2367 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
2368 dig_t->tdma_dig_state, reg_c50);
2369
2370 dig_t->tdma_dig_cnt++;
2371
2372 if (dig_t->tdma_dig_state == 1) {
2373 /* update IGI from tdma_dig_state == 0*/
2374 if (dig_t->cur_ig_value_tdma == 0)
2375 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
2376
2377 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2378 phydm_tdma_false_alarm_counter_check(dm);
2379 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
2380 dig_t->tdma_dig_state);
2381
2382 } else if (dig_t->tdma_dig_state == 0) {
2383 /* update dig_t->CurIGValue,*/
2384 /* @it may different from dig_t->cur_ig_value_tdma */
2385 /* TDMA IGI upperbond @ L-state = */
2386 /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
2387
2388 if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
2389 dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
2390 else
2391 dig_t->low_ig_value = dig_t->cur_ig_value;
2392
2393 odm_write_dig(dm, dig_t->low_ig_value);
2394 phydm_tdma_false_alarm_counter_check(dm);
2395 } else {
2396 phydm_tdma_false_alarm_counter_check(dm);
2397 }
2398 }
2399
2400 /*@============================================================*/
2401 /*@FASLE ALARM CHECK*/
2402 /*@============================================================*/
phydm_tdma_false_alarm_counter_check(void * dm_void)2403 void phydm_tdma_false_alarm_counter_check(void *dm_void)
2404 {
2405 struct dm_struct *dm = (struct dm_struct *)dm_void;
2406 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2407 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2408 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2409 boolean rssi_dump_en = 0;
2410 u32 timestamp = 0;
2411 u8 tdma_dig_state_number = 0;
2412 u32 start_th = 0;
2413
2414 if (dig_t->tdma_dig_state == 1)
2415 phydm_false_alarm_counter_reset(dm);
2416 /* Reset FalseAlarmCounterStatistics */
2417 /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
2418 /* @fa_end_tsf = fa_start_tsf = TSF */
2419 else {
2420 phydm_false_alarm_counter_statistics(dm);
2421 if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
2422 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2423 else {
2424 PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
2425 return;
2426 }
2427 dig_t->fa_end_timestamp = timestamp;
2428 dig_t->fa_acc_1sec_timestamp +=
2429 (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
2430
2431 /*prevent dumb*/
2432 if (dm->tdma_dig_state_number == 1)
2433 dm->tdma_dig_state_number = 2;
2434
2435 tdma_dig_state_number = dm->tdma_dig_state_number;
2436 dig_t->sec_factor =
2437 tdma_dig_state_number / (tdma_dig_state_number - 1);
2438
2439 /*@1sec = 1000000us*/
2440 if (dig_t->sec_factor)
2441 start_th = (u32)(1000000 / dig_t->sec_factor);
2442
2443 if (dig_t->fa_acc_1sec_timestamp >= start_th) {
2444 rssi_dump_en = 1;
2445 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2446 PHYDM_DBG(dm, DBG_DIG,
2447 "sec_factor=%d, total FA=%d, is_linked=%d\n",
2448 dig_t->sec_factor, falm_cnt_acc->cnt_all,
2449 dm->is_linked);
2450
2451 phydm_noisy_detection(dm);
2452 #ifdef PHYDM_SUPPORT_CCKPD
2453 phydm_cck_pd_th(dm);
2454 #endif
2455 phydm_dig(dm);
2456 phydm_false_alarm_counter_acc_reset(dm);
2457
2458 /* Reset FalseAlarmCounterStatistics */
2459 /* @fa_end_tsf = fa_start_tsf = TSF, keep */
2460 /* @fa_acc_1sec_tsf = 0 */
2461 phydm_false_alarm_counter_reset(dm);
2462 } else {
2463 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2464 }
2465 }
2466 }
2467
phydm_false_alarm_counter_acc(void * dm_void,boolean rssi_dump_en)2468 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
2469 {
2470 struct dm_struct *dm = (struct dm_struct *)dm_void;
2471 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2472 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2473 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2474
2475 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
2476 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
2477 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
2478 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
2479 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
2480 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
2481 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
2482 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
2483 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
2484 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
2485 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
2486 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
2487 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
2488 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
2489 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
2490 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
2491 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
2492 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
2493 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
2494 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
2495 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
2496 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
2497
2498 if (rssi_dump_en == 1) {
2499 falm_cnt_acc->cnt_all_1sec =
2500 falm_cnt_acc->cnt_all * dig_t->sec_factor;
2501 falm_cnt_acc->cnt_cca_all_1sec =
2502 falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
2503 falm_cnt_acc->cnt_cck_fail_1sec =
2504 falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
2505 }
2506 }
2507
phydm_false_alarm_counter_acc_reset(void * dm_void)2508 void phydm_false_alarm_counter_acc_reset(void *dm_void)
2509 {
2510 struct dm_struct *dm = (struct dm_struct *)dm_void;
2511 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
2512
2513 #ifdef IS_USE_NEW_TDMA
2514 struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
2515 u32 tmp_cca_1sec = 0;
2516 u32 tmp_fa_1sec = 0;
2517
2518 /*@clear L-fa_acc struct*/
2519 falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
2520 tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
2521 tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
2522 odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
2523 falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
2524 falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
2525
2526 /*@clear H-fa_acc struct*/
2527 falm_cnt_acc = &dm->false_alm_cnt_acc;
2528 tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
2529 tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
2530 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
2531 falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
2532 falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
2533 #else
2534 falm_cnt_acc = &dm->false_alm_cnt_acc;
2535 /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
2536 /* @do NOT need to be reset */
2537 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
2538 #endif
2539 }
2540
phydm_false_alarm_counter_reset(void * dm_void)2541 void phydm_false_alarm_counter_reset(void *dm_void)
2542 {
2543 struct dm_struct *dm = (struct dm_struct *)dm_void;
2544 struct phydm_fa_struct *falm_cnt;
2545 struct phydm_dig_struct *dig_t;
2546 u32 timestamp;
2547
2548 falm_cnt = &dm->false_alm_cnt;
2549 dig_t = &dm->dm_dig_table;
2550
2551 memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
2552 phydm_false_alarm_counter_reg_reset(dm);
2553
2554 #ifdef IS_USE_NEW_TDMA
2555 return;
2556 #endif
2557 if (dig_t->tdma_dig_state != 1)
2558 dig_t->fa_acc_1sec_timestamp = 0;
2559 else
2560 dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
2561
2562 /*REG_FREERUN_CNT*/
2563 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2564 dig_t->fa_start_timestamp = timestamp;
2565 dig_t->fa_end_timestamp = timestamp;
2566 }
2567
phydm_tdma_dig_para_upd(void * dm_void,enum upd_type type,u8 input)2568 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
2569 {
2570 struct dm_struct *dm = (struct dm_struct *)dm_void;
2571
2572 switch (type) {
2573 case ENABLE_TDMA:
2574 dm->original_dig_restore = !((boolean)input);
2575 break;
2576 case MODE_DECISION:
2577 if (input == (u8)MODE_PERFORMANCE)
2578 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
2579 else if (input == (u8)MODE_COVERAGE)
2580 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2581 else
2582 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2583 break;
2584 }
2585 }
2586
2587 #ifdef IS_USE_NEW_TDMA
2588 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
pre_phydm_tdma_dig_cbk(unsigned long task_dm)2589 static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
2590 {
2591 struct dm_struct *dm = (struct dm_struct *)task_dm;
2592 struct rtl8192cd_priv *priv = dm->priv;
2593 struct priv_shared_info *pshare = priv->pshare;
2594
2595 if (!(priv->drv_state & DRV_STATE_OPEN))
2596 return;
2597
2598 if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
2599 printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
2600 __FUNCTION__, pshare->bDriverStopped,
2601 pshare->bSurpriseRemoved);
2602 return;
2603 }
2604
2605 rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
2606 ENQUEUE_TO_TAIL);
2607 }
2608
phydm_tdma_dig_timers_usb(void * dm_void,u8 state)2609 void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
2610 {
2611 struct dm_struct *dm = (struct dm_struct *)dm_void;
2612 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2613
2614 if (state == INIT_TDMA_DIG_TIMMER) {
2615 struct rtl8192cd_priv *priv = dm->priv;
2616
2617 init_timer(&dm->tdma_dig_timer);
2618 dm->tdma_dig_timer.data = (unsigned long)dm;
2619 dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
2620 INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
2621 phydm_tdma_dig_cbk,
2622 (unsigned long)dm);
2623 } else if (state == CANCEL_TDMA_DIG_TIMMER) {
2624 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2625 } else if (state == RELEASE_TDMA_DIG_TIMMER) {
2626 odm_release_timer(dm, &dm->tdma_dig_timer);
2627 }
2628 }
2629 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2630
phydm_tdma_dig_timers(void * dm_void,u8 state)2631 void phydm_tdma_dig_timers(void *dm_void, u8 state)
2632 {
2633 struct dm_struct *dm = (struct dm_struct *)dm_void;
2634 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2635 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
2636 struct rtl8192cd_priv *priv = dm->priv;
2637
2638 if (priv->hci_type == RTL_HCI_USB) {
2639 phydm_tdma_dig_timers_usb(dm_void, state);
2640 return;
2641 }
2642 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2643
2644 if (state == INIT_TDMA_DIG_TIMMER)
2645 odm_initialize_timer(dm, &dm->tdma_dig_timer,
2646 (void *)phydm_tdma_dig_cbk,
2647 NULL, "phydm_tdma_dig_timer");
2648 else if (state == CANCEL_TDMA_DIG_TIMMER)
2649 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2650 else if (state == RELEASE_TDMA_DIG_TIMMER)
2651 odm_release_timer(dm, &dm->tdma_dig_timer);
2652 }
2653
get_new_igi_bound(struct dm_struct * dm,u8 igi,u32 fa_cnt,u8 * rx_gain_max,u8 * rx_gain_min,boolean is_dfs_band)2654 u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
2655 u8 *rx_gain_min, boolean is_dfs_band)
2656 {
2657 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2658 u8 step[3] = {0};
2659 u8 cur_igi = igi;
2660
2661 if (dm->is_linked) {
2662 if (dm->pre_rssi_min <= dm->rssi_min) {
2663 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
2664 step[0] = 2;
2665 step[1] = 1;
2666 step[2] = 2;
2667 } else {
2668 step[0] = 4;
2669 step[1] = 2;
2670 step[2] = 2;
2671 }
2672 } else {
2673 step[0] = 2;
2674 step[1] = 1;
2675 step[2] = 2;
2676 }
2677
2678 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
2679 step[0]);
2680
2681 if (dm->first_connect) {
2682 if (is_dfs_band) {
2683 if (dm->rssi_min > DIG_MAX_DFS)
2684 igi = DIG_MAX_DFS;
2685 else
2686 igi = dm->rssi_min;
2687 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
2688 *rx_gain_max);
2689 } else {
2690 igi = *rx_gain_min;
2691 }
2692
2693 #if 0
2694 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2695 #if (RTL8812A_SUPPORT)
2696 if (dm->support_ic_type == ODM_RTL8812)
2697 odm_config_bb_with_header_file(dm,
2698 CONFIG_BB_AGC_TAB_DIFF);
2699 #endif
2700 #endif
2701 #endif
2702 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
2703 } else {
2704 /* @2 Before link */
2705 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
2706
2707 if (dm->first_disconnect) {
2708 igi = dig_t->dm_dig_min;
2709 PHYDM_DBG(dm, DBG_DIG,
2710 "First disconnect:foce IGI to lower bound\n");
2711 } else {
2712 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
2713 igi, fa_cnt);
2714
2715 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2716 }
2717 }
2718 /*@Check IGI by dyn-upper/lower bound */
2719 if (igi < *rx_gain_min)
2720 igi = *rx_gain_min;
2721
2722 if (igi > *rx_gain_max)
2723 igi = *rx_gain_max;
2724
2725 PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
2726 fa_cnt, cur_igi, igi);
2727
2728 return igi;
2729 }
2730
phydm_write_tdma_dig(void * dm_void,u8 new_igi)2731 void phydm_write_tdma_dig(void *dm_void, u8 new_igi)
2732 {
2733 struct dm_struct *dm = (struct dm_struct *)dm_void;
2734 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2735 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
2736
2737 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
2738 #if 0
2739 /* @1 Check IGI by upper bound */
2740 if (adaptivity->igi_lmt_en &&
2741 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
2742 new_igi = adaptivity->adapt_igi_up;
2743
2744 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
2745 new_igi);
2746 }
2747 #endif
2748 phydm_write_dig_reg(dm, new_igi);
2749
2750 PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n",
2751 (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H",
2752 new_igi);
2753 }
2754
phydm_tdma_dig_new(void * dm_void)2755 void phydm_tdma_dig_new(void *dm_void)
2756 {
2757 struct dm_struct *dm = (struct dm_struct *)dm_void;
2758 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2759
2760 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2761 return;
2762 /*@
2763 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2764 * dig_t->tdma_dig_state);
2765 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2766 * dig_t->cur_ig_value_tdma,
2767 * dig_t->low_ig_value);
2768 */
2769 phydm_tdma_fa_cnt_chk(dm);
2770
2771 /*@prevent dumb*/
2772 if (dm->tdma_dig_state_number < 2)
2773 dm->tdma_dig_state_number = 2;
2774
2775 /*@update state*/
2776 dig_t->tdma_dig_cnt++;
2777 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2778
2779 /*@
2780 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2781 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2782 */
2783
2784 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2785 odm_write_dig(dm, dig_t->low_ig_value);
2786 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2787 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2788
2789 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2790 }
2791
2792 /*@callback function triggered by SW timer*/
2793 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_tdma_dig_cbk(struct phydm_timer_list * timer)2794 void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
2795 {
2796 void *adapter = (void *)timer->Adapter;
2797 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2798 struct dm_struct *dm = &hal_data->DM_OutSrcs;
2799
2800 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2801 #if USE_WORKITEM
2802 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2803 #else
2804 phydm_tdma_dig_new(dm);
2805 #endif
2806 #else
2807 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2808 #endif
2809 }
2810
phydm_tdma_dig_workitem_callback(void * context)2811 void phydm_tdma_dig_workitem_callback(void *context)
2812 {
2813 void *adapter = (void *)context;
2814 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2815 struct dm_struct *dm = &hal_data->DM_OutSrc;
2816
2817 phydm_tdma_dig_new(dm);
2818 }
2819
2820 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_tdma_dig_cbk(void * dm_void)2821 void phydm_tdma_dig_cbk(void *dm_void)
2822 {
2823 struct dm_struct *dm = (struct dm_struct *)dm_void;
2824 void *padapter = dm->adapter;
2825
2826 if (dm->support_interface == ODM_ITRF_PCIE)
2827 phydm_tdma_dig_workitem_callback(dm);
2828 /* @Can't do I/O in timer callback*/
2829 else
2830 phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,
2831 dm);
2832 }
2833
phydm_tdma_dig_workitem_callback(void * dm_void)2834 void phydm_tdma_dig_workitem_callback(void *dm_void)
2835 {
2836 struct dm_struct *dm = (struct dm_struct *)dm_void;
2837 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2838
2839 if (phydm_dig_abort(dm) || (dm->original_dig_restore))
2840 return;
2841 /*@
2842 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2843 * dig_t->tdma_dig_state);
2844 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2845 * dig_t->cur_ig_value_tdma,
2846 * dig_t->low_ig_value);
2847 */
2848 phydm_tdma_fa_cnt_chk(dm);
2849
2850 /*@prevent dumb*/
2851 if (dm->tdma_dig_state_number < 2)
2852 dm->tdma_dig_state_number = 2;
2853
2854 /*@update state*/
2855 dig_t->tdma_dig_cnt++;
2856 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2857
2858 /*@
2859 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2860 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2861 */
2862
2863 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2864 odm_write_dig(dm, dig_t->low_ig_value);
2865 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2866 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2867
2868 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2869 }
2870 #else
phydm_tdma_dig_cbk(void * dm_void)2871 void phydm_tdma_dig_cbk(void *dm_void)
2872 {
2873 struct dm_struct *dm = (struct dm_struct *)dm_void;
2874 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2875
2876 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2877 return;
2878 /*@
2879 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2880 * dig_t->tdma_dig_state);
2881 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2882 * dig_t->cur_ig_value_tdma,
2883 * dig_t->low_ig_value);
2884 */
2885 phydm_tdma_fa_cnt_chk(dm);
2886
2887 /*@prevent dumb*/
2888 if (dm->tdma_dig_state_number < 2)
2889 dm->tdma_dig_state_number = 2;
2890
2891 /*@update state*/
2892 dig_t->tdma_dig_cnt++;
2893 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2894
2895 /*@
2896 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2897 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2898 */
2899
2900 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2901 phydm_write_tdma_dig(dm, dig_t->low_ig_value);
2902 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2903 phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma);
2904
2905 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2906 }
2907 #endif
2908 /*@============================================================*/
2909 /*@FASLE ALARM CHECK*/
2910 /*@============================================================*/
phydm_tdma_fa_cnt_chk(void * dm_void)2911 void phydm_tdma_fa_cnt_chk(void *dm_void)
2912 {
2913 struct dm_struct *dm = (struct dm_struct *)dm_void;
2914 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2915 struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
2916 struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
2917 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2918 boolean tdma_dig_block_1sec_flag = false;
2919 u32 timestamp = 0;
2920 u8 states_per_block = dm->tdma_dig_state_number;
2921 u8 cur_tdma_dig_state = 0;
2922 u32 start_th = 0;
2923 u8 state_diff = 0;
2924 u32 tdma_dig_block_period_ms = 0;
2925 u32 tdma_dig_block_cnt_thd = 0;
2926 u32 timestamp_diff = 0;
2927
2928 /*@calculate duration of a tdma block*/
2929 tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
2930
2931 /*@
2932 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
2933 *or FA will be fewer.
2934 */
2935 tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
2936
2937 /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
2938 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2939 cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
2940 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2941 cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
2942 /*@
2943 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
2944 * cur_tdma_dig_state, dig_t->tdma_dig_cnt);
2945 */
2946 if (cur_tdma_dig_state == 0) {
2947 /*@L-state indicates next block*/
2948 dig_t->tdma_dig_block_cnt++;
2949
2950 /*@1sec dump check*/
2951 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2952 tdma_dig_block_1sec_flag = true;
2953
2954 /*@
2955 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
2956 * dig_t->tdma_dig_block_cnt);
2957 */
2958
2959 /*@collect FA till this block end*/
2960 phydm_false_alarm_counter_statistics(dm);
2961 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2962 cur_tdma_dig_state);
2963 /*@1s L-FA collect end*/
2964
2965 /*@1sec dump reached*/
2966 if (tdma_dig_block_1sec_flag) {
2967 /*@L-DIG*/
2968 phydm_noisy_detection(dm);
2969 #ifdef PHYDM_SUPPORT_CCKPD
2970 phydm_cck_pd_th(dm);
2971 #endif
2972 PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
2973 phydm_tdma_low_dig(dm);
2974 PHYDM_DBG(dm, DBG_DIG, "\n\n");
2975 }
2976 } else if (cur_tdma_dig_state == 1) {
2977 /*@1sec dump check*/
2978 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2979 tdma_dig_block_1sec_flag = true;
2980
2981 /*@
2982 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
2983 * dig_t->tdma_dig_block_cnt);
2984 */
2985
2986 /*@collect FA till this block end*/
2987 phydm_false_alarm_counter_statistics(dm);
2988 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2989 cur_tdma_dig_state);
2990 /*@1s H-FA collect end*/
2991
2992 /*@1sec dump reached*/
2993 state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
2994 if (tdma_dig_block_1sec_flag && state_diff == 1) {
2995 /*@H-DIG*/
2996 phydm_noisy_detection(dm);
2997 #ifdef PHYDM_SUPPORT_CCKPD
2998 phydm_cck_pd_th(dm);
2999 #endif
3000 PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
3001 phydm_tdma_high_dig(dm);
3002 PHYDM_DBG(dm, DBG_DIG, "\n\n");
3003 PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
3004 dm->is_linked);
3005 PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
3006 fa_t_acc_low->cnt_cca_all_1sec,
3007 fa_t_acc_low->cnt_all_1sec);
3008 PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
3009 fa_t_acc->cnt_cca_all_1sec,
3010 fa_t_acc->cnt_all_1sec);
3011 PHYDM_DBG(dm, DBG_DIG,
3012 "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
3013 fa_t_acc->cnt_cca_all +
3014 fa_t_acc_low->cnt_cca_all,
3015 fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
3016
3017 /*@Reset AccFalseAlarmCounterStatistics */
3018 phydm_false_alarm_counter_acc_reset(dm);
3019 dig_t->tdma_dig_block_cnt = 0;
3020 }
3021 }
3022 /*@Reset FalseAlarmCounterStatistics */
3023 phydm_false_alarm_counter_reset(dm);
3024 }
3025
phydm_tdma_low_dig(void * dm_void)3026 void phydm_tdma_low_dig(void *dm_void)
3027 {
3028 struct dm_struct *dm = (struct dm_struct *)dm_void;
3029 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3030 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3031 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
3032 #ifdef CFG_DIG_DAMPING_CHK
3033 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
3034 #endif
3035 u8 igi = dig_t->cur_ig_value;
3036 u8 new_igi = 0x20;
3037 u8 tdma_l_igi = dig_t->low_ig_value;
3038 u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
3039 u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
3040 u32 fa_cnt = falm_cnt->cnt_all;
3041 boolean dfs_mode_en = false, is_performance = true;
3042 u8 rssi_min = dm->rssi_min;
3043 u8 igi_upper_rssi_min = 0;
3044 u8 offset = 15;
3045
3046 if (!(dm->original_dig_restore)) {
3047 if (tdma_l_igi == 0)
3048 tdma_l_igi = igi;
3049
3050 fa_cnt = falm_cnt_acc->cnt_all_1sec;
3051 }
3052
3053 if (phydm_dig_abort(dm)) {
3054 dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
3055 return;
3056 }
3057
3058 /*@Mode Decision*/
3059 dfs_mode_en = false;
3060 is_performance = true;
3061
3062 /* @Abs Boundary Decision*/
3063 dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
3064 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
3065 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
3066
3067 if (dm->is_dfs_band) {
3068 if (*dm->band_width == CHANNEL_WIDTH_20){
3069 if (dm->support_ic_type &
3070 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
3071 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
3072 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
3073 else
3074 dig_t->dm_dig_min = DIG_MIN_DFS;
3075 }
3076 else
3077 dig_t->dm_dig_min = DIG_MIN_DFS;
3078 }
3079 else
3080 dig_t->dm_dig_min = DIG_MIN_DFS;
3081
3082 } else {
3083 #if 0
3084 if (dm->support_ic_type &
3085 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
3086 dig_t->dm_dig_min = 0x1c;
3087 else if (dm->support_ic_type & ODM_RTL8197F)
3088 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
3089 #endif
3090 }
3091
3092 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
3093 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
3094
3095 /* @Dyn Boundary by RSSI*/
3096 if (!dm->is_linked) {
3097 /*@if no link, always stay at lower bound*/
3098 tdma_l_dym_max = 0x26;
3099 tdma_l_dym_min = dig_t->dm_dig_min;
3100
3101 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
3102 tdma_l_dym_max, tdma_l_dym_min);
3103 } else {
3104 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
3105 dm->rssi_min, offset);
3106
3107 /* @DIG lower bound in L-state*/
3108 tdma_l_dym_min = dig_t->dm_dig_min;
3109 if (dm->is_dfs_band)
3110 tdma_l_dym_min = DIG_MIN_DFS;
3111 /*@
3112 *#ifdef CFG_DIG_DAMPING_CHK
3113 *@Limit Dyn min by damping
3114 *if (dig_t->dig_dl_en &&
3115 * dig_rc->damping_limit_en &&
3116 * tdma_l_dym_min < dig_rc->damping_limit_val) {
3117 * PHYDM_DBG(dm, DBG_DIG,
3118 * "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
3119 * tdma_l_dym_min, dig_rc->damping_limit_val);
3120 *
3121 * tdma_l_dym_min = dig_rc->damping_limit_val;
3122 *}
3123 *#endif
3124 */
3125
3126 /*@DIG upper bound in L-state*/
3127 igi_upper_rssi_min = rssi_min + offset;
3128 if (igi_upper_rssi_min > dig_t->dm_dig_max)
3129 tdma_l_dym_max = dig_t->dm_dig_max;
3130 else if (igi_upper_rssi_min < dig_t->dm_dig_min)
3131 tdma_l_dym_max = dig_t->dm_dig_min;
3132 else
3133 tdma_l_dym_max = igi_upper_rssi_min;
3134
3135 /* @1 Force Lower Bound for AntDiv */
3136 /*@
3137 *if (!dm->is_one_entry_only &&
3138 *(dm->support_ability & ODM_BB_ANT_DIV) &&
3139 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
3140 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
3141 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
3142 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
3143 *else
3144 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
3145 *
3146 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
3147 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
3148 *}
3149 */
3150
3151 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
3152 tdma_l_dym_max, tdma_l_dym_min);
3153 }
3154
3155 /*@Abnormal Case Check*/
3156 /*@Abnormal lower bound case*/
3157 if (tdma_l_dym_min > tdma_l_dym_max)
3158 tdma_l_dym_min = tdma_l_dym_max;
3159
3160 PHYDM_DBG(dm, DBG_DIG,
3161 "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
3162 tdma_l_dym_max, tdma_l_dym_min);
3163
3164 /*@False Alarm Threshold Decision*/
3165 phydm_fa_threshold_check(dm, dfs_mode_en);
3166
3167 /*@Adjust Initial Gain by False Alarm*/
3168 /*Select new IGI by FA */
3169 if (!(dm->original_dig_restore)) {
3170 tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
3171 &tdma_l_dym_max,
3172 &tdma_l_dym_min,
3173 dfs_mode_en);
3174 } else {
3175 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3176 }
3177
3178 /*Update status*/
3179 if (!(dm->original_dig_restore)) {
3180 if (dig_t->tdma_force_l_igi == 0xff)
3181 dig_t->low_ig_value = tdma_l_igi;
3182 else
3183 dig_t->low_ig_value = dig_t->tdma_force_l_igi;
3184 dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
3185 dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
3186 #if 0
3187 /*odm_write_dig(dm, tdma_l_igi);*/
3188 #endif
3189 } else {
3190 odm_write_dig(dm, new_igi);
3191 }
3192 }
3193
phydm_tdma_high_dig(void * dm_void)3194 void phydm_tdma_high_dig(void *dm_void)
3195 {
3196 struct dm_struct *dm = (struct dm_struct *)dm_void;
3197 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3198 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3199 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
3200 #ifdef CFG_DIG_DAMPING_CHK
3201 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
3202 #endif
3203 u8 igi = dig_t->cur_ig_value;
3204 u8 new_igi = 0x20;
3205 u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
3206 u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
3207 u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
3208 u32 fa_cnt = falm_cnt->cnt_all;
3209 boolean dfs_mode_en = false, is_performance = true;
3210 u8 rssi_min = dm->rssi_min;
3211 u8 igi_upper_rssi_min = 0;
3212 u8 offset = 15;
3213
3214 if (!(dm->original_dig_restore)) {
3215 if (tdma_h_igi == 0)
3216 tdma_h_igi = igi;
3217
3218 fa_cnt = falm_cnt_acc->cnt_all_1sec;
3219 }
3220
3221 if (phydm_dig_abort(dm)) {
3222 dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
3223 return;
3224 }
3225
3226 /*@Mode Decision*/
3227 dfs_mode_en = false;
3228 is_performance = true;
3229
3230 /*@Abs Boundary Decision*/
3231 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
3232
3233 if (!dm->is_linked) {
3234 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
3235 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
3236 } else if (dm->is_dfs_band) {
3237 if (*dm->band_width == CHANNEL_WIDTH_20){
3238 if (dm->support_ic_type &
3239 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
3240 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
3241 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
3242 else
3243 dig_t->dm_dig_min = DIG_MIN_DFS;
3244 }
3245 else
3246 dig_t->dm_dig_min = DIG_MIN_DFS;
3247 }
3248 else
3249 dig_t->dm_dig_min = DIG_MIN_DFS;
3250
3251 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3252 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3253 } else {
3254 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
3255 /*service > 2 devices*/
3256 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3257 #if (DIG_HW == 1)
3258 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
3259 #else
3260 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3261 #endif
3262 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
3263 /*service 1 devices*/
3264 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
3265 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3266 }
3267
3268 #if 0
3269 if (dm->support_ic_type &
3270 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
3271 dig_t->dm_dig_min = 0x1c;
3272 else if (dm->support_ic_type & ODM_RTL8197F)
3273 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
3274 else
3275 #endif
3276 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
3277 }
3278 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
3279 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
3280
3281 /*@Dyn Boundary by RSSI*/
3282 if (!dm->is_linked) {
3283 /*@if no link, always stay at lower bound*/
3284 tdma_h_dym_max = dig_t->dig_max_of_min;
3285 tdma_h_dym_min = dig_t->dm_dig_min;
3286
3287 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
3288 tdma_h_dym_max, tdma_h_dym_min);
3289 } else {
3290 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
3291 dm->rssi_min, offset);
3292
3293 /* @DIG lower bound in H-state*/
3294 if (dm->is_dfs_band)
3295 tdma_h_dym_min = DIG_MIN_DFS;
3296 else if (rssi_min < dig_t->dm_dig_min)
3297 tdma_h_dym_min = dig_t->dm_dig_min;
3298 else
3299 tdma_h_dym_min = rssi_min; // turbo not considered yet
3300
3301 #ifdef CFG_DIG_DAMPING_CHK
3302 /*@Limit Dyn min by damping*/
3303 if (dig_t->dig_dl_en &&
3304 dig_rc->damping_limit_en &&
3305 tdma_h_dym_min < dig_rc->damping_limit_val) {
3306 PHYDM_DBG(dm, DBG_DIG,
3307 "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
3308 tdma_h_dym_min, dig_rc->damping_limit_val);
3309
3310 tdma_h_dym_min = dig_rc->damping_limit_val;
3311 }
3312 #endif
3313
3314 /*@DIG upper bound in H-state*/
3315 igi_upper_rssi_min = rssi_min + offset;
3316 if (igi_upper_rssi_min > dig_t->dm_dig_max)
3317 tdma_h_dym_max = dig_t->dm_dig_max;
3318 else
3319 tdma_h_dym_max = igi_upper_rssi_min;
3320
3321 /* @1 Force Lower Bound for AntDiv */
3322 /*@
3323 *if (!dm->is_one_entry_only &&
3324 *(dm->support_ability & ODM_BB_ANT_DIV) &&
3325 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
3326 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
3327 * if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
3328 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
3329 * else
3330 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
3331 */
3332 /*@
3333 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
3334 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
3335 *}
3336 */
3337 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
3338 tdma_h_dym_max, tdma_h_dym_min);
3339 }
3340
3341 /*@Abnormal Case Check*/
3342 /*@Abnormal low higher bound case*/
3343 if (tdma_h_dym_max < dig_t->dm_dig_min)
3344 tdma_h_dym_max = dig_t->dm_dig_min;
3345 /*@Abnormal lower bound case*/
3346 if (tdma_h_dym_min > tdma_h_dym_max)
3347 tdma_h_dym_min = tdma_h_dym_max;
3348
3349 PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
3350 tdma_h_dym_max, tdma_h_dym_min);
3351
3352 /*@False Alarm Threshold Decision*/
3353 phydm_fa_threshold_check(dm, dfs_mode_en);
3354
3355 /*@Adjust Initial Gain by False Alarm*/
3356 /*Select new IGI by FA */
3357 if (!(dm->original_dig_restore)) {
3358 tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
3359 &tdma_h_dym_max,
3360 &tdma_h_dym_min,
3361 dfs_mode_en);
3362 } else {
3363 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3364 }
3365
3366 /*Update status*/
3367 if (!(dm->original_dig_restore)) {
3368 if (dig_t->tdma_force_h_igi == 0xff)
3369 dig_t->cur_ig_value_tdma = tdma_h_igi;
3370 else
3371 dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi;
3372 dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
3373 dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
3374 #if 0
3375 /*odm_write_dig(dm, tdma_h_igi);*/
3376 #endif
3377 } else {
3378 odm_write_dig(dm, new_igi);
3379 }
3380 }
3381
phydm_fa_cnt_acc(void * dm_void,boolean tdma_dig_block_1sec_flag,u8 cur_tdma_dig_state)3382 void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
3383 u8 cur_tdma_dig_state)
3384 {
3385 struct dm_struct *dm = (struct dm_struct *)dm_void;
3386 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3387 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
3388 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3389 u8 factor_num = 0;
3390 u8 factor_denum = 1;
3391 u8 total_state_number = 0;
3392
3393 if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
3394 falm_cnt_acc = &dm->false_alm_cnt_acc_low;
3395 else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
3396
3397 falm_cnt_acc = &dm->false_alm_cnt_acc;
3398 /*@
3399 *PHYDM_DBG(dm, DBG_DIG,
3400 * "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
3401 * cur_tdma_dig_state, tdma_dig_block_1sec_flag);
3402 */
3403 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
3404 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
3405 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
3406 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
3407 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
3408 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
3409 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
3410 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
3411 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
3412 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
3413 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
3414 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
3415 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
3416 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
3417 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
3418 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
3419 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
3420 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
3421 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
3422 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
3423 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
3424 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
3425
3426 /*@
3427 *PHYDM_DBG(dm, DBG_DIG,
3428 * "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3429 * falm_cnt->cnt_cck_cca,
3430 * falm_cnt->cnt_ofdm_cca,
3431 * falm_cnt->cnt_cca_all);
3432 *PHYDM_DBG(dm, DBG_DIG,
3433 * "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3434 * falm_cnt->cnt_cck_fail,
3435 * falm_cnt->cnt_ofdm_fail,
3436 * falm_cnt->cnt_all);
3437 */
3438 if (tdma_dig_block_1sec_flag) {
3439 total_state_number = dm->tdma_dig_state_number;
3440
3441 if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
3442 factor_num = total_state_number;
3443 factor_denum = total_state_number - 1;
3444 } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
3445 factor_num = total_state_number;
3446 factor_denum = 1;
3447 }
3448
3449 falm_cnt_acc->cnt_all_1sec =
3450 falm_cnt_acc->cnt_all * factor_num / factor_denum;
3451 falm_cnt_acc->cnt_cca_all_1sec =
3452 falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
3453 falm_cnt_acc->cnt_cck_fail_1sec =
3454 falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
3455
3456 PHYDM_DBG(dm, DBG_DIG,
3457 "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3458 falm_cnt_acc->cnt_cck_cca,
3459 falm_cnt_acc->cnt_ofdm_cca,
3460 falm_cnt_acc->cnt_cca_all);
3461 PHYDM_DBG(dm, DBG_DIG,
3462 "[ACC FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
3463 falm_cnt_acc->cnt_cck_fail,
3464 falm_cnt_acc->cnt_ofdm_fail,
3465 falm_cnt_acc->cnt_all);
3466
3467 }
3468 }
3469 #endif /*@#ifdef IS_USE_NEW_TDMA*/
3470 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
3471
phydm_dig_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3472 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
3473 u32 *_out_len)
3474 {
3475 struct dm_struct *dm = (struct dm_struct *)dm_void;
3476 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3477 char help[] = "-h";
3478 u32 var1[10] = {0};
3479 u32 used = *_used;
3480 u32 out_len = *_out_len;
3481 u8 i = 0;
3482
3483 if ((strcmp(input[1], help) == 0)) {
3484 PDM_SNPF(out_len, used, output + used, out_len - used,
3485 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
3486 PDM_SNPF(out_len, used, output + used, out_len - used,
3487 "{1} {Damping Limit en}\n");
3488 #ifdef PHYDM_TDMA_DIG_SUPPORT
3489 PDM_SNPF(out_len, used, output + used, out_len - used,
3490 "{2} {original_dig_restore = %d}\n",
3491 dm->original_dig_restore);
3492 PDM_SNPF(out_len, used, output + used, out_len - used,
3493 "{3} {tdma_dig_timer_ms = %d}\n",
3494 dm->tdma_dig_timer_ms);
3495 PDM_SNPF(out_len, used, output + used, out_len - used,
3496 "{4} {tdma_dig_state_number = %d}\n",
3497 dm->tdma_dig_state_number);
3498 PDM_SNPF(out_len, used, output + used, out_len - used,
3499 "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n",
3500 dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi);
3501 #endif
3502 PDM_SNPF(out_len, used, output + used, out_len - used,
3503 "{6} {fw_dig_en}\n");
3504 PDM_SNPF(out_len, used, output + used, out_len - used,
3505 "{7} FA source:{0:original/1:Experimental duration/2:IFS_CLM/3:FAHM}\n");
3506 } else {
3507 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
3508
3509 for (i = 1; i < 10; i++)
3510 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
3511
3512 if (var1[0] == 0) {
3513 if (var1[1] == 1) {
3514 dig_t->is_dbg_fa_th = true;
3515 dig_t->fa_th[0] = (u32)var1[2];
3516 dig_t->fa_th[1] = (u32)var1[3];
3517 dig_t->fa_th[2] = (u32)var1[4];
3518
3519 PDM_SNPF(out_len, used, output + used,
3520 out_len - used,
3521 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
3522 dig_t->fa_th[0], dig_t->fa_th[1],
3523 dig_t->fa_th[2]);
3524 } else {
3525 dig_t->is_dbg_fa_th = false;
3526 }
3527 #ifdef PHYDM_TDMA_DIG_SUPPORT
3528 } else if (var1[0] == 2) {
3529 dm->original_dig_restore = (u8)var1[1];
3530 if (dm->original_dig_restore == 1) {
3531 PDM_SNPF(out_len, used, output + used,
3532 out_len - used, "Disable TDMA-DIG\n");
3533 } else {
3534 PDM_SNPF(out_len, used, output + used,
3535 out_len - used, "Enable TDMA-DIG\n");
3536 }
3537 } else if (var1[0] == 3) {
3538 dm->tdma_dig_timer_ms = (u8)var1[1];
3539 PDM_SNPF(out_len, used, output + used,
3540 out_len - used, "tdma_dig_timer_ms = %d\n",
3541 dm->tdma_dig_timer_ms);
3542 } else if (var1[0] == 4) {
3543 dm->tdma_dig_state_number = (u8)var1[1];
3544 PDM_SNPF(out_len, used, output + used,
3545 out_len - used, "tdma_dig_state_number = %d\n",
3546 dm->tdma_dig_state_number);
3547 } else if (var1[0] == 5) {
3548 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
3549 if (var1[1] == 0) {
3550 dig_t->tdma_force_l_igi = (u8)var1[2];
3551 PDM_SNPF(out_len, used, output + used,
3552 out_len - used,
3553 "force L-state IGI = %2x\n",
3554 dig_t->tdma_force_l_igi);
3555 } else if (var1[1] == 1) {
3556 dig_t->tdma_force_h_igi = (u8)var1[2];
3557 PDM_SNPF(out_len, used, output + used,
3558 out_len - used,
3559 "force H-state IGI = %2x\n",
3560 dig_t->tdma_force_h_igi);
3561 }
3562 #endif
3563 }
3564
3565 #ifdef CFG_DIG_DAMPING_CHK
3566 else if (var1[0] == 1) {
3567 dig_t->dig_dl_en = (u8)var1[1];
3568 /*@*/
3569 }
3570 #endif
3571 else if (var1[0] == 6) {
3572 phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]);
3573 PDM_SNPF(out_len, used, output + used, out_len - used,
3574 "fw_dig_enable = %2x\n", dig_t->fw_dig_enable);
3575 } else if (var1[0] == 7) {
3576 dig_t->fa_source = (u8)var1[1];
3577 PDM_SNPF(out_len, used, output + used, out_len - used,
3578 "FA source = %d\n", dig_t->fa_source);
3579 }
3580 }
3581 *_used = used;
3582 *_out_len = out_len;
3583 }
3584
3585 #ifdef CONFIG_MCC_DM
3586 #if (RTL8822B_SUPPORT || RTL8822C_SUPPORT|| RTL8723F_SUPPORT)
phydm_mcc_igi_clr(void * dm_void,u8 clr_port)3587 void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
3588 {
3589 struct dm_struct *dm = (struct dm_struct *)dm_void;
3590 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3591
3592 mcc_dm->mcc_rssi[clr_port] = 0xff;
3593 mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
3594 mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
3595 }
3596
phydm_mcc_igi_chk(void * dm_void)3597 void phydm_mcc_igi_chk(void *dm_void)
3598 {
3599 struct dm_struct *dm = (struct dm_struct *)dm_void;
3600 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3601
3602 if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
3603 mcc_dm->mcc_dm_val[0][1] == 0xff) {
3604 mcc_dm->mcc_dm_reg[0] = 0xffff;
3605 mcc_dm->mcc_reg_id[0] = 0xff;
3606 }
3607 if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
3608 mcc_dm->mcc_dm_val[1][1] == 0xff) {
3609 mcc_dm->mcc_dm_reg[1] = 0xffff;
3610 mcc_dm->mcc_reg_id[1] = 0xff;
3611 }
3612 }
3613
phydm_mcc_igi_cal(void * dm_void)3614 void phydm_mcc_igi_cal(void *dm_void)
3615 {
3616 struct dm_struct *dm = (struct dm_struct *)dm_void;
3617 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3618 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3619 u8 shift = 0;
3620 u8 igi_val0, igi_val1;
3621
3622 if (mcc_dm->mcc_rssi[0] == 0xff)
3623 phydm_mcc_igi_clr(dm, 0);
3624 if (mcc_dm->mcc_rssi[1] == 0xff)
3625 phydm_mcc_igi_clr(dm, 1);
3626 phydm_mcc_igi_chk(dm);
3627 igi_val0 = mcc_dm->mcc_rssi[0] - shift;
3628 igi_val1 = mcc_dm->mcc_rssi[1] - shift;
3629
3630 if (igi_val0 < DIG_MIN_PERFORMANCE)
3631 igi_val0 = DIG_MIN_PERFORMANCE;
3632
3633 if (igi_val1 < DIG_MIN_PERFORMANCE)
3634 igi_val1 = DIG_MIN_PERFORMANCE;
3635
3636 switch (dm->ic_ip_series) {
3637 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
3638 case PHYDM_IC_JGR3:
3639 phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
3640 phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
3641 break;
3642 #endif
3643 default:
3644 phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);
3645 phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);
3646 break;
3647 }
3648
3649 PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
3650 mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
3651 mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
3652 }
3653 #endif /*#if (RTL8822B_SUPPORT)*/
3654 #endif /*#ifdef CONFIG_MCC_DM*/
3655