1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_AUTO_DEGBUG
34
phydm_check_hang_reset(void * dm_void)35 void phydm_check_hang_reset(
36 void *dm_void)
37 {
38 struct dm_struct *dm = (struct dm_struct *)dm_void;
39 struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
40
41 atd_t->dbg_step = 0;
42 atd_t->auto_dbg_type = AUTO_DBG_STOP;
43 phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
44 dm->debug_components &= (~ODM_COMP_API);
45 }
46
phydm_check_hang_init(void * dm_void)47 void phydm_check_hang_init(
48 void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51 struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
52
53 atd_t->dbg_step = 0;
54 atd_t->auto_dbg_type = AUTO_DBG_STOP;
55 phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
56 }
57
58 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_auto_check_hang_engine_n(void * dm_void)59 void phydm_auto_check_hang_engine_n(
60 void *dm_void)
61 {
62 struct dm_struct *dm = (struct dm_struct *)dm_void;
63 struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
64 struct n_dbgport_803 dbgport_803 = {0};
65 u32 value32_tmp = 0, value32_tmp_2 = 0;
66 u8 i;
67 u32 curr_dbg_port_val[DBGPORT_CHK_NUM] = {0, 0, 0, 0, 0, 0};
68 u16 curr_ofdm_t_cnt;
69 u16 curr_ofdm_r_cnt;
70 u16 curr_cck_t_cnt;
71 u16 curr_cck_r_cnt;
72 u16 curr_ofdm_crc_error_cnt;
73 u16 curr_cck_crc_error_cnt;
74 u16 diff_ofdm_t_cnt;
75 u16 diff_ofdm_r_cnt;
76 u16 diff_cck_t_cnt;
77 u16 diff_cck_r_cnt;
78 u16 diff_ofdm_crc_error_cnt;
79 u16 diff_cck_crc_error_cnt;
80 u8 rf_mode;
81
82 if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
83 return;
84
85 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
86 phydm_check_hang_reset(dm);
87 return;
88 }
89
90 if (atd_t->dbg_step == 0) {
91 pr_debug("dbg_step=0\n\n");
92
93 /*Reset all packet counter*/
94 odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
95 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
96
97 } else if (atd_t->dbg_step == 1) {
98 pr_debug("dbg_step=1\n\n");
99
100 /*Check packet counter Register*/
101 atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
102 atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
103 atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
104 MASKHWORD);
105
106 atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
107 atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
108 atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
109 0x3fff);
110
111 /*Check Debug Port*/
112 for (i = 0; i < DBGPORT_CHK_NUM; i++) {
113 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
114 (u32)atd_t->dbg_port_table[i])
115 ) {
116 atd_t->dbg_port_val[i] =
117 phydm_get_bb_dbg_port_val(dm);
118 phydm_release_bb_dbg_port(dm);
119 }
120 }
121
122 } else if (atd_t->dbg_step == 2) {
123 pr_debug("dbg_step=2\n\n");
124
125 /*Check packet counter Register*/
126 curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
127 curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
128 curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
129 MASKHWORD);
130
131 curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
132 curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
133 curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
134 0x3fff);
135
136 /*Check Debug Port*/
137 for (i = 0; i < DBGPORT_CHK_NUM; i++) {
138 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
139 (u32)atd_t->dbg_port_table[i])
140 ) {
141 curr_dbg_port_val[i] =
142 phydm_get_bb_dbg_port_val(dm);
143 phydm_release_bb_dbg_port(dm);
144 }
145 }
146
147 /*=== Make check hang decision ===============================*/
148 pr_debug("Check Hang Decision\n\n");
149
150 /* ----- Check RF Register -----------------------------------*/
151 for (i = 0; i < dm->num_rf_path; i++) {
152 rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);
153 pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
154 if (rf_mode > 3) {
155 pr_debug("Incorrect RF mode\n");
156 pr_debug("ReasonCode:RHN-1\n");
157 }
158 }
159 value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);
160 if (dm->support_ic_type == ODM_RTL8188E) {
161 if (value32_tmp != 0xff8c8) {
162 pr_debug("ReasonCode:RHN-3\n");
163 }
164 }
165 /* ----- Check BB Register ----------------------------------*/
166 /*BB mode table*/
167 value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);
168 value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);
169 pr_debug("BB TX mode table {A, B}= {%d, %d}\n",
170 value32_tmp, value32_tmp_2);
171
172 if (value32_tmp > 3 || value32_tmp_2 > 3) {
173 pr_debug("ReasonCode:RHN-2\n");
174 }
175
176 value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);
177 value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);
178 pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp,
179 value32_tmp_2);
180
181 if (value32_tmp > 3 || value32_tmp_2 > 3) {
182 pr_debug("ReasonCode:RHN-2\n");
183 }
184
185 /*BB HW Block*/
186 value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);
187
188 if (!(value32_tmp & BIT(24))) {
189 pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
190 pr_debug("ReasonCode: THN-3\n");
191 }
192
193 if (!(value32_tmp & BIT(25))) {
194 pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
195 pr_debug("ReasonCode:THN-3\n");
196 }
197
198 /*BB Continue TX*/
199 value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);
200 pr_debug("Continue TX=%d\n", value32_tmp);
201 if (value32_tmp != 0) {
202 pr_debug("ReasonCode: THN-4\n");
203 }
204
205 /* ----- Check Packet Counter --------------------------------*/
206 diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
207 diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
208 diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -
209 atd_t->ofdm_crc_error_cnt;
210
211 diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
212 diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
213 diff_cck_crc_error_cnt = curr_cck_crc_error_cnt -
214 atd_t->cck_crc_error_cnt;
215
216 pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
217 atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,
218 atd_t->ofdm_crc_error_cnt);
219 pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
220 curr_ofdm_t_cnt, curr_ofdm_r_cnt,
221 curr_ofdm_crc_error_cnt);
222 pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
223 diff_ofdm_t_cnt, diff_ofdm_r_cnt,
224 diff_ofdm_crc_error_cnt);
225
226 pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
227 atd_t->cck_t_cnt, atd_t->cck_r_cnt,
228 atd_t->cck_crc_error_cnt);
229 pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
230 curr_cck_t_cnt, curr_cck_r_cnt,
231 curr_cck_crc_error_cnt);
232 pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
233 diff_cck_t_cnt, diff_cck_r_cnt,
234 diff_cck_crc_error_cnt);
235
236 /* ----- Check Dbg Port --------------------------------*/
237
238 for (i = 0; i < DBGPORT_CHK_NUM; i++) {
239 pr_debug("Dbg_port=((0x%x))\n",
240 atd_t->dbg_port_table[i]);
241 pr_debug("Val{pre, curr}={0x%x, 0x%x}\n",
242 atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
243
244 if (atd_t->dbg_port_table[i] == 0) {
245 if (atd_t->dbg_port_val[i] ==
246 curr_dbg_port_val[i]) {
247 pr_debug("BB state hang\n");
248 pr_debug("ReasonCode:\n");
249 }
250
251 } else if (atd_t->dbg_port_table[i] == 0x803) {
252 if (atd_t->dbg_port_val[i] ==
253 curr_dbg_port_val[i]) {
254 /* dbgport_803 = */
255 /* (struct n_dbgport_803 ) */
256 /* (atd_t->dbg_port_val[i]); */
257 odm_move_memory(dm, &dbgport_803,
258 &atd_t->dbg_port_val[i],
259 sizeof(struct n_dbgport_803));
260 pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n",
261 dbgport_803.bb_rst_b,
262 dbgport_803.glb_rst_b,
263 dbgport_803.ofdm_rst_b);
264 pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n",
265 dbgport_803.ofdm_tx_en,
266 dbgport_803.cck_tx_en,
267 dbgport_803.phy_tx_on);
268 pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n",
269 dbgport_803.ofdm_cca_pp,
270 dbgport_803.cck_cca_pp);
271
272 if (dbgport_803.phy_tx_on)
273 pr_debug("Maybe TX Hang\n");
274 else if (dbgport_803.ofdm_cca_pp ||
275 dbgport_803.cck_cca_pp)
276 pr_debug("Maybe RX Hang\n");
277 }
278
279 } else if (atd_t->dbg_port_table[i] == 0x208) {
280 if ((atd_t->dbg_port_val[i] & BIT(30)) &&
281 (curr_dbg_port_val[i] & BIT(30))) {
282 pr_debug("EDCCA Pause TX\n");
283 pr_debug("ReasonCode: THN-2\n");
284 }
285
286 } else if (atd_t->dbg_port_table[i] == 0xab0) {
287 /* atd_t->dbg_port_val[i] & 0xffffff == 0 */
288 /* curr_dbg_port_val[i] & 0xffffff == 0 */
289 if (((atd_t->dbg_port_val[i] &
290 MASK24BITS) == 0) ||
291 ((curr_dbg_port_val[i] &
292 MASK24BITS) == 0)) {
293 pr_debug("Wrong L-SIG formate\n");
294 pr_debug("ReasonCode: THN-1\n");
295 }
296 }
297 }
298
299 phydm_check_hang_reset(dm);
300 }
301
302 atd_t->dbg_step++;
303 }
304
phydm_bb_auto_check_hang_start_n(void * dm_void,u32 * _used,char * output,u32 * _out_len)305 void phydm_bb_auto_check_hang_start_n(
306 void *dm_void,
307 u32 *_used,
308 char *output,
309 u32 *_out_len)
310 {
311 u32 value32 = 0;
312 struct dm_struct *dm = (struct dm_struct *)dm_void;
313 struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
314 u32 used = *_used;
315 u32 out_len = *_out_len;
316
317 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
318 return;
319
320 PDM_SNPF(out_len, used, output + used, out_len - used,
321 "PHYDM auto check hang (N-series) is started, Please check the system log\n");
322
323 dm->debug_components |= ODM_COMP_API;
324 atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
325 atd_t->dbg_step = 0;
326
327 phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
328
329 *_used = used;
330 *_out_len = out_len;
331 }
332
phydm_dbg_port_dump_n(void * dm_void,u32 * _used,char * output,u32 * _out_len)333 void phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output,
334 u32 *_out_len)
335 {
336 u32 value32 = 0;
337 struct dm_struct *dm = (struct dm_struct *)dm_void;
338 u32 used = *_used;
339 u32 out_len = *_out_len;
340
341 if (dm->support_ic_type & ODM_IC_11AC_SERIES)
342 return;
343
344 PDM_SNPF(out_len, used, output + used, out_len - used,
345 "not support now\n");
346
347 *_used = used;
348 *_out_len = out_len;
349 }
350
351 #endif
352
353 #if (ODM_IC_11AC_SERIES_SUPPORT == 1)
phydm_dbg_port_dump_ac(void * dm_void,u32 * _used,char * output,u32 * _out_len)354 void phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output,
355 u32 *_out_len)
356 {
357 u32 value32 = 0;
358 struct dm_struct *dm = (struct dm_struct *)dm_void;
359 u32 used = *_used;
360 u32 out_len = *_out_len;
361
362 if (dm->support_ic_type & ODM_IC_11N_SERIES)
363 return;
364
365 value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
366 PDM_SNPF(out_len, used, output + used, out_len - used,
367 "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32);
368
369 if (dm->support_ic_type & ODM_RTL8822B)
370 odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);
371
372 /* dbg_port = basic state machine */
373 {
374 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
375 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
376 PDM_SNPF(out_len, used, output + used, out_len - used,
377 "\r\n %-35s = 0x%x", "0x8fc", value32);
378
379 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
380 PDM_SNPF(out_len, used, output + used, out_len - used,
381 "\r\n %-35s = 0x%x", "basic state machine", value32);
382 }
383
384 /* dbg_port = state machine */
385 {
386 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
387 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
388 PDM_SNPF(out_len, used, output + used, out_len - used,
389 "\r\n %-35s = 0x%x", "0x8fc", value32);
390
391 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
392 PDM_SNPF(out_len, used, output + used, out_len - used,
393 "\r\n %-35s = 0x%x", "state machine", value32);
394 }
395
396 /* dbg_port = CCA-related*/
397 {
398 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
399 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
400 PDM_SNPF(out_len, used, output + used, out_len - used,
401 "\r\n %-35s = 0x%x", "0x8fc", value32);
402
403 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
404 PDM_SNPF(out_len, used, output + used, out_len - used,
405 "\r\n %-35s = 0x%x", "CCA-related", value32);
406 }
407
408 /* dbg_port = edcca/rxd*/
409 {
410 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
411 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
412 PDM_SNPF(out_len, used, output + used, out_len - used,
413 "\r\n %-35s = 0x%x", "0x8fc", value32);
414
415 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
416 PDM_SNPF(out_len, used, output + used, out_len - used,
417 "\r\n %-35s = 0x%x", "edcca/rxd", value32);
418 }
419
420 /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
421 {
422 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
423 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
424 PDM_SNPF(out_len, used, output + used, out_len - used,
425 "\r\n %-35s = 0x%x", "0x8fc", value32);
426
427 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
428 PDM_SNPF(out_len, used, output + used, out_len - used,
429 "\r\n %-35s = 0x%x",
430 "rx_state/mux_state/ADC_MASK_OFDM", value32);
431 }
432
433 /* dbg_port = bf-related*/
434 {
435 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
436 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
437 PDM_SNPF(out_len, used, output + used, out_len - used,
438 "\r\n %-35s = 0x%x", "0x8fc", value32);
439
440 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
441 PDM_SNPF(out_len, used, output + used, out_len - used,
442 "\r\n %-35s = 0x%x", "bf-related", value32);
443 }
444
445 /* dbg_port = bf-related*/
446 {
447 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
448 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
449 PDM_SNPF(out_len, used, output + used, out_len - used,
450 "\r\n %-35s = 0x%x", "0x8fc", value32);
451
452 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
453 PDM_SNPF(out_len, used, output + used, out_len - used,
454 "\r\n %-35s = 0x%x", "bf-related", value32);
455 }
456
457 /* dbg_port = txon/rxd*/
458 {
459 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
460 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
461 PDM_SNPF(out_len, used, output + used, out_len - used,
462 "\r\n %-35s = 0x%x", "0x8fc", value32);
463
464 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
465 PDM_SNPF(out_len, used, output + used, out_len - used,
466 "\r\n %-35s = 0x%x", "txon/rxd", value32);
467 }
468
469 /* dbg_port = l_rate/l_length*/
470 {
471 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
472 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
473 PDM_SNPF(out_len, used, output + used, out_len - used,
474 "\r\n %-35s = 0x%x", "0x8fc", value32);
475
476 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
477 PDM_SNPF(out_len, used, output + used, out_len - used,
478 "\r\n %-35s = 0x%x", "l_rate/l_length", value32);
479 }
480
481 /* dbg_port = rxd/rxd_hit*/
482 {
483 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
484 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
485 PDM_SNPF(out_len, used, output + used, out_len - used,
486 "\r\n %-35s = 0x%x", "0x8fc", value32);
487
488 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
489 PDM_SNPF(out_len, used, output + used, out_len - used,
490 "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
491 }
492
493 /* dbg_port = dis_cca*/
494 {
495 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
496 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
497 PDM_SNPF(out_len, used, output + used, out_len - used,
498 "\r\n %-35s = 0x%x", "0x8fc", value32);
499
500 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
501 PDM_SNPF(out_len, used, output + used, out_len - used,
502 "\r\n %-35s = 0x%x", "dis_cca", value32);
503 }
504
505 /* dbg_port = tx*/
506 {
507 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
508 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
509 PDM_SNPF(out_len, used, output + used, out_len - used,
510 "\r\n %-35s = 0x%x", "0x8fc", value32);
511
512 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
513 PDM_SNPF(out_len, used, output + used, out_len - used,
514 "\r\n %-35s = 0x%x", "tx", value32);
515 }
516
517 /* dbg_port = rx plcp*/
518 {
519 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
520 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
521 PDM_SNPF(out_len, used, output + used, out_len - used,
522 "\r\n %-35s = 0x%x", "0x8fc", value32);
523
524 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
525 PDM_SNPF(out_len, used, output + used, out_len - used,
526 "\r\n %-35s = 0x%x", "rx plcp", value32);
527
528 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
529 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
530 PDM_SNPF(out_len, used, output + used, out_len - used,
531 "\r\n %-35s = 0x%x", "0x8fc", value32);
532
533 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
534 PDM_SNPF(out_len, used, output + used, out_len - used,
535 "\r\n %-35s = 0x%x", "rx plcp", value32);
536
537 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
538 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
539 PDM_SNPF(out_len, used, output + used, out_len - used,
540 "\r\n %-35s = 0x%x", "0x8fc", value32);
541
542 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
543 PDM_SNPF(out_len, used, output + used, out_len - used,
544 "\r\n %-35s = 0x%x", "rx plcp", value32);
545
546 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
547 value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
548 PDM_SNPF(out_len, used, output + used, out_len - used,
549 "\r\n %-35s = 0x%x", "0x8fc", value32);
550
551 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
552 PDM_SNPF(out_len, used, output + used, out_len - used,
553 "\r\n %-35s = 0x%x", "rx plcp", value32);
554 }
555 *_used = used;
556 *_out_len = out_len;
557 }
558 #endif
559
560 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_dbg_port_dump_jgr3(void * dm_void,u32 * _used,char * output,u32 * _out_len)561 void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
562 u32 *_out_len)
563 {
564 struct dm_struct *dm = (struct dm_struct *)dm_void;
565 u32 used = *_used;
566 u32 out_len = *_out_len;
567 /*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/
568 u32 val = 0;
569 u32 dbg_port_idx = 0;
570 u32 i = 0;
571
572 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
573 return;
574
575 PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
576 "%-17s = %s\n", "DbgPort index", "Value");
577
578 #if 0
579 /*0x000/0x001/0x002*/
580 for (i = 0; i < 3; i++) {
581 dbg_port_idx = dbg_port_idx_all[i];
582 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
583 val = phydm_get_bb_dbg_port_val(dm);
584 PDM_SNPF(out_len, used, output + used, out_len - used,
585 "0x%-15x = 0x%x\n", dbg_port_idx, val);
586 phydm_release_bb_dbg_port(dm);
587 }
588 }
589 #endif
590 for (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) {
591 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
592 val = phydm_get_bb_dbg_port_val(dm);
593 PDM_VAST_SNPF(out_len, used, output + used,
594 out_len - used,
595 "0x%-15x = 0x%x\n", dbg_port_idx, val);
596 phydm_release_bb_dbg_port(dm);
597 }
598 }
599 *_used = used;
600 *_out_len = out_len;
601 }
602 #endif
603
phydm_dbg_port_dump(void * dm_void,u32 * _used,char * output,u32 * _out_len)604 void phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
605 {
606 struct dm_struct *dm = (struct dm_struct *)dm_void;
607 u32 used = *_used;
608 u32 out_len = *_out_len;
609
610 PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
611 "------ BB debug port start ------\n");
612
613 switch (dm->ic_ip_series) {
614 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
615 case PHYDM_IC_JGR3:
616 phydm_dbg_port_dump_jgr3(dm, &used, output, &out_len);
617 break;
618 #endif
619
620 #if (ODM_IC_11AC_SERIES_SUPPORT == 1)
621 case PHYDM_IC_AC:
622 phydm_dbg_port_dump_ac(dm, &used, output, &out_len);
623 break;
624 #endif
625
626 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
627 case PHYDM_IC_N:
628 phydm_dbg_port_dump_n(dm, &used, output, &out_len);
629 break;
630 #endif
631
632 default:
633 break;
634 }
635 *_used = used;
636 *_out_len = out_len;
637 }
638
phydm_auto_dbg_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)639 void phydm_auto_dbg_console(
640 void *dm_void,
641 char input[][16],
642 u32 *_used,
643 char *output,
644 u32 *_out_len)
645 {
646 struct dm_struct *dm = (struct dm_struct *)dm_void;
647 char help[] = "-h";
648 u32 var1[10] = {0};
649 u32 used = *_used;
650 u32 out_len = *_out_len;
651
652 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
653
654 if ((strcmp(input[1], help) == 0)) {
655 PDM_SNPF(out_len, used, output + used, out_len - used,
656 "hang: {1} {1:Show DbgPort, 2:Auto check hang}\n");
657 return;
658 } else if (var1[0] == 1) {
659 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
660 if (var1[1] == 1) {
661 phydm_dbg_port_dump(dm, &used, output, &out_len);
662 } else if (var1[1] == 2) {
663 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
664 PDM_SNPF(out_len, used, output + used,
665 out_len - used, "Not support\n");
666 } else {
667 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
668 phydm_bb_auto_check_hang_start_n(dm, &used,
669 output,
670 &out_len);
671 #else
672 PDM_SNPF(out_len, used, output + used,
673 out_len - used, "Not support\n");
674 #endif
675 }
676 }
677 }
678
679 *_used = used;
680 *_out_len = out_len;
681 }
682
phydm_auto_dbg_engine(void * dm_void)683 void phydm_auto_dbg_engine(void *dm_void)
684 {
685 u32 value32 = 0;
686
687 struct dm_struct *dm = (struct dm_struct *)dm_void;
688 struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
689
690 if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
691 return;
692
693 pr_debug("%s ======>\n", __func__);
694
695 if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
696 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
697 pr_debug("Not Support\n");
698 } else {
699 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
700 phydm_auto_check_hang_engine_n(dm);
701 #else
702 pr_debug("Not Support\n");
703 #endif
704 }
705
706 } else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
707 pr_debug("Not Support\n");
708 }
709 }
710
phydm_auto_dbg_engine_init(void * dm_void)711 void phydm_auto_dbg_engine_init(void *dm_void)
712 {
713 struct dm_struct *dm = (struct dm_struct *)dm_void;
714 struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
715 u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
716 0xab1, 0xab2};
717
718 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
719
720 odm_move_memory(dm, &atd_t->dbg_port_table[0],
721 &dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
722
723 phydm_check_hang_init(dm);
724 }
725 #endif
726