1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
phydm_rxsc_2_bw(void * dm_void,u8 rxsc)34 enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 enum channel_width bw = 0;
38
39 /* @Check RX bandwidth */
40 if (rxsc == 0)
41 bw = *dm->band_width; /*@full bw*/
42 else if (rxsc >= 1 && rxsc <= 8)
43 bw = CHANNEL_WIDTH_20;
44 else if (rxsc >= 9 && rxsc <= 12)
45 bw = CHANNEL_WIDTH_40;
46 else /*if (rxsc >= 13)*/
47 bw = CHANNEL_WIDTH_80;
48
49 return bw;
50 }
51
phydm_reset_bb_hw_cnt(void * dm_void)52 void phydm_reset_bb_hw_cnt(void *dm_void)
53 {
54 struct dm_struct *dm = (struct dm_struct *)dm_void;
55
56 /*@ Reset all counter when 1 */
57 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
58 #if (RTL8723F_SUPPORT)
59 if (dm->support_ic_type & ODM_RTL8723F) {
60 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
61 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
62 }
63 #endif
64 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
65 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
66 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
67 /*@ Reset all counter when 1 (including PMAC and PHY)*/
68 /* Reset Page F counter*/
69 odm_set_bb_reg(dm, R_0xb58, BIT(0), 1);
70 odm_set_bb_reg(dm, R_0xb58, BIT(0), 0);
71 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
72 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1);
73 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);
74 }
75 }
76
phydm_dynamic_ant_weighting(void * dm_void)77 void phydm_dynamic_ant_weighting(void *dm_void)
78 {
79 struct dm_struct *dm = (struct dm_struct *)dm_void;
80
81 #ifdef DYN_ANT_WEIGHTING_SUPPORT
82 #if (RTL8197F_SUPPORT)
83 if (dm->support_ic_type & (ODM_RTL8197F))
84 phydm_dynamic_ant_weighting_8197f(dm);
85 #endif
86
87 #if (RTL8812A_SUPPORT)
88 if (dm->support_ic_type & (ODM_RTL8812)) {
89 phydm_dynamic_ant_weighting_8812a(dm);
90 }
91 #endif
92
93 #if (RTL8822B_SUPPORT)
94 if (dm->support_ic_type & (ODM_RTL8822B))
95 phydm_dynamic_ant_weighting_8822b(dm);
96 #endif
97 #endif
98 }
99
100 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_ant_weight_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)101 void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
102 char *output, u32 *_out_len)
103 {
104 struct dm_struct *dm = (struct dm_struct *)dm_void;
105 char help[] = "-h";
106 u32 var1[10] = {0};
107 u32 used = *_used;
108 u32 out_len = *_out_len;
109
110 if (!(dm->support_ic_type &
111 (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8812 | ODM_RTL8197F))) {
112 return;
113 }
114
115 if ((strcmp(input[1], help) == 0)) {
116 PDM_SNPF(out_len, used, output + used, out_len - used,
117 "echo dis_dym_ant_weighting {0/1}\n");
118
119 } else {
120 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
121
122 if (var1[0] == 1) {
123 dm->is_disable_dym_ant_weighting = 1;
124 PDM_SNPF(out_len, used, output + used, out_len - used,
125 "Disable dyn-ant-weighting\n");
126 } else {
127 dm->is_disable_dym_ant_weighting = 0;
128 PDM_SNPF(out_len, used, output + used, out_len - used,
129 "Enable dyn-ant-weighting\n");
130 }
131 }
132 *_used = used;
133 *_out_len = out_len;
134 }
135 #endif
136
phydm_trx_antenna_setting_init(void * dm_void,u8 num_rf_path)137 void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
138 {
139 struct dm_struct *dm = (struct dm_struct *)dm_void;
140 u8 rx_ant = 0, tx_ant = 0;
141 u8 path_bitmap = 1;
142
143 path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
144
145 /*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
146
147 dm->tx_ant_status = path_bitmap;
148 dm->rx_ant_status = path_bitmap;
149
150 if (num_rf_path == PDM_1SS)
151 return;
152
153 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
154 if (dm->support_ic_type &
155 (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {
156 dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);
157 dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);
158 } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {
159 dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);
160 dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);
161 }
162 #endif
163 /* @trx_ant_status are already updated in trx mode API in JGR3 ICs */
164
165 PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n",
166 __func__, dm->tx_ant_status, dm->rx_ant_status);
167 }
168
phydm_config_ofdm_tx_path(void * dm_void,enum bb_path path)169 void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path)
170 {
171 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT || RTL8812A_SUPPORT)
172 struct dm_struct *dm = (struct dm_struct *)dm_void;
173 u8 ofdm_tx_path = 0x33;
174
175 if (dm->num_rf_path == PDM_1SS)
176 return;
177
178 switch (dm->support_ic_type) {
179 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
180 case ODM_RTL8192E:
181 case ODM_RTL8192F:
182 if (path == BB_PATH_A)
183 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
184 else if (path == BB_PATH_B)
185 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221323);
186 else if (path == BB_PATH_AB)
187 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
188
189 break;
190 #endif
191
192 #if (RTL8812A_SUPPORT)
193 case ODM_RTL8812:
194 if (path == BB_PATH_A)
195 ofdm_tx_path = 0x11;
196 else if (path == BB_PATH_B)
197 ofdm_tx_path = 0x22;
198 else if (path == BB_PATH_AB)
199 ofdm_tx_path = 0x33;
200
201 odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);
202
203 break;
204 #endif
205
206 default:
207 break;
208 }
209 #endif
210 }
211
phydm_config_ofdm_rx_path(void * dm_void,enum bb_path path)212 void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path)
213 {
214 struct dm_struct *dm = (struct dm_struct *)dm_void;
215 u8 val = 0;
216
217 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8192F)) {
218 #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
219 if (path == BB_PATH_A)
220 val = 1;
221 else if (path == BB_PATH_B)
222 val = 2;
223 else if (path == BB_PATH_AB)
224 val = 3;
225
226 odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));
227 odm_set_bb_reg(dm, R_0xd04, 0xf, val);
228 #endif
229 }
230 #if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
231 else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
232 if (path == BB_PATH_A)
233 val = 1;
234 else if (path == BB_PATH_B)
235 val = 2;
236 else if (path == BB_PATH_AB)
237 val = 3;
238
239 odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));
240 }
241 #endif
242 }
243
phydm_config_cck_rx_antenna_init(void * dm_void)244 void phydm_config_cck_rx_antenna_init(void *dm_void)
245 {
246 struct dm_struct *dm = (struct dm_struct *)dm_void;
247
248 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
249 if (dm->support_ic_type & ODM_IC_1SS)
250 return;
251
252 /*@CCK 2R CCA parameters*/
253 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/
254 odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/
255 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/
256 odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
257 odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/
258
259 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))
260 odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
261 else if (dm->support_ic_type & ODM_RTL8814A)
262 odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/
263 #endif
264 }
265
phydm_config_cck_rx_path(void * dm_void,enum bb_path path)266 void phydm_config_cck_rx_path(void *dm_void, enum bb_path path)
267 {
268 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
269 struct dm_struct *dm = (struct dm_struct *)dm_void;
270 u8 path_div_select = 0;
271 u8 cck_path[2] = {0};
272 u8 en_2R_path = 0;
273 u8 en_2R_mrc = 0;
274 u8 i = 0, j = 0;
275 u8 num_enable_path = 0;
276 u8 cck_mrc_max_path = 2;
277
278 if (dm->support_ic_type & ODM_IC_1SS)
279 return;
280
281 for (i = 0; i < 4; i++) {
282 if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/
283 num_enable_path++;
284 cck_path[j] = i;
285 j++;
286 }
287 if (num_enable_path >= cck_mrc_max_path)
288 break;
289 }
290
291 if (num_enable_path > 1) {
292 path_div_select = 1;
293 en_2R_path = 1;
294 en_2R_mrc = 1;
295 } else {
296 path_div_select = 0;
297 en_2R_path = 0;
298 en_2R_mrc = 0;
299 }
300 /*@CCK_1 input signal path*/
301 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);
302 /*@CCK_2 input signal path*/
303 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);
304 /*@enable Rx path diversity*/
305 odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);
306 /*@enable 2R Rx path*/
307 odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);
308 /*@enable 2R MRC*/
309 odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);
310 if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
311 if (path == BB_PATH_A) {
312 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
313 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
314 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
315 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
316 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
317 } else if (path == BB_PATH_B) {/*@for DC cancellation*/
318 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
319 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
320 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
321 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
322 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
323 } else if (path == BB_PATH_AB) {
324 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
325 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
326 odm_set_bb_reg(dm, R_0xa74, BIT(8), 1);
327 odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);
328 odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);
329 }
330 } else if (dm->support_ic_type & ODM_RTL8822B) {
331 if (path == BB_PATH_A) {
332 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
333 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
334 } else {
335 odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
336 odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
337 }
338 }
339
340 #endif
341 }
342
phydm_config_cck_tx_path(void * dm_void,enum bb_path path)343 void phydm_config_cck_tx_path(void *dm_void, enum bb_path path)
344 {
345 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
346 struct dm_struct *dm = (struct dm_struct *)dm_void;
347
348 if (path == BB_PATH_A)
349 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
350 else if (path == BB_PATH_B)
351 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
352 else /*if (path == BB_PATH_AB)*/
353 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
354 #endif
355 }
356
phydm_config_trx_path_v2(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)357 void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
358 char *output, u32 *_out_len)
359 {
360 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
361 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\
362 RTL8812F_SUPPORT || RTL8198F_SUPPORT)
363 struct dm_struct *dm = (struct dm_struct *)dm_void;
364 u32 used = *_used;
365 u32 out_len = *_out_len;
366 u32 val[10] = {0};
367 char help[] = "-h";
368 u8 i = 0, input_idx = 0;
369 enum bb_path tx_path, rx_path, tx_path_ctrl;
370 boolean dbg_mode_en;
371
372 if (!(dm->support_ic_type &
373 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |
374 ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8198F)))
375 return;
376
377 for (i = 0; i < 5; i++) {
378 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
379 input_idx++;
380 }
381
382 if (input_idx == 0)
383 return;
384
385 dbg_mode_en = (boolean)val[0];
386 tx_path = (enum bb_path)val[1];
387 rx_path = (enum bb_path)val[2];
388 tx_path_ctrl = (enum bb_path)val[3];
389
390 if ((strcmp(input[1], help) == 0)) {
391 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8822B |
392 ODM_RTL8192F)) {
393 PDM_SNPF(out_len, used, output + used, out_len - used,
394 "{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\n"
395 );
396 } else {
397 PDM_SNPF(out_len, used, output + used, out_len - used,
398 "{en} {tx_path} {rx_path} {is_tx_2_path}\n");
399 }
400
401 } else if (dbg_mode_en) {
402 dm->is_disable_phy_api = false;
403 phydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl);
404 dm->is_disable_phy_api = true;
405 PDM_SNPF(out_len, used, output + used, out_len - used,
406 "T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\n",
407 tx_path, rx_path, tx_path_ctrl);
408 PDM_SNPF(out_len, used, output + used, out_len - used,
409 "T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\n",
410 dm->tx_ant_status, dm->rx_ant_status,
411 dm->tx_1ss_status);
412 } else {
413 dm->is_disable_phy_api = false;
414 PDM_SNPF(out_len, used, output + used, out_len - used,
415 "Disable API debug mode\n");
416 }
417 #endif
418 }
419
phydm_config_trx_path_v1(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)420 void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,
421 char *output, u32 *_out_len)
422 {
423 #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
424 struct dm_struct *dm = (struct dm_struct *)dm_void;
425 u32 used = *_used;
426 u32 out_len = *_out_len;
427 u32 val[10] = {0};
428 char help[] = "-h";
429 u8 i = 0, input_idx = 0;
430
431 if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))
432 return;
433
434 for (i = 0; i < 5; i++) {
435 if (input[i + 1]) {
436 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
437 input_idx++;
438 }
439 }
440
441 if (input_idx == 0)
442 return;
443
444 if ((strcmp(input[1], help) == 0)) {
445 PDM_SNPF(out_len, used, output + used, out_len - used,
446 "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n");
447
448 *_used = used;
449 *_out_len = out_len;
450 return;
451
452 } else if (val[0] == 0) {
453 /* @CCK */
454 if (val[1] == 1) { /*TX*/
455 if (val[2] == 1)
456 phydm_config_cck_tx_path(dm, BB_PATH_A);
457 else if (val[2] == 2)
458 phydm_config_cck_tx_path(dm, BB_PATH_B);
459 else if (val[2] == 3)
460 phydm_config_cck_tx_path(dm, BB_PATH_AB);
461 } else if (val[1] == 2) { /*RX*/
462
463 phydm_config_cck_rx_antenna_init(dm);
464
465 if (val[2] == 1)
466 phydm_config_cck_rx_path(dm, BB_PATH_A);
467 else if (val[2] == 2)
468 phydm_config_cck_rx_path(dm, BB_PATH_B);
469 else if (val[2] == 3)
470 phydm_config_cck_rx_path(dm, BB_PATH_AB);
471 }
472 }
473 /* OFDM */
474 else if (val[0] == 1) {
475 if (val[1] == 1) /*TX*/
476 phydm_config_ofdm_tx_path(dm, val[2]);
477 else if (val[1] == 2) /*RX*/
478 phydm_config_ofdm_rx_path(dm, val[2]);
479 }
480
481 PDM_SNPF(out_len, used, output + used, out_len - used,
482 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
483 (val[0] == 1) ? "OFDM" : "CCK",
484 (val[1] == 1) ? "TX" : "RX",
485 (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "",
486 (val[2] & 0x4) ? "C" : "",
487 (val[2] & 0x8) ? "D" : "");
488
489 *_used = used;
490 *_out_len = out_len;
491 #endif
492 }
493
phydm_config_trx_path(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)494 void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
495 char *output, u32 *_out_len)
496 {
497 struct dm_struct *dm = (struct dm_struct *)dm_void;
498
499 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
500 #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
501 phydm_config_trx_path_v1(dm, input, _used, output, _out_len);
502 #endif
503 } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |
504 ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |
505 ODM_RTL8197G | ODM_RTL8814B | ODM_RTL8198F)) {
506 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\
507 RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
508 RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
509 RTL8197G_SUPPORT || RTL8198F_SUPPORT)
510 phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
511 #endif
512 }
513 }
514
phydm_tx_2path(void * dm_void)515 void phydm_tx_2path(void *dm_void)
516 {
517 #if (defined(PHYDM_COMPILE_IC_2SS))
518 struct dm_struct *dm = (struct dm_struct *)dm_void;
519 enum bb_path rx_path = (enum bb_path)dm->rx_ant_status;
520
521 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
522
523
524 if (!(dm->support_ic_type & ODM_IC_2SS))
525 return;
526
527 #if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\
528 RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
529 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |
530 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
531 phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB);
532 #endif
533
534 #if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)
535 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
536 phydm_config_cck_tx_path(dm, BB_PATH_AB);
537 phydm_config_ofdm_tx_path(dm, BB_PATH_AB);
538 }
539 #endif
540 #endif
541 }
542
phydm_stop_3_wire(void * dm_void,u8 set_type)543 void phydm_stop_3_wire(void *dm_void, u8 set_type)
544 {
545 struct dm_struct *dm = (struct dm_struct *)dm_void;
546
547 if (set_type == PHYDM_SET) {
548 /*@[Stop 3-wires]*/
549 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
550 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0);
551 odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
552
553 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
554 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
555 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0);
556 odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
557 }
558 #endif
559
560 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
561 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
562 odm_set_bb_reg(dm, R_0x520c, 0x3, 0x0);
563 odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
564 odm_set_bb_reg(dm, R_0x530c, 0x3, 0x0);
565 odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
566 }
567 #endif
568 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
569 odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);
570 odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);
571 } else {
572 odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);
573 }
574
575 } else { /*@if (set_type == PHYDM_REVERT)*/
576
577 /*@[Start 3-wires]*/
578 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
579 odm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);
580 odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
581
582 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
583 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
584 odm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);
585 odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
586 }
587 #endif
588
589 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
590 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
591 odm_set_bb_reg(dm, R_0x520c, 0x3, 0x3);
592 odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
593 odm_set_bb_reg(dm, R_0x530c, 0x3, 0x3);
594 odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
595 }
596 #endif
597 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
598 odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);
599 odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);
600 } else {
601 odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);
602 }
603 }
604 }
605
phydm_stop_ic_trx(void * dm_void,u8 set_type)606 u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
607 {
608 struct dm_struct *dm = (struct dm_struct *)dm_void;
609 struct phydm_api_stuc *api = &dm->api_table;
610 u8 i = 0;
611 boolean trx_idle_success = false;
612 u32 dbg_port_value = 0;
613
614 if (set_type == PHYDM_SET) {
615 /*[Stop TRX]---------------------------------------------------------*/
616 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
617 #if (RTL8723F_SUPPORT)
618 /*Judy 2020-0515*/
619 /*set debug port to 0x0*/
620 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
621 return PHYDM_SET_FAIL;
622 #endif
623 for (i = 0; i < 100; i++) {
624 dbg_port_value = odm_get_bb_reg(dm, R_0x2db4,
625 MASKDWORD);
626 /* BB idle */
627 if ((dbg_port_value & 0x1FFEFF3F) == 0 &&
628 (dbg_port_value & 0xC0010000) ==
629 0xC0010000) {
630 PHYDM_DBG(dm, ODM_COMP_API,
631 "Stop trx wait for (%d) times\n",
632 i);
633
634 trx_idle_success = true;
635 break;
636 }
637 }
638 } else {
639 /*set debug port to 0x0*/
640 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
641 return PHYDM_SET_FAIL;
642 for (i = 0; i < 100; i++) {
643 dbg_port_value = phydm_get_bb_dbg_port_val(dm);
644 /* PHYTXON && CCA_all */
645 if (dm->support_ic_type & (ODM_RTL8721D |
646 ODM_RTL8710B | ODM_RTL8710C |
647 ODM_RTL8188F | ODM_RTL8723D)) {
648 if ((dbg_port_value &
649 (BIT(20) | BIT(15))) == 0) {
650 PHYDM_DBG(dm, ODM_COMP_API,
651 "Stop trx wait for (%d) times\n",
652 i);
653
654 trx_idle_success = true;
655 break;
656 }
657 } else {
658 if ((dbg_port_value &
659 (BIT(17) | BIT(3))) == 0) {
660 PHYDM_DBG(dm, ODM_COMP_API,
661 "Stop trx wait for (%d) times\n",
662 i);
663
664 trx_idle_success = true;
665 break;
666 }
667 }
668 ODM_delay_ms(1);
669 }
670 phydm_release_bb_dbg_port(dm);
671 }
672
673 if (trx_idle_success) {
674 api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
675
676 /*pause all TX queue*/
677 odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);
678
679 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
680 /*disable OFDM RX CCA*/
681 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
682 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
683 /*disable OFDM RX CCA*/
684 odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
685 } else {
686 api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
687 api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
688 /* [ Set IQK Matrix = 0 ]
689 * equivalent to [ Turn off CCA]
690 */
691 odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
692 odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);
693 }
694 phydm_dis_cck_trx(dm, PHYDM_SET);
695 } else {
696 return PHYDM_SET_FAIL;
697 }
698
699 return PHYDM_SET_SUCCESS;
700
701 } else { /*@if (set_type == PHYDM_REVERT)*/
702 /*Release all TX queue*/
703 odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);
704
705 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
706 /*@enable OFDM RX CCA*/
707 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
708 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
709 /*@enable OFDM RX CCA*/
710 odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
711 } else {
712 /* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/
713 odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);
714 odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);
715 }
716 phydm_dis_cck_trx(dm, PHYDM_REVERT);
717 return PHYDM_SET_SUCCESS;
718 }
719 }
720
phydm_dis_cck_trx(void * dm_void,u8 set_type)721 void phydm_dis_cck_trx(void *dm_void, u8 set_type)
722 {
723 struct dm_struct *dm = (struct dm_struct *)dm_void;
724 struct phydm_api_stuc *api = &dm->api_table;
725
726 if (set_type == PHYDM_SET) {
727 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
728 if(dm->support_ic_type & ODM_RTL8723F) {
729 api->ccktx_path = 1;
730 /* @disable CCK CCA */
731 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
732 /* @disable CCK Tx */
733 odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x1);
734 } else {
735 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
736 0xf0000000);
737 /* @CCK RxIQ weighting = [0,0] */
738 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
739 /* @disable CCK Tx */
740 odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
741 }
742 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
743 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
744 0xf0000000);
745 /* @disable CCK block */
746 odm_set_bb_reg(dm, R_0x808, BIT(28), 0);
747 /* @disable CCK Tx */
748 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
749 } else {
750 api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
751 0xf0000000);
752 /* @disable whole CCK block */
753 odm_set_bb_reg(dm, R_0x800, BIT(24), 0);
754 /* @disable CCK Tx */
755 odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
756 }
757 } else if (set_type == PHYDM_REVERT) {
758 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
759 if(dm->support_ic_type & ODM_RTL8723F) {
760 /* @enable CCK CCA */
761 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
762 /* @enable CCK Tx */
763 odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x0);
764 } else {
765 /* @CCK RxIQ weighting = [1,1] */
766 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
767 /* @enable CCK Tx */
768 odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
769 api->ccktx_path);
770 }
771 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
772 /* @enable CCK block */
773 odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
774 /* @enable CCK Tx */
775 odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
776 api->ccktx_path);
777 } else {
778 /* @enable whole CCK block */
779 odm_set_bb_reg(dm, R_0x800, BIT(24), 1);
780 /* @enable CCK Tx */
781 odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
782 api->ccktx_path);
783 }
784 }
785 }
786
phydm_bw_fixed_enable(void * dm_void,u8 enable)787 void phydm_bw_fixed_enable(void *dm_void, u8 enable)
788 {
789 #ifdef CONFIG_BW_INDICATION
790 struct dm_struct *dm = (struct dm_struct *)dm_void;
791 boolean val = (enable == FUNC_ENABLE) ? 1 : 0;
792
793 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B))
794 odm_set_bb_reg(dm, R_0x840, BIT(4), val);
795 else if (dm->support_ic_type & ODM_RTL8822C)
796 odm_set_bb_reg(dm, R_0x878, BIT(28), val);
797 #endif
798 }
799
phydm_bw_fixed_setting(void * dm_void)800 void phydm_bw_fixed_setting(void *dm_void)
801 {
802 #ifdef CONFIG_BW_INDICATION
803 struct dm_struct *dm = (struct dm_struct *)dm_void;
804 struct phydm_api_stuc *api = &dm->api_table;
805 u8 bw = *dm->band_width;
806 u32 reg = 0, reg_mask = 0, reg_value = 0;
807
808 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
809 return;
810
811 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
812 ODM_RTL8195B)) {
813 reg = R_0x840;
814 reg_mask = 0xf;
815 reg_value = api->pri_ch_idx;
816 } else if (dm->support_ic_type & ODM_RTL8822C) {
817 reg = R_0x878;
818 reg_mask = 0xc0000000;
819 reg_value = 0x0;
820 }
821
822 switch (bw) {
823 case CHANNEL_WIDTH_80:
824 odm_set_bb_reg(dm, reg, reg_mask, reg_value);
825 break;
826 case CHANNEL_WIDTH_40:
827 odm_set_bb_reg(dm, reg, reg_mask, reg_value);
828 break;
829 default:
830 odm_set_bb_reg(dm, reg, reg_mask, 0x0);
831 }
832
833 phydm_bw_fixed_enable(dm, FUNC_ENABLE);
834 #endif
835 }
836
phydm_set_ext_switch(void * dm_void,u32 ext_ant_switch)837 void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
838 {
839 #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
840 struct dm_struct *dm = (struct dm_struct *)dm_void;
841
842 if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))
843 return;
844
845 /*Output Pin Settings*/
846
847 /*select DPDT_P and DPDT_N as output pin*/
848 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
849
850 /*@by WLAN control*/
851 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
852
853 /*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/
854 odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);
855
856 if (ext_ant_switch == 1) { /*@2b'01*/
857 odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);
858 PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n");
859 } else if (ext_ant_switch == 2) { /*@2b'10*/
860 odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);
861 PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n");
862 }
863 #endif
864 }
865
phydm_csi_mask_enable(void * dm_void,u32 enable)866 void phydm_csi_mask_enable(void *dm_void, u32 enable)
867 {
868 struct dm_struct *dm = (struct dm_struct *)dm_void;
869 boolean en = false;
870
871 en = (enable == FUNC_ENABLE) ? true : false;
872
873 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
874 odm_set_bb_reg(dm, R_0xd2c, BIT(28), en);
875 PHYDM_DBG(dm, ODM_COMP_API,
876 "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", en);
877 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
878 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
879 odm_set_bb_reg(dm, R_0xc0c, BIT(3), en);
880 PHYDM_DBG(dm, ODM_COMP_API,
881 "Enable CSI Mask: Reg 0xc0c[3] = ((0x%x))\n", en);
882 #endif
883 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
884 odm_set_bb_reg(dm, R_0x874, BIT(0), en);
885 PHYDM_DBG(dm, ODM_COMP_API,
886 "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", en);
887 }
888 }
889
phydm_clean_all_csi_mask(void * dm_void)890 void phydm_clean_all_csi_mask(void *dm_void)
891 {
892 struct dm_struct *dm = (struct dm_struct *)dm_void;
893
894 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
895 odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);
896 odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);
897 odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);
898 odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);
899 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
900 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
901 u8 i = 0, idx_lmt = 0;
902
903 if (dm->support_ic_type &
904 (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
905 idx_lmt = 127;
906 else /*@for IC supporting 80 + 80*/
907 idx_lmt = 255;
908
909 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
910 odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
911 for (i = 0; i < idx_lmt; i++) {
912 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);
913 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);
914 }
915 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
916 #endif
917 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
918 odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
919 odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
920 odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
921 odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
922 odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
923 odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
924 odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
925 odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
926 }
927 }
928
phydm_set_csi_mask(void * dm_void,u32 tone_idx_tmp,u8 tone_direction)929 void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)
930 {
931 struct dm_struct *dm = (struct dm_struct *)dm_void;
932 u8 byte_offset = 0, bit_offset = 0;
933 u32 target_reg = 0;
934 u8 reg_tmp_value = 0;
935 u32 tone_num = 64;
936 u32 tone_num_shift = 0;
937 u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
938
939 /* @calculate real tone idx*/
940 if ((tone_idx_tmp % 10) >= 5)
941 tone_idx_tmp += 10;
942
943 tone_idx_tmp = (tone_idx_tmp / 10);
944
945 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
946 tone_num = 64;
947 csi_mask_reg_p = 0xD40;
948 csi_mask_reg_n = 0xD48;
949
950 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
951 tone_num = 128;
952 csi_mask_reg_p = 0x880;
953 csi_mask_reg_n = 0x890;
954 }
955
956 if (tone_direction == FREQ_POSITIVE) {
957 if (tone_idx_tmp >= (tone_num - 1))
958 tone_idx_tmp = (tone_num - 1);
959
960 byte_offset = (u8)(tone_idx_tmp >> 3);
961 bit_offset = (u8)(tone_idx_tmp & 0x7);
962 target_reg = csi_mask_reg_p + byte_offset;
963
964 } else {
965 tone_num_shift = tone_num;
966
967 if (tone_idx_tmp >= tone_num)
968 tone_idx_tmp = tone_num;
969
970 tone_idx_tmp = tone_num - tone_idx_tmp;
971
972 byte_offset = (u8)(tone_idx_tmp >> 3);
973 bit_offset = (u8)(tone_idx_tmp & 0x7);
974 target_reg = csi_mask_reg_n + byte_offset;
975 }
976
977 reg_tmp_value = odm_read_1byte(dm, target_reg);
978 PHYDM_DBG(dm, ODM_COMP_API,
979 "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
980 (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
981 reg_tmp_value |= BIT(bit_offset);
982 odm_write_1byte(dm, target_reg, reg_tmp_value);
983 PHYDM_DBG(dm, ODM_COMP_API,
984 "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
985 (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
986 }
987
phydm_set_nbi_reg(void * dm_void,u32 tone_idx_tmp,u32 bw)988 void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
989 {
990 struct dm_struct *dm = (struct dm_struct *)dm_void;
991 /*tone_idx X 10*/
992 u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,
993 155, 185, 205, 225, 245,
994 265, 285, 305, 335, 355,
995 375, 395, 415, 435, 455,
996 485, 505, 525, 555, 585, 615, 635};
997 /*tone_idx X 10*/
998 u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,
999 155, 175, 195, 225, 245,
1000 265, 285, 305, 325, 345,
1001 365, 385, 405, 425, 445,
1002 465, 485, 505, 525, 545,
1003 565, 585, 605, 625, 645,
1004 665, 695, 715, 735, 755,
1005 775, 795, 815, 835, 855,
1006 875, 895, 915, 935, 955,
1007 975, 995, 1015, 1035, 1055,
1008 1085, 1105, 1125, 1145, 1175,
1009 1195, 1225, 1255, 1275};
1010 u32 reg_idx = 0;
1011 u32 i;
1012 u8 nbi_table_idx = FFT_128_TYPE;
1013
1014 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1015 nbi_table_idx = FFT_128_TYPE;
1016 } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
1017 nbi_table_idx = FFT_256_TYPE;
1018 } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
1019 if (bw == 80)
1020 nbi_table_idx = FFT_256_TYPE;
1021 else /*@20M, 40M*/
1022 nbi_table_idx = FFT_128_TYPE;
1023 }
1024
1025 if (nbi_table_idx == FFT_128_TYPE) {
1026 for (i = 0; i < NBI_128TONE; i++) {
1027 if (tone_idx_tmp < nbi_128[i]) {
1028 reg_idx = i + 1;
1029 break;
1030 }
1031 }
1032
1033 } else if (nbi_table_idx == FFT_256_TYPE) {
1034 for (i = 0; i < NBI_256TONE; i++) {
1035 if (tone_idx_tmp < nbi_256[i]) {
1036 reg_idx = i + 1;
1037 break;
1038 }
1039 }
1040 }
1041
1042 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1043 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);
1044 PHYDM_DBG(dm, ODM_COMP_API,
1045 "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n",
1046 reg_idx);
1047 } else {
1048 odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);
1049 PHYDM_DBG(dm, ODM_COMP_API,
1050 "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
1051 reg_idx);
1052 }
1053 }
1054
phydm_nbi_enable(void * dm_void,u32 enable)1055 void phydm_nbi_enable(void *dm_void, u32 enable)
1056 {
1057 struct dm_struct *dm = (struct dm_struct *)dm_void;
1058 u32 val = 0;
1059
1060 val = (enable == FUNC_ENABLE) ? 1 : 0;
1061
1062 PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
1063
1064 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1065 if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
1066 val = (enable == FUNC_ENABLE) ? 0xf : 0;
1067 odm_set_bb_reg(dm, R_0xc50, 0xf000000, val);
1068 } else {
1069 odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
1070 }
1071 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1072 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
1073 ODM_RTL8195B)) {
1074 odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
1075 odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
1076 if (dm->rf_type > RF_1T1R)
1077 odm_set_bb_reg(dm, R_0xe20, BIT(28), val);
1078 } else {
1079 odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
1080 }
1081 }
1082 }
1083
phydm_find_fc(void * dm_void,u32 channel,u32 bw,u32 second_ch,u32 * fc_in)1084 u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)
1085 {
1086 struct dm_struct *dm = (struct dm_struct *)dm_void;
1087 u32 fc = *fc_in;
1088 u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,
1089 108, 116, 124, 132, 140,
1090 149, 157, 165, 173};
1091 u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,
1092 149, 165};
1093 u32 *start_ch = &start_ch_per_40m[0];
1094 u32 num_start_channel = NUM_START_CH_40M;
1095 u32 channel_offset = 0;
1096 u32 i;
1097
1098 /*@2.4G*/
1099 if (channel <= 14 && channel > 0) {
1100 if (bw == 80)
1101 return PHYDM_SET_FAIL;
1102
1103 fc = 2412 + (channel - 1) * 5;
1104
1105 if (bw == 40 && second_ch == PHYDM_ABOVE) {
1106 if (channel >= 10) {
1107 PHYDM_DBG(dm, ODM_COMP_API,
1108 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1109 channel, second_ch);
1110 return PHYDM_SET_FAIL;
1111 }
1112 fc += 10;
1113 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
1114 if (channel <= 2) {
1115 PHYDM_DBG(dm, ODM_COMP_API,
1116 "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1117 channel, second_ch);
1118 return PHYDM_SET_FAIL;
1119 }
1120 fc -= 10;
1121 }
1122 }
1123 /*@5G*/
1124 else if (channel >= 36 && channel <= 177) {
1125 if (bw != 20) {
1126 if (bw == 40) {
1127 num_start_channel = NUM_START_CH_40M;
1128 start_ch = &start_ch_per_40m[0];
1129 channel_offset = CH_OFFSET_40M;
1130 } else if (bw == 80) {
1131 num_start_channel = NUM_START_CH_80M;
1132 start_ch = &start_ch_per_80m[0];
1133 channel_offset = CH_OFFSET_80M;
1134 }
1135
1136 for (i = 0; i < (num_start_channel - 1); i++) {
1137 if (channel < start_ch[i + 1]) {
1138 channel = start_ch[i] + channel_offset;
1139 break;
1140 }
1141 }
1142 PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n",
1143 channel);
1144 }
1145
1146 fc = 5180 + (channel - 36) * 5;
1147
1148 } else {
1149 PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
1150 channel);
1151 return PHYDM_SET_FAIL;
1152 }
1153
1154 *fc_in = fc;
1155
1156 return PHYDM_SET_SUCCESS;
1157 }
1158
phydm_find_intf_distance(void * dm_void,u32 bw,u32 fc,u32 f_interference,u32 * tone_idx_tmp_in)1159 u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,
1160 u32 *tone_idx_tmp_in)
1161 {
1162 struct dm_struct *dm = (struct dm_struct *)dm_void;
1163 u32 bw_up = 0, bw_low = 0;
1164 u32 int_distance = 0;
1165 u32 tone_idx_tmp = 0;
1166 u8 set_result = PHYDM_SET_NO_NEED;
1167
1168 bw_up = fc + bw / 2;
1169 bw_low = fc - bw / 2;
1170
1171 PHYDM_DBG(dm, ODM_COMP_API,
1172 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1173 fc, bw_up, f_interference);
1174
1175 if (f_interference >= bw_low && f_interference <= bw_up) {
1176 int_distance = DIFF_2(fc, f_interference);
1177 /*@10*(int_distance /0.3125)*/
1178 tone_idx_tmp = (int_distance << 5);
1179 PHYDM_DBG(dm, ODM_COMP_API,
1180 "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
1181 int_distance, tone_idx_tmp / 10,
1182 tone_idx_tmp % 10);
1183 *tone_idx_tmp_in = tone_idx_tmp;
1184 set_result = PHYDM_SET_SUCCESS;
1185 }
1186
1187 return set_result;
1188 }
1189
phydm_csi_mask_setting(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch)1190 u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
1191 u32 f_intf, u32 sec_ch)
1192 {
1193 struct dm_struct *dm = (struct dm_struct *)dm_void;
1194 u32 fc = 2412;
1195 u8 direction = FREQ_POSITIVE;
1196 u32 tone_idx = 0;
1197 u8 set_result = PHYDM_SET_SUCCESS;
1198 u8 rpt = 0;
1199
1200 if (enable == FUNC_DISABLE) {
1201 set_result = PHYDM_SET_SUCCESS;
1202 phydm_clean_all_csi_mask(dm);
1203
1204 } else {
1205 PHYDM_DBG(dm, ODM_COMP_API,
1206 "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1207 ch, bw, f_intf,
1208 (((bw == 20) || (ch > 14)) ? "Don't care" :
1209 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
1210
1211 /*@calculate fc*/
1212 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1213 set_result = PHYDM_SET_FAIL;
1214 } else {
1215 /*@calculate interference distance*/
1216 rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
1217 &tone_idx);
1218 if (rpt == PHYDM_SET_SUCCESS) {
1219 if (f_intf >= fc)
1220 direction = FREQ_POSITIVE;
1221 else
1222 direction = FREQ_NEGATIVE;
1223
1224 phydm_set_csi_mask(dm, tone_idx, direction);
1225 set_result = PHYDM_SET_SUCCESS;
1226 } else {
1227 set_result = PHYDM_SET_NO_NEED;
1228 }
1229 }
1230 }
1231
1232 if (set_result == PHYDM_SET_SUCCESS)
1233 phydm_csi_mask_enable(dm, enable);
1234 else
1235 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1236
1237 return set_result;
1238 }
1239
phydm_spur_case_mapping(void * dm_void)1240 boolean phydm_spur_case_mapping(void *dm_void)
1241 {
1242 struct dm_struct *dm = (struct dm_struct *)dm_void;
1243 u8 channel = *dm->channel, bw = *dm->band_width;
1244 boolean mapping_result = false;
1245 #if (RTL8814B_SUPPORT == 1)
1246 if (channel == 153 && bw == CHANNEL_WIDTH_20)
1247 mapping_result = true;
1248 else if (channel == 151 && bw == CHANNEL_WIDTH_40)
1249 mapping_result = true;
1250 else if (channel == 155 && bw == CHANNEL_WIDTH_80)
1251 mapping_result = true;
1252 #endif
1253 return mapping_result;
1254 }
1255
phydm_ch_to_rf_band(void * dm_void,u8 central_ch)1256 enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch)
1257 {
1258 struct dm_struct *dm = (struct dm_struct *)dm_void;
1259 enum odm_rf_band rf_band = ODM_RF_BAND_5G_LOW;
1260
1261 if (central_ch <= 14)
1262 rf_band = ODM_RF_BAND_2G;
1263 else if (central_ch >= 36 && central_ch <= 64)
1264 rf_band = ODM_RF_BAND_5G_LOW;
1265 else if ((central_ch >= 100) && (central_ch <= 144))
1266 rf_band = ODM_RF_BAND_5G_MID;
1267 else if (central_ch >= 149)
1268 rf_band = ODM_RF_BAND_5G_HIGH;
1269 else
1270 PHYDM_DBG(dm, ODM_COMP_API, "mapping channel to band fail\n");
1271
1272 return rf_band;
1273 }
1274
1275 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_rf_psd_jgr3(void * dm_void,u8 path,u32 tone_idx)1276 u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx)
1277 {
1278 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
1279 struct dm_struct *dm = (struct dm_struct *)dm_void;
1280 u32 reg_1b04 = 0, reg_1b08 = 0, reg_1b0c_11_10 = 0;
1281 u32 reg_1b14 = 0, reg_1b18 = 0, reg_1b1c = 0;
1282 u32 reg_1b28 = 0;
1283 u32 reg_1bcc_5_0 = 0;
1284 u32 reg_1b2c_27_16 = 0, reg_1b34 = 0, reg_1bd4 = 0;
1285 u32 reg_180c = 0, reg_410c = 0, reg_520c = 0, reg_530c = 0;
1286 u32 igi = 0;
1287 u32 i = 0;
1288 u32 psd_val = 0, psd_val_msb = 0, psd_val_lsb = 0, psd_max = 0;
1289 u32 psd_status_temp = 0;
1290 u16 poll_cnt = 0;
1291
1292 /*read and record the ori. value*/
1293 reg_1b04 = odm_get_bb_reg(dm, R_0x1b04, MASKDWORD);
1294 reg_1b08 = odm_get_bb_reg(dm, R_0x1b08, MASKDWORD);
1295 reg_1b0c_11_10 = odm_get_bb_reg(dm, R_0x1b0c, 0xc00);
1296 reg_1b14 = odm_get_bb_reg(dm, R_0x1b14, MASKDWORD);
1297 reg_1b18 = odm_get_bb_reg(dm, R_0x1b18, MASKDWORD);
1298 reg_1b1c = odm_get_bb_reg(dm, R_0x1b1c, MASKDWORD);
1299 reg_1b28 = odm_get_bb_reg(dm, R_0x1b28, MASKDWORD);
1300 reg_1bcc_5_0 = odm_get_bb_reg(dm, R_0x1bcc, 0x3f);
1301 reg_1b2c_27_16 = odm_get_bb_reg(dm, R_0x1b2c, 0xfff0000);
1302 reg_1b34 = odm_get_bb_reg(dm, R_0x1b34, MASKDWORD);
1303 reg_1bd4 = odm_get_bb_reg(dm, R_0x1bd4, MASKDWORD);
1304 igi = odm_get_bb_reg(dm, R_0x1d70, MASKDWORD);
1305 reg_180c = odm_get_bb_reg(dm, R_0x180c, 0x3);
1306 reg_410c = odm_get_bb_reg(dm, R_0x410c, 0x3);
1307 reg_520c = odm_get_bb_reg(dm, R_0x520c, 0x3);
1308 reg_530c = odm_get_bb_reg(dm, R_0x530c, 0x3);
1309
1310 /*rf psd reg setting*/
1311 odm_set_bb_reg(dm, R_0x1b00, 0x6, path); /*path is RF_path*/
1312 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x0);
1313 odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x80);
1314 odm_set_bb_reg(dm, R_0x1b0c, 0xc00, 0x3);
1315 odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x0);
1316 odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x1);
1317 /*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
1318 odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x82103D21);
1319 /*#else*/
1320 /*odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x821A3D21);*/
1321 /*#endif*/
1322 odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, 0x0);
1323 odm_set_bb_reg(dm, R_0x1bcc, 0x3f, 0x3f);
1324 odm_set_bb_reg(dm, R_0x8a0, 0xf, 0x0); /* AGC off */
1325 odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, 0x20202020);
1326
1327 for (i = tone_idx - 1; i <= tone_idx + 1; i++) {
1328 /*set psd tone_idx for detection*/
1329 odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, i);
1330 /*one shot for RXIQK psd*/
1331 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
1332 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
1333
1334 if (dm->support_ic_type & ODM_RTL8814B)
1335 for (poll_cnt = 0; poll_cnt < 20; poll_cnt++) {
1336 odm_set_bb_reg(dm, R_0x1bd4, 0x3f0000, 0x2b);
1337 psd_status_temp = odm_get_bb_reg(dm, R_0x1bfc,
1338 BIT(1));
1339 if (!psd_status_temp)
1340 ODM_delay_us(10);
1341 else
1342 break;
1343 }
1344 else
1345 ODM_delay_us(250);
1346
1347 /*read RxIQK power*/
1348 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
1349 if (dm->support_ic_type & ODM_RTL8814B)
1350 psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x7ff0000);
1351 else if (dm->support_ic_type & ODM_RTL8198F)
1352 psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x1f0000);
1353
1354 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
1355 psd_val_lsb = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
1356 if (dm->support_ic_type & ODM_RTL8814B)
1357 psd_val = (psd_val_msb << 21) + (psd_val_lsb >> 11);
1358 else if (dm->support_ic_type & ODM_RTL8198F)
1359 psd_val = (psd_val_msb << 27) + (psd_val_lsb >> 5);
1360
1361 if (psd_val > psd_max)
1362 psd_max = psd_val;
1363 }
1364
1365 /*refill the ori. value*/
1366 odm_set_bb_reg(dm, R_0x1b00, 0x6, path);
1367 odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, reg_1b04);
1368 odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, reg_1b08);
1369 odm_set_bb_reg(dm, R_0x1b0c, 0xc00, reg_1b0c_11_10);
1370 odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, reg_1b14);
1371 odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, reg_1b18);
1372 odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, reg_1b1c);
1373 odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, reg_1b28);
1374 odm_set_bb_reg(dm, R_0x1bcc, 0x3f, reg_1bcc_5_0);
1375 odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, reg_1b2c_27_16);
1376 odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, reg_1b34);
1377 odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, reg_1bd4);
1378 odm_set_bb_reg(dm, R_0x8a0, 0xf, 0xf); /* AGC on */
1379 odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, igi);
1380 PHYDM_DBG(dm, ODM_COMP_API, "psd_max %d\n", psd_max);
1381
1382 return psd_max;
1383 #else
1384 return 0;
1385 #endif
1386 }
1387
phydm_find_intf_distance_jgr3(void * dm_void,u32 bw,u32 fc,u32 f_interference,u32 * tone_idx_tmp_in)1388 u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
1389 u32 f_interference, u32 *tone_idx_tmp_in)
1390 {
1391 struct dm_struct *dm = (struct dm_struct *)dm_void;
1392 u32 bw_up = 0, bw_low = 0;
1393 u32 int_distance = 0;
1394 u32 tone_idx_tmp = 0;
1395 u8 set_result = PHYDM_SET_NO_NEED;
1396 u8 channel = *dm->channel;
1397
1398 bw_up = 1000 * (fc + bw / 2);
1399 bw_low = 1000 * (fc - bw / 2);
1400 fc = 1000 * fc;
1401
1402 PHYDM_DBG(dm, ODM_COMP_API,
1403 "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1404 fc, bw_up, f_interference);
1405
1406 if (f_interference >= bw_low && f_interference <= bw_up) {
1407 int_distance = DIFF_2(fc, f_interference);
1408 /*@10*(int_distance /0.3125)*/
1409 if (channel < 15 &&
1410 (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F)))
1411 tone_idx_tmp = int_distance / 312;
1412 else
1413 tone_idx_tmp = ((int_distance + 156) / 312);
1414 PHYDM_DBG(dm, ODM_COMP_API,
1415 "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n",
1416 int_distance, tone_idx_tmp);
1417 *tone_idx_tmp_in = tone_idx_tmp;
1418 set_result = PHYDM_SET_SUCCESS;
1419 }
1420
1421 return set_result;
1422 }
1423
phydm_csi_mask_setting_jgr3(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch,u8 wgt)1424 u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
1425 u32 f_intf, u32 sec_ch, u8 wgt)
1426 {
1427 struct dm_struct *dm = (struct dm_struct *)dm_void;
1428 u32 fc = 2412;
1429 u8 direction = FREQ_POSITIVE;
1430 u32 tone_idx = 0;
1431 u8 set_result = PHYDM_SET_SUCCESS;
1432 u8 rpt = 0;
1433
1434 if (enable == FUNC_DISABLE) {
1435 phydm_csi_mask_enable(dm, FUNC_ENABLE);
1436 phydm_clean_all_csi_mask(dm);
1437 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1438 set_result = PHYDM_SET_SUCCESS;
1439 } else {
1440 PHYDM_DBG(dm, ODM_COMP_API,
1441 "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n",
1442 ch, bw, f_intf,
1443 (((bw == 20) || (ch > 14)) ? "Don't care" :
1444 (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt);
1445
1446 /*@calculate fc*/
1447 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1448 set_result = PHYDM_SET_FAIL;
1449 } else {
1450 /*@calculate interference distance*/
1451 rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
1452 &tone_idx);
1453 if (rpt == PHYDM_SET_SUCCESS) {
1454 if (f_intf >= 1000 * fc)
1455 direction = FREQ_POSITIVE;
1456 else
1457 direction = FREQ_NEGATIVE;
1458
1459 phydm_csi_mask_enable(dm, FUNC_ENABLE);
1460 phydm_set_csi_mask_jgr3(dm, tone_idx, direction,
1461 wgt);
1462 set_result = PHYDM_SET_SUCCESS;
1463 } else {
1464 set_result = PHYDM_SET_NO_NEED;
1465 }
1466 }
1467 if (!(set_result == PHYDM_SET_SUCCESS))
1468 phydm_csi_mask_enable(dm, FUNC_DISABLE);
1469 }
1470
1471 return set_result;
1472 }
1473
phydm_set_csi_mask_jgr3(void * dm_void,u32 tone_idx_tmp,u8 tone_direction,u8 wgt)1474 void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
1475 u8 wgt)
1476 {
1477 struct dm_struct *dm = (struct dm_struct *)dm_void;
1478 u32 multi_tone_idx_tmp = 0;
1479 u32 reg_tmp = 0;
1480 u32 tone_num = 64;
1481 u32 table_addr = 0;
1482 u32 addr = 0;
1483 u8 rf_bw = 0;
1484 u8 value = 0;
1485 u8 channel = *dm->channel;
1486
1487 rf_bw = odm_read_1byte(dm, R_0x9b0);
1488 if (((rf_bw & 0xc) >> 2) == 0x2)
1489 tone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */
1490 else
1491 tone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */
1492
1493 if (tone_direction == FREQ_POSITIVE) {
1494 if (tone_idx_tmp >= (tone_num - 1))
1495 tone_idx_tmp = (tone_num - 1);
1496 } else {
1497 if (tone_idx_tmp >= tone_num)
1498 tone_idx_tmp = tone_num;
1499
1500 tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
1501 }
1502 table_addr = tone_idx_tmp >> 1;
1503
1504 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1505 PHYDM_DBG(dm, ODM_COMP_API,
1506 "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1507 tone_idx_tmp, reg_tmp);
1508 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
1509 odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
1510
1511 if (channel < 15 &&
1512 (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F))) {
1513 if (tone_idx_tmp % 2 == 1) {
1514 if (tone_direction == FREQ_POSITIVE) {
1515 /*===Tone 1===*/
1516 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1517 (table_addr & 0xff));
1518 value = (BIT(3) | (wgt & 0x7)) << 4;
1519 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1520 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1521 PHYDM_DBG(dm, ODM_COMP_API,
1522 "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1523 tone_idx_tmp, reg_tmp);
1524 /*===Tone 2===*/
1525 value = 0;
1526 multi_tone_idx_tmp = tone_idx_tmp + 1;
1527 table_addr = multi_tone_idx_tmp >> 1;
1528 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1529 (table_addr & 0xff));
1530 value = (BIT(3) | (wgt & 0x7));
1531 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1532 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1533 PHYDM_DBG(dm, ODM_COMP_API,
1534 "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1535 tone_idx_tmp, reg_tmp);
1536 } else {
1537 /*===Tone 1 & 2===*/
1538 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1539 (table_addr & 0xff));
1540 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1541 (BIT(3) | (wgt & 0x7));
1542 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1543 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1544 PHYDM_DBG(dm, ODM_COMP_API,
1545 "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1546 tone_idx_tmp, reg_tmp);
1547 }
1548 } else {
1549 if (tone_direction == FREQ_POSITIVE) {
1550 /*===Tone 1 & 2===*/
1551 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1552 (table_addr & 0xff));
1553 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1554 (BIT(3) | (wgt & 0x7));
1555 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1556 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1557 PHYDM_DBG(dm, ODM_COMP_API,
1558 "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1559 tone_idx_tmp, reg_tmp);
1560 } else {
1561 /*===Tone 1===*/
1562 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1563 (table_addr & 0xff));
1564 value = (BIT(3) | (wgt & 0x7));
1565 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1566 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1567 PHYDM_DBG(dm, ODM_COMP_API,
1568 "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1569 tone_idx_tmp, reg_tmp);
1570
1571 /*===Tone 2===*/
1572 value = 0;
1573 multi_tone_idx_tmp = tone_idx_tmp - 1;
1574 table_addr = multi_tone_idx_tmp >> 1;
1575 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1576 (table_addr & 0xff));
1577 value = (BIT(3) | (wgt & 0x7)) << 4;
1578 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1579 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1580 PHYDM_DBG(dm, ODM_COMP_API,
1581 "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
1582 tone_idx_tmp, reg_tmp);
1583 }
1584 }
1585 } else {
1586 if ((dm->support_ic_type & (ODM_RTL8814B)) &&
1587 phydm_spur_case_mapping(dm)) {
1588 if (!(tone_idx_tmp % 2)) {
1589 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1590 (table_addr & 0xff));
1591 value = ((BIT(3) | (((wgt + 4) <= 7 ? (wgt +
1592 4) : 7) & 0x7)) << 4) | (BIT(3) |
1593 (wgt & 0x7));
1594 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1595 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1596 PHYDM_DBG(dm, ODM_COMP_API,
1597 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1598 tone_idx_tmp, reg_tmp);
1599 if (tone_idx_tmp == 0)
1600 table_addr = tone_num - 1;
1601 else
1602 table_addr = table_addr - 1;
1603 if (tone_idx_tmp != tone_num) {
1604 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1605 (table_addr & 0xff));
1606 value = (BIT(3) | (((wgt + 4) <= 7 ?
1607 (wgt + 4) : 7) & 0x7)) << 4;
1608 odm_set_bb_reg(dm, R_0x1d94, 0xff,
1609 value);
1610 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1611 PHYDM_DBG(dm, ODM_COMP_API,
1612 "New Mask Reg0x1d94 = ((0x%x))\n",
1613 reg_tmp);
1614 }
1615 } else {
1616 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1617 (table_addr & 0xff));
1618 value = ((BIT(3) | (wgt & 0x7)) << 4) |
1619 (BIT(3) | (((wgt + 4) <= 7 ? (wgt +
1620 4) : 7) & 0x7));
1621 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1622 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1623 PHYDM_DBG(dm, ODM_COMP_API,
1624 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1625 tone_idx_tmp, reg_tmp);
1626 if (tone_idx_tmp == (tone_num << 1) - 1)
1627 table_addr = 0;
1628 else
1629 table_addr = table_addr + 1;
1630 if (tone_idx_tmp != tone_num - 1) {
1631 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
1632 (table_addr & 0xff));
1633 value = (BIT(3) | (((wgt + 4) <= 7 ?
1634 (wgt + 4) : 7) & 0x7));
1635 odm_set_bb_reg(dm, R_0x1d94, 0xff,
1636 value);
1637 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1638 PHYDM_DBG(dm, ODM_COMP_API,
1639 "New Mask Reg0x1d94 = ((0x%x))\n",
1640 reg_tmp);
1641 }
1642 }
1643 } else {
1644 odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr &
1645 0xff));
1646 if (tone_idx_tmp % 2)
1647 value = (BIT(3) | (wgt & 0x7)) << 4;
1648 else
1649 value = BIT(3) | (wgt & 0x7);
1650
1651 odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
1652 reg_tmp = odm_read_4byte(dm, R_0x1d94);
1653 PHYDM_DBG(dm, ODM_COMP_API,
1654 "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
1655 tone_idx_tmp, reg_tmp);
1656 }
1657 }
1658 odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
1659 }
1660
phydm_nbi_reset_jgr3(void * dm_void)1661 void phydm_nbi_reset_jgr3(void *dm_void)
1662 {
1663 struct dm_struct *dm = (struct dm_struct *)dm_void;
1664
1665 odm_set_bb_reg(dm, R_0x818, BIT(3), 1);
1666 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0);
1667 odm_set_bb_reg(dm, R_0x818, BIT(3), 0);
1668 odm_set_bb_reg(dm, R_0x818, BIT(11), 0);
1669 #if RTL8814B_SUPPORT
1670 if (dm->support_ic_type & ODM_RTL8814B) {
1671 odm_set_bb_reg(dm, R_0x1944, 0x300, 0x3);
1672 odm_set_bb_reg(dm, R_0x4044, 0x300, 0x3);
1673 odm_set_bb_reg(dm, R_0x5044, 0x300, 0x3);
1674 odm_set_bb_reg(dm, R_0x5144, 0x300, 0x3);
1675 odm_set_bb_reg(dm, R_0x810, 0xf, 0x0);
1676 odm_set_bb_reg(dm, R_0x810, 0xf0000, 0x0);
1677 odm_set_bb_reg(dm, R_0xc24, MASKDWORD, 0x406000ff);
1678 }
1679 #endif
1680 }
1681
phydm_nbi_setting_jgr3(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch,u8 path)1682 u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
1683 u32 sec_ch, u8 path)
1684 {
1685 struct dm_struct *dm = (struct dm_struct *)dm_void;
1686 u32 fc = 2412;
1687 u8 direction = FREQ_POSITIVE;
1688 u32 tone_idx = 0;
1689 u8 set_result = PHYDM_SET_SUCCESS;
1690 u8 rpt = 0;
1691
1692 if (enable == FUNC_DISABLE) {
1693 phydm_nbi_reset_jgr3(dm);
1694 set_result = PHYDM_SET_SUCCESS;
1695 } else {
1696 PHYDM_DBG(dm, ODM_COMP_API,
1697 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1698 ch, bw, f_intf,
1699 (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1700 (ch > 14)) ? "Don't care" :
1701 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
1702
1703 /*@calculate fc*/
1704 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
1705 set_result = PHYDM_SET_FAIL;
1706 } else {
1707 /*@calculate interference distance*/
1708 rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
1709 &tone_idx);
1710 if (rpt == PHYDM_SET_SUCCESS) {
1711 if (f_intf >= 1000 * fc)
1712 direction = FREQ_POSITIVE;
1713 else
1714 direction = FREQ_NEGATIVE;
1715
1716 phydm_set_nbi_reg_jgr3(dm, tone_idx, direction,
1717 path);
1718 set_result = PHYDM_SET_SUCCESS;
1719 } else {
1720 set_result = PHYDM_SET_NO_NEED;
1721 }
1722 }
1723 }
1724
1725 if (set_result == PHYDM_SET_SUCCESS)
1726 phydm_nbi_enable_jgr3(dm, enable, path);
1727 else
1728 phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);
1729
1730 if (dm->support_ic_type & ODM_RTL8814B)
1731 odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0);
1732
1733 return set_result;
1734 }
1735
phydm_set_nbi_reg_jgr3(void * dm_void,u32 tone_idx_tmp,u8 tone_direction,u8 path)1736 void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
1737 u8 path)
1738 {
1739 struct dm_struct *dm = (struct dm_struct *)dm_void;
1740 u32 reg_tmp_value = 0;
1741 u32 tone_num = 64;
1742 u32 addr = 0;
1743 u8 rf_bw = 0;
1744
1745 rf_bw = odm_read_1byte(dm, R_0x9b0);
1746 if (((rf_bw & 0xc) >> 2) == 0x2)
1747 tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
1748 else
1749 tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
1750
1751 if (tone_direction == FREQ_POSITIVE) {
1752 if (tone_idx_tmp >= (tone_num - 1))
1753 tone_idx_tmp = (tone_num - 1);
1754 } else {
1755 if (tone_idx_tmp >= tone_num)
1756 tone_idx_tmp = tone_num;
1757
1758 tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
1759 }
1760 /*Mark the tone idx for Packet detection*/
1761 #if RTL8814B_SUPPORT
1762 if (dm->support_ic_type & ODM_RTL8814B) {
1763 odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff);
1764 if ((*dm->channel == 5) &&
1765 (*dm->band_width == CHANNEL_WIDTH_40))
1766 odm_set_bb_reg(dm, R_0xc24, 0xff00, 0x1a);
1767 else
1768 odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
1769 }
1770 #endif
1771 switch (path) {
1772 case RF_PATH_A:
1773 odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);
1774 PHYDM_DBG(dm, ODM_COMP_API,
1775 "Set tone idx[%d]:PATH-A = ((0x%x))\n",
1776 tone_idx_tmp, tone_idx_tmp);
1777 break;
1778 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1779 case RF_PATH_B:
1780 odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);
1781 PHYDM_DBG(dm, ODM_COMP_API,
1782 "Set tone idx[%d]:PATH-B = ((0x%x))\n",
1783 tone_idx_tmp, tone_idx_tmp);
1784 break;
1785 #endif
1786 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1787 case RF_PATH_C:
1788 odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);
1789 PHYDM_DBG(dm, ODM_COMP_API,
1790 "Set tone idx[%d]:PATH-C = ((0x%x))\n",
1791 tone_idx_tmp, tone_idx_tmp);
1792 break;
1793 #endif
1794 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1795 case RF_PATH_D:
1796 odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);
1797 PHYDM_DBG(dm, ODM_COMP_API,
1798 "Set tone idx[%d]:PATH-D = ((0x%x))\n",
1799 tone_idx_tmp, tone_idx_tmp);
1800 break;
1801 #endif
1802 default:
1803 break;
1804 }
1805 }
1806
phydm_nbi_enable_jgr3(void * dm_void,u32 enable,u8 path)1807 void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
1808 {
1809 struct dm_struct *dm = (struct dm_struct *)dm_void;
1810 boolean val = false;
1811
1812 val = (enable == FUNC_ENABLE) ? true : false;
1813
1814 PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
1815
1816 if (dm->support_ic_type & ODM_RTL8814B) {
1817 odm_set_bb_reg(dm, R_0x1d3c, BIT(19), val);
1818 odm_set_bb_reg(dm, R_0x818, BIT(3), val);
1819 } else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
1820 odm_set_bb_reg(dm, R_0x818, BIT(3), !val);
1821 }
1822 odm_set_bb_reg(dm, R_0x818, BIT(11), val);
1823 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf);
1824
1825 if (enable == FUNC_ENABLE) {
1826 switch (path) {
1827 case RF_PATH_A:
1828 odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
1829 break;
1830 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1831 case RF_PATH_B:
1832 odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
1833 break;
1834 #endif
1835 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1836 case RF_PATH_C:
1837 odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
1838 break;
1839 #endif
1840 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1841 case RF_PATH_D:
1842 odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
1843 break;
1844 #endif
1845 default:
1846 break;
1847 }
1848 } else {
1849 odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
1850 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
1851 odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
1852 #endif
1853 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1854 odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
1855 #endif
1856 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
1857 odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
1858 #endif
1859 #if RTL8812F_SUPPORT
1860 if (dm->support_ic_type & ODM_RTL8812F) {
1861 odm_set_bb_reg(dm, R_0x818, BIT(3), val);
1862 odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0);
1863 }
1864 #endif
1865 }
1866 }
1867
phydm_phystat_rpt_jgr3(void * dm_void,enum phystat_rpt info,enum rf_path ant_path)1868 u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
1869 enum rf_path ant_path)
1870 {
1871 struct dm_struct *dm = (struct dm_struct *)dm_void;
1872 s8 evm_org, cfo_org, rxsnr_org;
1873 u8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0;
1874
1875 /* Update the status for each pkt */
1876 odm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448);
1877 odm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001);
1878 /* PHY status Page1 */
1879 odm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1);
1880 /*choose debug port for phystatus */
1881 odm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380);
1882
1883 if (info == PHY_PWDB) {
1884 /* Choose the report of the diff path */
1885 if (ant_path == RF_PATH_A)
1886 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1);
1887 else if (ant_path == RF_PATH_B)
1888 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2);
1889 else if (ant_path == RF_PATH_C)
1890 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3);
1891 else if (ant_path == RF_PATH_D)
1892 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4);
1893 } else if (info == PHY_EVM) {
1894 /* Choose the report of the diff path */
1895 if (ant_path == RF_PATH_A)
1896 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
1897 else if (ant_path == RF_PATH_B)
1898 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11);
1899 else if (ant_path == RF_PATH_C)
1900 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
1901 else if (ant_path == RF_PATH_D)
1902 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
1903 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1904 } else if (info == PHY_CFO) {
1905 /* Choose the report of the diff path */
1906 if (ant_path == RF_PATH_A)
1907 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
1908 else if (ant_path == RF_PATH_B)
1909 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
1910 else if (ant_path == RF_PATH_C)
1911 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16);
1912 else if (ant_path == RF_PATH_D)
1913 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17);
1914 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1915 } else if (info == PHY_RXSNR) {
1916 /* Choose the report of the diff path */
1917 if (ant_path == RF_PATH_A)
1918 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18);
1919 else if (ant_path == RF_PATH_B)
1920 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19);
1921 else if (ant_path == RF_PATH_C)
1922 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a);
1923 else if (ant_path == RF_PATH_D)
1924 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b);
1925 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1926 } else if (info == PHY_LGAIN) {
1927 /* choose page */
1928 odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
1929 /* Choose the report of the diff path */
1930 if (ant_path == RF_PATH_A) {
1931 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
1932 tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
1933 return_info = tmp_info;
1934 } else if (ant_path == RF_PATH_B) {
1935 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
1936 tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0);
1937 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
1938 tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf);
1939 tmp_info |= (tmp_msb << 2) | tmp_lsb;
1940 return_info = tmp_info;
1941 } else if (ant_path == RF_PATH_C) {
1942 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
1943 tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0);
1944 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf);
1945 tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3);
1946 tmp_info |= (tmp_msb << 4) | tmp_lsb;
1947 return_info = tmp_info;
1948 } else if (ant_path == RF_PATH_D) {
1949 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
1950 tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
1951 return_info = tmp_info;
1952 }
1953 } else if (info == PHY_HT_AAGC_GAIN) {
1954 /* choose page */
1955 odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
1956 /* Choose the report of the diff path */
1957 if (ant_path == RF_PATH_A)
1958 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
1959 else if (ant_path == RF_PATH_B)
1960 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
1961 else if (ant_path == RF_PATH_C)
1962 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
1963 else if (ant_path == RF_PATH_D)
1964 odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
1965 return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
1966 }
1967 return return_info;
1968 }
1969
phydm_ex_hal8814b_wifi_only_hw_config(void * dm_void)1970 void phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void)
1971 {
1972 /*BB control*/
1973 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/
1974 /*SW control*/
1975 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/
1976 /*antenna mux switch */
1977 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/
1978
1979 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/
1980
1981 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/
1982 /*switch to WL side controller and gnt_wl gnt_bt debug signal */
1983 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/
1984 /*gnt_wl=1 , gnt_bt=0*/
1985 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff,
1986 * 0x7700);
1987 */
1988 /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff,
1989 * 0xc00f0038);
1990 */
1991 }
1992
phydm_user_position_for_sniffer(void * dm_void,u8 user_position)1993 void phydm_user_position_for_sniffer(void *dm_void, u8 user_position)
1994 {
1995 struct dm_struct *dm = (struct dm_struct *)dm_void;
1996
1997 /* user position valid */
1998 odm_set_bb_reg(dm, R_0xa68, BIT(17), 1);
1999 /* Select user seat from pmac */
2000 odm_set_bb_reg(dm, R_0xa68, BIT(16), 1);
2001 /*user seat*/
2002 odm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position);
2003 }
2004
2005 boolean
phydm_bb_ctrl_txagc_ofst_jgr3(void * dm_void,s8 pw_offset,u8 add_half_db)2006 phydm_bb_ctrl_txagc_ofst_jgr3(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2007 u8 add_half_db /*@(+0.5 dB)*/)
2008 {
2009 struct dm_struct *dm = (struct dm_struct *)dm_void;
2010 s8 pw_idx = pw_offset * 4; /*@ 7Bit, 0.25dB unit*/
2011
2012 if (pw_offset < -16 || pw_offset > 15) {
2013 pr_debug("[Warning][%s]Ofst error=%d", __func__, pw_offset);
2014 return false;
2015 }
2016
2017 if (add_half_db)
2018 pw_idx += 2;
2019
2020 PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
2021
2022 odm_set_bb_reg(dm, R_0x18a0, 0x3f, pw_idx);
2023
2024 if (dm->num_rf_path >= 2)
2025 odm_set_bb_reg(dm, R_0x41a0, 0x3f, pw_idx);
2026
2027 if (dm->num_rf_path >= 3)
2028 odm_set_bb_reg(dm, R_0x52a0, 0x3f, pw_idx);
2029
2030 if (dm->num_rf_path >= 4)
2031 odm_set_bb_reg(dm, R_0x53a0, 0x3f, pw_idx);
2032
2033 return true;
2034 }
2035
2036 #endif
phydm_nbi_setting(void * dm_void,u32 enable,u32 ch,u32 bw,u32 f_intf,u32 sec_ch)2037 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
2038 u32 sec_ch)
2039 {
2040 struct dm_struct *dm = (struct dm_struct *)dm_void;
2041 u32 fc = 2412;
2042 u8 direction = FREQ_POSITIVE;
2043 u32 tone_idx = 0;
2044 u8 set_result = PHYDM_SET_SUCCESS;
2045 u8 rpt = 0;
2046
2047 if (enable == FUNC_DISABLE) {
2048 set_result = PHYDM_SET_SUCCESS;
2049 } else {
2050 PHYDM_DBG(dm, ODM_COMP_API,
2051 "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2052 ch, bw, f_intf,
2053 (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
2054 (ch > 14)) ? "Don't care" :
2055 (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
2056
2057 /*@calculate fc*/
2058 if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
2059 set_result = PHYDM_SET_FAIL;
2060 } else {
2061 /*@calculate interference distance*/
2062 rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
2063 &tone_idx);
2064 if (rpt == PHYDM_SET_SUCCESS) {
2065 if (f_intf >= fc)
2066 direction = FREQ_POSITIVE;
2067 else
2068 direction = FREQ_NEGATIVE;
2069
2070 phydm_set_nbi_reg(dm, tone_idx, bw);
2071
2072 set_result = PHYDM_SET_SUCCESS;
2073 } else {
2074 set_result = PHYDM_SET_NO_NEED;
2075 }
2076 }
2077 }
2078
2079 if (set_result == PHYDM_SET_SUCCESS)
2080 phydm_nbi_enable(dm, enable);
2081 else
2082 phydm_nbi_enable(dm, FUNC_DISABLE);
2083
2084 return set_result;
2085 }
2086
phydm_nbi_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2087 void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2088 u32 *_out_len)
2089 {
2090 struct dm_struct *dm = (struct dm_struct *)dm_void;
2091 u32 used = *_used;
2092 u32 out_len = *_out_len;
2093 u32 val[10] = {0};
2094 char help[] = "-h";
2095 u8 i = 0, input_idx = 0, idx_lmt = 0;
2096 u32 enable = 0; /*@function enable*/
2097 u32 ch = 0;
2098 u32 bw = 0;
2099 u32 f_int = 0; /*@interference frequency*/
2100 u32 sec_ch = 0; /*secondary channel*/
2101 u8 rpt = 0;
2102 u8 path = 0;
2103
2104 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2105 idx_lmt = 6;
2106 else
2107 idx_lmt = 5;
2108 for (i = 0; i < idx_lmt; i++) {
2109 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
2110 input_idx++;
2111 }
2112
2113 if (input_idx == 0)
2114 return;
2115
2116 enable = val[0];
2117 ch = val[1];
2118 bw = val[2];
2119 f_int = val[3];
2120 sec_ch = val[4];
2121 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2122 path = (u8)val[5];
2123 #endif
2124
2125 if ((strcmp(input[1], help) == 0)) {
2126 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2127 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2128 PDM_SNPF(out_len, used, output + used, out_len - used,
2129 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n");
2130 else
2131 #endif
2132 PDM_SNPF(out_len, used, output + used, out_len - used,
2133 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\n");
2134 *_used = used;
2135 *_out_len = out_len;
2136 return;
2137 } else if (val[0] == FUNC_ENABLE) {
2138 PDM_SNPF(out_len, used, output + used, out_len - used,
2139 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2140 ch, bw, f_int,
2141 ((sec_ch == PHYDM_DONT_CARE) ||
2142 (bw == 20) || (ch > 14)) ? "Don't care" :
2143 ((sec_ch == PHYDM_ABOVE) ? "H" : "L"));
2144 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2145 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2146 rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
2147 sec_ch, path);
2148 else
2149 #endif
2150 rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
2151 sec_ch);
2152 } else if (val[0] == FUNC_DISABLE) {
2153 PDM_SNPF(out_len, used, output + used, out_len - used,
2154 "[Disable NBI]\n");
2155 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2156 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2157 rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
2158 sec_ch, path);
2159 else
2160 #endif
2161 rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
2162 sec_ch);
2163 } else {
2164 rpt = PHYDM_SET_FAIL;
2165 }
2166
2167 PDM_SNPF(out_len, used, output + used, out_len - used,
2168 "[NBI set result: %s]\n",
2169 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
2170 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
2171
2172 *_used = used;
2173 *_out_len = out_len;
2174 }
2175
phydm_csi_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2176 void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2177 u32 *_out_len)
2178 {
2179 struct dm_struct *dm = (struct dm_struct *)dm_void;
2180 u32 used = *_used;
2181 u32 out_len = *_out_len;
2182 u32 val[10] = {0};
2183 char help[] = "-h";
2184 u8 i = 0, input_idx = 0, idx_lmt = 0;
2185 u32 enable = 0; /*@function enable*/
2186 u32 ch = 0;
2187 u32 bw = 0;
2188 u32 f_int = 0; /*@interference frequency*/
2189 u32 sec_ch = 0; /*secondary channel*/
2190 u8 rpt = 0;
2191 u8 wgt = 0;
2192
2193 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2194 idx_lmt = 6;
2195 else
2196 idx_lmt = 5;
2197
2198 for (i = 0; i < idx_lmt; i++) {
2199 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
2200 input_idx++;
2201 }
2202
2203 if (input_idx == 0)
2204 return;
2205
2206 enable = val[0];
2207 ch = val[1];
2208 bw = val[2];
2209 f_int = val[3];
2210 sec_ch = val[4];
2211 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2212 wgt = (u8)val[5];
2213 #endif
2214
2215 if ((strcmp(input[1], help) == 0)) {
2216 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2217 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2218 PDM_SNPF(out_len, used, output + used, out_len - used,
2219 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\n");
2220 else
2221 #endif
2222 PDM_SNPF(out_len, used, output + used, out_len - used,
2223 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
2224
2225 *_used = used;
2226 *_out_len = out_len;
2227 return;
2228
2229 } else if (val[0] == FUNC_ENABLE) {
2230 PDM_SNPF(out_len, used, output + used, out_len - used,
2231 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
2232 ch, bw, f_int,
2233 (ch > 14) ? "Don't care" :
2234 (((sec_ch == PHYDM_DONT_CARE) ||
2235 (bw == 20) || (ch > 14)) ? "H" : "L"));
2236 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2237 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2238 rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
2239 f_int, sec_ch, wgt);
2240 else
2241 #endif
2242 rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
2243 sec_ch);
2244 } else if (val[0] == FUNC_DISABLE) {
2245 PDM_SNPF(out_len, used, output + used, out_len - used,
2246 "[Disable CSI MASK]\n");
2247 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2248 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2249 rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
2250 f_int, sec_ch, wgt);
2251 else
2252 #endif
2253 rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
2254 sec_ch);
2255 } else {
2256 rpt = PHYDM_SET_FAIL;
2257 }
2258 PDM_SNPF(out_len, used, output + used, out_len - used,
2259 "[CSI MASK set result: %s]\n",
2260 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
2261 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
2262
2263 *_used = used;
2264 *_out_len = out_len;
2265 }
2266
phydm_stop_ck320(void * dm_void,u8 enable)2267 void phydm_stop_ck320(void *dm_void, u8 enable)
2268 {
2269 struct dm_struct *dm = (struct dm_struct *)dm_void;
2270 u32 val = enable ? 1 : 0;
2271
2272 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2273 odm_set_bb_reg(dm, R_0x8b4, BIT(6), val);
2274 } else {
2275 if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/
2276 odm_set_bb_reg(dm, R_0x87c, BIT(29), val);
2277 else /*N-1SS*/
2278 odm_set_bb_reg(dm, R_0x87c, BIT(31), val);
2279 }
2280 }
2281
2282 boolean
phydm_bb_ctrl_txagc_ofst(void * dm_void,s8 pw_offset,u8 add_half_db)2283 phydm_bb_ctrl_txagc_ofst(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2284 u8 add_half_db /*@(+0.5 dB)*/)
2285 {
2286 struct dm_struct *dm = (struct dm_struct *)dm_void;
2287 s8 pw_idx;
2288 u8 offset_bit_num = 0;
2289
2290 if (dm->support_ic_type & N_IC_TX_OFFEST_5_BIT) {
2291 /*@ 5Bit, 0.5dB unit*/
2292 if (pw_offset < -8 || pw_offset > 7) {
2293 pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
2294 return false;
2295 }
2296 offset_bit_num = 5;
2297 } else {
2298 if (pw_offset < -16 || pw_offset > 15) {
2299 pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
2300 return false;
2301 }
2302 if (dm->support_ic_type & N_IC_TX_OFFEST_7_BIT) {
2303 /*@ 7Bit, 0.25dB unit*/
2304 offset_bit_num = 7;
2305 } else {
2306 /*@ 6Bit, 0.5dB unit*/
2307 offset_bit_num = 6;
2308 }
2309 }
2310
2311 pw_idx = (offset_bit_num == 7) ? pw_offset * 4 : pw_offset * 2;
2312
2313 if (add_half_db)
2314 pw_idx = (offset_bit_num == 7) ? pw_idx + 2 : pw_idx + 1;
2315
2316 PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
2317
2318 switch (dm->ic_ip_series) {
2319 case PHYDM_IC_AC:
2320 odm_set_bb_reg(dm, R_0x8b4, 0x3f, pw_idx); /*6Bit*/
2321 break;
2322 case PHYDM_IC_N:
2323 if (offset_bit_num == 5) {
2324 odm_set_bb_reg(dm, R_0x80c, 0x1f00, pw_idx);
2325 if (dm->num_rf_path >= 2)
2326 odm_set_bb_reg(dm, R_0x80c, 0x3e000, pw_idx);
2327 } else if (offset_bit_num == 6) {
2328 odm_set_bb_reg(dm, R_0x80c, 0x3f00, pw_idx);
2329 if (dm->num_rf_path >= 2)
2330 odm_set_bb_reg(dm, R_0x80c, 0xfc000, pw_idx);
2331 } else { /*7Bit*/
2332 odm_set_bb_reg(dm, R_0x80c, 0x7f00, pw_idx);
2333 if (dm->num_rf_path >= 2)
2334 odm_set_bb_reg(dm, R_0x80c, 0x3f8000, pw_idx);
2335 }
2336 break;
2337 }
2338 return true;
2339 }
2340
2341 boolean
phydm_set_bb_txagc_offset(void * dm_void,s8 pw_offset,u8 add_half_db)2342 phydm_set_bb_txagc_offset(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
2343 u8 add_half_db /*@(+0.5 dB)*/)
2344 {
2345 struct dm_struct *dm = (struct dm_struct *)dm_void;
2346 boolean rpt = false;
2347
2348 PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n",
2349 pw_offset, add_half_db);
2350
2351 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2352 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
2353 rpt = phydm_bb_ctrl_txagc_ofst_jgr3(dm, pw_offset, add_half_db);
2354 } else
2355 #endif
2356 {
2357 rpt = phydm_bb_ctrl_txagc_ofst(dm, pw_offset, add_half_db);
2358 }
2359
2360 PHYDM_DBG(dm, ODM_COMP_API, "TX AGC Offset set_success=%d", rpt);
2361
2362 return rpt;
2363 }
2364
2365 #ifdef PHYDM_COMMON_API_SUPPORT
phydm_reset_txagc(void * dm_void)2366 void phydm_reset_txagc(void *dm_void)
2367 {
2368 struct dm_struct *dm = (struct dm_struct *)dm_void;
2369 u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
2370 u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
2371 u32 r_txagc_diff = R_0x3a00;
2372 u8 i = 0;
2373
2374 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
2375 PHYDM_DBG(dm, ODM_COMP_API, "Only for JGR3 ICs!\n");
2376 return;
2377 }
2378
2379 for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
2380 odm_set_bb_reg(dm, r_txagc_cck[i], 0x7f0000, 0x0);
2381 odm_set_bb_reg(dm, r_txagc_ofdm[i], 0x1fc00, 0x0);
2382 }
2383
2384 for (i = 0; i <= ODM_RATEVHTSS4MCS6; i = i + 4)
2385 odm_set_bb_reg(dm, r_txagc_diff + i, MASKDWORD, 0x0);
2386 }
2387 boolean
phydm_api_shift_txagc(void * dm_void,u32 pwr_offset,enum rf_path path,boolean is_positive)2388 phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
2389 boolean is_positive) {
2390 struct dm_struct *dm = (struct dm_struct *)dm_void;
2391 boolean ret = false;
2392 u32 txagc_cck = 0;
2393 u32 txagc_ofdm = 0;
2394 u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
2395 u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
2396 u32 r_new_txagc[1] = {R_0x4308};
2397
2398 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
2399 if (dm->support_ic_type &
2400 (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
2401 if (path > RF_PATH_B) {
2402 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2403 path);
2404 return false;
2405 }
2406 txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
2407 0x7F0000);
2408 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
2409 0x1FC00);
2410 if (is_positive) {
2411 if (((txagc_cck + pwr_offset) > 127) ||
2412 ((txagc_ofdm + pwr_offset) > 127))
2413 return false;
2414
2415 txagc_cck += pwr_offset;
2416 txagc_ofdm += pwr_offset;
2417 } else {
2418 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2419 return false;
2420
2421 txagc_cck -= pwr_offset;
2422 txagc_ofdm -= pwr_offset;
2423 }
2424 #if (RTL8822C_SUPPORT)
2425 ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,
2426 path, PDM_CCK);
2427 ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,
2428 path, PDM_OFDM);
2429 #endif
2430 #if (RTL8812F_SUPPORT)
2431 ret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck,
2432 path, PDM_CCK);
2433 ret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm,
2434 path, PDM_OFDM);
2435 #endif
2436 #if (RTL8197G_SUPPORT)
2437 ret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck,
2438 path, PDM_CCK);
2439 ret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm,
2440 path, PDM_OFDM);
2441 #endif
2442 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2443 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2444 __func__, path, txagc_cck, txagc_ofdm);
2445 }
2446 #endif
2447
2448 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
2449 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
2450 if (path > RF_PATH_D) {
2451 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2452 path);
2453 return false;
2454 }
2455 txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
2456 0x7F0000);
2457 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
2458 0x1FC00);
2459 if (is_positive) {
2460 if (((txagc_cck + pwr_offset) > 127) ||
2461 ((txagc_ofdm + pwr_offset) > 127))
2462 return false;
2463
2464 txagc_cck += pwr_offset;
2465 txagc_ofdm += pwr_offset;
2466 } else {
2467 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2468 return false;
2469
2470 txagc_cck -= pwr_offset;
2471 txagc_ofdm -= pwr_offset;
2472 }
2473 #if (RTL8198F_SUPPORT)
2474 ret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck,
2475 path, PDM_CCK);
2476 ret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm,
2477 path, PDM_OFDM);
2478 #endif
2479 #if (RTL8814B_SUPPORT)
2480 ret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck,
2481 path, PDM_CCK);
2482 ret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm,
2483 path, PDM_OFDM);
2484 #endif
2485 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2486 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2487 __func__, path, txagc_cck, txagc_ofdm);
2488 }
2489 #endif
2490
2491 #if (RTL8723F_SUPPORT)
2492 if (dm->support_ic_type & (ODM_RTL8723F)) {
2493 if (path > RF_PATH_A) {
2494 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
2495 path);
2496 return false;
2497 }
2498 txagc_cck = (u8)odm_get_bb_reg(dm, r_new_txagc[path],
2499 0x0000007f);
2500 txagc_ofdm = (u8)odm_get_bb_reg(dm, r_new_txagc[path],
2501 0x00007f00);
2502 if (is_positive) {
2503 if (((txagc_cck + pwr_offset) > 127) ||
2504 ((txagc_ofdm + pwr_offset) > 127))
2505 return false;
2506
2507 txagc_cck += pwr_offset;
2508 txagc_ofdm += pwr_offset;
2509 } else {
2510 if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
2511 return false;
2512
2513 txagc_cck -= pwr_offset;
2514 txagc_ofdm -= pwr_offset;
2515 }
2516 #if (RTL8723F_SUPPORT)
2517 ret = config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_cck,
2518 path, PDM_CCK);
2519 ret &= config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_ofdm,
2520 path, PDM_OFDM);
2521 #endif
2522 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2523 "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
2524 __func__, path, txagc_cck, txagc_ofdm);
2525 }
2526 #endif
2527
2528 return ret;
2529 }
2530
2531 boolean
phydm_api_set_txagc(void * dm_void,u32 pwr_idx,enum rf_path path,u8 rate,boolean is_single_rate)2532 phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
2533 u8 rate, boolean is_single_rate)
2534 {
2535 struct dm_struct *dm = (struct dm_struct *)dm_void;
2536 boolean ret = false;
2537 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\
2538 RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
2539 u8 base = 0;
2540 u8 txagc_tmp = 0;
2541 s8 pw_by_rate_tmp = 0;
2542 s8 pw_by_rate_new = 0;
2543 #endif
2544 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2545 u8 i = 0;
2546 #endif
2547
2548 #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
2549 if (dm->support_ic_type &
2550 (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
2551 if (is_single_rate) {
2552 #if (RTL8822B_SUPPORT)
2553 if (dm->support_ic_type == ODM_RTL8822B)
2554 ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,
2555 path, rate);
2556 #endif
2557
2558 #if (RTL8821C_SUPPORT)
2559 if (dm->support_ic_type == ODM_RTL8821C)
2560 ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,
2561 path, rate);
2562 #endif
2563
2564 #if (RTL8195B_SUPPORT)
2565 if (dm->support_ic_type == ODM_RTL8195B)
2566 ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,
2567 path, rate);
2568 #endif
2569
2570 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2571 set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);
2572 #endif
2573
2574 } else {
2575 #if (RTL8822B_SUPPORT)
2576 if (dm->support_ic_type == ODM_RTL8822B)
2577 ret = config_phydm_write_txagc_8822b(dm,
2578 pwr_idx,
2579 path,
2580 rate);
2581 #endif
2582
2583 #if (RTL8821C_SUPPORT)
2584 if (dm->support_ic_type == ODM_RTL8821C)
2585 ret = config_phydm_write_txagc_8821c(dm,
2586 pwr_idx,
2587 path,
2588 rate);
2589 #endif
2590
2591 #if (RTL8195B_SUPPORT)
2592 if (dm->support_ic_type == ODM_RTL8195B)
2593 ret = config_phydm_write_txagc_8195b(dm,
2594 pwr_idx,
2595 path,
2596 rate);
2597 #endif
2598
2599 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2600 for (i = 0; i < 4; i++)
2601 set_current_tx_agc(dm->priv, path, (rate + i),
2602 (u8)pwr_idx);
2603 #endif
2604 }
2605 }
2606 #endif
2607
2608 #if (RTL8198F_SUPPORT)
2609 if (dm->support_ic_type & ODM_RTL8198F) {
2610 if (rate < 0x4)
2611 txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
2612 rate,
2613 PDM_CCK);
2614 else
2615 txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
2616 rate,
2617 PDM_OFDM);
2618
2619 pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);
2620 base = txagc_tmp - pw_by_rate_tmp;
2621 base = base & 0x7f;
2622 if (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127)
2623 return false;
2624
2625 pw_by_rate_new = (s8)(pwr_idx - base);
2626 ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);
2627 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2628 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2629 __func__, path, rate, base, pw_by_rate_new);
2630 }
2631 #endif
2632
2633 #if (RTL8822C_SUPPORT)
2634 if (dm->support_ic_type & ODM_RTL8822C) {
2635 if (rate < 0x4)
2636 txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
2637 rate,
2638 PDM_CCK);
2639 else
2640 txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
2641 rate,
2642 PDM_OFDM);
2643
2644 pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);
2645 base = txagc_tmp - pw_by_rate_tmp;
2646 base = base & 0x7f;
2647 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2648 return false;
2649
2650 pw_by_rate_new = (s8)(pwr_idx - base);
2651 ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);
2652 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2653 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2654 __func__, path, rate, base, pw_by_rate_new);
2655 }
2656 #endif
2657
2658 #if (RTL8814B_SUPPORT)
2659 if (dm->support_ic_type & ODM_RTL8814B) {
2660 if (rate < 0x4)
2661 txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
2662 rate,
2663 PDM_CCK);
2664 else
2665 txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
2666 rate,
2667 PDM_OFDM);
2668
2669 pw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate);
2670 base = txagc_tmp - pw_by_rate_tmp;
2671 base = base & 0x7f;
2672 if (DIFF_2((pwr_idx & 0x7f), base) > 64)
2673 return false;
2674
2675 pw_by_rate_new = (s8)(pwr_idx - base);
2676 ret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate);
2677 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2678 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2679 __func__, path, rate, base, pw_by_rate_new);
2680 }
2681 #endif
2682
2683 #if (RTL8812F_SUPPORT)
2684 if (dm->support_ic_type & ODM_RTL8812F) {
2685 if (rate < 0x4)
2686 txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
2687 rate,
2688 PDM_CCK);
2689 else
2690 txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
2691 rate,
2692 PDM_OFDM);
2693
2694 pw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate);
2695 base = txagc_tmp - pw_by_rate_tmp;
2696 base = base & 0x7f;
2697 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2698 return false;
2699
2700 pw_by_rate_new = (s8)(pwr_idx - base);
2701 ret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate);
2702 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2703 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2704 __func__, path, rate, base, pw_by_rate_new);
2705 }
2706 #endif
2707
2708 #if (RTL8197G_SUPPORT)
2709 if (dm->support_ic_type & ODM_RTL8197G) {
2710 if (rate < 0x4)
2711 txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
2712 rate,
2713 PDM_CCK);
2714 else
2715 txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
2716 rate,
2717 PDM_OFDM);
2718
2719 pw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate);
2720 base = txagc_tmp - pw_by_rate_tmp;
2721 base = base & 0x7f;
2722 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2723 return false;
2724
2725 pw_by_rate_new = (s8)(pwr_idx - base);
2726 ret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate);
2727 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2728 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2729 __func__, path, rate, base, pw_by_rate_new);
2730 }
2731 #endif
2732 #if (RTL8723F_SUPPORT)
2733 if (dm->support_ic_type & ODM_RTL8723F) {
2734 if (rate < 0x4)
2735 txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
2736 rate,
2737 PDM_CCK);
2738 else
2739 txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
2740 rate,
2741 PDM_OFDM);
2742
2743 pw_by_rate_tmp = config_phydm_read_txagc_diff_8723f(dm, rate);
2744 base = txagc_tmp - pw_by_rate_tmp;
2745 base = base & 0x7f;
2746 if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
2747 return false;
2748
2749 pw_by_rate_new = (s8)(pwr_idx - base);
2750 ret = phydm_write_txagc_1byte_8723f(dm, pw_by_rate_new, rate);
2751 PHYDM_DBG(dm, ODM_PHY_CONFIG,
2752 "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
2753 __func__, path, rate, base, pw_by_rate_new);
2754 }
2755 #endif
2756
2757 #if (RTL8197F_SUPPORT)
2758 if (dm->support_ic_type & ODM_RTL8197F)
2759 ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);
2760 #endif
2761
2762 #if (RTL8192F_SUPPORT)
2763 if (dm->support_ic_type & ODM_RTL8192F)
2764 ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);
2765 #endif
2766
2767 #if (RTL8721D_SUPPORT)
2768 if (dm->support_ic_type & ODM_RTL8721D)
2769 ret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate);
2770 #endif
2771 #if (RTL8710C_SUPPORT)
2772 if (dm->support_ic_type & ODM_RTL8710C)
2773 ret = config_phydm_write_txagc_8710c(dm, pwr_idx, path, rate);
2774 #endif
2775 return ret;
2776 }
2777
phydm_api_get_txagc(void * dm_void,enum rf_path path,u8 hw_rate)2778 u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
2779 {
2780 struct dm_struct *dm = (struct dm_struct *)dm_void;
2781 u8 ret = 0;
2782
2783 #if (RTL8822B_SUPPORT)
2784 if (dm->support_ic_type & ODM_RTL8822B)
2785 ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
2786 #endif
2787
2788 #if (RTL8197F_SUPPORT)
2789 if (dm->support_ic_type & ODM_RTL8197F)
2790 ret = config_phydm_read_txagc_8197f(dm, path, hw_rate);
2791 #endif
2792
2793 #if (RTL8821C_SUPPORT)
2794 if (dm->support_ic_type & ODM_RTL8821C)
2795 ret = config_phydm_read_txagc_8821c(dm, path, hw_rate);
2796 #endif
2797
2798 #if (RTL8195B_SUPPORT)
2799 if (dm->support_ic_type & ODM_RTL8195B)
2800 ret = config_phydm_read_txagc_8195b(dm, path, hw_rate);
2801 #endif
2802
2803 /*@jj add 20170822*/
2804 #if (RTL8192F_SUPPORT)
2805 if (dm->support_ic_type & ODM_RTL8192F)
2806 ret = config_phydm_read_txagc_8192f(dm, path, hw_rate);
2807 #endif
2808
2809 #if (RTL8198F_SUPPORT)
2810 if (dm->support_ic_type & ODM_RTL8198F) {
2811 if (hw_rate < 0x4) {
2812 ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
2813 PDM_CCK);
2814 } else {
2815 ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
2816 PDM_OFDM);
2817 }
2818 }
2819 #endif
2820
2821 #if (RTL8822C_SUPPORT)
2822 if (dm->support_ic_type & ODM_RTL8822C) {
2823 if (hw_rate < 0x4) {
2824 ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
2825 PDM_CCK);
2826 } else {
2827 ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
2828 PDM_OFDM);
2829 }
2830 }
2831 #endif
2832
2833 #if (RTL8723F_SUPPORT)
2834 if (dm->support_ic_type & ODM_RTL8723F) {
2835 if (hw_rate < 0x4) {
2836 ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
2837 PDM_CCK);
2838 } else {
2839 ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
2840 PDM_OFDM);
2841 }
2842 }
2843 #endif
2844
2845 #if (RTL8814B_SUPPORT)
2846 if (dm->support_ic_type & ODM_RTL8814B) {
2847 if (hw_rate < 0x4) {
2848 ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
2849 PDM_CCK);
2850 } else {
2851 ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
2852 PDM_OFDM);
2853 }
2854 }
2855 #endif
2856
2857 #if (RTL8812F_SUPPORT)
2858 if (dm->support_ic_type & ODM_RTL8812F) {
2859 if (hw_rate < 0x4) {
2860 ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
2861 PDM_CCK);
2862 } else {
2863 ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
2864 PDM_OFDM);
2865 }
2866 }
2867 #endif
2868
2869 #if (RTL8197G_SUPPORT)
2870 if (dm->support_ic_type & ODM_RTL8197G) {
2871 if (hw_rate < 0x4) {
2872 ret = config_phydm_read_txagc_8197g(dm, path,
2873 hw_rate,
2874 PDM_CCK);
2875 } else {
2876 ret = config_phydm_read_txagc_8197g(dm, path,
2877 hw_rate,
2878 PDM_OFDM);
2879 }
2880 }
2881 #endif
2882
2883 #if (RTL8721D_SUPPORT)
2884 if (dm->support_ic_type & ODM_RTL8721D)
2885 ret = config_phydm_read_txagc_8721d(dm, path, hw_rate);
2886 #endif
2887 #if (RTL8710C_SUPPORT)
2888 if (dm->support_ic_type & ODM_RTL8710C)
2889 ret = config_phydm_read_txagc_8710c(dm, path, hw_rate);
2890 #endif
2891 return ret;
2892 }
2893
2894 #if (RTL8822C_SUPPORT)
phydm_shift_rxagc_table(void * dm_void,boolean is_pos_shift,u8 sft)2895 void phydm_shift_rxagc_table(void *dm_void, boolean is_pos_shift, u8 sft)
2896 {
2897 struct dm_struct *dm = (struct dm_struct *)dm_void;
2898 u8 i = 0;
2899 u8 j = 0;
2900 u32 reg = 0;
2901 u16 max_rf_gain = 0;
2902 u16 min_rf_gain = 0;
2903
2904 dm->is_agc_tab_pos_shift = is_pos_shift;
2905 dm->agc_table_shift = sft;
2906
2907 for (i = 0; i <= dm->agc_table_cnt; i++) {
2908 max_rf_gain = dm->agc_rf_gain_ori[i][0];
2909 min_rf_gain = dm->agc_rf_gain_ori[i][63];
2910
2911 if (dm->support_ic_type & ODM_RTL8822C)
2912 dm->l_bnd_detect[i] = false;
2913
2914 for (j = 0; j < 64; j++) {
2915 if (is_pos_shift) {
2916 if (j < sft)
2917 reg = (max_rf_gain & 0x3ff);
2918 else
2919 reg = (dm->agc_rf_gain_ori[i][j - sft] &
2920 0x3ff);
2921 } else {
2922 if (j > 63 - sft)
2923 reg = (min_rf_gain & 0x3ff);
2924
2925 else
2926 reg = (dm->agc_rf_gain_ori[i][j + sft] &
2927 0x3ff);
2928 }
2929 dm->agc_rf_gain[i][j] = (u16)(reg & 0x3ff);
2930
2931 reg |= (j & 0x3f) << 16;/*mp_gain_idx*/
2932 reg |= (i & 0xf) << 22;/*table*/
2933 reg |= BIT(29) | BIT(28);/*write en*/
2934 odm_set_bb_reg(dm, R_0x1d90, MASKDWORD, reg);
2935 }
2936 }
2937
2938 if (dm->support_ic_type & ODM_RTL8822C)
2939 odm_set_bb_reg(dm, R_0x828, 0xf8, L_BND_DEFAULT_8822C);
2940 }
2941 #endif
2942
2943 boolean
phydm_api_switch_bw_channel(void * dm_void,u8 ch,u8 pri_ch,enum channel_width bw)2944 phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
2945 enum channel_width bw)
2946 {
2947 struct dm_struct *dm = (struct dm_struct *)dm_void;
2948 boolean ret = false;
2949
2950 switch (dm->support_ic_type) {
2951 #if (RTL8822B_SUPPORT)
2952 case ODM_RTL8822B:
2953 ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);
2954 break;
2955 #endif
2956
2957 #if (RTL8197F_SUPPORT)
2958 case ODM_RTL8197F:
2959 ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);
2960 break;
2961 #endif
2962
2963 #if (RTL8821C_SUPPORT)
2964 case ODM_RTL8821C:
2965 ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);
2966 break;
2967 #endif
2968
2969 #if (RTL8195B_SUPPORT)
2970 case ODM_RTL8195B:
2971 ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw);
2972 break;
2973 #endif
2974
2975 #if (RTL8192F_SUPPORT)
2976 case ODM_RTL8192F:
2977 ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
2978 break;
2979 #endif
2980
2981 #if (RTL8198F_SUPPORT)
2982 case ODM_RTL8198F:
2983 ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);
2984 break;
2985 #endif
2986
2987 #if (RTL8822C_SUPPORT)
2988 case ODM_RTL8822C:
2989 ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);
2990 break;
2991 #endif
2992
2993 #if (RTL8723F_SUPPORT)
2994 case ODM_RTL8723F:
2995 ret = config_phydm_switch_channel_bw_8723f(dm, ch, pri_ch, bw);
2996 break;
2997 #endif
2998
2999 #if (RTL8814B_SUPPORT)
3000 case ODM_RTL8814B:
3001 ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);
3002 break;
3003 #endif
3004
3005 #if (RTL8812F_SUPPORT)
3006 case ODM_RTL8812F:
3007 ret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw);
3008 break;
3009 #endif
3010
3011 #if (RTL8197G_SUPPORT)
3012 case ODM_RTL8197G:
3013 ret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw);
3014 break;
3015 #endif
3016
3017 #if (RTL8721D_SUPPORT)
3018 case ODM_RTL8721D:
3019 ret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw);
3020 break;
3021 #endif
3022 #if (RTL8710C_SUPPORT)
3023 case ODM_RTL8710C:
3024 ret = config_phydm_switch_channel_bw_8710c(dm, ch, pri_ch, bw);
3025 break;
3026 #endif
3027
3028 default:
3029 break;
3030 }
3031 return ret;
3032 }
3033
3034 boolean
phydm_api_trx_mode(void * dm_void,enum bb_path tx_path,enum bb_path rx_path,enum bb_path tx_path_ctrl)3035 phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
3036 enum bb_path tx_path_ctrl)
3037 {
3038 struct dm_struct *dm = (struct dm_struct *)dm_void;
3039 boolean ret = false;
3040 boolean is_2tx = false;
3041
3042 if (tx_path_ctrl == BB_PATH_AB)
3043 is_2tx = true;
3044
3045 switch (dm->support_ic_type) {
3046 #if (RTL8822B_SUPPORT)
3047 case ODM_RTL8822B:
3048 ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
3049 tx_path_ctrl);
3050 break;
3051 #endif
3052
3053 #if (RTL8197F_SUPPORT)
3054 case ODM_RTL8197F:
3055 ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);
3056 break;
3057 #endif
3058
3059 #if (RTL8192F_SUPPORT)
3060 case ODM_RTL8192F:
3061 ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path,
3062 tx_path_ctrl);
3063 break;
3064 #endif
3065
3066 #if (RTL8198F_SUPPORT)
3067 case ODM_RTL8198F:
3068 ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);
3069 break;
3070 #endif
3071
3072 #if (RTL8814B_SUPPORT)
3073 case ODM_RTL8814B:
3074 ret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path);
3075 break;
3076 #endif
3077
3078 #if (RTL8822C_SUPPORT)
3079 case ODM_RTL8822C:
3080 ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path,
3081 tx_path_ctrl);
3082 break;
3083 #endif
3084
3085 #if (RTL8812F_SUPPORT)
3086 case ODM_RTL8812F:
3087 ret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx);
3088 break;
3089 #endif
3090
3091 #if (RTL8197G_SUPPORT)
3092 case ODM_RTL8197G:
3093 ret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx);
3094 break;
3095 #endif
3096
3097 #if (RTL8721D_SUPPORT)
3098 case ODM_RTL8721D:
3099 ret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx);
3100 break;
3101 #endif
3102
3103 #if (RTL8710C_SUPPORT)
3104 case ODM_RTL8710C:
3105 ret = config_phydm_trx_mode_8710c(dm, tx_path, rx_path, is_2tx);
3106 break;
3107 #endif
3108 }
3109 return ret;
3110 }
3111 #endif
3112
3113 #ifdef PHYDM_COMMON_API_NOT_SUPPORT
config_phydm_read_txagc_n(void * dm_void,enum rf_path path,u8 hw_rate)3114 u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
3115 {
3116 struct dm_struct *dm = (struct dm_struct *)dm_void;
3117 u8 read_back_data = INVALID_TXAGC_DATA;
3118 u32 reg_txagc;
3119 u32 reg_mask;
3120 /* This function is for 92E/88E etc... */
3121 /* @Input need to be HW rate index, not driver rate index!!!! */
3122
3123 /* @Error handling */
3124 if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {
3125 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n",
3126 __func__, path);
3127 return INVALID_TXAGC_DATA;
3128 }
3129
3130 if (path == RF_PATH_A) {
3131 switch (hw_rate) {
3132 case ODM_RATE1M:
3133 reg_txagc = R_0xe08;
3134 reg_mask = 0x00007f00;
3135 break;
3136 case ODM_RATE2M:
3137 reg_txagc = R_0x86c;
3138 reg_mask = 0x00007f00;
3139 break;
3140 case ODM_RATE5_5M:
3141 reg_txagc = R_0x86c;
3142 reg_mask = 0x007f0000;
3143 break;
3144 case ODM_RATE11M:
3145 reg_txagc = R_0x86c;
3146 reg_mask = 0x7f000000;
3147 break;
3148
3149 case ODM_RATE6M:
3150 reg_txagc = R_0xe00;
3151 reg_mask = 0x0000007f;
3152 break;
3153 case ODM_RATE9M:
3154 reg_txagc = R_0xe00;
3155 reg_mask = 0x00007f00;
3156 break;
3157 case ODM_RATE12M:
3158 reg_txagc = R_0xe00;
3159 reg_mask = 0x007f0000;
3160 break;
3161 case ODM_RATE18M:
3162 reg_txagc = R_0xe00;
3163 reg_mask = 0x7f000000;
3164 break;
3165 case ODM_RATE24M:
3166 reg_txagc = R_0xe04;
3167 reg_mask = 0x0000007f;
3168 break;
3169 case ODM_RATE36M:
3170 reg_txagc = R_0xe04;
3171 reg_mask = 0x00007f00;
3172 break;
3173 case ODM_RATE48M:
3174 reg_txagc = R_0xe04;
3175 reg_mask = 0x007f0000;
3176 break;
3177 case ODM_RATE54M:
3178 reg_txagc = R_0xe04;
3179 reg_mask = 0x7f000000;
3180 break;
3181
3182 case ODM_RATEMCS0:
3183 reg_txagc = R_0xe10;
3184 reg_mask = 0x0000007f;
3185 break;
3186 case ODM_RATEMCS1:
3187 reg_txagc = R_0xe10;
3188 reg_mask = 0x00007f00;
3189 break;
3190 case ODM_RATEMCS2:
3191 reg_txagc = R_0xe10;
3192 reg_mask = 0x007f0000;
3193 break;
3194 case ODM_RATEMCS3:
3195 reg_txagc = R_0xe10;
3196 reg_mask = 0x7f000000;
3197 break;
3198 case ODM_RATEMCS4:
3199 reg_txagc = R_0xe14;
3200 reg_mask = 0x0000007f;
3201 break;
3202 case ODM_RATEMCS5:
3203 reg_txagc = R_0xe14;
3204 reg_mask = 0x00007f00;
3205 break;
3206 case ODM_RATEMCS6:
3207 reg_txagc = R_0xe14;
3208 reg_mask = 0x007f0000;
3209 break;
3210 case ODM_RATEMCS7:
3211 reg_txagc = R_0xe14;
3212 reg_mask = 0x7f000000;
3213 break;
3214 case ODM_RATEMCS8:
3215 reg_txagc = R_0xe18;
3216 reg_mask = 0x0000007f;
3217 break;
3218 case ODM_RATEMCS9:
3219 reg_txagc = R_0xe18;
3220 reg_mask = 0x00007f00;
3221 break;
3222 case ODM_RATEMCS10:
3223 reg_txagc = R_0xe18;
3224 reg_mask = 0x007f0000;
3225 break;
3226 case ODM_RATEMCS11:
3227 reg_txagc = R_0xe18;
3228 reg_mask = 0x7f000000;
3229 break;
3230 case ODM_RATEMCS12:
3231 reg_txagc = R_0xe1c;
3232 reg_mask = 0x0000007f;
3233 break;
3234 case ODM_RATEMCS13:
3235 reg_txagc = R_0xe1c;
3236 reg_mask = 0x00007f00;
3237 break;
3238 case ODM_RATEMCS14:
3239 reg_txagc = R_0xe1c;
3240 reg_mask = 0x007f0000;
3241 break;
3242 case ODM_RATEMCS15:
3243 reg_txagc = R_0xe1c;
3244 reg_mask = 0x7f000000;
3245 break;
3246
3247 default:
3248 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
3249 break;
3250 }
3251 } else if (path == RF_PATH_B) {
3252 switch (hw_rate) {
3253 case ODM_RATE1M:
3254 reg_txagc = R_0x838;
3255 reg_mask = 0x00007f00;
3256 break;
3257 case ODM_RATE2M:
3258 reg_txagc = R_0x838;
3259 reg_mask = 0x007f0000;
3260 break;
3261 case ODM_RATE5_5M:
3262 reg_txagc = R_0x838;
3263 reg_mask = 0x7f000000;
3264 break;
3265 case ODM_RATE11M:
3266 reg_txagc = R_0x86c;
3267 reg_mask = 0x0000007f;
3268 break;
3269
3270 case ODM_RATE6M:
3271 reg_txagc = R_0x830;
3272 reg_mask = 0x0000007f;
3273 break;
3274 case ODM_RATE9M:
3275 reg_txagc = R_0x830;
3276 reg_mask = 0x00007f00;
3277 break;
3278 case ODM_RATE12M:
3279 reg_txagc = R_0x830;
3280 reg_mask = 0x007f0000;
3281 break;
3282 case ODM_RATE18M:
3283 reg_txagc = R_0x830;
3284 reg_mask = 0x7f000000;
3285 break;
3286 case ODM_RATE24M:
3287 reg_txagc = R_0x834;
3288 reg_mask = 0x0000007f;
3289 break;
3290 case ODM_RATE36M:
3291 reg_txagc = R_0x834;
3292 reg_mask = 0x00007f00;
3293 break;
3294 case ODM_RATE48M:
3295 reg_txagc = R_0x834;
3296 reg_mask = 0x007f0000;
3297 break;
3298 case ODM_RATE54M:
3299 reg_txagc = R_0x834;
3300 reg_mask = 0x7f000000;
3301 break;
3302
3303 case ODM_RATEMCS0:
3304 reg_txagc = R_0x83c;
3305 reg_mask = 0x0000007f;
3306 break;
3307 case ODM_RATEMCS1:
3308 reg_txagc = R_0x83c;
3309 reg_mask = 0x00007f00;
3310 break;
3311 case ODM_RATEMCS2:
3312 reg_txagc = R_0x83c;
3313 reg_mask = 0x007f0000;
3314 break;
3315 case ODM_RATEMCS3:
3316 reg_txagc = R_0x83c;
3317 reg_mask = 0x7f000000;
3318 break;
3319 case ODM_RATEMCS4:
3320 reg_txagc = R_0x848;
3321 reg_mask = 0x0000007f;
3322 break;
3323 case ODM_RATEMCS5:
3324 reg_txagc = R_0x848;
3325 reg_mask = 0x00007f00;
3326 break;
3327 case ODM_RATEMCS6:
3328 reg_txagc = R_0x848;
3329 reg_mask = 0x007f0000;
3330 break;
3331 case ODM_RATEMCS7:
3332 reg_txagc = R_0x848;
3333 reg_mask = 0x7f000000;
3334 break;
3335
3336 case ODM_RATEMCS8:
3337 reg_txagc = R_0x84c;
3338 reg_mask = 0x0000007f;
3339 break;
3340 case ODM_RATEMCS9:
3341 reg_txagc = R_0x84c;
3342 reg_mask = 0x00007f00;
3343 break;
3344 case ODM_RATEMCS10:
3345 reg_txagc = R_0x84c;
3346 reg_mask = 0x007f0000;
3347 break;
3348 case ODM_RATEMCS11:
3349 reg_txagc = R_0x84c;
3350 reg_mask = 0x7f000000;
3351 break;
3352 case ODM_RATEMCS12:
3353 reg_txagc = R_0x868;
3354 reg_mask = 0x0000007f;
3355 break;
3356 case ODM_RATEMCS13:
3357 reg_txagc = R_0x868;
3358 reg_mask = 0x00007f00;
3359 break;
3360 case ODM_RATEMCS14:
3361 reg_txagc = R_0x868;
3362 reg_mask = 0x007f0000;
3363 break;
3364 case ODM_RATEMCS15:
3365 reg_txagc = R_0x868;
3366 reg_mask = 0x7f000000;
3367 break;
3368
3369 default:
3370 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
3371 break;
3372 }
3373 } else {
3374 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n");
3375 }
3376 read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);
3377 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n",
3378 __func__, path, hw_rate, read_back_data);
3379 return read_back_data;
3380 }
3381 #endif
3382
3383 #ifdef CONFIG_MCC_DM
3384 #ifdef DYN_ANT_WEIGHTING_SUPPORT
phydm_set_weighting_cmn(struct dm_struct * dm)3385 void phydm_set_weighting_cmn(struct dm_struct *dm)
3386 {
3387 PHYDM_DBG(dm, DBG_COMP_MCC, "%s\n", __func__);
3388 odm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0);
3389 odm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0);
3390 }
3391
phydm_set_weighting_mcc(u8 b_equal_weighting,void * dm_void,u8 port)3392 void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)
3393 {
3394 /*u8 reg_8;*/
3395 struct dm_struct *dm = (struct dm_struct *)dm_void;
3396 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3397 u8 val_0x98e, val_0x98f, val_0x81b;
3398 u32 temp_reg;
3399
3400 PHYDM_DBG(dm, DBG_COMP_MCC, "ant_weighting_mcc, port = %d\n", port);
3401 if (b_equal_weighting) {
3402 temp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000);
3403 val_0x98e = (u8)(temp_reg >> 16) & 0xc0;
3404 temp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000);
3405 val_0x98f = (u8)(temp_reg >> 24) & 0x7f;
3406 temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
3407 val_0x81b = (u8)(temp_reg >> 24) & 0xfd;
3408 PHYDM_DBG(dm, DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n",
3409 dm->rssi_min);
3410 /*equal weighting*/
3411 } else {
3412 val_0x98e = 0x44;
3413 val_0x98f = 0x43;
3414 temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
3415 val_0x81b = (u8)(temp_reg >> 24) | BIT(2);
3416 PHYDM_DBG(dm, DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n",
3417 dm->rssi_min);
3418 /*fix sec_min_wgt = 1/2*/
3419 }
3420 mcc_dm->mcc_reg_id[2] = 0x2;
3421 mcc_dm->mcc_dm_reg[2] = 0x98e;
3422 mcc_dm->mcc_dm_val[2][port] = val_0x98e;
3423
3424 mcc_dm->mcc_reg_id[3] = 0x3;
3425 mcc_dm->mcc_dm_reg[3] = 0x98f;
3426 mcc_dm->mcc_dm_val[3][port] = val_0x98f;
3427
3428 mcc_dm->mcc_reg_id[4] = 0x4;
3429 mcc_dm->mcc_dm_reg[4] = 0x81b;
3430 mcc_dm->mcc_dm_val[4][port] = val_0x81b;
3431 }
3432
phydm_dyn_ant_dec_mcc(u8 port,u8 rssi_in,void * dm_void)3433 void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)
3434 {
3435 struct dm_struct *dm = (struct dm_struct *)dm_void;
3436 u8 rssi_l2h = 43, rssi_h2l = 37;
3437
3438 if (rssi_in == 0xff)
3439 phydm_set_weighting_mcc(FALSE, dm, port);
3440 else if (rssi_in >= rssi_l2h)
3441 phydm_set_weighting_mcc(TRUE, dm, port);
3442 else if (rssi_in <= rssi_h2l)
3443 phydm_set_weighting_mcc(FALSE, dm, port);
3444 }
3445
phydm_dynamic_ant_weighting_mcc_8822b(void * dm_void)3446 void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)
3447 {
3448 struct dm_struct *dm = (struct dm_struct *)dm_void;
3449 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3450 u8 i;
3451
3452 phydm_set_weighting_cmn(dm);
3453 for (i = 0; i <= 1; i++)
3454 phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);
3455 }
3456 #endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
3457
phydm_mcc_init(void * dm_void)3458 void phydm_mcc_init(void *dm_void)
3459 {
3460 struct dm_struct *dm = (struct dm_struct *)dm_void;
3461 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3462 u8 i;
3463
3464 /*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/
3465 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n");
3466 for (i = 0; i < MCC_DM_REG_NUM; i++) {
3467 mcc_dm->mcc_reg_id[i] = 0xff;
3468 mcc_dm->mcc_dm_reg[i] = 0;
3469 mcc_dm->mcc_dm_val[i][0] = 0;
3470 mcc_dm->mcc_dm_val[i][1] = 0;
3471 }
3472 for (i = 0; i < NUM_STA; i++) {
3473 mcc_dm->sta_macid[0][i] = 0xff;
3474 mcc_dm->sta_macid[1][i] = 0xff;
3475 }
3476 /* Function init */
3477 dm->is_stop_dym_ant_weighting = 0;
3478 }
3479
phydm_check(void * dm_void)3480 u8 phydm_check(void *dm_void)
3481 {
3482 struct dm_struct *dm = (struct dm_struct *)dm_void;
3483 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3484 struct cmn_sta_info *p_entry = NULL;
3485 u8 shift = 0;
3486 u8 i = 0;
3487 u8 j = 0;
3488 u8 rssi_min[2] = {0xff, 0xff};
3489 u8 sta_num = 8;
3490 u8 mcc_macid = 0;
3491
3492 for (i = 0; i <= 1; i++) {
3493 for (j = 0; j < sta_num; j++) {
3494 if (mcc_dm->sta_macid[i][j] != 0xff) {
3495 mcc_macid = mcc_dm->sta_macid[i][j];
3496 p_entry = dm->phydm_sta_info[mcc_macid];
3497 if (!p_entry) {
3498 PHYDM_DBG(dm, DBG_COMP_MCC,
3499 "PEntry NULL(mac=%d)\n",
3500 mcc_dm->sta_macid[i][j]);
3501 return _FAIL;
3502 }
3503 PHYDM_DBG(dm, DBG_COMP_MCC,
3504 "undec_smoothed_pwdb=%d\n",
3505 p_entry->rssi_stat.rssi);
3506 if (p_entry->rssi_stat.rssi < rssi_min[i])
3507 rssi_min[i] = p_entry->rssi_stat.rssi;
3508 }
3509 }
3510 }
3511 mcc_dm->mcc_rssi[0] = (u8)rssi_min[0];
3512 mcc_dm->mcc_rssi[1] = (u8)rssi_min[1];
3513 return _SUCCESS;
3514 }
3515
phydm_mcc_h2ccmd_rst(void * dm_void)3516 void phydm_mcc_h2ccmd_rst(void *dm_void)
3517 {
3518 struct dm_struct *dm = (struct dm_struct *)dm_void;
3519 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3520 u8 i;
3521 u8 regid;
3522 u8 h2c_mcc[H2C_MAX_LENGTH];
3523
3524 /* RST MCC */
3525 for (i = 0; i < H2C_MAX_LENGTH; i++)
3526 h2c_mcc[i] = 0xff;
3527 h2c_mcc[0] = 0x00;
3528 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
3529 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n");
3530 }
3531
phydm_mcc_h2ccmd(void * dm_void)3532 void phydm_mcc_h2ccmd(void *dm_void)
3533 {
3534 struct dm_struct *dm = (struct dm_struct *)dm_void;
3535 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3536 u8 i;
3537 u8 regid;
3538 u8 h2c_mcc[H2C_MAX_LENGTH];
3539
3540 if (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) {
3541 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n");
3542 return;
3543 }
3544 /* Set Channel number */
3545 for (i = 0; i < H2C_MAX_LENGTH; i++)
3546 h2c_mcc[i] = 0xff;
3547 h2c_mcc[0] = 0xe0;
3548 h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]);
3549 h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8);
3550 h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]);
3551 h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8);
3552 h2c_mcc[5] = 0xff;
3553 h2c_mcc[6] = 0xff;
3554 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
3555 PHYDM_DBG(dm, DBG_COMP_MCC,
3556 "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3557 h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3],
3558 h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]);
3559
3560 /* Set Reg and value*/
3561 for (i = 0; i < H2C_MAX_LENGTH; i++)
3562 h2c_mcc[i] = 0xff;
3563
3564 for (i = 0; i < MCC_DM_REG_NUM; i++) {
3565 regid = mcc_dm->mcc_reg_id[i];
3566 if (regid != 0xff) {
3567 h2c_mcc[0] = 0xa0 | (regid & 0x1f);
3568 h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);
3569 h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
3570 h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];
3571 h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];
3572 h2c_mcc[5] = 0xff;
3573 h2c_mcc[6] = 0xff;
3574 odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH,
3575 h2c_mcc);
3576 PHYDM_DBG(dm, DBG_COMP_MCC,
3577 "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3578 h2c_mcc[0], h2c_mcc[1], h2c_mcc[2],
3579 h2c_mcc[3], h2c_mcc[4],
3580 h2c_mcc[5], h2c_mcc[6]);
3581 }
3582 }
3583 }
3584
phydm_mcc_ctrl(void * dm_void)3585 void phydm_mcc_ctrl(void *dm_void)
3586 {
3587 struct dm_struct *dm = (struct dm_struct *)dm_void;
3588 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3589 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3590
3591 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status);
3592 /*MCC stage no change*/
3593 if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)
3594 return;
3595 /*Not in MCC stage*/
3596 if (mcc_dm->mcc_status == 0) {
3597 /* Enable normal Ant-weighting */
3598 dm->is_stop_dym_ant_weighting = 0;
3599 /* Enable normal DIG */
3600 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);
3601 } else {
3602 /* Disable normal Ant-weighting */
3603 dm->is_stop_dym_ant_weighting = 1;
3604 /* Enable normal DIG */
3605 odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1,
3606 0x20);
3607 }
3608 if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)
3609 phydm_mcc_init(dm);
3610 mcc_dm->mcc_pre_status = mcc_dm->mcc_status;
3611 }
3612
phydm_fill_mcccmd(void * dm_void,u8 regid,u16 reg_add,u8 val0,u8 val1)3613 void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
3614 u8 val0, u8 val1)
3615 {
3616 struct dm_struct *dm = (struct dm_struct *)dm_void;
3617 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3618
3619 mcc_dm->mcc_reg_id[regid] = regid;
3620 mcc_dm->mcc_dm_reg[regid] = reg_add;
3621 mcc_dm->mcc_dm_val[regid][0] = val0;
3622 mcc_dm->mcc_dm_val[regid][1] = val1;
3623 }
3624
phydm_mcc_switch(void * dm_void)3625 void phydm_mcc_switch(void *dm_void)
3626 {
3627 struct dm_struct *dm = (struct dm_struct *)dm_void;
3628 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3629 s8 ret;
3630
3631 phydm_mcc_ctrl(dm);
3632 if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/
3633 phydm_mcc_h2ccmd_rst(dm);
3634 return;
3635 }
3636 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n");
3637 ret = phydm_check(dm);
3638 if (ret == _FAIL) {
3639 PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n");
3640 return;
3641 }
3642 /* Set IGI*/
3643 phydm_mcc_igi_cal(dm);
3644
3645 /* Set Antenna Gain*/
3646 #if (RTL8822B_SUPPORT == 1)
3647 phydm_dynamic_ant_weighting_mcc_8822b(dm);
3648 #endif
3649 /* Set H2C Cmd*/
3650 phydm_mcc_h2ccmd(dm);
3651 }
3652 #endif
3653
3654 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_normal_driver_rx_sniffer(struct dm_struct * dm,u8 * desc,PRT_RFD_STATUS rt_rfd_status,u8 * drv_info,u8 phy_status)3655 void phydm_normal_driver_rx_sniffer(
3656 struct dm_struct *dm,
3657 u8 *desc,
3658 PRT_RFD_STATUS rt_rfd_status,
3659 u8 *drv_info,
3660 u8 phy_status)
3661 {
3662 #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
3663 u32 *msg;
3664 u16 seq_num;
3665
3666 if (rt_rfd_status->packet_report_type != NORMAL_RX)
3667 return;
3668
3669 if (!dm->is_linked) {
3670 if (rt_rfd_status->is_hw_error)
3671 return;
3672 }
3673
3674 if (phy_status == true) {
3675 if (dm->rx_pkt_type == type_block_ack ||
3676 dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)
3677 seq_num = 0;
3678 else
3679 seq_num = rt_rfd_status->seq_num;
3680
3681 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3682 "%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
3683 seq_num,
3684 /*rt_rfd_status->mac_id,*/
3685 (rt_rfd_status->is_crc ? "C" :
3686 rt_rfd_status->is_ampdu ? "A" : "_"),
3687 rt_rfd_status->data_rate,
3688 rt_rfd_status->length,
3689 ((rt_rfd_status->band_width == 0) ? "20M" :
3690 ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
3691 (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
3692
3693 if (dm->rx_pkt_type == type_asoc_req)
3694 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ");
3695 else if (dm->rx_pkt_type == type_asoc_rsp)
3696 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP");
3697 else if (dm->rx_pkt_type == type_probe_req)
3698 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ");
3699 else if (dm->rx_pkt_type == type_probe_rsp)
3700 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP");
3701 else if (dm->rx_pkt_type == type_deauth)
3702 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH");
3703 else if (dm->rx_pkt_type == type_beacon)
3704 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON");
3705 else if (dm->rx_pkt_type == type_block_ack_req)
3706 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ");
3707 else if (dm->rx_pkt_type == type_rts)
3708 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_");
3709 else if (dm->rx_pkt_type == type_cts)
3710 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_");
3711 else if (dm->rx_pkt_type == type_ack)
3712 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_");
3713 else if (dm->rx_pkt_type == type_block_ack)
3714 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__");
3715 else if (dm->rx_pkt_type == type_data)
3716 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_");
3717 else if (dm->rx_pkt_type == type_data_ack)
3718 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack");
3719 else if (dm->rx_pkt_type == type_qos_data)
3720 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data");
3721 else
3722 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]",
3723 dm->rx_pkt_type);
3724
3725 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]",
3726 dm->rssi_a,
3727 dm->rssi_b,
3728 dm->rssi_c,
3729 dm->rssi_d);
3730
3731 msg = (u32 *)drv_info;
3732
3733 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3734 " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
3735 msg[6], msg[5], msg[4], msg[3],
3736 msg[2], msg[1], msg[1]);
3737 } else {
3738 PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
3739 "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
3740 rt_rfd_status->seq_num,
3741 /*rt_rfd_status->mac_id,*/
3742 (rt_rfd_status->is_crc ? "C" :
3743 (rt_rfd_status->is_ampdu) ? "A" : "_"),
3744 rt_rfd_status->data_rate,
3745 rt_rfd_status->length,
3746 ((rt_rfd_status->band_width == 0) ? "20M" :
3747 ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
3748 (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
3749 }
3750
3751 #endif
3752 }
3753
3754 #endif
3755