1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 const u16 phy_rate_table[] = {
34 /*@20M*/
35 1, 2, 5, 11,
36 6, 9, 12, 18, 24, 36, 48, 54,
37 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
38 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
39 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
40 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
41 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
42 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
43 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
44 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
45 };
46
phydm_traffic_load_decision(void * dm_void)47 void phydm_traffic_load_decision(void *dm_void)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 u8 shift = 0;
51
52 /*@---TP & Trafic-load calculation---*/
53
54 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
55 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
56
57 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
58 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
59
60 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
61 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
62 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
63 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
64
65 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
66 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
67 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
68
69 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
70 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
71
72 dm->total_tp = dm->tx_tp + dm->rx_tp;
73
74 /*@[Calculate TX/RX state]*/
75 if (dm->tx_tp > (dm->rx_tp << 1))
76 dm->txrx_state_all = TX_STATE;
77 else if (dm->rx_tp > (dm->tx_tp << 1))
78 dm->txrx_state_all = RX_STATE;
79 else
80 dm->txrx_state_all = BI_DIRECTION_STATE;
81
82 /*@[Traffic load decision]*/
83 dm->pre_traffic_load = dm->traffic_load;
84
85 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
86 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
87 dm->traffic_load = TRAFFIC_HIGH;
88 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
89 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
90 dm->traffic_load = TRAFFIC_MID;
91 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
92 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
93 dm->traffic_load = TRAFFIC_LOW;
94 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
95 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
96 dm->traffic_load = TRAFFIC_ULTRA_LOW;
97 } else {
98 dm->traffic_load = TRAFFIC_NO_TP;
99 }
100
101 /*@[Calculate consecutive idlel time]*/
102 if (dm->traffic_load == 0)
103 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
104 else
105 dm->consecutive_idlel_time = 0;
106
107 #if 0
108 PHYDM_DBG(dm, DBG_COMMON_FLOW,
109 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
110 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
111 dm->last_rx_ok_cnt);
112
113 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
114 dm->rx_tp);
115 #endif
116 }
117
phydm_cck_new_agc_chk(struct dm_struct * dm)118 void phydm_cck_new_agc_chk(struct dm_struct *dm)
119 {
120 u32 new_agc_addr = 0x0;
121
122 dm->cck_new_agc = false;
123 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
124 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
125 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
126 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
127 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
128 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
129 ODM_RTL8721D | ODM_RTL8710C)) {
130 new_agc_addr = R_0xa9c;
131 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
132 ODM_RTL8814B | ODM_RTL8197G)) {
133 new_agc_addr = R_0x1a9c;
134 }
135
136 /*@1: new agc 0: old agc*/
137 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
138 #endif
139 #if (RTL8723F_SUPPORT)
140 if (dm->support_ic_type & (ODM_RTL8723F))
141 dm->cck_new_agc = true;
142 #endif
143 }
144
145 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)146 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
147 {
148 boolean report_type = 0;
149 #if (RTL8192E_SUPPORT)
150 u32 value_824, value_82c;
151 #endif
152
153 #if (RTL8192E_SUPPORT)
154 if (dm->support_ic_type & (ODM_RTL8192E)) {
155 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
156 * should be equal or CCK RSSI report may be incorrect
157 */
158 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
159 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
160
161 if (value_824 != value_82c)
162 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
163 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
164 report_type = (boolean)value_824;
165 }
166 #endif
167
168 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
169 if (dm->support_ic_type &
170 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
171 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
172
173 if (report_type != 1)
174 pr_debug("[Warning] CCK should be 4bit LNA\n");
175 }
176 #endif
177
178 #if (RTL8821C_SUPPORT)
179 if (dm->support_ic_type & ODM_RTL8821C) {
180 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
181 report_type = 1;
182 }
183 #endif
184
185 dm->cck_agc_report_type = report_type;
186
187 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
188 dm->cck_agc_report_type);
189 }
190
phydm_init_cck_setting(struct dm_struct * dm)191 void phydm_init_cck_setting(struct dm_struct *dm)
192 {
193 u32 reg_tmp = 0;
194 u32 mask_tmp = 0;
195
196 phydm_cck_new_agc_chk(dm);
197
198 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
199 return;
200
201 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
202 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
203 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
204
205 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
206
207 phydm_config_cck_rx_antenna_init(dm);
208
209 if (dm->support_ic_type & ODM_RTL8192F)
210 phydm_config_cck_rx_path(dm, BB_PATH_AB);
211 else if (dm->valid_path_set == BB_PATH_A)
212 phydm_config_cck_rx_path(dm, BB_PATH_A);
213 else if (dm->valid_path_set == BB_PATH_B)
214 phydm_config_cck_rx_path(dm, BB_PATH_B);
215
216 phydm_cck_lna_bit_num_chk(dm);
217 phydm_get_cck_rssi_table_from_reg(dm);
218 }
219
220 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)221 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
222 {
223 #if (RTL8821C_SUPPORT)
224 if (dm->support_ic_type & ODM_RTL8821C)
225 phydm_init_hw_info_by_rfe_type_8821c(dm);
226 #endif
227 #if (RTL8197F_SUPPORT)
228 if (dm->support_ic_type & ODM_RTL8197F)
229 phydm_init_hw_info_by_rfe_type_8197f(dm);
230 #endif
231 #if (RTL8197G_SUPPORT)
232 if (dm->support_ic_type & ODM_RTL8197G)
233 phydm_init_hw_info_by_rfe_type_8197g(dm);
234 #endif
235 }
236 #endif
237
phydm_common_info_self_init(struct dm_struct * dm)238 void phydm_common_info_self_init(struct dm_struct *dm)
239 {
240 u32 reg_tmp = 0;
241 u32 mask_tmp = 0;
242
243 dm->run_in_drv_fw = RUN_IN_DRIVER;
244
245 /*@BB IP Generation*/
246 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
247 dm->ic_ip_series = PHYDM_IC_JGR3;
248 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
249 dm->ic_ip_series = PHYDM_IC_AC;
250 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
251 dm->ic_ip_series = PHYDM_IC_N;
252
253 /*@BB phy-status Generation*/
254 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
255 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
256 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
257 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
258 else
259 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
260
261 phydm_init_cck_setting(dm);
262
263 reg_tmp = ODM_REG(BB_RX_PATH, dm);
264 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
265 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
266 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
267 dm->is_net_closed = &dm->BOOLEAN_temp;
268
269 phydm_init_debug_setting(dm);
270 #endif
271 phydm_init_soft_ml_setting(dm);
272
273 dm->phydm_sys_up_time = 0;
274
275 if (dm->support_ic_type & ODM_IC_1SS)
276 dm->num_rf_path = 1;
277 else if (dm->support_ic_type & ODM_IC_2SS)
278 dm->num_rf_path = 2;
279 #if 0
280 /* @RTK do not has IC which is equipped with 3 RF paths,
281 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
282 */
283 else if (dm->support_ic_type & ODM_IC_3SS)
284 dm->num_rf_path = 3;
285 #endif
286 else if (dm->support_ic_type & ODM_IC_4SS)
287 dm->num_rf_path = 4;
288 else
289 dm->num_rf_path = 1;
290
291 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
292
293 dm->tx_rate = 0xFF;
294 dm->rssi_min_by_path = 0xFF;
295
296 dm->number_linked_client = 0;
297 dm->pre_number_linked_client = 0;
298 dm->number_active_client = 0;
299 dm->pre_number_active_client = 0;
300
301 dm->last_tx_ok_cnt = 0;
302 dm->last_rx_ok_cnt = 0;
303 dm->tx_tp = 0;
304 dm->rx_tp = 0;
305 dm->total_tp = 0;
306 dm->traffic_load = TRAFFIC_LOW;
307
308 dm->nbi_set_result = 0;
309 dm->is_init_hw_info_by_rfe = false;
310 dm->pre_dbg_priority = DBGPORT_RELEASE;
311 dm->tp_active_th = 5;
312 dm->disable_phydm_watchdog = 0;
313
314 dm->u8_dummy = 0xf;
315 dm->u16_dummy = 0xffff;
316 dm->u32_dummy = 0xffffffff;
317 #if (RTL8814B_SUPPORT)
318 /*@------------For spur detection Default Mode------------@*/
319 dm->dsde_sel = DET_CSI;
320 dm->csi_wgt = 4;
321 /*@-------------------------------------------------------@*/
322 #endif
323 dm->pre_is_linked = false;
324 dm->is_linked = false;
325 /*dym bw thre and it can config by registry*/
326 if (dm->en_auto_bw_th == 0)
327 dm->en_auto_bw_th = 20;
328
329 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
330 if (!(dm->is_fcs_mode_enable)) {
331 dm->is_fcs_mode_enable = &dm->boolean_dummy;
332 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
333 }
334 #endif
335 /*init IOT table*/
336 odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
337 }
338
phydm_iot_patch_id_update(void * dm_void,u32 iot_idx,boolean en)339 void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
340 {
341 struct dm_struct *dm = (struct dm_struct *)dm_void;
342 struct phydm_iot_center *iot_table = &dm->iot_table;
343
344 PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
345 switch (iot_idx) {
346 case 0x100f0401:
347 iot_table->patch_id_100f0401 = en;
348 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
349 iot_table->patch_id_100f0401);
350 break;
351 case 0x10120200:
352 iot_table->patch_id_10120200 = en;
353 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
354 iot_table->patch_id_10120200);
355 break;
356 case 0x40010700:
357 iot_table->patch_id_40010700 = en;
358 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
359 iot_table->patch_id_40010700);
360 break;
361 case 0x021f0800:
362 iot_table->patch_id_021f0800 = en;
363 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
364 iot_table->patch_id_021f0800);
365 break;
366 case 0x011f0500:
367 iot_table->patch_id_011f0500 = en;
368 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_011f0500 = %d\n",
369 iot_table->patch_id_011f0500);
370 break;
371 default:
372 pr_debug("[%s] warning!\n", __func__);
373 break;
374 }
375 }
376
phydm_cmn_sta_info_update(void * dm_void,u8 macid)377 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
378 {
379 struct dm_struct *dm = (struct dm_struct *)dm_void;
380 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
381 struct ra_sta_info *ra = NULL;
382
383 if (is_sta_active(sta)) {
384 ra = &sta->ra_info;
385 } else {
386 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
387 __func__);
388 return;
389 }
390
391 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
392 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
393
394 /*@[Calculate TX/RX state]*/
395 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
396 ra->txrx_state = TX_STATE;
397 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
398 ra->txrx_state = RX_STATE;
399 else
400 ra->txrx_state = BI_DIRECTION_STATE;
401
402 ra->is_noisy = dm->noisy_decision;
403 }
404
phydm_common_info_self_update(struct dm_struct * dm)405 void phydm_common_info_self_update(struct dm_struct *dm)
406 {
407 u8 sta_cnt = 0, num_active_client = 0;
408 u32 i, one_entry_macid = 0;
409 u32 ma_rx_tp = 0;
410 u32 tp_diff = 0;
411 struct cmn_sta_info *sta;
412 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
413 PADAPTER adapter = (PADAPTER)dm->adapter;
414 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
415
416 sta = dm->phydm_sta_info[0];
417
418 /* STA mode is linked to AP */
419 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
420 dm->bsta_state = true;
421 else
422 dm->bsta_state = false;
423 #endif
424
425 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
426 sta = dm->phydm_sta_info[i];
427 if (is_sta_active(sta)) {
428 sta_cnt++;
429
430 if (sta_cnt == 1)
431 one_entry_macid = i;
432
433 phydm_cmn_sta_info_update(dm, (u8)i);
434 #ifdef PHYDM_BEAMFORMING_SUPPORT
435 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
436 #endif
437
438 ma_rx_tp = sta->rx_moving_average_tp +
439 sta->tx_moving_average_tp;
440
441 PHYDM_DBG(dm, DBG_COMMON_FLOW,
442 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
443
444 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
445 num_active_client++;
446 }
447 }
448
449 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
450 dm->is_linked = (sta_cnt != 0) ? true : false;
451 #endif
452
453 if (sta_cnt == 1) {
454 dm->is_one_entry_only = true;
455 dm->one_entry_macid = one_entry_macid;
456 dm->one_entry_tp = ma_rx_tp;
457
458 dm->tp_active_occur = 0;
459
460 PHYDM_DBG(dm, DBG_COMMON_FLOW,
461 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
462 dm->one_entry_tp, dm->pre_one_entry_tp);
463
464 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
465 dm->pre_one_entry_tp <= 2) {
466 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
467
468 if (tp_diff > dm->tp_active_th)
469 dm->tp_active_occur = 1;
470 }
471 dm->pre_one_entry_tp = dm->one_entry_tp;
472 } else {
473 dm->is_one_entry_only = false;
474 }
475
476 dm->pre_number_linked_client = dm->number_linked_client;
477 dm->pre_number_active_client = dm->number_active_client;
478
479 dm->number_linked_client = sta_cnt;
480 dm->number_active_client = num_active_client;
481
482 /*Traffic load information update*/
483 phydm_traffic_load_decision(dm);
484
485 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
486
487 dm->is_dfs_band = phydm_is_dfs_band(dm);
488 dm->phy_dbg_info.show_phy_sts_cnt = 0;
489
490 /*[Link Status Check]*/
491 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
492 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
493 dm->pre_is_linked = dm->is_linked;
494 }
495
phydm_common_info_self_reset(struct dm_struct * dm)496 void phydm_common_info_self_reset(struct dm_struct *dm)
497 {
498 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
499
500 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
501 dbg_t->num_qry_beacon_pkt = 0;
502
503 dm->rxsc_l = 0xff;
504 dm->rxsc_20 = 0xff;
505 dm->rxsc_40 = 0xff;
506 dm->rxsc_80 = 0xff;
507 }
508
509 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)510 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
511
512 {
513 void *structure = NULL;
514
515 switch (structure_type) {
516 case PHYDM_FALSEALMCNT:
517 structure = &dm->false_alm_cnt;
518 break;
519
520 case PHYDM_CFOTRACK:
521 structure = &dm->dm_cfo_track;
522 break;
523
524 case PHYDM_ADAPTIVITY:
525 structure = &dm->adaptivity;
526 break;
527 #ifdef CONFIG_PHYDM_DFS_MASTER
528 case PHYDM_DFS:
529 structure = &dm->dfs;
530 break;
531 #endif
532 default:
533 break;
534 }
535
536 return structure;
537 }
538
phydm_phy_info_update(struct dm_struct * dm)539 void phydm_phy_info_update(struct dm_struct *dm)
540 {
541 #if (RTL8822B_SUPPORT)
542 if (dm->support_ic_type == ODM_RTL8822B)
543 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
544 #endif
545 }
546
phydm_hw_setting(struct dm_struct * dm)547 void phydm_hw_setting(struct dm_struct *dm)
548 {
549 #if (RTL8821A_SUPPORT)
550 if (dm->support_ic_type & ODM_RTL8821)
551 odm_hw_setting_8821a(dm);
552 #endif
553
554 #if (RTL8814A_SUPPORT)
555 if (dm->support_ic_type & ODM_RTL8814A)
556 phydm_hwsetting_8814a(dm);
557 #endif
558
559 #if (RTL8822B_SUPPORT)
560 if (dm->support_ic_type & ODM_RTL8822B)
561 phydm_hwsetting_8822b(dm);
562 #endif
563
564 #if (RTL8812A_SUPPORT)
565 if (dm->support_ic_type & ODM_RTL8812)
566 phydm_hwsetting_8812a(dm);
567 #endif
568
569 #if (RTL8197F_SUPPORT)
570 if (dm->support_ic_type & ODM_RTL8197F)
571 phydm_hwsetting_8197f(dm);
572 #endif
573
574 #if (RTL8192F_SUPPORT)
575 if (dm->support_ic_type & ODM_RTL8192F)
576 phydm_hwsetting_8192f(dm);
577 #endif
578
579 #if (RTL8822C_SUPPORT)
580 if (dm->support_ic_type & ODM_RTL8822C)
581 phydm_hwsetting_8822c(dm);
582 #endif
583
584 #if (RTL8197G_SUPPORT)
585 if (dm->support_ic_type & ODM_RTL8197G)
586 phydm_hwsetting_8197g(dm);
587 #endif
588
589 #if (RTL8723F_SUPPORT)
590 if (dm->support_ic_type & ODM_RTL8723F)
591 phydm_hwsetting_8723f(dm);
592 #endif
593
594 #if (RTL8821C_SUPPORT)
595 if (dm->support_ic_type & ODM_RTL8821C)
596 phydm_hwsetting_8821c(dm);
597 #endif
598
599 #if (RTL8812F_SUPPORT)
600 if (dm->support_ic_type & ODM_RTL8812F)
601 phydm_hwsetting_8812f(dm);
602 #endif
603
604 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
605 phydm_cck_rx_pathdiv_watchdog(dm);
606 #endif
607 }
608
609 __odm_func__
phydm_chk_bb_rf_pkg_set_valid(struct dm_struct * dm)610 boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
611 {
612 boolean valid = true;
613
614 if (dm->support_ic_type == ODM_RTL8822C) {
615 #if (RTL8822C_SUPPORT)
616 valid = phydm_chk_pkg_set_valid_8822c(dm,
617 RELEASE_VERSION_8822C,
618 RF_RELEASE_VERSION_8822C);
619 #else
620 valid = true; /*@Just for preventing compile warnings*/
621 #endif
622 #if (RTL8812F_SUPPORT)
623 } else if (dm->support_ic_type == ODM_RTL8812F) {
624 valid = phydm_chk_pkg_set_valid_8812f(dm,
625 RELEASE_VERSION_8812F,
626 RF_RELEASE_VERSION_8812F);
627 #endif
628 #if (RTL8197G_SUPPORT)
629 } else if (dm->support_ic_type == ODM_RTL8197G) {
630 valid = phydm_chk_pkg_set_valid_8197g(dm,
631 RELEASE_VERSION_8197G,
632 RF_RELEASE_VERSION_8197G);
633 #endif
634 #if (RTL8812F_SUPPORT)
635 } else if (dm->support_ic_type == ODM_RTL8812F) {
636 valid = phydm_chk_pkg_set_valid_8812f(dm,
637 RELEASE_VERSION_8812F,
638 RF_RELEASE_VERSION_8812F);
639 #endif
640 #if (RTL8198F_SUPPORT)
641 } else if (dm->support_ic_type == ODM_RTL8198F) {
642 valid = phydm_chk_pkg_set_valid_8198f(dm,
643 RELEASE_VERSION_8198F,
644 RF_RELEASE_VERSION_8198F);
645 #endif
646 #if (RTL8814B_SUPPORT)
647 } else if (dm->support_ic_type == ODM_RTL8814B) {
648 valid = phydm_chk_pkg_set_valid_8814b(dm,
649 RELEASE_VERSION_8814B,
650 RF_RELEASE_VERSION_8814B);
651 #endif
652 #if (RTL8723F_SUPPORT)
653 } else if (dm->support_ic_type == ODM_RTL8723F) {
654 valid = phydm_chk_pkg_set_valid_8723f(dm,
655 RELEASE_VERSION_8723F,
656 RF_RELEASE_VERSION_8723F);
657 #endif
658 }
659
660 return valid;
661 }
662
663 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)664 u64 phydm_supportability_init_win(
665 void *dm_void)
666 {
667 struct dm_struct *dm = (struct dm_struct *)dm_void;
668 u64 support_ability = 0;
669
670 switch (dm->support_ic_type) {
671 /*@---------------N Series--------------------*/
672 #if (RTL8188E_SUPPORT)
673 case ODM_RTL8188E:
674 support_ability |=
675 ODM_BB_DIG |
676 ODM_BB_RA_MASK |
677 /*ODM_BB_DYNAMIC_TXPWR |*/
678 ODM_BB_FA_CNT |
679 ODM_BB_RSSI_MONITOR |
680 ODM_BB_CCK_PD |
681 /*ODM_BB_PWR_TRAIN |*/
682 ODM_BB_RATE_ADAPTIVE |
683 ODM_BB_ADAPTIVITY |
684 ODM_BB_CFO_TRACKING |
685 ODM_BB_ENV_MONITOR |
686 ODM_BB_PRIMARY_CCA;
687 break;
688 #endif
689
690 #if (RTL8192E_SUPPORT)
691 case ODM_RTL8192E:
692 support_ability |=
693 ODM_BB_DIG |
694 ODM_BB_RA_MASK |
695 /*ODM_BB_DYNAMIC_TXPWR |*/
696 ODM_BB_FA_CNT |
697 ODM_BB_RSSI_MONITOR |
698 ODM_BB_CCK_PD |
699 /*ODM_BB_PWR_TRAIN |*/
700 ODM_BB_RATE_ADAPTIVE |
701 ODM_BB_ADAPTIVITY |
702 ODM_BB_CFO_TRACKING |
703 ODM_BB_ENV_MONITOR |
704 ODM_BB_PRIMARY_CCA;
705 break;
706 #endif
707
708 #if (RTL8723B_SUPPORT)
709 case ODM_RTL8723B:
710 support_ability |=
711 ODM_BB_DIG |
712 ODM_BB_RA_MASK |
713 /*ODM_BB_DYNAMIC_TXPWR |*/
714 ODM_BB_FA_CNT |
715 ODM_BB_RSSI_MONITOR |
716 ODM_BB_CCK_PD |
717 /*ODM_BB_PWR_TRAIN |*/
718 ODM_BB_RATE_ADAPTIVE |
719 ODM_BB_ADAPTIVITY |
720 ODM_BB_CFO_TRACKING |
721 ODM_BB_ENV_MONITOR |
722 ODM_BB_PRIMARY_CCA;
723 break;
724 #endif
725
726 #if (RTL8703B_SUPPORT)
727 case ODM_RTL8703B:
728 support_ability |=
729 ODM_BB_DIG |
730 ODM_BB_RA_MASK |
731 /*ODM_BB_DYNAMIC_TXPWR |*/
732 ODM_BB_FA_CNT |
733 ODM_BB_RSSI_MONITOR |
734 ODM_BB_CCK_PD |
735 /*ODM_BB_PWR_TRAIN |*/
736 ODM_BB_RATE_ADAPTIVE |
737 ODM_BB_ADAPTIVITY |
738 ODM_BB_CFO_TRACKING |
739 ODM_BB_ENV_MONITOR;
740 break;
741 #endif
742
743 #if (RTL8723D_SUPPORT)
744 case ODM_RTL8723D:
745 support_ability |=
746 ODM_BB_DIG |
747 ODM_BB_RA_MASK |
748 /*ODM_BB_DYNAMIC_TXPWR |*/
749 ODM_BB_FA_CNT |
750 ODM_BB_RSSI_MONITOR |
751 ODM_BB_CCK_PD |
752 ODM_BB_PWR_TRAIN |
753 ODM_BB_RATE_ADAPTIVE |
754 ODM_BB_ADAPTIVITY |
755 ODM_BB_CFO_TRACKING |
756 ODM_BB_ENV_MONITOR;
757 break;
758 #endif
759
760 #if (RTL8710B_SUPPORT)
761 case ODM_RTL8710B:
762 support_ability |=
763 ODM_BB_DIG |
764 ODM_BB_RA_MASK |
765 /*ODM_BB_DYNAMIC_TXPWR |*/
766 ODM_BB_FA_CNT |
767 ODM_BB_RSSI_MONITOR |
768 ODM_BB_CCK_PD |
769 ODM_BB_PWR_TRAIN |
770 ODM_BB_RATE_ADAPTIVE |
771 ODM_BB_ADAPTIVITY |
772 ODM_BB_CFO_TRACKING |
773 ODM_BB_ENV_MONITOR;
774 break;
775 #endif
776
777 #if (RTL8188F_SUPPORT)
778 case ODM_RTL8188F:
779 support_ability |=
780 ODM_BB_DIG |
781 ODM_BB_RA_MASK |
782 /*ODM_BB_DYNAMIC_TXPWR |*/
783 ODM_BB_FA_CNT |
784 ODM_BB_RSSI_MONITOR |
785 ODM_BB_CCK_PD |
786 /*ODM_BB_PWR_TRAIN |*/
787 ODM_BB_RATE_ADAPTIVE |
788 ODM_BB_ADAPTIVITY |
789 ODM_BB_CFO_TRACKING |
790 ODM_BB_ENV_MONITOR;
791 break;
792 #endif
793
794 #if (RTL8192F_SUPPORT)
795 case ODM_RTL8192F:
796 support_ability |=
797 ODM_BB_DIG |
798 ODM_BB_RA_MASK |
799 ODM_BB_FA_CNT |
800 ODM_BB_RSSI_MONITOR |
801 ODM_BB_CCK_PD |
802 ODM_BB_PWR_TRAIN |
803 ODM_BB_RATE_ADAPTIVE |
804 /*ODM_BB_PATH_DIV |*/
805 ODM_BB_ADAPTIVITY |
806 ODM_BB_CFO_TRACKING |
807 ODM_BB_ADAPTIVE_SOML |
808 ODM_BB_ENV_MONITOR;
809 /*ODM_BB_LNA_SAT_CHK |*/
810 /*ODM_BB_PRIMARY_CCA*/
811
812 break;
813 #endif
814
815 /*@---------------AC Series-------------------*/
816
817 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
818 case ODM_RTL8812:
819 case ODM_RTL8821:
820 support_ability |=
821 ODM_BB_DIG |
822 ODM_BB_RA_MASK |
823 ODM_BB_DYNAMIC_TXPWR |
824 ODM_BB_FA_CNT |
825 ODM_BB_RSSI_MONITOR |
826 ODM_BB_CCK_PD |
827 /*ODM_BB_PWR_TRAIN |*/
828 ODM_BB_RATE_ADAPTIVE |
829 ODM_BB_ADAPTIVITY |
830 ODM_BB_CFO_TRACKING |
831 ODM_BB_ENV_MONITOR;
832 break;
833 #endif
834
835 #if (RTL8814A_SUPPORT)
836 case ODM_RTL8814A:
837 support_ability |=
838 ODM_BB_DIG |
839 ODM_BB_RA_MASK |
840 ODM_BB_DYNAMIC_TXPWR |
841 ODM_BB_FA_CNT |
842 ODM_BB_RSSI_MONITOR |
843 ODM_BB_CCK_PD |
844 /*ODM_BB_PWR_TRAIN |*/
845 ODM_BB_RATE_ADAPTIVE |
846 ODM_BB_ADAPTIVITY |
847 ODM_BB_CFO_TRACKING |
848 ODM_BB_ENV_MONITOR;
849 break;
850 #endif
851
852 #if (RTL8822B_SUPPORT)
853 case ODM_RTL8822B:
854 support_ability |=
855 ODM_BB_DIG |
856 ODM_BB_RA_MASK |
857 /*ODM_BB_DYNAMIC_TXPWR |*/
858 ODM_BB_FA_CNT |
859 ODM_BB_RSSI_MONITOR |
860 ODM_BB_CCK_PD |
861 /*ODM_BB_PWR_TRAIN |*/
862 /*ODM_BB_ADAPTIVE_SOML |*/
863 ODM_BB_RATE_ADAPTIVE |
864 /*ODM_BB_PATH_DIV |*/
865 ODM_BB_ADAPTIVITY |
866 ODM_BB_CFO_TRACKING |
867 ODM_BB_ENV_MONITOR;
868 break;
869 #endif
870
871 #if (RTL8821C_SUPPORT)
872 case ODM_RTL8821C:
873 support_ability |=
874 ODM_BB_DIG |
875 ODM_BB_RA_MASK |
876 /*ODM_BB_DYNAMIC_TXPWR |*/
877 ODM_BB_FA_CNT |
878 ODM_BB_RSSI_MONITOR |
879 ODM_BB_CCK_PD |
880 /*ODM_BB_PWR_TRAIN |*/
881 ODM_BB_RATE_ADAPTIVE |
882 ODM_BB_ADAPTIVITY |
883 ODM_BB_CFO_TRACKING |
884 ODM_BB_ENV_MONITOR;
885 break;
886 #endif
887
888 /*@---------------JGR3 Series-------------------*/
889
890 #if (RTL8822C_SUPPORT)
891 case ODM_RTL8822C:
892 support_ability |=
893 ODM_BB_DIG |
894 ODM_BB_RA_MASK |
895 ODM_BB_DYNAMIC_TXPWR |
896 ODM_BB_FA_CNT |
897 ODM_BB_RSSI_MONITOR |
898 ODM_BB_CCK_PD |
899 ODM_BB_RATE_ADAPTIVE |
900 ODM_BB_PATH_DIV |
901 ODM_BB_ADAPTIVITY |
902 ODM_BB_CFO_TRACKING |
903 ODM_BB_ENV_MONITOR;
904 break;
905 #endif
906
907 #if (RTL8814B_SUPPORT)
908 case ODM_RTL8814B:
909 support_ability |=
910 ODM_BB_DIG |
911 ODM_BB_RA_MASK |
912 /*ODM_BB_DYNAMIC_TXPWR |*/
913 ODM_BB_FA_CNT |
914 ODM_BB_RSSI_MONITOR |
915 ODM_BB_CCK_PD |
916 /*ODM_BB_PWR_TRAIN |*/
917 ODM_BB_RATE_ADAPTIVE |
918 ODM_BB_ADAPTIVITY |
919 ODM_BB_CFO_TRACKING;
920 /*ODM_BB_ENV_MONITOR;*/
921 break;
922 #endif
923
924 #if (RTL8723F_SUPPORT)
925 case ODM_RTL8723F:
926 support_ability |=
927 ODM_BB_DIG |
928 ODM_BB_RA_MASK |
929 /* ODM_BB_DYNAMIC_TXPWR |*/
930 ODM_BB_FA_CNT |
931 ODM_BB_RSSI_MONITOR |
932 ODM_BB_CCK_PD |
933 /*ODM_BB_PWR_TRAIN |*/
934 ODM_BB_RATE_ADAPTIVE |
935 ODM_BB_ADAPTIVITY |
936 ODM_BB_CFO_TRACKING |
937 ODM_BB_ENV_MONITOR;
938 break;
939 #endif
940 default:
941 support_ability |=
942 ODM_BB_DIG |
943 ODM_BB_RA_MASK |
944 /*ODM_BB_DYNAMIC_TXPWR |*/
945 ODM_BB_FA_CNT |
946 ODM_BB_RSSI_MONITOR |
947 ODM_BB_CCK_PD |
948 /*ODM_BB_PWR_TRAIN |*/
949 ODM_BB_RATE_ADAPTIVE |
950 ODM_BB_ADAPTIVITY |
951 ODM_BB_CFO_TRACKING |
952 ODM_BB_ENV_MONITOR;
953
954 pr_debug("[Warning] Supportability Init Warning !!!\n");
955 break;
956 }
957
958 return support_ability;
959 }
960 #endif
961
962 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)963 u64 phydm_supportability_init_ce(void *dm_void)
964 {
965 struct dm_struct *dm = (struct dm_struct *)dm_void;
966 u64 support_ability = 0;
967
968 switch (dm->support_ic_type) {
969 /*@---------------N Series--------------------*/
970 #if (RTL8188E_SUPPORT)
971 case ODM_RTL8188E:
972 support_ability |=
973 ODM_BB_DIG |
974 ODM_BB_RA_MASK |
975 /*@ODM_BB_DYNAMIC_TXPWR |*/
976 ODM_BB_FA_CNT |
977 ODM_BB_RSSI_MONITOR |
978 ODM_BB_CCK_PD |
979 /*@ODM_BB_PWR_TRAIN |*/
980 ODM_BB_RATE_ADAPTIVE |
981 ODM_BB_ADAPTIVITY |
982 ODM_BB_CFO_TRACKING |
983 ODM_BB_ENV_MONITOR |
984 ODM_BB_PRIMARY_CCA;
985 break;
986 #endif
987
988 #if (RTL8192E_SUPPORT)
989 case ODM_RTL8192E:
990 support_ability |=
991 ODM_BB_DIG |
992 ODM_BB_RA_MASK |
993 /*@ODM_BB_DYNAMIC_TXPWR |*/
994 ODM_BB_FA_CNT |
995 ODM_BB_RSSI_MONITOR |
996 ODM_BB_CCK_PD |
997 /*@ODM_BB_PWR_TRAIN |*/
998 ODM_BB_RATE_ADAPTIVE |
999 ODM_BB_ADAPTIVITY |
1000 ODM_BB_CFO_TRACKING |
1001 ODM_BB_ENV_MONITOR |
1002 ODM_BB_PRIMARY_CCA;
1003 break;
1004 #endif
1005
1006 #if (RTL8723B_SUPPORT)
1007 case ODM_RTL8723B:
1008 support_ability |=
1009 ODM_BB_DIG |
1010 ODM_BB_RA_MASK |
1011 /*@ODM_BB_DYNAMIC_TXPWR |*/
1012 ODM_BB_FA_CNT |
1013 ODM_BB_RSSI_MONITOR |
1014 ODM_BB_CCK_PD |
1015 /*@ODM_BB_PWR_TRAIN |*/
1016 ODM_BB_RATE_ADAPTIVE |
1017 ODM_BB_ADAPTIVITY |
1018 ODM_BB_CFO_TRACKING |
1019 ODM_BB_ENV_MONITOR |
1020 ODM_BB_PRIMARY_CCA;
1021 break;
1022 #endif
1023
1024 #if (RTL8703B_SUPPORT)
1025 case ODM_RTL8703B:
1026 support_ability |=
1027 ODM_BB_DIG |
1028 ODM_BB_RA_MASK |
1029 /*@ODM_BB_DYNAMIC_TXPWR |*/
1030 ODM_BB_FA_CNT |
1031 ODM_BB_RSSI_MONITOR |
1032 ODM_BB_CCK_PD |
1033 /*@ODM_BB_PWR_TRAIN |*/
1034 ODM_BB_RATE_ADAPTIVE |
1035 ODM_BB_ADAPTIVITY |
1036 ODM_BB_CFO_TRACKING |
1037 ODM_BB_ENV_MONITOR;
1038 break;
1039 #endif
1040
1041 #if (RTL8723D_SUPPORT)
1042 case ODM_RTL8723D:
1043 support_ability |=
1044 ODM_BB_DIG |
1045 ODM_BB_RA_MASK |
1046 /*@ODM_BB_DYNAMIC_TXPWR |*/
1047 ODM_BB_FA_CNT |
1048 ODM_BB_RSSI_MONITOR |
1049 ODM_BB_CCK_PD |
1050 ODM_BB_PWR_TRAIN |
1051 ODM_BB_RATE_ADAPTIVE |
1052 ODM_BB_ADAPTIVITY |
1053 ODM_BB_CFO_TRACKING |
1054 ODM_BB_ENV_MONITOR;
1055 break;
1056 #endif
1057
1058 #if (RTL8710B_SUPPORT)
1059 case ODM_RTL8710B:
1060 support_ability |=
1061 ODM_BB_DIG |
1062 ODM_BB_RA_MASK |
1063 /*@ODM_BB_DYNAMIC_TXPWR |*/
1064 ODM_BB_FA_CNT |
1065 ODM_BB_RSSI_MONITOR |
1066 ODM_BB_CCK_PD |
1067 /*@ODM_BB_PWR_TRAIN |*/
1068 ODM_BB_RATE_ADAPTIVE |
1069 ODM_BB_ADAPTIVITY |
1070 ODM_BB_CFO_TRACKING |
1071 ODM_BB_ENV_MONITOR;
1072 break;
1073 #endif
1074
1075 #if (RTL8188F_SUPPORT)
1076 case ODM_RTL8188F:
1077 support_ability |=
1078 ODM_BB_DIG |
1079 ODM_BB_RA_MASK |
1080 /*@ODM_BB_DYNAMIC_TXPWR |*/
1081 ODM_BB_FA_CNT |
1082 ODM_BB_RSSI_MONITOR |
1083 ODM_BB_CCK_PD |
1084 /*@ODM_BB_PWR_TRAIN |*/
1085 ODM_BB_RATE_ADAPTIVE |
1086 ODM_BB_ADAPTIVITY |
1087 ODM_BB_CFO_TRACKING |
1088 ODM_BB_ENV_MONITOR;
1089 break;
1090 #endif
1091
1092 #if (RTL8192F_SUPPORT)
1093 case ODM_RTL8192F:
1094 support_ability |=
1095 ODM_BB_DIG |
1096 ODM_BB_RA_MASK |
1097 ODM_BB_FA_CNT |
1098 ODM_BB_RSSI_MONITOR |
1099 ODM_BB_CCK_PD |
1100 ODM_BB_PWR_TRAIN |
1101 ODM_BB_RATE_ADAPTIVE |
1102 /*ODM_BB_PATH_DIV |*/
1103 ODM_BB_ADAPTIVITY |
1104 ODM_BB_CFO_TRACKING |
1105 /*@ODM_BB_ADAPTIVE_SOML |*/
1106 ODM_BB_ENV_MONITOR;
1107 /*@ODM_BB_LNA_SAT_CHK |*/
1108 /*@ODM_BB_PRIMARY_CCA*/
1109 break;
1110 #endif
1111 /*@---------------AC Series-------------------*/
1112
1113 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
1114 case ODM_RTL8812:
1115 case ODM_RTL8821:
1116 support_ability |=
1117 ODM_BB_DIG |
1118 ODM_BB_RA_MASK |
1119 /*@ODM_BB_DYNAMIC_TXPWR |*/
1120 ODM_BB_FA_CNT |
1121 ODM_BB_RSSI_MONITOR |
1122 ODM_BB_CCK_PD |
1123 /*@ODM_BB_PWR_TRAIN |*/
1124 ODM_BB_RATE_ADAPTIVE |
1125 ODM_BB_ADAPTIVITY |
1126 ODM_BB_CFO_TRACKING |
1127 ODM_BB_ENV_MONITOR;
1128 break;
1129 #endif
1130
1131 #if (RTL8814A_SUPPORT)
1132 case ODM_RTL8814A:
1133 support_ability |=
1134 ODM_BB_DIG |
1135 ODM_BB_RA_MASK |
1136 /*@ODM_BB_DYNAMIC_TXPWR |*/
1137 ODM_BB_FA_CNT |
1138 ODM_BB_RSSI_MONITOR |
1139 ODM_BB_CCK_PD |
1140 /*@ODM_BB_PWR_TRAIN |*/
1141 ODM_BB_RATE_ADAPTIVE |
1142 ODM_BB_ADAPTIVITY |
1143 ODM_BB_CFO_TRACKING |
1144 ODM_BB_ENV_MONITOR;
1145 break;
1146 #endif
1147
1148 #if (RTL8822B_SUPPORT)
1149 case ODM_RTL8822B:
1150 support_ability |=
1151 ODM_BB_DIG |
1152 ODM_BB_RA_MASK |
1153 ODM_BB_DYNAMIC_TXPWR |
1154 ODM_BB_FA_CNT |
1155 ODM_BB_RSSI_MONITOR |
1156 ODM_BB_CCK_PD |
1157 /*@ODM_BB_PWR_TRAIN |*/
1158 ODM_BB_RATE_ADAPTIVE |
1159 /*ODM_BB_PATH_DIV |*/
1160 ODM_BB_ADAPTIVITY |
1161 ODM_BB_CFO_TRACKING |
1162 ODM_BB_ENV_MONITOR;
1163 break;
1164 #endif
1165
1166 #if (RTL8821C_SUPPORT)
1167 case ODM_RTL8821C:
1168 support_ability |=
1169 ODM_BB_DIG |
1170 ODM_BB_RA_MASK |
1171 ODM_BB_DYNAMIC_TXPWR |
1172 ODM_BB_FA_CNT |
1173 ODM_BB_RSSI_MONITOR |
1174 ODM_BB_CCK_PD |
1175 /*@ODM_BB_PWR_TRAIN |*/
1176 ODM_BB_RATE_ADAPTIVE |
1177 ODM_BB_ADAPTIVITY |
1178 ODM_BB_CFO_TRACKING |
1179 ODM_BB_ENV_MONITOR;
1180 break;
1181 #endif
1182
1183 /*@---------------JGR3 Series-------------------*/
1184
1185 #if (RTL8822C_SUPPORT)
1186 case ODM_RTL8822C:
1187 support_ability |=
1188 ODM_BB_DIG |
1189 ODM_BB_RA_MASK |
1190 ODM_BB_DYNAMIC_TXPWR |
1191 ODM_BB_FA_CNT |
1192 ODM_BB_RSSI_MONITOR |
1193 ODM_BB_CCK_PD |
1194 ODM_BB_RATE_ADAPTIVE |
1195 /* ODM_BB_PATH_DIV | */
1196 ODM_BB_ADAPTIVITY |
1197 ODM_BB_CFO_TRACKING |
1198 ODM_BB_ENV_MONITOR;
1199 break;
1200 #endif
1201
1202 #if (RTL8814B_SUPPORT)
1203 case ODM_RTL8814B:
1204 support_ability |=
1205 ODM_BB_DIG |
1206 ODM_BB_RA_MASK |
1207 /*@ODM_BB_DYNAMIC_TXPWR |*/
1208 ODM_BB_FA_CNT |
1209 ODM_BB_RSSI_MONITOR |
1210 ODM_BB_CCK_PD |
1211 /*@ODM_BB_PWR_TRAIN |*/
1212 /*ODM_BB_RATE_ADAPTIVE |*/
1213 ODM_BB_ADAPTIVITY |
1214 ODM_BB_CFO_TRACKING;
1215 /*ODM_BB_ENV_MONITOR;*/
1216 break;
1217 #endif
1218 #if (RTL8723F_SUPPORT)
1219 case ODM_RTL8723F:
1220 support_ability |=
1221 ODM_BB_DIG |
1222 ODM_BB_RA_MASK |
1223 ODM_BB_DYNAMIC_TXPWR |
1224 ODM_BB_FA_CNT |
1225 ODM_BB_RSSI_MONITOR |
1226 ODM_BB_CCK_PD |
1227 ODM_BB_RATE_ADAPTIVE |
1228 /* ODM_BB_PATH_DIV | */
1229 ODM_BB_ADAPTIVITY |
1230 ODM_BB_CFO_TRACKING |
1231 ODM_BB_ENV_MONITOR;
1232 break;
1233 #endif
1234 default:
1235 support_ability |=
1236 ODM_BB_DIG |
1237 ODM_BB_RA_MASK |
1238 /*@ODM_BB_DYNAMIC_TXPWR |*/
1239 ODM_BB_FA_CNT |
1240 ODM_BB_RSSI_MONITOR |
1241 ODM_BB_CCK_PD |
1242 /*@ODM_BB_PWR_TRAIN |*/
1243 ODM_BB_RATE_ADAPTIVE |
1244 ODM_BB_ADAPTIVITY |
1245 ODM_BB_CFO_TRACKING |
1246 ODM_BB_ENV_MONITOR;
1247
1248 pr_debug("[Warning] Supportability Init Warning !!!\n");
1249 break;
1250 }
1251
1252 return support_ability;
1253 }
1254 #endif
1255
1256 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1257 u64 phydm_supportability_init_ap(
1258 void *dm_void)
1259 {
1260 struct dm_struct *dm = (struct dm_struct *)dm_void;
1261 u64 support_ability = 0;
1262
1263 switch (dm->support_ic_type) {
1264 /*@---------------N Series--------------------*/
1265 #if (RTL8188E_SUPPORT)
1266 case ODM_RTL8188E:
1267 support_ability |=
1268 ODM_BB_DIG |
1269 ODM_BB_RA_MASK |
1270 ODM_BB_FA_CNT |
1271 ODM_BB_RSSI_MONITOR |
1272 ODM_BB_CCK_PD |
1273 /*ODM_BB_PWR_TRAIN |*/
1274 ODM_BB_RATE_ADAPTIVE |
1275 ODM_BB_ADAPTIVITY |
1276 ODM_BB_CFO_TRACKING |
1277 ODM_BB_ENV_MONITOR |
1278 ODM_BB_PRIMARY_CCA;
1279 break;
1280 #endif
1281
1282 #if (RTL8192E_SUPPORT)
1283 case ODM_RTL8192E:
1284 support_ability |=
1285 ODM_BB_DIG |
1286 ODM_BB_RA_MASK |
1287 ODM_BB_FA_CNT |
1288 ODM_BB_RSSI_MONITOR |
1289 ODM_BB_CCK_PD |
1290 /*ODM_BB_PWR_TRAIN |*/
1291 ODM_BB_RATE_ADAPTIVE |
1292 ODM_BB_ADAPTIVITY |
1293 ODM_BB_CFO_TRACKING |
1294 ODM_BB_ENV_MONITOR |
1295 ODM_BB_PRIMARY_CCA;
1296 break;
1297 #endif
1298
1299 #if (RTL8723B_SUPPORT)
1300 case ODM_RTL8723B:
1301 support_ability |=
1302 ODM_BB_DIG |
1303 ODM_BB_RA_MASK |
1304 ODM_BB_FA_CNT |
1305 ODM_BB_RSSI_MONITOR |
1306 ODM_BB_CCK_PD |
1307 /*ODM_BB_PWR_TRAIN |*/
1308 ODM_BB_RATE_ADAPTIVE |
1309 ODM_BB_ADAPTIVITY |
1310 ODM_BB_CFO_TRACKING |
1311 ODM_BB_ENV_MONITOR;
1312 break;
1313 #endif
1314
1315 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1316 case ODM_RTL8198F:
1317 support_ability |=
1318 ODM_BB_DIG |
1319 ODM_BB_RA_MASK |
1320 ODM_BB_FA_CNT |
1321 ODM_BB_RSSI_MONITOR |
1322 ODM_BB_CCK_PD |
1323 /*ODM_BB_PWR_TRAIN |*/
1324 /*ODM_BB_RATE_ADAPTIVE |*/
1325 ODM_BB_ADAPTIVITY |
1326 ODM_BB_CFO_TRACKING;
1327 /*ODM_BB_ADAPTIVE_SOML |*/
1328 /*ODM_BB_ENV_MONITOR |*/
1329 /*ODM_BB_LNA_SAT_CHK |*/
1330 /*ODM_BB_PRIMARY_CCA;*/
1331 break;
1332 case ODM_RTL8197F:
1333 support_ability |=
1334 ODM_BB_DIG |
1335 ODM_BB_RA_MASK |
1336 ODM_BB_FA_CNT |
1337 ODM_BB_RSSI_MONITOR |
1338 ODM_BB_CCK_PD |
1339 /*ODM_BB_PWR_TRAIN |*/
1340 ODM_BB_RATE_ADAPTIVE |
1341 ODM_BB_ADAPTIVITY |
1342 ODM_BB_CFO_TRACKING |
1343 ODM_BB_ADAPTIVE_SOML |
1344 ODM_BB_ENV_MONITOR |
1345 ODM_BB_LNA_SAT_CHK |
1346 ODM_BB_PRIMARY_CCA;
1347 break;
1348 #endif
1349
1350 #if (RTL8192F_SUPPORT)
1351 case ODM_RTL8192F:
1352 support_ability |=
1353 ODM_BB_DIG |
1354 ODM_BB_RA_MASK |
1355 ODM_BB_FA_CNT |
1356 ODM_BB_RSSI_MONITOR |
1357 ODM_BB_CCK_PD |
1358 /*ODM_BB_PWR_TRAIN |*/
1359 ODM_BB_RATE_ADAPTIVE |
1360 ODM_BB_ADAPTIVITY |
1361 /*ODM_BB_CFO_TRACKING |*/
1362 ODM_BB_ADAPTIVE_SOML |
1363 /*ODM_BB_PATH_DIV |*/
1364 ODM_BB_ENV_MONITOR |
1365 /*ODM_BB_LNA_SAT_CHK |*/
1366 /*ODM_BB_PRIMARY_CCA |*/
1367 0;
1368 break;
1369 #endif
1370
1371 /*@---------------AC Series-------------------*/
1372
1373 #if (RTL8881A_SUPPORT)
1374 case ODM_RTL8881A:
1375 support_ability |=
1376 ODM_BB_DIG |
1377 ODM_BB_RA_MASK |
1378 ODM_BB_FA_CNT |
1379 ODM_BB_RSSI_MONITOR |
1380 ODM_BB_CCK_PD |
1381 /*ODM_BB_PWR_TRAIN |*/
1382 ODM_BB_RATE_ADAPTIVE |
1383 ODM_BB_ADAPTIVITY |
1384 ODM_BB_CFO_TRACKING |
1385 ODM_BB_ENV_MONITOR;
1386 break;
1387 #endif
1388
1389 #if (RTL8814A_SUPPORT)
1390 case ODM_RTL8814A:
1391 support_ability |=
1392 ODM_BB_DIG |
1393 ODM_BB_RA_MASK |
1394 ODM_BB_FA_CNT |
1395 ODM_BB_RSSI_MONITOR |
1396 ODM_BB_CCK_PD |
1397 /*ODM_BB_PWR_TRAIN |*/
1398 ODM_BB_RATE_ADAPTIVE |
1399 ODM_BB_ADAPTIVITY |
1400 ODM_BB_CFO_TRACKING |
1401 ODM_BB_ENV_MONITOR;
1402 break;
1403 #endif
1404
1405 #if (RTL8822B_SUPPORT)
1406 case ODM_RTL8822B:
1407 support_ability |=
1408 ODM_BB_DIG |
1409 ODM_BB_RA_MASK |
1410 ODM_BB_FA_CNT |
1411 ODM_BB_RSSI_MONITOR |
1412 ODM_BB_CCK_PD |
1413 /*ODM_BB_PWR_TRAIN |*/
1414 /*ODM_BB_ADAPTIVE_SOML |*/
1415 ODM_BB_RATE_ADAPTIVE |
1416 ODM_BB_ADAPTIVITY |
1417 ODM_BB_CFO_TRACKING |
1418 ODM_BB_ENV_MONITOR;
1419 break;
1420 #endif
1421
1422 #if (RTL8821C_SUPPORT)
1423 case ODM_RTL8821C:
1424 support_ability |=
1425 ODM_BB_DIG |
1426 ODM_BB_RA_MASK |
1427 ODM_BB_FA_CNT |
1428 ODM_BB_RSSI_MONITOR |
1429 ODM_BB_CCK_PD |
1430 /*ODM_BB_PWR_TRAIN |*/
1431 ODM_BB_RATE_ADAPTIVE |
1432 ODM_BB_ADAPTIVITY |
1433 ODM_BB_CFO_TRACKING |
1434 ODM_BB_ENV_MONITOR;
1435
1436 break;
1437 #endif
1438
1439 /*@---------------JGR3 Series-------------------*/
1440
1441 #if (RTL8814B_SUPPORT)
1442 case ODM_RTL8814B:
1443 support_ability |=
1444 ODM_BB_DIG |
1445 ODM_BB_RA_MASK |
1446 ODM_BB_FA_CNT |
1447 ODM_BB_RSSI_MONITOR |
1448 ODM_BB_CCK_PD |
1449 /*ODM_BB_PWR_TRAIN |*/
1450 /*ODM_BB_RATE_ADAPTIVE |*/
1451 ODM_BB_ADAPTIVITY |
1452 ODM_BB_CFO_TRACKING |
1453 ODM_BB_ENV_MONITOR;
1454 break;
1455 #endif
1456
1457 #if (RTL8197G_SUPPORT)
1458 case ODM_RTL8197G:
1459 support_ability |=
1460 ODM_BB_DIG |
1461 ODM_BB_RA_MASK |
1462 ODM_BB_FA_CNT |
1463 ODM_BB_RSSI_MONITOR |
1464 ODM_BB_CCK_PD |
1465 /*ODM_BB_PWR_TRAIN |*/
1466 ODM_BB_RATE_ADAPTIVE |
1467 ODM_BB_ADAPTIVITY |
1468 ODM_BB_CFO_TRACKING |
1469 ODM_BB_ENV_MONITOR;
1470 break;
1471 #endif
1472
1473 #if (RTL8812F_SUPPORT)
1474 case ODM_RTL8812F:
1475 support_ability |=
1476 ODM_BB_DIG |
1477 ODM_BB_RA_MASK |
1478 ODM_BB_DYNAMIC_TXPWR |
1479 ODM_BB_FA_CNT |
1480 ODM_BB_RSSI_MONITOR |
1481 /*ODM_BB_CCK_PD |*/
1482 /*ODM_BB_PWR_TRAIN |*/
1483 ODM_BB_RATE_ADAPTIVE |
1484 ODM_BB_ADAPTIVITY |
1485 ODM_BB_CFO_TRACKING |
1486 ODM_BB_ENV_MONITOR;
1487 break;
1488 #endif
1489
1490 #if (RTL8723F_SUPPORT)
1491 case ODM_RTL8723F:
1492 support_ability |=
1493 ODM_BB_DIG |
1494 ODM_BB_RA_MASK |
1495 ODM_BB_FA_CNT |
1496 ODM_BB_RSSI_MONITOR |
1497 ODM_BB_CCK_PD |
1498 /*ODM_BB_PWR_TRAIN |*/
1499 ODM_BB_RATE_ADAPTIVE |
1500 ODM_BB_ADAPTIVITY |
1501 ODM_BB_CFO_TRACKING |
1502 ODM_BB_ENV_MONITOR;
1503 break;
1504 #endif
1505 default:
1506 support_ability |=
1507 ODM_BB_DIG |
1508 ODM_BB_RA_MASK |
1509 ODM_BB_FA_CNT |
1510 ODM_BB_RSSI_MONITOR |
1511 ODM_BB_CCK_PD |
1512 /*ODM_BB_PWR_TRAIN |*/
1513 ODM_BB_RATE_ADAPTIVE |
1514 ODM_BB_ADAPTIVITY |
1515 ODM_BB_CFO_TRACKING |
1516 ODM_BB_ENV_MONITOR;
1517
1518 pr_debug("[Warning] Supportability Init Warning !!!\n");
1519 break;
1520 }
1521
1522 return support_ability;
1523 }
1524 #endif
1525
1526 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1527 u64 phydm_supportability_init_iot(
1528 void *dm_void)
1529 {
1530 struct dm_struct *dm = (struct dm_struct *)dm_void;
1531 u64 support_ability = 0;
1532
1533 switch (dm->support_ic_type) {
1534 #if (RTL8710B_SUPPORT)
1535 case ODM_RTL8710B:
1536 support_ability |=
1537 ODM_BB_DIG |
1538 ODM_BB_RA_MASK |
1539 /*ODM_BB_DYNAMIC_TXPWR |*/
1540 ODM_BB_FA_CNT |
1541 ODM_BB_RSSI_MONITOR |
1542 ODM_BB_CCK_PD |
1543 /*ODM_BB_PWR_TRAIN |*/
1544 ODM_BB_RATE_ADAPTIVE |
1545 ODM_BB_CFO_TRACKING |
1546 ODM_BB_ENV_MONITOR;
1547 break;
1548 #endif
1549
1550 #if (RTL8195A_SUPPORT)
1551 case ODM_RTL8195A:
1552 support_ability |=
1553 ODM_BB_DIG |
1554 ODM_BB_RA_MASK |
1555 /*ODM_BB_DYNAMIC_TXPWR |*/
1556 ODM_BB_FA_CNT |
1557 ODM_BB_RSSI_MONITOR |
1558 ODM_BB_CCK_PD |
1559 /*ODM_BB_PWR_TRAIN |*/
1560 ODM_BB_RATE_ADAPTIVE |
1561 ODM_BB_CFO_TRACKING |
1562 ODM_BB_ENV_MONITOR;
1563 break;
1564 #endif
1565
1566 #if (RTL8195B_SUPPORT)
1567 case ODM_RTL8195B:
1568 support_ability |=
1569 ODM_BB_DIG |
1570 ODM_BB_RA_MASK |
1571 /*ODM_BB_DYNAMIC_TXPWR |*/
1572 ODM_BB_FA_CNT |
1573 ODM_BB_RSSI_MONITOR |
1574 ODM_BB_CCK_PD |
1575 /*ODM_BB_PWR_TRAIN |*/
1576 ODM_BB_RATE_ADAPTIVE |
1577 ODM_BB_ADAPTIVITY |
1578 ODM_BB_CFO_TRACKING |
1579 ODM_BB_ENV_MONITOR;
1580 break;
1581 #endif
1582
1583 #if (RTL8721D_SUPPORT)
1584 case ODM_RTL8721D:
1585 support_ability |=
1586 ODM_BB_DIG |
1587 ODM_BB_RA_MASK |
1588 /*ODM_BB_DYNAMIC_TXPWR |*/
1589 ODM_BB_FA_CNT |
1590 ODM_BB_RSSI_MONITOR |
1591 ODM_BB_CCK_PD |
1592 /*ODM_BB_PWR_TRAIN |*/
1593 ODM_BB_RATE_ADAPTIVE |
1594 ODM_BB_ADAPTIVITY |
1595 ODM_BB_CFO_TRACKING |
1596 ODM_BB_ENV_MONITOR;
1597 break;
1598 #endif
1599
1600 #if (RTL8710C_SUPPORT)
1601 case ODM_RTL8710C:
1602 support_ability |=
1603 ODM_BB_DIG |
1604 ODM_BB_RA_MASK |
1605 /*ODM_BB_DYNAMIC_TXPWR |*/
1606 ODM_BB_FA_CNT |
1607 ODM_BB_RSSI_MONITOR |
1608 ODM_BB_CCK_PD |
1609 /*ODM_BB_PWR_TRAIN |*/
1610 ODM_BB_RATE_ADAPTIVE |
1611 ODM_BB_ADAPTIVITY |
1612 ODM_BB_CFO_TRACKING |
1613 ODM_BB_ENV_MONITOR;
1614 break;
1615 #endif
1616 default:
1617 support_ability |=
1618 ODM_BB_DIG |
1619 ODM_BB_RA_MASK |
1620 /*ODM_BB_DYNAMIC_TXPWR |*/
1621 ODM_BB_FA_CNT |
1622 ODM_BB_RSSI_MONITOR |
1623 ODM_BB_CCK_PD |
1624 /*ODM_BB_PWR_TRAIN |*/
1625 ODM_BB_RATE_ADAPTIVE |
1626 ODM_BB_CFO_TRACKING |
1627 ODM_BB_ENV_MONITOR;
1628
1629 pr_debug("[Warning] Supportability Init Warning !!!\n");
1630 break;
1631 }
1632
1633 return support_ability;
1634 }
1635 #endif
1636
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1637 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1638 enum phydm_offload_ability offload_ability)
1639 {
1640 switch (offload_ability) {
1641 case PHYDM_PHY_PARAM_OFFLOAD:
1642 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1643 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1644 break;
1645
1646 case PHYDM_RF_IQK_OFFLOAD:
1647 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1648 break;
1649
1650 case PHYDM_RF_DPK_OFFLOAD:
1651 dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
1652 break;
1653
1654 default:
1655 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1656 break;
1657 }
1658
1659 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1660 dm->fw_offload_ability);
1661 }
1662
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1663 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1664 enum phydm_offload_ability offload_ability)
1665 {
1666 switch (offload_ability) {
1667 case PHYDM_PHY_PARAM_OFFLOAD:
1668 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1669 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1670 break;
1671
1672 case PHYDM_RF_IQK_OFFLOAD:
1673 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1674 break;
1675
1676 case PHYDM_RF_DPK_OFFLOAD:
1677 dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
1678 break;
1679
1680 default:
1681 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1682 break;
1683 }
1684
1685 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1686 dm->fw_offload_ability);
1687 }
1688
phydm_supportability_init(void * dm_void)1689 void phydm_supportability_init(void *dm_void)
1690 {
1691 struct dm_struct *dm = (struct dm_struct *)dm_void;
1692 u64 support_ability;
1693
1694 if (dm->manual_supportability &&
1695 *dm->manual_supportability != 0xffffffff) {
1696 support_ability = *dm->manual_supportability;
1697 } else if (*dm->mp_mode) {
1698 support_ability = 0;
1699 } else {
1700 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1701 support_ability = phydm_supportability_init_win(dm);
1702 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1703 support_ability = phydm_supportability_init_ap(dm);
1704 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1705 support_ability = phydm_supportability_init_ce(dm);
1706 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1707 support_ability = phydm_supportability_init_iot(dm);
1708 #endif
1709
1710 /*@[Config Antenna Diversity]*/
1711 if (IS_FUNC_EN(dm->enable_antdiv))
1712 support_ability |= ODM_BB_ANT_DIV;
1713
1714 /*@[Config TXpath Diversity]*/
1715 if (IS_FUNC_EN(dm->enable_pathdiv))
1716 support_ability |= ODM_BB_PATH_DIV;
1717
1718 /*@[Config Adaptive SOML]*/
1719 if (IS_FUNC_EN(dm->en_adap_soml))
1720 support_ability |= ODM_BB_ADAPTIVE_SOML;
1721
1722 /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
1723 if(IS_FUNC_EN(&dm->en_tssi_mode) &&
1724 (dm->support_ic_type & ODM_RTL8822C))
1725 support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
1726 /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
1727 if(IS_FUNC_EN(&dm->en_tssi_mode) &&
1728 (dm->support_ic_type & ODM_RTL8723F))
1729 support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
1730 }
1731 dm->support_ability = support_ability;
1732 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1733 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1734 }
1735
phydm_rfe_init(void * dm_void)1736 void phydm_rfe_init(void *dm_void)
1737 {
1738 struct dm_struct *dm = (struct dm_struct *)dm_void;
1739
1740 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1741 #if (RTL8822B_SUPPORT == 1)
1742 if (dm->support_ic_type == ODM_RTL8822B)
1743 phydm_rfe_8822b_init(dm);
1744 #endif
1745 }
1746
1747 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
phydm_tx_collsion_th_init(void * dm_void)1748 void phydm_tx_collsion_th_init(void *dm_void)
1749 {
1750
1751 struct dm_struct *dm = (struct dm_struct *)dm_void;
1752
1753 #if (RTL8197G_SUPPORT)
1754 if (dm->support_ic_type & ODM_RTL8197G)
1755 phydm_tx_collsion_th_init_8197g(dm);
1756 #endif
1757
1758 #if (RTL8812F_SUPPORT)
1759 if (dm->support_ic_type & ODM_RTL8812F)
1760 phydm_tx_collsion_th_init_8812f(dm);
1761 #endif
1762
1763 }
1764
phydm_tx_collsion_th_set(void * dm_void,u8 val_r2t,u8 val_t2r)1765 void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
1766 {
1767 struct dm_struct *dm = (struct dm_struct *)dm_void;
1768
1769 #if (RTL8197G_SUPPORT)
1770 if (dm->support_ic_type & ODM_RTL8197G)
1771 phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
1772 #endif
1773
1774 #if (RTL8812F_SUPPORT)
1775 if (dm->support_ic_type & ODM_RTL8812F)
1776 phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
1777 #endif
1778
1779 }
1780 #endif
1781
phydm_dm_early_init(struct dm_struct * dm)1782 void phydm_dm_early_init(struct dm_struct *dm)
1783 {
1784 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1785 phydm_init_debug_setting(dm);
1786 #endif
1787 }
1788
odm_dm_init(struct dm_struct * dm)1789 enum phydm_init_result odm_dm_init(struct dm_struct *dm)
1790 {
1791 enum phydm_init_result result = PHYDM_INIT_SUCCESS;
1792
1793 if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
1794 pr_debug("[Warning][%s] Init fail\n", __func__);
1795 return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
1796 }
1797
1798 halrf_init(dm);
1799 phydm_supportability_init(dm);
1800 phydm_pause_func_init(dm);
1801 phydm_rfe_init(dm);
1802 phydm_common_info_self_init(dm);
1803 phydm_rx_phy_status_init(dm);
1804 #ifdef PHYDM_AUTO_DEGBUG
1805 phydm_auto_dbg_engine_init(dm);
1806 #endif
1807 phydm_dig_init(dm);
1808 #ifdef PHYDM_SUPPORT_CCKPD
1809 #ifdef PHYDM_DCC_ENHANCE
1810 phydm_dig_cckpd_coex_init(dm);
1811 #endif
1812 phydm_cck_pd_init(dm);
1813 #endif
1814 phydm_env_monitor_init(dm);
1815 phydm_adaptivity_init(dm);
1816 phydm_ra_info_init(dm);
1817 phydm_rssi_monitor_init(dm);
1818 phydm_cfo_tracking_init(dm);
1819 phydm_rf_init(dm);
1820 phydm_dc_cancellation(dm);
1821 #ifdef PHYDM_TXA_CALIBRATION
1822 phydm_txcurrentcalibration(dm);
1823 phydm_get_pa_bias_offset(dm);
1824 #endif
1825 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1826 odm_antenna_diversity_init(dm);
1827 #endif
1828 #ifdef CONFIG_ADAPTIVE_SOML
1829 phydm_adaptive_soml_init(dm);
1830 #endif
1831 #ifdef CONFIG_PATH_DIVERSITY
1832 phydm_tx_path_diversity_init(dm);
1833 #endif
1834 #ifdef CONFIG_DYNAMIC_TX_TWR
1835 phydm_dynamic_tx_power_init(dm);
1836 #endif
1837 #if (PHYDM_LA_MODE_SUPPORT)
1838 phydm_la_init(dm);
1839 #endif
1840
1841 #ifdef PHYDM_BEAMFORMING_VERSION1
1842 phydm_beamforming_init(dm);
1843 #endif
1844
1845 #if (RTL8188E_SUPPORT)
1846 odm_ra_info_init_all(dm);
1847 #endif
1848 #ifdef PHYDM_PRIMARY_CCA
1849 phydm_primary_cca_init(dm);
1850 #endif
1851 #ifdef CONFIG_PSD_TOOL
1852 phydm_psd_init(dm);
1853 #endif
1854
1855 #ifdef CONFIG_SMART_ANTENNA
1856 phydm_smt_ant_init(dm);
1857 #endif
1858 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1859 phydm_lna_sat_check_init(dm);
1860 #endif
1861 #ifdef CONFIG_MCC_DM
1862 phydm_mcc_init(dm);
1863 #endif
1864
1865 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1866 phydm_cck_rx_pathdiv_init(dm);
1867 #endif
1868
1869 #ifdef CONFIG_MU_RSOML
1870 phydm_mu_rsoml_init(dm);
1871 #endif
1872
1873 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
1874 phydm_tx_collsion_th_init(dm);
1875 #endif
1876
1877 return result;
1878 }
1879
odm_dm_reset(struct dm_struct * dm)1880 void odm_dm_reset(struct dm_struct *dm)
1881 {
1882 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1883 odm_ant_div_reset(dm);
1884 #endif
1885 phydm_set_edcca_threshold_api(dm);
1886 }
1887
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1888 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1889 char *output, u32 *_out_len)
1890 {
1891 struct dm_struct *dm = (struct dm_struct *)dm_void;
1892 u32 dm_value[10] = {0};
1893 u64 pre_support_ability, one = 1;
1894 u64 comp = 0;
1895 u32 used = *_used;
1896 u32 out_len = *_out_len;
1897 u8 i;
1898
1899 for (i = 0; i < 5; i++) {
1900 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1901 }
1902
1903 pre_support_ability = dm->support_ability;
1904 comp = dm->support_ability;
1905
1906 PDM_SNPF(out_len, used, output + used, out_len - used,
1907 "\n================================\n");
1908
1909 if (dm_value[0] == 100) {
1910 PDM_SNPF(out_len, used, output + used, out_len - used,
1911 "[Supportability] PhyDM Selection\n");
1912 PDM_SNPF(out_len, used, output + used, out_len - used,
1913 "================================\n");
1914 PDM_SNPF(out_len, used, output + used, out_len - used,
1915 "00. (( %s ))DIG\n",
1916 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1917 PDM_SNPF(out_len, used, output + used, out_len - used,
1918 "01. (( %s ))RA_MASK\n",
1919 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1920 PDM_SNPF(out_len, used, output + used, out_len - used,
1921 "02. (( %s ))DYN_TXPWR\n",
1922 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1923 PDM_SNPF(out_len, used, output + used, out_len - used,
1924 "03. (( %s ))FA_CNT\n",
1925 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1926 PDM_SNPF(out_len, used, output + used, out_len - used,
1927 "04. (( %s ))RSSI_MNTR\n",
1928 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1929 PDM_SNPF(out_len, used, output + used, out_len - used,
1930 "05. (( %s ))CCK_PD\n",
1931 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1932 PDM_SNPF(out_len, used, output + used, out_len - used,
1933 "06. (( %s ))ANT_DIV\n",
1934 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1935 PDM_SNPF(out_len, used, output + used, out_len - used,
1936 "07. (( %s ))SMT_ANT\n",
1937 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1938 PDM_SNPF(out_len, used, output + used, out_len - used,
1939 "08. (( %s ))PWR_TRAIN\n",
1940 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1941 PDM_SNPF(out_len, used, output + used, out_len - used,
1942 "09. (( %s ))RA\n",
1943 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1944 PDM_SNPF(out_len, used, output + used, out_len - used,
1945 "10. (( %s ))PATH_DIV\n",
1946 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1947 PDM_SNPF(out_len, used, output + used, out_len - used,
1948 "11. (( %s ))DFS\n",
1949 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1950 PDM_SNPF(out_len, used, output + used, out_len - used,
1951 "12. (( %s ))DYN_ARFR\n",
1952 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1953 PDM_SNPF(out_len, used, output + used, out_len - used,
1954 "13. (( %s ))ADAPTIVITY\n",
1955 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1956 PDM_SNPF(out_len, used, output + used, out_len - used,
1957 "14. (( %s ))CFO_TRACK\n",
1958 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1959 PDM_SNPF(out_len, used, output + used, out_len - used,
1960 "15. (( %s ))ENV_MONITOR\n",
1961 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1962 PDM_SNPF(out_len, used, output + used, out_len - used,
1963 "16. (( %s ))PRI_CCA\n",
1964 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1965 PDM_SNPF(out_len, used, output + used, out_len - used,
1966 "17. (( %s ))ADPTV_SOML\n",
1967 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1968 PDM_SNPF(out_len, used, output + used, out_len - used,
1969 "18. (( %s ))LNA_SAT_CHK\n",
1970 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1971 PDM_SNPF(out_len, used, output + used, out_len - used,
1972 "================================\n");
1973 PDM_SNPF(out_len, used, output + used, out_len - used,
1974 "[Supportability] PhyDM offload ability\n");
1975 PDM_SNPF(out_len, used, output + used, out_len - used,
1976 "================================\n");
1977
1978 PDM_SNPF(out_len, used, output + used, out_len - used,
1979 "00. (( %s ))PHY PARAM OFFLOAD\n",
1980 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1981 ("V") : (".")));
1982 PDM_SNPF(out_len, used, output + used, out_len - used,
1983 "01. (( %s ))RF IQK OFFLOAD\n",
1984 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1985 ("V") : (".")));
1986 PDM_SNPF(out_len, used, output + used, out_len - used,
1987 "================================\n");
1988
1989 } else if (dm_value[0] == 101) {
1990 dm->support_ability = 0;
1991 PDM_SNPF(out_len, used, output + used, out_len - used,
1992 "Disable all support_ability components\n");
1993 } else {
1994 if (dm_value[1] == 1) { /* @enable */
1995 dm->support_ability |= (one << dm_value[0]);
1996 } else if (dm_value[1] == 2) {/* @disable */
1997 dm->support_ability &= ~(one << dm_value[0]);
1998 } else {
1999 PDM_SNPF(out_len, used, output + used, out_len - used,
2000 "[Warning!!!] 1:enable, 2:disable\n");
2001 }
2002 }
2003 PDM_SNPF(out_len, used, output + used, out_len - used,
2004 "pre-supportability = 0x%llx\n", pre_support_ability);
2005 PDM_SNPF(out_len, used, output + used, out_len - used,
2006 "Cur-supportability = 0x%llx\n", dm->support_ability);
2007 PDM_SNPF(out_len, used, output + used, out_len - used,
2008 "================================\n");
2009
2010 *_used = used;
2011 *_out_len = out_len;
2012 }
2013
phydm_watchdog_lps_32k(struct dm_struct * dm)2014 void phydm_watchdog_lps_32k(struct dm_struct *dm)
2015 {
2016 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2017
2018 phydm_common_info_self_update(dm);
2019 phydm_rssi_monitor_check(dm);
2020 phydm_dig_lps_32k(dm);
2021 phydm_common_info_self_reset(dm);
2022 }
2023
phydm_watchdog_lps(struct dm_struct * dm)2024 void phydm_watchdog_lps(struct dm_struct *dm)
2025 {
2026 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
2027 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2028
2029 phydm_common_info_self_update(dm);
2030 phydm_rssi_monitor_check(dm);
2031 phydm_basic_dbg_message(dm);
2032 phydm_receiver_blocking(dm);
2033 phydm_false_alarm_counter_statistics(dm);
2034 phydm_dig_by_rssi_lps(dm);
2035 #ifdef PHYDM_SUPPORT_CCKPD
2036 phydm_cck_pd_th(dm);
2037 #endif
2038 phydm_adaptivity(dm);
2039 #ifdef CONFIG_BW_INDICATION
2040 phydm_dyn_bw_indication(dm);
2041 #endif
2042 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
2043 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2044 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
2045 odm_antenna_diversity(dm);
2046 #endif
2047 #endif
2048 phydm_common_info_self_reset(dm);
2049 #endif
2050 }
2051
phydm_watchdog_mp(struct dm_struct * dm)2052 void phydm_watchdog_mp(struct dm_struct *dm)
2053 {
2054 }
2055
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)2056 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
2057 {
2058 struct dm_struct *dm = (struct dm_struct *)dm_void;
2059
2060 if (pause_type == PHYDM_PAUSE) {
2061 dm->disable_phydm_watchdog = 1;
2062 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
2063 } else {
2064 dm->disable_phydm_watchdog = 0;
2065 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
2066 }
2067 }
2068
phydm_pause_func_init(void * dm_void)2069 void phydm_pause_func_init(void *dm_void)
2070 {
2071 struct dm_struct *dm = (struct dm_struct *)dm_void;
2072
2073 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
2074 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2075 dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
2076 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2077 dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
2078 dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
2079 }
2080
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)2081 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
2082 enum phydm_pause_type pause_type,
2083 enum phydm_pause_level pause_lv, u8 val_lehgth,
2084 u32 *val_buf)
2085 {
2086 struct dm_struct *dm = (struct dm_struct *)dm_void;
2087 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
2088 s8 *pause_lv_pre = &dm->s8_dummy;
2089 u32 *bkp_val = &dm->u32_dummy;
2090 u32 ori_val[5] = {0};
2091 u64 pause_func_bitmap = (u64)BIT(pause_func);
2092 u8 i = 0;
2093 u8 en_2rcca = 0;
2094 u8 en_bw40m = 0;
2095 u8 pause_result = PAUSE_FAIL;
2096
2097 PHYDM_DBG(dm, ODM_COMP_API, "\n");
2098 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
2099 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2100 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2101 pause_lv, val_lehgth);
2102
2103 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
2104 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
2105 return PAUSE_FAIL;
2106 }
2107
2108 if (pause_func == F00_DIG) {
2109 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
2110
2111 if (val_lehgth != 1) {
2112 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2113 return PAUSE_FAIL;
2114 }
2115
2116 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
2117 pause_lv_pre = &dm->pause_lv_table.lv_dig;
2118 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
2119 /*@function pointer hook*/
2120 func_t->pause_phydm_handler = phydm_set_dig_val;
2121
2122 #ifdef PHYDM_SUPPORT_CCKPD
2123 } else if (pause_func == F05_CCK_PD) {
2124 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
2125
2126 if (val_lehgth != 1) {
2127 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2128 return PAUSE_FAIL;
2129 }
2130
2131 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
2132 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
2133 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
2134 /*@function pointer hook*/
2135 func_t->pause_phydm_handler = phydm_set_cckpd_val;
2136 #endif
2137
2138 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2139 } else if (pause_func == F06_ANT_DIV) {
2140 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
2141
2142 if (val_lehgth != 1) {
2143 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2144 return PAUSE_FAIL;
2145 }
2146 /*@default antenna*/
2147 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
2148 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
2149 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
2150 /*@function pointer hook*/
2151 func_t->pause_phydm_handler = phydm_set_antdiv_val;
2152
2153 #endif
2154 #ifdef PHYDM_SUPPORT_ADAPTIVITY
2155 } else if (pause_func == F13_ADPTVTY) {
2156 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
2157
2158 if (val_lehgth != 2) {
2159 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
2160 return PAUSE_FAIL;
2161 }
2162
2163 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
2164 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
2165 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
2166 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
2167 /*@function pointer hook*/
2168 func_t->pause_phydm_handler = phydm_set_edcca_val;
2169
2170 #endif
2171 #ifdef CONFIG_ADAPTIVE_SOML
2172 } else if (pause_func == F17_ADPTV_SOML) {
2173 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
2174
2175 if (val_lehgth != 1) {
2176 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2177 return PAUSE_FAIL;
2178 }
2179 /*SOML_ON/OFF*/
2180 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
2181
2182 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
2183 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
2184 /*@function pointer hook*/
2185 func_t->pause_phydm_handler = phydm_set_adsl_val;
2186
2187 #endif
2188 } else {
2189 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
2190 return PAUSE_FAIL;
2191 }
2192
2193 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
2194 pause_lv, *pause_lv_pre);
2195
2196 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
2197 if (pause_lv <= *pause_lv_pre) {
2198 PHYDM_DBG(dm, ODM_COMP_API,
2199 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
2200 return PAUSE_FAIL;
2201 }
2202
2203 if (!(dm->pause_ability & pause_func_bitmap)) {
2204 for (i = 0; i < val_lehgth; i++)
2205 bkp_val[i] = ori_val[i];
2206 }
2207
2208 dm->pause_ability |= pause_func_bitmap;
2209 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2210 dm->pause_ability);
2211
2212 if (pause_type == PHYDM_PAUSE) {
2213 for (i = 0; i < val_lehgth; i++)
2214 PHYDM_DBG(dm, ODM_COMP_API,
2215 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
2216 i, val_buf[i], bkp_val[i]);
2217 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
2218 } else {
2219 for (i = 0; i < val_lehgth; i++)
2220 PHYDM_DBG(dm, ODM_COMP_API,
2221 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
2222 i, bkp_val[i]);
2223 }
2224
2225 *pause_lv_pre = pause_lv;
2226 pause_result = PAUSE_SUCCESS;
2227
2228 } else if (pause_type == PHYDM_RESUME) {
2229 if (pause_lv < *pause_lv_pre) {
2230 PHYDM_DBG(dm, ODM_COMP_API,
2231 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2232 return PAUSE_FAIL;
2233 }
2234
2235 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2236 PHYDM_DBG(dm, ODM_COMP_API,
2237 "[RESUME] No Need to Revert\n");
2238 return PAUSE_SUCCESS;
2239 }
2240
2241 dm->pause_ability &= ~pause_func_bitmap;
2242 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2243 dm->pause_ability);
2244
2245 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2246
2247 for (i = 0; i < val_lehgth; i++) {
2248 PHYDM_DBG(dm, ODM_COMP_API,
2249 "[RESUME] val_idx[%d]={0x%x}\n", i,
2250 bkp_val[i]);
2251 }
2252
2253 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2254
2255 pause_result = PAUSE_SUCCESS;
2256 } else {
2257 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2258 pause_result = PAUSE_FAIL;
2259 }
2260 return pause_result;
2261 }
2262
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2263 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2264 char *output, u32 *_out_len)
2265 {
2266 struct dm_struct *dm = (struct dm_struct *)dm_void;
2267 char help[] = "-h";
2268 u32 var1[10] = {0};
2269 u32 used = *_used;
2270 u32 out_len = *_out_len;
2271 u32 i;
2272 u8 length = 0;
2273 u32 buf[5] = {0};
2274 u8 set_result = 0;
2275 enum phydm_func_idx func = 0;
2276 enum phydm_pause_type type = 0;
2277 enum phydm_pause_level lv = 0;
2278
2279 if ((strcmp(input[1], help) == 0)) {
2280 PDM_SNPF(out_len, used, output + used, out_len - used,
2281 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2282
2283 goto out;
2284 }
2285
2286 for (i = 0; i < 10; i++) {
2287 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2288 }
2289
2290 func = (enum phydm_func_idx)var1[0];
2291 type = (enum phydm_pause_type)var1[1];
2292 lv = (enum phydm_pause_level)var1[2];
2293
2294 for (i = 0; i < 5; i++)
2295 buf[i] = var1[3 + i];
2296
2297 if (func == F00_DIG) {
2298 PDM_SNPF(out_len, used, output + used, out_len - used,
2299 "[DIG]\n");
2300 length = 1;
2301
2302 } else if (func == F05_CCK_PD) {
2303 PDM_SNPF(out_len, used, output + used, out_len - used,
2304 "[CCK_PD]\n");
2305 length = 1;
2306 } else if (func == F06_ANT_DIV) {
2307 PDM_SNPF(out_len, used, output + used, out_len - used,
2308 "[Ant_Div]\n");
2309 length = 1;
2310 } else if (func == F13_ADPTVTY) {
2311 PDM_SNPF(out_len, used, output + used, out_len - used,
2312 "[Adaptivity]\n");
2313 length = 2;
2314 } else if (func == F17_ADPTV_SOML) {
2315 PDM_SNPF(out_len, used, output + used, out_len - used,
2316 "[ADSL]\n");
2317 length = 1;
2318 } else {
2319 PDM_SNPF(out_len, used, output + used, out_len - used,
2320 "[Set Function Error]\n");
2321 length = 0;
2322 }
2323
2324 if (length != 0) {
2325 PDM_SNPF(out_len, used, output + used, out_len - used,
2326 "{%s, lv=%d} val = %d, %d}\n",
2327 ((type == PHYDM_PAUSE) ? "Pause" :
2328 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2329 lv, var1[3], var1[4]);
2330
2331 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2332 }
2333
2334 PDM_SNPF(out_len, used, output + used, out_len - used,
2335 "set_result = %d\n", set_result);
2336
2337 out:
2338 *_used = used;
2339 *_out_len = out_len;
2340 }
2341
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2342 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2343 enum phydm_pause_type pause_type, u8 rssi)
2344 {
2345 u32 igi_val = rssi + 10;
2346 u32 th_buf[2];
2347
2348 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2349 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2350 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2351 rssi);
2352
2353 if (pause_type == PHYDM_RESUME) {
2354 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2355 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2356
2357 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2358 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2359 } else {
2360 odm_write_dig(dm, (u8)igi_val);
2361 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2362 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2363
2364 th_buf[0] = 0xff;
2365 th_buf[1] = 0xff;
2366
2367 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2368 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2369 }
2370 }
2371
phydm_stop_dm_watchdog_check(void * dm_void)2372 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2373 {
2374 struct dm_struct *dm = (struct dm_struct *)dm_void;
2375
2376 if (dm->disable_phydm_watchdog == 1) {
2377 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2378 return true;
2379 } else {
2380 return false;
2381 }
2382 }
2383
phydm_watchdog(struct dm_struct * dm)2384 void phydm_watchdog(struct dm_struct *dm)
2385 {
2386 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2387
2388 phydm_common_info_self_update(dm);
2389 phydm_phy_info_update(dm);
2390 phydm_rssi_monitor_check(dm);
2391 phydm_basic_dbg_message(dm);
2392 phydm_dm_summary(dm, FIRST_MACID);
2393 #ifdef PHYDM_AUTO_DEGBUG
2394 phydm_auto_dbg_engine(dm);
2395 #endif
2396 phydm_receiver_blocking(dm);
2397
2398 if (phydm_stop_dm_watchdog_check(dm) == true)
2399 return;
2400
2401 phydm_hw_setting(dm);
2402
2403 phydm_env_mntr_result_watchdog(dm);
2404
2405 #ifdef PHYDM_TDMA_DIG_SUPPORT
2406 if (dm->original_dig_restore == 0) {
2407 phydm_tdma_dig_timer_check(dm);
2408 } else
2409 #endif
2410 {
2411 phydm_false_alarm_counter_statistics(dm);
2412 #if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
2413 if (dm->support_ic_type & (ODM_IC_11N_SERIES |
2414 ODM_IC_11AC_SERIES))
2415 phydm_noisy_detection(dm);
2416 #endif
2417
2418 #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
2419 phydm_dig_cckpd_coex(dm);
2420 #else
2421 phydm_dig(dm);
2422 #ifdef PHYDM_SUPPORT_CCKPD
2423 phydm_cck_pd_th(dm);
2424 #endif
2425 #endif
2426 }
2427
2428 #ifdef PHYDM_HW_IGI
2429 phydm_hwigi(dm);
2430 #endif
2431 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2432 phydm_update_power_training_state(dm);
2433 #endif
2434 phydm_adaptivity(dm);
2435 phydm_ra_info_watchdog(dm);
2436 #ifdef CONFIG_PATH_DIVERSITY
2437 phydm_tx_path_diversity(dm);
2438 #endif
2439 phydm_cfo_tracking(dm);
2440 #ifdef CONFIG_DYNAMIC_TX_TWR
2441 phydm_dynamic_tx_power(dm);
2442 #endif
2443 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2444 odm_antenna_diversity(dm);
2445 #endif
2446 #ifdef CONFIG_ADAPTIVE_SOML
2447 phydm_adaptive_soml(dm);
2448 #endif
2449
2450 #ifdef PHYDM_BEAMFORMING_VERSION1
2451 phydm_beamforming_watchdog(dm);
2452 #endif
2453
2454 halrf_watchdog(dm);
2455 #ifdef PHYDM_PRIMARY_CCA
2456 phydm_primary_cca(dm);
2457 #endif
2458 #ifdef CONFIG_BW_INDICATION
2459 phydm_dyn_bw_indication(dm);
2460 #endif
2461 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2462 odm_dtc(dm);
2463 #endif
2464
2465 phydm_env_mntr_set_watchdog(dm);
2466
2467 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2468 phydm_lna_sat_chk_watchdog(dm);
2469 #endif
2470
2471 #ifdef CONFIG_MCC_DM
2472 phydm_mcc_switch(dm);
2473 #endif
2474
2475 #ifdef CONFIG_MU_RSOML
2476 phydm_mu_rsoml_decision(dm);
2477 #endif
2478
2479 phydm_common_info_self_reset(dm);
2480 }
2481
phydm_fw_dm_ctrl_en(void * dm_void,enum phydm_func_idx fun_idx,boolean enable)2482 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
2483 boolean enable)
2484 {
2485 struct dm_struct *dm = (struct dm_struct *)dm_void;
2486 u8 h2c_val[H2C_MAX_LENGTH] = {0};
2487 u8 para4[4]; /*4 bit*/
2488 u8 para8[4]; /*8 bit*/
2489 u8 i = 0;
2490
2491 for (i = 0; i < 4; i++) {
2492 para4[i] = 0;
2493 para8[i] = 0;
2494 }
2495
2496 switch (fun_idx) {
2497 case F00_DIG:
2498 phydm_fill_fw_dig_info(dm, &enable, para4, para8);
2499 break;
2500 default:
2501 pr_debug("[Warning] %s\n", __func__);
2502 return;
2503 }
2504
2505 h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
2506 h2c_val[1] = para8[0];
2507 h2c_val[2] = para8[1];
2508 h2c_val[3] = para8[2];
2509 h2c_val[4] = para8[3];
2510 h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
2511 h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
2512
2513 PHYDM_DBG(dm, DBG_FW_DM,
2514 "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
2515 fun_idx, enable,
2516 para8[0], para8[1], para8[2], para8[3],
2517 para4[0], para4[1], para4[2], para4[3]);
2518
2519 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
2520 }
2521
2522 /*@
2523 * Init /.. Fixed HW value. Only init time.
2524 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2525 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2526 u64 value)
2527 {
2528 /* This section is used for init value */
2529 switch (cmn_info) {
2530 /* @Fixed ODM value. */
2531 case ODM_CMNINFO_ABILITY:
2532 dm->support_ability = (u64)value;
2533 break;
2534
2535 case ODM_CMNINFO_RF_TYPE:
2536 dm->rf_type = (u8)value;
2537 break;
2538
2539 case ODM_CMNINFO_PLATFORM:
2540 dm->support_platform = (u8)value;
2541 break;
2542
2543 case ODM_CMNINFO_INTERFACE:
2544 dm->support_interface = (u8)value;
2545 break;
2546
2547 case ODM_CMNINFO_MP_TEST_CHIP:
2548 dm->is_mp_chip = (u8)value;
2549 break;
2550
2551 case ODM_CMNINFO_IC_TYPE:
2552 dm->support_ic_type = (u32)value;
2553 break;
2554
2555 case ODM_CMNINFO_CUT_VER:
2556 dm->cut_version = (u8)value;
2557 break;
2558
2559 case ODM_CMNINFO_FAB_VER:
2560 dm->fab_version = (u8)value;
2561 break;
2562 case ODM_CMNINFO_FW_VER:
2563 dm->fw_version = (u8)value;
2564 break;
2565 case ODM_CMNINFO_FW_SUB_VER:
2566 dm->fw_sub_version = (u8)value;
2567 break;
2568 case ODM_CMNINFO_RFE_TYPE:
2569 #if (RTL8821C_SUPPORT)
2570 if (dm->support_ic_type & ODM_RTL8821C)
2571 dm->rfe_type_expand = (u8)value;
2572 else
2573 #endif
2574 dm->rfe_type = (u8)value;
2575
2576 #ifdef CONFIG_RFE_BY_HW_INFO
2577 phydm_init_hw_info_by_rfe(dm);
2578 #endif
2579 break;
2580
2581 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2582 dm->ant_div_type = (u8)value;
2583 break;
2584
2585 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2586 dm->with_extenal_ant_switch = (u8)value;
2587 break;
2588
2589 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2590 case ODM_CMNINFO_BE_FIX_TX_ANT:
2591 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2592 break;
2593 #endif
2594
2595 case ODM_CMNINFO_BOARD_TYPE:
2596 if (!dm->is_init_hw_info_by_rfe)
2597 dm->board_type = (u8)value;
2598 break;
2599
2600 case ODM_CMNINFO_PACKAGE_TYPE:
2601 if (!dm->is_init_hw_info_by_rfe)
2602 dm->package_type = (u8)value;
2603 break;
2604
2605 case ODM_CMNINFO_EXT_LNA:
2606 if (!dm->is_init_hw_info_by_rfe)
2607 dm->ext_lna = (u8)value;
2608 break;
2609
2610 case ODM_CMNINFO_5G_EXT_LNA:
2611 if (!dm->is_init_hw_info_by_rfe)
2612 dm->ext_lna_5g = (u8)value;
2613 break;
2614
2615 case ODM_CMNINFO_EXT_PA:
2616 if (!dm->is_init_hw_info_by_rfe)
2617 dm->ext_pa = (u8)value;
2618 break;
2619
2620 case ODM_CMNINFO_5G_EXT_PA:
2621 if (!dm->is_init_hw_info_by_rfe)
2622 dm->ext_pa_5g = (u8)value;
2623 break;
2624
2625 case ODM_CMNINFO_GPA:
2626 if (!dm->is_init_hw_info_by_rfe)
2627 dm->type_gpa = (u16)value;
2628 break;
2629
2630 case ODM_CMNINFO_APA:
2631 if (!dm->is_init_hw_info_by_rfe)
2632 dm->type_apa = (u16)value;
2633 break;
2634
2635 case ODM_CMNINFO_GLNA:
2636 if (!dm->is_init_hw_info_by_rfe)
2637 dm->type_glna = (u16)value;
2638 break;
2639
2640 case ODM_CMNINFO_ALNA:
2641 if (!dm->is_init_hw_info_by_rfe)
2642 dm->type_alna = (u16)value;
2643 break;
2644
2645 case ODM_CMNINFO_EXT_TRSW:
2646 if (!dm->is_init_hw_info_by_rfe)
2647 dm->ext_trsw = (u8)value;
2648 break;
2649 case ODM_CMNINFO_EXT_LNA_GAIN:
2650 dm->ext_lna_gain = (u8)value;
2651 break;
2652 case ODM_CMNINFO_PATCH_ID:
2653 dm->iot_table.win_patch_id = (u8)value;
2654 break;
2655 case ODM_CMNINFO_BINHCT_TEST:
2656 dm->is_in_hct_test = (boolean)value;
2657 break;
2658 case ODM_CMNINFO_BWIFI_TEST:
2659 dm->wifi_test = (u8)value;
2660 break;
2661 case ODM_CMNINFO_SMART_CONCURRENT:
2662 dm->is_dual_mac_smart_concurrent = (boolean)value;
2663 break;
2664 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2665 case ODM_CMNINFO_CONFIG_BB_RF:
2666 dm->config_bbrf = (boolean)value;
2667 break;
2668 #endif
2669 case ODM_CMNINFO_IQKPAOFF:
2670 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2671 break;
2672 case ODM_CMNINFO_REGRFKFREEENABLE:
2673 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2674 break;
2675 case ODM_CMNINFO_RFKFREEENABLE:
2676 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2677 break;
2678 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2679 dm->normal_rx_path = (u8)value;
2680 break;
2681 case ODM_CMNINFO_VALID_PATH_SET:
2682 dm->valid_path_set = (u8)value;
2683 break;
2684 case ODM_CMNINFO_EFUSE0X3D8:
2685 dm->efuse0x3d8 = (u8)value;
2686 break;
2687 case ODM_CMNINFO_EFUSE0X3D7:
2688 dm->efuse0x3d7 = (u8)value;
2689 break;
2690 case ODM_CMNINFO_ADVANCE_OTA:
2691 dm->p_advance_ota = (u8)value;
2692 break;
2693
2694 #ifdef CONFIG_PHYDM_DFS_MASTER
2695 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2696 dm->dfs_region_domain = (u8)value;
2697 break;
2698 #endif
2699 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2700 dm->soft_ap_special_setting = (u32)value;
2701 break;
2702
2703 case ODM_CMNINFO_X_CAP_SETTING:
2704 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2705 break;
2706
2707 case ODM_CMNINFO_DPK_EN:
2708 /*@dm->dpk_en = (u1Byte)value;*/
2709 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2710 break;
2711
2712 case ODM_CMNINFO_HP_HWID:
2713 dm->hp_hw_id = (boolean)value;
2714 break;
2715 case ODM_CMNINFO_TSSI_ENABLE:
2716 dm->en_tssi_mode = (u8)value;
2717 break;
2718 case ODM_CMNINFO_DIS_DPD:
2719 dm->en_dis_dpd = (boolean)value;
2720 break;
2721 case ODM_CMNINFO_EN_AUTO_BW_TH:
2722 dm->en_auto_bw_th = (u8)value;
2723 break;
2724 #if (RTL8721D_SUPPORT)
2725 case ODM_CMNINFO_POWER_VOLTAGE:
2726 dm->power_voltage = (u8)value;
2727 break;
2728 case ODM_CMNINFO_ANTDIV_GPIO:
2729 dm->antdiv_gpio = (u8)value;
2730 break;
2731 case ODM_CMNINFO_PEAK_DETECT_MODE:
2732 dm->peak_detect_mode = (u8)value;
2733 break;
2734 #endif
2735 default:
2736 break;
2737 }
2738 }
2739
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2740 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2741 void *value)
2742 {
2743 /* @Hook call by reference pointer. */
2744 switch (cmn_info) {
2745 /* @Dynamic call by reference pointer. */
2746 case ODM_CMNINFO_TX_UNI:
2747 dm->num_tx_bytes_unicast = (u64 *)value;
2748 break;
2749
2750 case ODM_CMNINFO_RX_UNI:
2751 dm->num_rx_bytes_unicast = (u64 *)value;
2752 break;
2753
2754 case ODM_CMNINFO_BAND:
2755 dm->band_type = (u8 *)value;
2756 break;
2757
2758 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2759 dm->sec_ch_offset = (u8 *)value;
2760 break;
2761
2762 case ODM_CMNINFO_SEC_MODE:
2763 dm->security = (u8 *)value;
2764 break;
2765
2766 case ODM_CMNINFO_BW:
2767 dm->band_width = (u8 *)value;
2768 break;
2769
2770 case ODM_CMNINFO_CHNL:
2771 dm->channel = (u8 *)value;
2772 break;
2773
2774 case ODM_CMNINFO_SCAN:
2775 dm->is_scan_in_process = (boolean *)value;
2776 break;
2777
2778 case ODM_CMNINFO_POWER_SAVING:
2779 dm->is_power_saving = (boolean *)value;
2780 break;
2781
2782 case ODM_CMNINFO_TDMA:
2783 dm->is_tdma = (boolean *)value;
2784 break;
2785
2786 case ODM_CMNINFO_ONE_PATH_CCA:
2787 dm->one_path_cca = (u8 *)value;
2788 break;
2789
2790 case ODM_CMNINFO_DRV_STOP:
2791 dm->is_driver_stopped = (boolean *)value;
2792 break;
2793 case ODM_CMNINFO_INIT_ON:
2794 dm->pinit_adpt_in_progress = (boolean *)value;
2795 break;
2796
2797 case ODM_CMNINFO_ANT_TEST:
2798 dm->antenna_test = (u8 *)value;
2799 break;
2800
2801 case ODM_CMNINFO_NET_CLOSED:
2802 dm->is_net_closed = (boolean *)value;
2803 break;
2804
2805 case ODM_CMNINFO_FORCED_RATE:
2806 dm->forced_data_rate = (u16 *)value;
2807 break;
2808 case ODM_CMNINFO_ANT_DIV:
2809 dm->enable_antdiv = (u8 *)value;
2810 break;
2811 case ODM_CMNINFO_PATH_DIV:
2812 dm->enable_pathdiv = (u8 *)value;
2813 break;
2814 case ODM_CMNINFO_ADAPTIVE_SOML:
2815 dm->en_adap_soml = (u8 *)value;
2816 break;
2817 case ODM_CMNINFO_ADAPTIVITY:
2818 dm->edcca_mode = (u8 *)value;
2819 break;
2820
2821 case ODM_CMNINFO_P2P_LINK:
2822 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2823 break;
2824
2825 case ODM_CMNINFO_IS1ANTENNA:
2826 dm->is_1_antenna = (boolean *)value;
2827 break;
2828
2829 case ODM_CMNINFO_RFDEFAULTPATH:
2830 dm->rf_default_path = (u8 *)value;
2831 break;
2832
2833 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2834 dm->is_fcs_mode_enable = (boolean *)value;
2835 break;
2836
2837 case ODM_CMNINFO_HUBUSBMODE:
2838 dm->hub_usb_mode = (u8 *)value;
2839 break;
2840 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2841 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2842 break;
2843 case ODM_CMNINFO_TX_TP:
2844 dm->current_tx_tp = (u32 *)value;
2845 break;
2846 case ODM_CMNINFO_RX_TP:
2847 dm->current_rx_tp = (u32 *)value;
2848 break;
2849 case ODM_CMNINFO_SOUNDING_SEQ:
2850 dm->sounding_seq = (u8 *)value;
2851 break;
2852 #ifdef CONFIG_PHYDM_DFS_MASTER
2853 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2854 dm->dfs_master_enabled = (u8 *)value;
2855 break;
2856 #endif
2857
2858 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2859 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2860 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2861 break;
2862 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2863 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2864 break;
2865 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2866 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2867 break;
2868 #endif
2869
2870 case ODM_CMNINFO_SOFT_AP_MODE:
2871 dm->soft_ap_mode = (u32 *)value;
2872 break;
2873 case ODM_CMNINFO_MP_MODE:
2874 dm->mp_mode = (u8 *)value;
2875 break;
2876 case ODM_CMNINFO_INTERRUPT_MASK:
2877 dm->interrupt_mask = (u32 *)value;
2878 break;
2879 case ODM_CMNINFO_BB_OPERATION_MODE:
2880 dm->bb_op_mode = (u8 *)value;
2881 break;
2882 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2883 dm->manual_supportability = (u32 *)value;
2884 break;
2885 case ODM_CMNINFO_EN_DYM_BW_INDICATION:
2886 dm->dis_dym_bw_indication = (u8 *)value;
2887 default:
2888 /*do nothing*/
2889 break;
2890 }
2891 }
2892
2893 /*@
2894 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2895 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2896 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2897 {
2898 /* This init variable may be changed in run time. */
2899 switch (cmn_info) {
2900 case ODM_CMNINFO_LINK_IN_PROGRESS:
2901 dm->is_link_in_process = (boolean)value;
2902 break;
2903
2904 case ODM_CMNINFO_ABILITY:
2905 dm->support_ability = (u64)value;
2906 break;
2907
2908 case ODM_CMNINFO_RF_TYPE:
2909 dm->rf_type = (u8)value;
2910 break;
2911
2912 case ODM_CMNINFO_WIFI_DIRECT:
2913 dm->is_wifi_direct = (boolean)value;
2914 break;
2915
2916 case ODM_CMNINFO_WIFI_DISPLAY:
2917 dm->is_wifi_display = (boolean)value;
2918 break;
2919
2920 case ODM_CMNINFO_LINK:
2921 dm->is_linked = (boolean)value;
2922 break;
2923
2924 case ODM_CMNINFO_CMW500LINK:
2925 dm->iot_table.is_linked_cmw500 = (boolean)value;
2926 break;
2927
2928 case ODM_CMNINFO_STATION_STATE:
2929 dm->bsta_state = (boolean)value;
2930 break;
2931
2932 case ODM_CMNINFO_RSSI_MIN:
2933 #if 0
2934 dm->rssi_min = (u8)value;
2935 #endif
2936 break;
2937
2938 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2939 dm->rssi_min_by_path = (u8)value;
2940 break;
2941
2942 case ODM_CMNINFO_DBG_COMP:
2943 dm->debug_components = (u64)value;
2944 break;
2945
2946 #ifdef ODM_CONFIG_BT_COEXIST
2947 /* The following is for BT HS mode and BT coexist mechanism. */
2948 case ODM_CMNINFO_BT_ENABLED:
2949 dm->bt_info_table.is_bt_enabled = (boolean)value;
2950 break;
2951
2952 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2953 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2954 break;
2955
2956 case ODM_CMNINFO_BT_HS_RSSI:
2957 dm->bt_info_table.bt_hs_rssi = (u8)value;
2958 break;
2959
2960 case ODM_CMNINFO_BT_OPERATION:
2961 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2962 break;
2963
2964 case ODM_CMNINFO_BT_LIMITED_DIG:
2965 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2966 break;
2967 #endif
2968
2969 case ODM_CMNINFO_AP_TOTAL_NUM:
2970 dm->ap_total_num = (u8)value;
2971 break;
2972
2973 #ifdef CONFIG_PHYDM_DFS_MASTER
2974 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2975 dm->dfs_region_domain = (u8)value;
2976 break;
2977 #endif
2978
2979 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2980 dm->is_bt_continuous_turn = (boolean)value;
2981 break;
2982 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2983 dm->is_download_fw = (boolean)value;
2984 break;
2985 case ODM_CMNINFO_PHYDM_PATCH_ID:
2986 dm->iot_table.phydm_patch_id = (u32)value;
2987 break;
2988 case ODM_CMNINFO_RRSR_VAL:
2989 dm->dm_ra_table.rrsr_val_init = (u32)value;
2990 break;
2991 case ODM_CMNINFO_LINKED_BF_SUPPORT:
2992 dm->linked_bf_support = (u8)value;
2993 break;
2994 case ODM_CMNINFO_FLATNESS_TYPE:
2995 dm->flatness_type = (u8)value;
2996 break;
2997 case ODM_CMNINFO_TSSI_ENABLE:
2998 dm->en_tssi_mode = (u8)value;
2999 break;
3000 default:
3001 break;
3002 }
3003 }
3004
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)3005 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
3006 {
3007 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
3008 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3009 struct ccx_info *ccx_info = &dm->dm_ccx_info;
3010
3011 switch (info_type) {
3012 /*@=== [FA Relative] ===========================================*/
3013 case PHYDM_INFO_FA_OFDM:
3014 return fa_t->cnt_ofdm_fail;
3015
3016 case PHYDM_INFO_FA_CCK:
3017 return fa_t->cnt_cck_fail;
3018
3019 case PHYDM_INFO_FA_TOTAL:
3020 return fa_t->cnt_all;
3021
3022 case PHYDM_INFO_CCA_OFDM:
3023 return fa_t->cnt_ofdm_cca;
3024
3025 case PHYDM_INFO_CCA_CCK:
3026 return fa_t->cnt_cck_cca;
3027
3028 case PHYDM_INFO_CCA_ALL:
3029 return fa_t->cnt_cca_all;
3030
3031 case PHYDM_INFO_CRC32_OK_VHT:
3032 return fa_t->cnt_vht_crc32_ok;
3033
3034 case PHYDM_INFO_CRC32_OK_HT:
3035 return fa_t->cnt_ht_crc32_ok;
3036
3037 case PHYDM_INFO_CRC32_OK_LEGACY:
3038 return fa_t->cnt_ofdm_crc32_ok;
3039
3040 case PHYDM_INFO_CRC32_OK_CCK:
3041 return fa_t->cnt_cck_crc32_ok;
3042
3043 case PHYDM_INFO_CRC32_ERROR_VHT:
3044 return fa_t->cnt_vht_crc32_error;
3045
3046 case PHYDM_INFO_CRC32_ERROR_HT:
3047 return fa_t->cnt_ht_crc32_error;
3048
3049 case PHYDM_INFO_CRC32_ERROR_LEGACY:
3050 return fa_t->cnt_ofdm_crc32_error;
3051
3052 case PHYDM_INFO_CRC32_ERROR_CCK:
3053 return fa_t->cnt_cck_crc32_error;
3054
3055 case PHYDM_INFO_EDCCA_FLAG:
3056 return fa_t->edcca_flag;
3057
3058 case PHYDM_INFO_OFDM_ENABLE:
3059 return fa_t->ofdm_block_enable;
3060
3061 case PHYDM_INFO_CCK_ENABLE:
3062 return fa_t->cck_block_enable;
3063
3064 case PHYDM_INFO_DBG_PORT_0:
3065 return fa_t->dbg_port0;
3066
3067 case PHYDM_INFO_CRC32_OK_HT_AGG:
3068 return fa_t->cnt_ht_crc32_ok_agg;
3069
3070 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
3071 return fa_t->cnt_ht_crc32_error_agg;
3072
3073 /*@=== [DIG] ================================================*/
3074
3075 case PHYDM_INFO_CURR_IGI:
3076 return dig_t->cur_ig_value;
3077
3078 /*@=== [RSSI] ===============================================*/
3079 case PHYDM_INFO_RSSI_MIN:
3080 return (u32)dm->rssi_min;
3081
3082 case PHYDM_INFO_RSSI_MAX:
3083 return (u32)dm->rssi_max;
3084
3085 case PHYDM_INFO_CLM_RATIO:
3086 return (u32)ccx_info->clm_ratio;
3087 case PHYDM_INFO_NHM_RATIO:
3088 return (u32)ccx_info->nhm_ratio;
3089 case PHYDM_INFO_NHM_NOISE_PWR:
3090 return (u32)ccx_info->nhm_level;
3091 case PHYDM_INFO_NHM_PWR:
3092 return (u32)ccx_info->nhm_pwr;
3093 case PHYDM_INFO_NHM_ENV_RATIO:
3094 return (u32)ccx_info->nhm_env_ratio;
3095 case PHYDM_INFO_TXEN_CCK:
3096 return (u32)fa_t->cnt_cck_txen;
3097 case PHYDM_INFO_TXEN_OFDM:
3098 return (u32)fa_t->cnt_ofdm_txen;
3099 default:
3100 return 0xffffffff;
3101 }
3102 }
3103
3104 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)3105 void odm_init_all_work_items(struct dm_struct *dm)
3106 {
3107 void *adapter = dm->adapter;
3108 #if USE_WORKITEM
3109
3110 #ifdef CONFIG_ADAPTIVE_SOML
3111 odm_initialize_work_item(dm,
3112 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
3113 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
3114 (void *)adapter,
3115 "AdaptiveSOMLWorkitem");
3116 #endif
3117
3118 #ifdef ODM_EVM_ENHANCE_ANTDIV
3119 odm_initialize_work_item(dm,
3120 &dm->phydm_evm_antdiv_workitem,
3121 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
3122 (void *)adapter,
3123 "EvmAntdivWorkitem");
3124 #endif
3125
3126 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3127 odm_initialize_work_item(dm,
3128 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
3129 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
3130 (void *)adapter,
3131 "AntennaSwitchWorkitem");
3132 #endif
3133 #if (defined(CONFIG_HL_SMART_ANTENNA))
3134 odm_initialize_work_item(dm,
3135 &dm->dm_sat_table.hl_smart_antenna_workitem,
3136 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
3137 (void *)adapter,
3138 "hl_smart_ant_workitem");
3139
3140 odm_initialize_work_item(dm,
3141 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
3142 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
3143 (void *)adapter,
3144 "hl_smart_ant_decision_workitem");
3145 #endif
3146
3147 odm_initialize_work_item(
3148 dm,
3149 &dm->ra_rpt_workitem,
3150 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
3151 (void *)adapter,
3152 "ra_rpt_workitem");
3153
3154 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3155 odm_initialize_work_item(
3156 dm,
3157 &dm->fast_ant_training_workitem,
3158 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
3159 (void *)adapter,
3160 "fast_ant_training_workitem");
3161 #endif
3162
3163 #endif /*#if USE_WORKITEM*/
3164
3165 #ifdef PHYDM_BEAMFORMING_SUPPORT
3166 odm_initialize_work_item(
3167 dm,
3168 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
3169 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
3170 (void *)adapter,
3171 "txbf_enter_work_item");
3172
3173 odm_initialize_work_item(
3174 dm,
3175 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
3176 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
3177 (void *)adapter,
3178 "txbf_leave_work_item");
3179
3180 odm_initialize_work_item(
3181 dm,
3182 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
3183 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
3184 (void *)adapter,
3185 "txbf_fw_ndpa_work_item");
3186
3187 odm_initialize_work_item(
3188 dm,
3189 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
3190 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
3191 (void *)adapter,
3192 "txbf_clk_work_item");
3193
3194 odm_initialize_work_item(
3195 dm,
3196 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
3197 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
3198 (void *)adapter,
3199 "txbf_rate_work_item");
3200
3201 odm_initialize_work_item(
3202 dm,
3203 &dm->beamforming_info.txbf_info.txbf_status_work_item,
3204 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
3205 (void *)adapter,
3206 "txbf_status_work_item");
3207
3208 odm_initialize_work_item(
3209 dm,
3210 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
3211 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
3212 (void *)adapter,
3213 "txbf_reset_tx_path_work_item");
3214
3215 odm_initialize_work_item(
3216 dm,
3217 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
3218 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
3219 (void *)adapter,
3220 "txbf_get_tx_rate_work_item");
3221 #endif
3222
3223 #if (PHYDM_LA_MODE_SUPPORT == 1)
3224 odm_initialize_work_item(
3225 dm,
3226 &dm->adcsmp.adc_smp_work_item,
3227 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3228 (void *)adapter,
3229 "adc_smp_work_item");
3230
3231 odm_initialize_work_item(
3232 dm,
3233 &dm->adcsmp.adc_smp_work_item_1,
3234 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3235 (void *)adapter,
3236 "adc_smp_work_item_1");
3237 #endif
3238 }
3239
odm_free_all_work_items(struct dm_struct * dm)3240 void odm_free_all_work_items(struct dm_struct *dm)
3241 {
3242 #if USE_WORKITEM
3243
3244 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3245 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
3246 #endif
3247
3248 #ifdef CONFIG_ADAPTIVE_SOML
3249 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
3250 #endif
3251
3252 #ifdef ODM_EVM_ENHANCE_ANTDIV
3253 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
3254 #endif
3255
3256 #if (defined(CONFIG_HL_SMART_ANTENNA))
3257 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
3258 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
3259 #endif
3260
3261 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3262 odm_free_work_item(&dm->fast_ant_training_workitem);
3263 #endif
3264 odm_free_work_item(&dm->ra_rpt_workitem);
3265 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
3266 #endif
3267
3268 #ifdef PHYDM_BEAMFORMING_SUPPORT
3269 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
3270 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
3271 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
3272 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
3273 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
3274 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
3275 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
3276 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
3277 #endif
3278
3279 #if (PHYDM_LA_MODE_SUPPORT == 1)
3280 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
3281 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
3282 #endif
3283 }
3284 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3285
odm_init_all_timers(struct dm_struct * dm)3286 void odm_init_all_timers(struct dm_struct *dm)
3287 {
3288 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3289 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
3290 #endif
3291 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
3292 #ifdef IS_USE_NEW_TDMA
3293 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
3294 #endif
3295 #endif
3296 #ifdef CONFIG_ADAPTIVE_SOML
3297 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
3298 #endif
3299 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3300 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3301 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
3302 #endif
3303 #endif
3304
3305 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3306 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3307 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3308 #ifdef PHYDM_BEAMFORMING_SUPPORT
3309 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3310 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3311 "txbf_fw_ndpa_timer");
3312 #endif
3313 #endif
3314
3315 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3316 #ifdef PHYDM_BEAMFORMING_SUPPORT
3317 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3318 (void *)beamforming_sw_timer_callback, NULL,
3319 "beamforming_timer");
3320 #endif
3321 #endif
3322 }
3323
odm_cancel_all_timers(struct dm_struct * dm)3324 void odm_cancel_all_timers(struct dm_struct *dm)
3325 {
3326 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3327 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3328 if (dm->adapter == NULL)
3329 return;
3330 #endif
3331
3332 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3333 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3334 #endif
3335 #ifdef PHYDM_TDMA_DIG_SUPPORT
3336 #ifdef IS_USE_NEW_TDMA
3337 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3338 #endif
3339 #endif
3340 #ifdef CONFIG_ADAPTIVE_SOML
3341 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3342 #endif
3343 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3344 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3345 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3346 #endif
3347 #endif
3348
3349 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3350 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3351 #ifdef PHYDM_BEAMFORMING_SUPPORT
3352 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3353 #endif
3354 #endif
3355
3356 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3357 #ifdef PHYDM_BEAMFORMING_SUPPORT
3358 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3359 #endif
3360 #endif
3361 }
3362
odm_release_all_timers(struct dm_struct * dm)3363 void odm_release_all_timers(struct dm_struct *dm)
3364 {
3365 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3366 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3367 #endif
3368 #ifdef PHYDM_TDMA_DIG_SUPPORT
3369 #ifdef IS_USE_NEW_TDMA
3370 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3371 #endif
3372 #endif
3373 #ifdef CONFIG_ADAPTIVE_SOML
3374 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3375 #endif
3376 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3377 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3378 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3379 #endif
3380 #endif
3381
3382 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3383 odm_release_timer(dm, &dm->sbdcnt_timer);
3384 #ifdef PHYDM_BEAMFORMING_SUPPORT
3385 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3386 #endif
3387 #endif
3388
3389 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3390 #ifdef PHYDM_BEAMFORMING_SUPPORT
3391 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3392 #endif
3393 #endif
3394 }
3395
3396 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3397 void odm_init_all_threads(
3398 struct dm_struct *dm)
3399 {
3400 #ifdef TPT_THREAD
3401 k_tpt_task_init(dm->priv);
3402 #endif
3403 }
3404
odm_stop_all_threads(struct dm_struct * dm)3405 void odm_stop_all_threads(
3406 struct dm_struct *dm)
3407 {
3408 #ifdef TPT_THREAD
3409 k_tpt_task_stop(dm->priv);
3410 #endif
3411 }
3412 #endif
3413
3414 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3415 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3416 * 2012/11/05
3417 */
odm_dtc(struct dm_struct * dm)3418 void odm_dtc(struct dm_struct *dm)
3419 {
3420 #ifdef CONFIG_DM_RESP_TXAGC
3421 /* RSSI higher than this value, start to decade TX power */
3422 #define DTC_BASE 35
3423
3424 /* RSSI lower than this value, start to increase TX power */
3425 #define DTC_DWN_BASE (DTC_BASE - 5)
3426
3427 /* RSSI vs TX power step mapping: decade TX power */
3428 static const u8 dtc_table_down[] = {
3429 DTC_BASE,
3430 (DTC_BASE + 5),
3431 (DTC_BASE + 10),
3432 (DTC_BASE + 15),
3433 (DTC_BASE + 20),
3434 (DTC_BASE + 25)};
3435
3436 /* RSSI vs TX power step mapping: increase TX power */
3437 static const u8 dtc_table_up[] = {
3438 DTC_DWN_BASE,
3439 (DTC_DWN_BASE - 5),
3440 (DTC_DWN_BASE - 10),
3441 (DTC_DWN_BASE - 15),
3442 (DTC_DWN_BASE - 15),
3443 (DTC_DWN_BASE - 20),
3444 (DTC_DWN_BASE - 20),
3445 (DTC_DWN_BASE - 25),
3446 (DTC_DWN_BASE - 25),
3447 (DTC_DWN_BASE - 30),
3448 (DTC_DWN_BASE - 35)};
3449
3450 u8 i;
3451 u8 dtc_steps = 0;
3452 u8 sign;
3453 u8 resp_txagc = 0;
3454
3455 if (dm->rssi_min > DTC_BASE) {
3456 /* need to decade the CTS TX power */
3457 sign = 1;
3458 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3459 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3460 break;
3461 else
3462 dtc_steps++;
3463 }
3464 }
3465 #if 0
3466 else if (dm->rssi_min > DTC_DWN_BASE) {
3467 /* needs to increase the CTS TX power */
3468 sign = 0;
3469 dtc_steps = 1;
3470 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3471 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3472 break;
3473 else
3474 dtc_steps++;
3475 }
3476 }
3477 #endif
3478 else {
3479 sign = 0;
3480 dtc_steps = 0;
3481 }
3482
3483 resp_txagc = dtc_steps | (sign << 4);
3484 resp_txagc = resp_txagc | (resp_txagc << 5);
3485 odm_write_1byte(dm, 0x06d9, resp_txagc);
3486
3487 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3488 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3489 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3490 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3491 }
3492
3493 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3494
3495 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3496 void phydm_dc_cancellation(struct dm_struct *dm)
3497 {
3498 #ifdef PHYDM_DC_CANCELLATION
3499 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3500 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3501 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3502 u8 path = RF_PATH_A;
3503 u8 set_result;
3504
3505 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3506 return;
3507 if ((dm->support_ic_type & ODM_RTL8188F) &&
3508 dm->cut_version < ODM_CUT_D)
3509 return;
3510 if ((dm->support_ic_type & ODM_RTL8192F) &&
3511 dm->cut_version == ODM_CUT_A)
3512 return;
3513 if (*dm->band_width == CHANNEL_WIDTH_5)
3514 return;
3515 if (*dm->band_width == CHANNEL_WIDTH_10)
3516 return;
3517
3518 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3519
3520 /*@DC_Estimation (only for 2x2 ic now) */
3521
3522 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3523 if (path > RF_PATH_A &&
3524 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3525 ODM_RTL8710B | ODM_RTL8721D |
3526 ODM_RTL8710C | ODM_RTL8723D))
3527 break;
3528 else if (path > RF_PATH_B &&
3529 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3530 break;
3531 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3532 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3533 return;
3534 }
3535 odm_write_dig(dm, 0x7e);
3536 /*@Disable LNA*/
3537 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3538 ODM_RTL8710C))
3539 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3540 /*Turn off 3-wire*/
3541 phydm_stop_3_wire(dm, PHYDM_SET);
3542 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3543 ODM_RTL8710B)) {
3544 /*set debug port to 0x235*/
3545 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3546 PHYDM_DBG(dm, ODM_COMP_API,
3547 "Set Debug port Fail\n");
3548 return;
3549 }
3550 } else if (dm->support_ic_type & (ODM_RTL8721D |
3551 ODM_RTL8710C)) {
3552 /*set debug port to 0x200*/
3553 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3554 PHYDM_DBG(dm, ODM_COMP_API,
3555 "Set Debug port Fail\n");
3556 return;
3557 }
3558 } else if (dm->support_ic_type & ODM_RTL8821C) {
3559 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3560 /*set debug port to 0x200*/
3561 PHYDM_DBG(dm, ODM_COMP_API,
3562 "Set Debug port Fail\n");
3563 return;
3564 }
3565 phydm_bb_dbg_port_header_sel(dm, 0x0);
3566 } else if (dm->support_ic_type & ODM_RTL8822B) {
3567 if (path == RF_PATH_A &&
3568 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3569 /*set debug port to 0x200*/
3570 PHYDM_DBG(dm, ODM_COMP_API,
3571 "Set Debug port Fail\n");
3572 return;
3573 }
3574 if (path == RF_PATH_B &&
3575 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3576 /*set debug port to 0x200*/
3577 PHYDM_DBG(dm, ODM_COMP_API,
3578 "Set Debug port Fail\n");
3579 return;
3580 }
3581 phydm_bb_dbg_port_header_sel(dm, 0x0);
3582 } else if (dm->support_ic_type & ODM_RTL8192F) {
3583 if (path == RF_PATH_A &&
3584 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3585 /*set debug port to 0x235*/
3586 PHYDM_DBG(dm, ODM_COMP_API,
3587 "Set Debug port Fail\n");
3588 return;
3589 }
3590 if (path == RF_PATH_B &&
3591 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3592 /*set debug port to 0x23d*/
3593 PHYDM_DBG(dm, ODM_COMP_API,
3594 "Set Debug port Fail\n");
3595 return;
3596 }
3597 }
3598
3599 /*@disable CCK DCNF*/
3600 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3601
3602 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3603
3604 phydm_stop_ck320(dm, true); /*stop ck320*/
3605
3606 /* the same debug port both for path-a and path-b*/
3607 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3608
3609 phydm_stop_ck320(dm, false); /*start ck320*/
3610
3611 phydm_release_bb_dbg_port(dm);
3612 /* @Turn on 3-wire*/
3613 phydm_stop_3_wire(dm, PHYDM_REVERT);
3614 /* @Enable LNA*/
3615 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3616 ODM_RTL8710C))
3617 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3618
3619 odm_write_dig(dm, 0x20);
3620
3621 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3622
3623 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3624 }
3625
3626 /*@DC_Cancellation*/
3627 /*@DC compensation to CCK data path*/
3628 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3629 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3630 ODM_RTL8710B)) {
3631 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3632 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3633
3634 /*@Before filling into registers,
3635 *offset should be multiplexed (-1)
3636 */
3637 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3638 (0x400 - offset_i_hex[0]) :
3639 (0x1ff - offset_i_hex[0]);
3640 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3641 (0x400 - offset_q_hex[0]) :
3642 (0x1ff - offset_q_hex[0]);
3643
3644 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3645 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3646 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3647 /* Path-a */
3648 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3649 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3650
3651 /*@Before filling into registers,
3652 *offset should be multiplexed (-1)
3653 */
3654 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3655 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3656
3657 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3658 (0x3c0 & offset_i_hex[0]) >> 6);
3659 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3660 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3661 (0x3c0 & offset_q_hex[0]) >> 6);
3662 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3663
3664 /* Path-b */
3665 if (dm->rf_type > RF_1T1R) {
3666 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3667 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3668
3669 /*@Before filling into registers,
3670 *offset should be multiplexed (-1)
3671 */
3672 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3673 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3674
3675 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3676 (0x3c0 & offset_i_hex[1]) >> 6);
3677 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3678 0x3f & offset_i_hex[1]);
3679 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3680 (0x3c0 & offset_q_hex[1]) >> 6);
3681 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3682 0x3f & offset_q_hex[1]);
3683 }
3684 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3685 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3686 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3687 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3688
3689 /*@Before filling into registers,
3690 *offset should be multiplexed (-1)
3691 */
3692 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3693 (0x400 - offset_i_hex[0]) :
3694 (0xff - offset_i_hex[0]);
3695 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3696 (0x400 - offset_q_hex[0]) :
3697 (0xff - offset_q_hex[0]);
3698 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3699 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3700 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3701
3702 /* Path-b */
3703 if (dm->rf_type > RF_1T1R) {
3704 /* @I:df4[27:18],Q:df4[17:8]*/
3705 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3706 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3707
3708 /*@Before filling into registers,
3709 *offset should be multiplexed (-1)
3710 */
3711 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3712 (0x400 - offset_i_hex[1]) :
3713 (0xff - offset_i_hex[1]);
3714 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3715 (0x400 - offset_q_hex[1]) :
3716 (0xff - offset_q_hex[1]);
3717 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3718 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3719 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3720 }
3721 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3722 /*judy modified 20180517*/
3723 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3724 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3725
3726 if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
3727 || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
3728 /*@Discard outliers*/
3729 offset_i_hex[0] = 0x0;
3730 offset_q_hex[0] = 0x0;
3731 } else {
3732 /*@Before filling into registers,
3733 *offset should be multiplexed (-1)
3734 */
3735 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3736 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3737 }
3738 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3739 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3740 }
3741 #endif
3742 }
3743
phydm_receiver_blocking(void * dm_void)3744 void phydm_receiver_blocking(void *dm_void)
3745 {
3746 #ifdef CONFIG_RECEIVER_BLOCKING
3747 struct dm_struct *dm = (struct dm_struct *)dm_void;
3748 u32 chnl = *dm->channel;
3749 u8 bw = *dm->band_width;
3750 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3751
3752 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3753 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3754 return;
3755
3756 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3757 dm->support_ic_type & ODM_RTL8192E) {
3758 /*@8188E_T version*/
3759 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3760 goto end;
3761
3762 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3763 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3764 PHYDM_DONT_CARE);
3765 dm->is_rx_blocking_en = true;
3766 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3767 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3768 PHYDM_DONT_CARE);
3769 dm->is_rx_blocking_en = true;
3770 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3771 phydm_nbi_enable(dm, FUNC_DISABLE);
3772 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3773 dm->is_rx_blocking_en = false;
3774 }
3775 return;
3776 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3777 /*@8188E_S version*/
3778 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3779 goto end;
3780
3781 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3782 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3783 PHYDM_DONT_CARE);
3784 dm->is_rx_blocking_en = true;
3785 } else if (dm->is_rx_blocking_en && chnl != 13) {
3786 phydm_nbi_enable(dm, FUNC_DISABLE);
3787 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3788 dm->is_rx_blocking_en = false;
3789 }
3790 return;
3791 }
3792
3793 end:
3794 if (dm->is_rx_blocking_en) {
3795 phydm_nbi_enable(dm, FUNC_DISABLE);
3796 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3797 dm->is_rx_blocking_en = false;
3798 }
3799 #endif
3800 }
3801
phydm_dyn_bw_indication(void * dm_void)3802 void phydm_dyn_bw_indication(void *dm_void)
3803 {
3804 #ifdef CONFIG_BW_INDICATION
3805 struct dm_struct *dm = (struct dm_struct *)dm_void;
3806 u8 en_auto_bw_th = dm->en_auto_bw_th;
3807
3808 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
3809 return;
3810
3811 /*driver decide bw cobime timing*/
3812 if (dm->dis_dym_bw_indication) {
3813 if (*dm->dis_dym_bw_indication)
3814 return;
3815 }
3816
3817 /*check for auto bw*/
3818 if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
3819 phydm_bw_fixed_enable(dm, FUNC_DISABLE);
3820 return;
3821 }
3822
3823 phydm_bw_fixed_setting(dm);
3824 #endif
3825 }
3826
3827