1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
18 #if RT_PLATFORM == PLATFORM_MACOSX
19 #include "phydm_precomp.h"
20 #else
21 #include "../phydm_precomp.h"
22 #endif
23 #else
24 #include "../../phydm_precomp.h"
25 #endif
26
27 #if (RTL8723D_SUPPORT == 1)
28
29 /*---------------------------Define Local Constant---------------------------*/
30 /*IQK*/
31 #define IQK_DELAY_TIME_8723D 10
32
33 /* 2010/04/25 MH Define the max tx power tracking tx agc power.*/
34 #define ODM_TXPWRTRACK_MAX_IDX_8723D 6
35
36 #define PATH_S1 0
37 #define idx_0xc94 0
38 #define idx_0xc80 1
39 #define idx_0xc4c 2
40
41 #define idx_0xc14 0
42 #define idx_0xca0 1
43
44 #define PATH_S0 1
45 #define idx_0xcd0 0
46 #define idx_0xcd4 1
47
48 #define idx_0xcd8 0
49 #define idx_0xcdc 1
50
51 #define KEY 0
52 #define VAL 1
53
54 /*---------------------------Define Local Constant---------------------------*/
55
56 /* Tx Power Tracking*/
57
set_iqk_matrix_8723d(struct dm_struct * dm,u8 OFDM_index,u8 rf_path,s32 iqk_result_x,s32 iqk_result_y)58 void set_iqk_matrix_8723d(struct dm_struct *dm, u8 OFDM_index, u8 rf_path,
59 s32 iqk_result_x, s32 iqk_result_y)
60 {
61 s32 ele_A = 0, ele_D = 0, ele_C = 0, value32;
62 s32 ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0;
63
64 if (OFDM_index >= OFDM_TABLE_SIZE)
65 OFDM_index = OFDM_TABLE_SIZE - 1;
66 else if (OFDM_index < 0)
67 OFDM_index = 0;
68
69 if (iqk_result_x != 0 && (*dm->band_type == ODM_BAND_2_4G)) {
70 /* new element D */
71 ele_D = (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22;
72 ele_D_ext = (((iqk_result_x * ele_D) >> 7) & 0x01);
73 /* new element A */
74 if ((iqk_result_x & 0x00000200) != 0) /* consider minus */
75 iqk_result_x = iqk_result_x | 0xFFFFFC00;
76 ele_A = ((iqk_result_x * ele_D) >> 8) & 0x000003FF;
77 ele_A_ext = ((iqk_result_x * ele_D) >> 7) & 0x1;
78 /* new element C */
79 if ((iqk_result_y & 0x00000200) != 0)
80 iqk_result_y = iqk_result_y | 0xFFFFFC00;
81 ele_C = ((iqk_result_y * ele_D) >> 8) & 0x000003FF;
82 ele_C_ext = ((iqk_result_y * ele_D) >> 7) & 0x1;
83
84 switch (rf_path) {
85 case RF_PATH_A:
86 /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */
87 /* write 0xc80 */
88 value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
89 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
90 /* write 0xc94 */
91 value32 = (ele_C & 0x000003C0) >> 6;
92 odm_set_bb_reg(dm, R_0xc94, MASKH4BITS, value32);
93 /* write 0xc4c */
94 value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29);
95 value32 = (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)))) | value32;
96 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
97 break;
98
99 case RF_PATH_B:
100 /*write new elements A, C, D to regCd0 and regCd4, element B is always 0*/
101 value32 = ele_D;
102 odm_set_bb_reg(dm, R_0xcd4, 0x007FE000, value32);
103
104 value32 = ele_C;
105 odm_set_bb_reg(dm, R_0xcd4, 0x000007FE, value32);
106
107 value32 = ele_A;
108 odm_set_bb_reg(dm, R_0xcd0, 0x000007FE, value32);
109
110 odm_set_bb_reg(dm, R_0xcd4, BIT(12), ele_D_ext);
111 odm_set_bb_reg(dm, R_0xcd0, BIT(0), ele_A_ext);
112 odm_set_bb_reg(dm, R_0xcd4, BIT(0), ele_C_ext);
113 break;
114 default:
115 break;
116 }
117 } else {
118 switch (rf_path) {
119 case RF_PATH_A:
120 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
121 odm_set_bb_reg(dm, R_0xc94, MASKH4BITS, 0x00);
122 value32 = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)));
123 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
124 break;
125
126 case RF_PATH_B:
127 /*image S1:c80 to S0:Cd0 and Cd4*/
128 odm_set_bb_reg(dm, R_0xcd0, 0x000007FE, ofdm_swing_table_new[OFDM_index] & 0x000003FF);
129 odm_set_bb_reg(dm, R_0xcd0, 0x0007E000, (ofdm_swing_table_new[OFDM_index] & 0x0000FC00) >> 10);
130 odm_set_bb_reg(dm, R_0xcd4, 0x0000007E, (ofdm_swing_table_new[OFDM_index] & 0x003F0000) >> 16);
131 odm_set_bb_reg(dm, R_0xcd4, 0x007FE000, (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22);
132
133 odm_set_bb_reg(dm, R_0xcd4, 0x00000780, 0x00);
134
135 odm_set_bb_reg(dm, R_0xcd4, BIT(12), 0x0);
136 odm_set_bb_reg(dm, R_0xcd4, BIT(0), 0x0);
137 odm_set_bb_reg(dm, R_0xcd0, BIT(0), 0x0);
138 break;
139 default:
140 break;
141 }
142 }
143 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
144 "TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n",
145 (rf_path == RF_PATH_A ? 'A' : 'B'), (u32)iqk_result_x,
146 (u32)iqk_result_y, (u32)ele_A, (u32)ele_C, (u32)ele_D,
147 (u32)ele_A_ext, (u32)ele_C_ext, (u32)ele_D_ext);
148 }
149
set_cck_filter_coefficient_8723d(struct dm_struct * dm,u8 cck_swing_index)150 void set_cck_filter_coefficient_8723d(struct dm_struct *dm, u8 cck_swing_index)
151 {
152 odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[cck_swing_index]);
153 }
154
do_iqk_8723d(void * dm_void,u8 delta_thermal_index,u8 thermal_value,u8 threshold)155 void do_iqk_8723d(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
156 u8 threshold)
157 {
158 u32 is_bt_enable = 0;
159
160 struct dm_struct *dm = (struct dm_struct *)dm_void;
161
162 if (!(*dm->mp_mode))
163 is_bt_enable = odm_get_mac_reg(dm, R_0xa8, MASKDWORD) & BIT(17);
164
165 if (is_bt_enable) {
166 RF_DBG(dm, DBG_RF_IQK, "[IQK]Skip IQK because BT is enable\n");
167 return;
168 }
169
170 RF_DBG(dm, DBG_RF_IQK, "[IQK]Do IQK because BT is disable\n");
171
172 odm_reset_iqk_result(dm);
173
174 dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
175
176 halrf_iqk_trigger(dm, false);
177 }
178
179 /*-----------------------------------------------------------------------------
180 * Function: odm_tx_pwr_track_set_pwr_8723d()
181 *
182 * Overview: 8723D change all channel tx power according to flag.
183 * OFDM & CCK are all different.
184 *
185 * Input: NONE
186 *
187 * Output: NONE
188 *
189 * Return: NONE
190 *
191 * Revised History:
192 * When Who Remark
193 * 04/23/2012 MHC Create version 0.
194 *
195 *---------------------------------------------------------------------------
196 */
odm_tx_pwr_track_set_pwr_8723d(void * dm_void,enum pwrtrack_method method,u8 rf_path,u8 channel_mapped_index)197 void odm_tx_pwr_track_set_pwr_8723d(void *dm_void, enum pwrtrack_method method,
198 u8 rf_path, u8 channel_mapped_index)
199 {
200 struct dm_struct *dm = (struct dm_struct *)dm_void;
201 #if !((DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211))
202 struct _ADAPTER *adapter = dm->adapter;
203 #endif
204 #if 0
205 //PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
206 #endif
207 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
208 struct _hal_rf_ *rf = &dm->rf_table;
209 u8 pwr_tracking_limit_ofdm = 30;
210 u8 pwr_tracking_limit_cck = 40;
211 u8 tx_rate = 0xFF;
212 u8 final_ofdm_swing_index = 0;
213 u8 final_cck_swing_index = 0;
214
215 if (*dm->mp_mode) {
216 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
217 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
218 #if (MP_DRIVER == 1)
219 PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
220
221 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
222 #endif
223 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
224 #ifdef CONFIG_MP_INCLUDED
225 PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
226
227 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
228 #endif
229 #endif
230 #endif
231 } else {
232 u16 rate = *dm->forced_data_rate;
233
234 if (!rate) { /*auto rate*/
235 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
236 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
237 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
238 tx_rate = dm->tx_rate;
239 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
240 if (dm->number_linked_client != 0)
241 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
242 else
243 tx_rate = rf->p_rate_index;
244 #endif
245 } else { /*force rate*/
246 tx_rate = (u8)rate;
247 }
248 }
249
250 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>ODM_TxPwrTrackSetPwr8723DA\n");
251
252 if (tx_rate != 0xFF) {
253 /*CCK*/
254 if ((tx_rate >= MGN_1M && tx_rate <= MGN_5_5M) || tx_rate == MGN_11M)
255 pwr_tracking_limit_cck = 40;
256 /*OFDM*/
257 else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
258 pwr_tracking_limit_ofdm = 36;
259 else if (tx_rate == MGN_54M)
260 pwr_tracking_limit_ofdm = 34;
261
262 /* HT*/
263 else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2))
264 pwr_tracking_limit_ofdm = 38;
265 else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4))
266 pwr_tracking_limit_ofdm = 36;
267 else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7))
268 pwr_tracking_limit_ofdm = 34;
269
270 else if ((tx_rate >= MGN_MCS8) && (tx_rate <= MGN_MCS10))
271 pwr_tracking_limit_ofdm = 38;
272 else if ((tx_rate >= MGN_MCS11) && (tx_rate <= MGN_MCS12))
273 pwr_tracking_limit_ofdm = 36;
274 else if ((tx_rate >= MGN_MCS13) && (tx_rate <= MGN_MCS15))
275 pwr_tracking_limit_ofdm = 34;
276
277 else
278 pwr_tracking_limit_ofdm = cali_info->default_ofdm_index; /*Default OFDM index = 30 */
279 }
280
281 if (method == TXAGC) {
282 u32 pwr = 0, tx_agc = 0;
283 /*void *adapter = dm->adapter;*/
284
285 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
286 "odm_TxPwrTrackSetPwr_8723D CH=%d\n", *dm->channel);
287
288 cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path]; /* Remnant index equal to aboslute compensate value. */
289
290 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
291
292 #if (MP_DRIVER != 1)
293 #if 0
294 PHY_SetTxPowerLevelByPath8723D(adapter, *dm->channel, rf_path); /* Using new set power function */
295 /* PHY_SetTxPowerLevel8723D(dm->adapter, *dm->channel); */
296 #endif
297 cali_info->modify_tx_agc_flag_path_a = true;
298 cali_info->modify_tx_agc_flag_path_b = true;
299 cali_info->modify_tx_agc_flag_path_a_cck = true;
300 if (rf_path == RF_PATH_A) {
301 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
302 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, OFDM);
303 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS0_MCS7);
304 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS8_MCS15);
305 } else {
306 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, CCK);
307 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, OFDM);
308 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, HT_MCS0_MCS7);
309 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, HT_MCS8_MCS15);
310 }
311 #else
312
313 if (rf_path == RF_PATH_A) {
314 /*CCK path S1*/
315 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
316 pwr += cali_info->power_index_offset[RF_PATH_A];
317 odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
318 tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
319 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0x00ffffff, tx_agc);
320 RT_DISP(FPHY, PHY_TXPWR, ("%s: CCK Tx-rf(A) Power = 0x%x\n", __func__, tx_agc));
321
322 /*OFDM path S1*/
323 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
324 pwr += (cali_info->bb_swing_idx_ofdm[RF_PATH_A] - cali_info->bb_swing_idx_ofdm_base[RF_PATH_A]);
325 tx_agc = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
326 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
327 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
328 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
329 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
330 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc);
331 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc);
332 RT_DISP(FPHY, PHY_TXPWR, ("%s: OFDM Tx-rf(A) Power = 0x%x\n", __func__, tx_agc));
333 } else if (rf_path == RF_PATH_B) {
334 pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_RATE18_06, 0xFF);
335 pwr += cali_info->power_index_offset[RF_PATH_B];
336 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_1_55_MCS32, MASKBYTE3, pwr);
337 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xff000000, pwr);
338 RT_DISP(FPHY, PHY_TXPWR, ("%s: CCK Tx-rf(B) Power = 0x%x\n", __func__, pwr));
339
340 pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_RATE18_06, 0xFF);
341 pwr += (cali_info->bb_swing_idx_ofdm[RF_PATH_B] - cali_info->bb_swing_idx_ofdm_base[RF_PATH_B]);
342 tx_agc = ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
343 odm_set_bb_reg(dm, REG_TX_AGC_B_RATE18_06, MASKDWORD, tx_agc);
344 odm_set_bb_reg(dm, REG_TX_AGC_B_RATE54_24, MASKDWORD, tx_agc);
345 odm_set_bb_reg(dm, REG_TX_AGC_B_MCS03_MCS00, MASKDWORD, tx_agc);
346 odm_set_bb_reg(dm, REG_TX_AGC_B_MCS07_MCS04, MASKDWORD, tx_agc);
347 odm_set_bb_reg(dm, REG_TX_AGC_B_MCS11_MCS08, MASKDWORD, tx_agc);
348 odm_set_bb_reg(dm, REG_TX_AGC_B_MCS15_MCS12, MASKDWORD, tx_agc);
349 RT_DISP(FPHY, PHY_TXPWR, ("%s: OFDM Tx-rf(B) Power = 0x%x\n", __func__, tx_agc));
350 }
351 #endif
352
353 #endif
354 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
355 /*phy_rf6052_set_cck_tx_power(dm->priv, *(dm->channel));
356 phy_rf6052_set_ofdm_tx_power(dm->priv, *(dm->channel));*/
357 #endif
358
359 } else if (method == BBSWING) {
360 final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
361 final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
362
363 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
364 " cali_info->default_ofdm_index=%d, cali_info->DefaultCCKIndex=%d, cali_info->absolute_ofdm_swing_idx[rf_path]=%d, cali_info->remnant_cck_swing_idx=%d rf_path = %d\n",
365 cali_info->default_ofdm_index,
366 cali_info->default_cck_index,
367 cali_info->absolute_ofdm_swing_idx[rf_path],
368 cali_info->remnant_cck_swing_idx, rf_path);
369
370 /* Adjust BB swing by OFDM IQ matrix */
371 if (final_ofdm_swing_index >= pwr_tracking_limit_ofdm)
372 final_ofdm_swing_index = pwr_tracking_limit_ofdm;
373 else if (final_ofdm_swing_index < 0)
374 final_ofdm_swing_index = 0;
375
376 if (final_cck_swing_index >= CCK_TABLE_SIZE_8723D)
377 final_cck_swing_index = CCK_TABLE_SIZE_8723D - 1;
378 else if (cali_info->bb_swing_idx_cck < 0)
379 final_cck_swing_index = 0;
380
381 set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_A,
382 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
383 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
384
385 set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_B,
386 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
387 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
388
389 set_cck_filter_coefficient_8723d(dm, final_cck_swing_index);
390
391 cali_info->modify_tx_agc_flag_path_a = true;
392
393 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
394 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, OFDM);
395 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, HT_MCS0_MCS7);
396
397 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "final_cck_swing_index=%d\n",
398 final_cck_swing_index);
399
400 } else if (method == MIX_MODE) {
401 #if (0) /*MP_DRIVER == 1*/
402 u32 tx_agc = 0; /*add by Mingzhi.Guo 2015-04-10*/
403 s32 pwr = 0;
404 #endif
405 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
406 "dm->default_ofdm_index=%d, dm->DefaultCCKIndex=%d, dm->absolute_ofdm_swing_idx[rf_path]=%d, rf_path = %d\n",
407 cali_info->default_ofdm_index,
408 cali_info->default_cck_index,
409 cali_info->absolute_ofdm_swing_idx[rf_path], rf_path);
410
411 final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
412
413 if (rf_path == RF_PATH_A) {
414 final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path]; /*CCK Follow path-A and lower CCK index means higher power.*/
415
416 if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) {
417 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
418
419 set_iqk_matrix_8723d(dm, pwr_tracking_limit_ofdm, RF_PATH_A,
420 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
421 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
422 set_iqk_matrix_8723d(dm, pwr_tracking_limit_ofdm, RF_PATH_B,
423 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
424 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
425
426 cali_info->modify_tx_agc_flag_path_a = true;
427 /*Set tx_agc Page C{};*/
428 #if 0
429 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, OFDM);*/
430 /* odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS0_MCS7);*/
431 #endif
432
433 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
434 "******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
435 pwr_tracking_limit_ofdm,
436 cali_info->remnant_ofdm_swing_idx[rf_path]);
437 } else if (final_ofdm_swing_index < 0) {
438 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
439
440 set_iqk_matrix_8723d(dm, 0, RF_PATH_A,
441 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
442 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
443 set_iqk_matrix_8723d(dm, 0, RF_PATH_B,
444 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
445 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
446
447 cali_info->modify_tx_agc_flag_path_a = true;
448
449 /*Set tx_agc Page C{};*/
450 #if 0
451 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, OFDM);*/
452 /* odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS0_MCS7);*/
453 #endif
454
455 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
456 "******Path_A Lower then BBSwing lower bound 0, Remnant tx_agc value = %d\n",
457 cali_info->remnant_ofdm_swing_idx[rf_path]);
458 } else {
459 set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_A,
460 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
461 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
462 set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_B,
463 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
464 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
465
466 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
467 "******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n",
468 final_ofdm_swing_index);
469
470 if (cali_info->modify_tx_agc_flag_path_a) {
471 cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
472
473 /*Set tx_agc Page C{};*/
474 #if 0
475 /* odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, OFDM );
476 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS0_MCS7 );
477 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, HT_MCS8_MCS15 );*/
478 #endif
479
480 cali_info->modify_tx_agc_flag_path_a = false;
481
482 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "******Path_A dm->Modify_TxAGC_Flag = false\n");
483 }
484 }
485 #if (0) /*MP_DRIVER == 1*/
486 if ((*dm->mp_mode) == 1) {
487 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
488 pwr += (cali_info->remnant_ofdm_swing_idx[RF_PATH_A] - cali_info->modify_tx_agc_value_ofdm);
489
490 if (pwr > 0x3F)
491 pwr = 0x3F;
492 else if (pwr < 0)
493 pwr = 0;
494
495 tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
496 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
497 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
498 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
499 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
500
501 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
502 "ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n",
503 tx_agc);
504 }
505 #endif
506
507 odm_set_tx_power_index_by_rate_section(dm, rf_path,
508 *dm->channel,
509 OFDM);
510 odm_set_tx_power_index_by_rate_section(dm, rf_path,
511 *dm->channel,
512 HT_MCS0_MCS7);
513 cali_info->modify_tx_agc_value_ofdm = cali_info->remnant_ofdm_swing_idx[RF_PATH_A];
514
515 if (final_cck_swing_index > pwr_tracking_limit_cck) {
516 cali_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit_cck;
517
518 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
519 "******Path_A CCK Over Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx = %d\n",
520 pwr_tracking_limit_cck,
521 cali_info->remnant_cck_swing_idx);
522
523 /* Adjust BB swing by CCK filter coefficient*/
524 odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[pwr_tracking_limit_cck]);
525
526 cali_info->modify_tx_agc_flag_path_a_cck = true;
527
528 /*Set tx_agc Page C{};*/
529 #if 0
530 /* odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, CCK);
531 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, CCK);*/
532 #endif
533
534 } else if (final_cck_swing_index < 0) {
535 cali_info->remnant_cck_swing_idx = final_cck_swing_index;
536
537 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
538 "******Path_A CCK Under Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx = %d\n",
539 0, cali_info->remnant_cck_swing_idx);
540
541 odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[0]);
542
543 cali_info->modify_tx_agc_flag_path_a_cck = true;
544
545 #if 0
546 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, CCK);
547 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, CCK);*/
548 #endif
549
550 } else {
551 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
552 "******Path_A CCK Compensate with BBSwing, final_cck_swing_index = %d\n",
553 final_cck_swing_index);
554
555 odm_set_bb_reg(dm, R_0xab4, 0x000007FF, cck_swing_table_ch1_ch14_8723d[final_cck_swing_index]);
556
557 #if 0
558 /* if (cali_info->modify_tx_agc_flag_path_a_cck) {*/
559 #endif
560 cali_info->remnant_cck_swing_idx = 0;
561
562 #if 0
563 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, hal_data->current_channel, CCK );
564 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, CCK );*/
565 #endif
566
567 cali_info->modify_tx_agc_flag_path_a_cck = false;
568
569 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
570 "******Path_A dm->Modify_TxAGC_Flag_CCK = false\n");
571 }
572 #if (0) /*MP_DRIVER == 1*/
573 if ((*dm->mp_mode)) {
574 pwr = odm_get_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, MASKBYTE1);
575 pwr += cali_info->remnant_cck_swing_idx - cali_info->modify_tx_agc_value_cck;
576
577 if (pwr > 0x3F)
578 pwr = 0x3F;
579 else if (pwr < 0)
580 pwr = 0;
581
582 odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
583 tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
584 odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc);
585 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
586 "ODM_TxPwrTrackSetPwr8723D: CCK Tx-rf(A) Power = 0x%x\n",
587 tx_agc);
588 } else
589 #endif
590
591 odm_set_tx_power_index_by_rate_section(dm, rf_path, *dm->channel, CCK);
592
593 cali_info->modify_tx_agc_value_cck = cali_info->remnant_cck_swing_idx;
594 }
595 #if 0
596 if (rf_path == RF_PATH_B) {
597 if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) {
598 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
599
600 set_iqk_matrix_8723d(dm, pwr_tracking_limit_ofdm, RF_PATH_B,
601 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
602 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
603
604 cali_info->modify_tx_agc_flag_path_a = true;
605
606
607 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, OFDM);
608 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, HT_MCS0_MCS7);*/
609
610 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
611 "******Path_B Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
612 pwr_tracking_limit_ofdm,
613 cali_info->remnant_ofdm_swing_idx[rf_path
614 ]);
615 } else if (final_ofdm_swing_index < 0) {
616 cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index ;
617
618 set_iqk_matrix_8723d(dm, 0, RF_PATH_B,
619 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
620 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
621
622 cali_info->modify_tx_agc_flag_path_a = true;
623
624
625 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, OFDM);
626 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, HT_MCS0_MCS7);*/
627
628 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
629 "******Path_B Lower then BBSwing lower bound 0, Remnant tx_agc value = %d\n",
630 cali_info->remnant_ofdm_swing_idx[rf_path
631 ]);
632 } else {
633 set_iqk_matrix_8723d(dm, final_ofdm_swing_index, RF_PATH_B,
634 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][4],
635 cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][5]);
636
637 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
638 "******Path_B Compensate with BBSwing, final_ofdm_swing_index = %d\n",
639 final_ofdm_swing_index);
640
641 if (cali_info->modify_tx_agc_flag_path_b) {
642 cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
643
644 /*odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, OFDM);
645 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, hal_data->current_channel, HT_MCS0_MCS7);*/
646
647 cali_info->modify_tx_agc_flag_path_a = false;
648
649 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "******Path_B dm->Modify_TxAGC_Flag = false\n");
650 }
651 }
652 #if (MP_DRIVER == 1)
653 if ((*dm->mp_mode) == 1) {
654 pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
655 pwr += (cali_info->remnant_ofdm_swing_idx[RF_PATH_B] - cali_info->modify_tx_agc_value_ofdm);
656
657 if (pwr > 0x3F)
658 pwr = 0x3F;
659 else if (pwr < 0)
660 pwr = 0;
661
662 tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
663 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
664 odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
665 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
666 odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
667
668 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
669 "ODM_TxPwrTrackSetPwr8723D: OFDM Tx-rf(A) Power = 0x%x\n",
670 tx_agc);
671
672 } else
673 #endif
674 {
675 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, OFDM);
676 odm_set_tx_power_index_by_rate_section(dm, RF_PATH_B, *dm->channel, HT_MCS0_MCS7);
677 }
678 cali_info->modify_tx_agc_value_ofdm = cali_info->remnant_ofdm_swing_idx[RF_PATH_B] ;
679 }
680 #endif
681 } else {
682 return;
683 }
684 }
685
get_delta_swing_table_8723d(void * dm_void,u8 ** temperature_up_a,u8 ** temperature_down_a,u8 ** temperature_up_b,u8 ** temperature_down_b)686 void get_delta_swing_table_8723d(void *dm_void, u8 **temperature_up_a,
687 u8 **temperature_down_a, u8 **temperature_up_b,
688 u8 **temperature_down_b)
689 {
690 struct dm_struct *dm = (struct dm_struct *)dm_void;
691 #if !((DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211))
692 struct _ADAPTER *adapter = dm->adapter;
693 #endif
694 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
695 struct _hal_rf_ *rf = &dm->rf_table;
696 u8 tx_rate = 0xFF;
697 u8 channel = *dm->channel;
698
699 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
700 static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
701 static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
702 #endif
703
704 if (*dm->mp_mode) {
705 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
706 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
707 #if (MP_DRIVER == 1)
708 PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
709
710 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
711 #endif
712 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
713 #ifdef CONFIG_MP_INCLUDED
714 PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
715
716 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
717 #endif
718 #endif
719 #endif
720 } else {
721 u16 rate = *dm->forced_data_rate;
722
723 if (!rate) { /*auto rate*/
724 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
725 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
726 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
727 tx_rate = dm->tx_rate;
728 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
729 if (dm->number_linked_client != 0)
730 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
731 else
732 tx_rate = rf->p_rate_index;
733 #endif
734 } else { /*force rate*/
735 tx_rate = (u8)rate;
736 }
737 }
738
739 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Power Tracking tx_rate=0x%X\n",
740 tx_rate);
741
742 if (channel >= 1 && channel <= 14) {
743 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
744 if (RX_HAL_IS_CCK_RATE(tx_rate)) {
745 #else
746 if (IS_CCK_RATE(tx_rate)) {
747 #endif
748 *temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
749 *temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
750 *temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
751 *temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
752 } else {
753 *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
754 *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
755 *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
756 *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
757 }
758 } else {
759 *temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
760 *temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
761 *temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
762 *temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
763 }
764 }
765
766 void get_delta_swing_xtal_table_8723d(void *dm_void, s8 **temperature_up_xtal,
767 s8 **temperature_down_xtal)
768 {
769 struct dm_struct *dm = (struct dm_struct *)dm_void;
770 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
771
772 *temperature_up_xtal = cali_info->delta_swing_table_xtal_p;
773 *temperature_down_xtal = cali_info->delta_swing_table_xtal_n;
774 }
775
776 void odm_txxtaltrack_set_xtal_8723d(void *dm_void)
777 {
778 struct dm_struct *dm = (struct dm_struct *)dm_void;
779 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
780 s8 crystal_cap;
781
782 crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x3F;
783 crystal_cap = crystal_cap + cali_info->xtal_offset;
784
785 if (crystal_cap < 0)
786 crystal_cap = 0;
787 else if (crystal_cap > 63)
788 crystal_cap = 63;
789
790 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
791 "crystal_cap(%d)= dm->dm_cfo_track.crystal_cap_default(%d) + cali_info->xtal_offset(%d)\n",
792 crystal_cap, dm->dm_cfo_track.crystal_cap_default, cali_info->xtal_offset);
793
794 odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
795
796 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "crystal_cap(0x2c) 0x%X\n",
797 odm_get_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000));
798 }
799
800 void configure_txpower_track_8723d(struct txpwrtrack_cfg *config)
801 {
802 config->swing_table_size_cck = CCK_TABLE_SIZE_8723D;
803 config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
804 config->threshold_iqk = IQK_THRESHOLD;
805 config->average_thermal_num = AVG_THERMAL_NUM_8723D;
806 config->rf_path_count = MAX_PATH_NUM_8723D;
807 config->thermal_reg_addr = RF_0x42;
808
809 config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr_8723d;
810 config->do_iqk = do_iqk_8723d;
811 config->phy_lc_calibrate = halrf_lck_trigger;
812 config->get_delta_swing_table = get_delta_swing_table_8723d;
813 config->get_delta_swing_xtal_table = get_delta_swing_xtal_table_8723d;
814 config->odm_txxtaltrack_set_xtal = odm_txxtaltrack_set_xtal_8723d;
815 }
816
817 #define MAX_TOLERANCE 5
818 #define IQK_DELAY_TIME 1
819
820 u8 phy_path_s1_iqk_8723d(struct dm_struct *dm, boolean config_path_s0)
821 {
822 u32 reg_eac, reg_e94, reg_e9c, path_sel_bb;
823 u8 result = 0x00, cnt;
824 u32 original_path, original_gnt;
825 u16 ktime;
826 RF_DBG(dm, DBG_RF_IQK, "[IQK]path S1 TXIQK!!\n");
827 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S1 TXIQK = 0x%x\n",
828 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
829 /*save RF path*/
830 path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
831 #if 0
832 /*RF_DBG(dm,DBG_RF_IQK, "[IQK]0x1e6@S1 TXIQK = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
833 #endif
834 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000000);
835
836 /*IQK setting*/
837 /*leave IQK mode*/
838 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
839
840 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
841 ODM_delay_us(10);
842
843 /* --- \A7\EF\BCgTXIQK mode table ---*/
844 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
845 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00004);
846 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005d);
847 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xBFFE0);
848 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
849
850 /*path-A IQK setting*/
851 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x08008c0c);
852 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
853 odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x8214019f);
854 odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160200);
855 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
856 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
857
858 /*LO calibration setting*/
859 odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x00462911);
860
861 /*PA, PAD setting*/
862 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
863 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x600, 0x0);
864 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x1E0, 0x3);
865 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8d, 0x1F, 0xf);
866
867 /*LOK setting added for 8723D*/
868 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x10, 0x1);
869 odm_set_rf_reg(dm, RF_PATH_A, RF_0x54, 0x1, 0x1);
870 #if 1
871
872 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe0d);
873 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x60d);
874 #endif
875
876 RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S1 TXIQK = 0x%x\n",
877 odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
878 RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S1 TXIQK = 0x%x\n",
879 odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
880
881 /*enter IQK mode*/
882 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
883
884 #if 1
885 /*backup path & GNT value */
886 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
887 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
888
889 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
890 ODM_delay_us(10);
891
892 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
893 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
894
895 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
896 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
897 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
898 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
899 #endif
900
901 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
902
903 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
904 ODM_delay_us(10);
905
906 RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S1 TXIQK = 0x%x\n",
907 odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
908 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S1 TXIQK = 0x%x\n",
909 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
910
911 /*One shot, path S1 LOK & IQK*/
912 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xfa000000);
913 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
914
915 /* delay x ms */
916 #if 0
917 /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
918 #endif
919
920 ktime = 0;
921 while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
922 ODM_delay_us(10);
923 ktime++;
924 }
925
926 #if 1
927 /*Restore GNT_WL/GNT_BT and path owner*/
928 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
929 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
930 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
931 #endif
932
933 /*reload RF path*/
934 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
935
936 /*leave IQK mode*/
937 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
938
939 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
940 ODM_delay_us(10);
941
942 /*PA/PAD controlled by 0x0*/
943 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
944 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
945 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
946
947 /* Check failed*/
948 reg_eac = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
949 reg_e94 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
950 reg_e9c = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
951 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
952 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
953 reg_e9c);
954 /*monitor image power before & after IQK*/
955 RF_DBG(dm, DBG_RF_IQK,
956 "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
957 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
958 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
959
960 if (!(reg_eac & BIT(28)) &&
961 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
962 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
963
964 result |= 0x01;
965 else
966 RF_DBG(dm, DBG_RF_IQK, "S1 TXIQK FAIL\n");
967 return result;
968 }
969
970 u8 phy_path_s1_rx_iqk_8723d(struct dm_struct *dm, boolean config_path_s0)
971 {
972 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp, tmp, path_sel_bb;
973 u8 result = 0x00, cnt;
974 u16 ktime;
975 u32 original_path, original_gnt;
976
977 path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
978
979 RF_DBG(dm, DBG_RF_IQK, "[IQK]path S1 RXIQK Step1!!\n");
980 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S1 RXIQK1 = 0x%x\n",
981 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
982 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000000);
983 #if 0
984 /*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S1 RXIQK1 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6)); */
985 #endif
986 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
987
988 /*IQK setting*/
989 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
990 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
991
992 /*path-A IQK setting*/
993 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x18008c1c);
994 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
995 odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
996 odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
997
998 odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82160000);
999 odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160000);
1000
1001 /*LO calibration setting*/
1002 odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a911);
1003
1004 /*modify RXIQK mode table*/
1005 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
1006 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00006);
1007 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
1008 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xa7ffb);
1009 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
1010
1011 /*---------PA/PAD=0----------*/
1012 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
1013 odm_set_rf_reg(dm, RF_PATH_A, RF_0x56, 0x600, 0x0);
1014 #if 1
1015 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe0d);
1016 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x60d);
1017 #endif
1018 RF_DBG(dm, DBG_RF_IQK, "RF0x1@ path S1 RXIQK1 = 0x%x\n",
1019 odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
1020 RF_DBG(dm, DBG_RF_IQK, "RF0x2@ path S1 RXIQK1 = 0x%x\n",
1021 odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
1022
1023 /*enter IQK mode*/
1024 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1025 #if 1
1026 /*backup path & GNT value */
1027 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
1028 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
1029
1030 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1031 ODM_delay_us(10);
1032
1033 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
1034 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
1035
1036 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
1037 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
1038 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
1039 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
1040 #endif
1041 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
1042
1043 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1044 ODM_delay_us(10);
1045
1046 RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S1 RXIQK1 = 0x%x\n",
1047 odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
1048 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S1 RXIQK1 = 0x%x\n",
1049 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
1050
1051 /*One shot, path S1 LOK & IQK*/
1052 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
1053 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
1054
1055 /*delay x ms*/
1056 #if 0
1057 /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
1058 #endif
1059
1060 ktime = 0;
1061 while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
1062 ODM_delay_us(10);
1063 ktime++;
1064 }
1065 reg_eac = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
1066 reg_e94 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
1067 reg_e9c = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
1068 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
1069 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
1070 reg_e9c);
1071 /*monitor image power before & after IQK*/
1072 RF_DBG(dm, DBG_RF_IQK,
1073 "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
1074 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
1075 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
1076 tmp = (reg_e9c & 0x03FF0000) >> 16;
1077 if ((tmp & 0x200) > 0)
1078 tmp = 0x400 - tmp;
1079
1080 if (!(reg_eac & BIT(28)) &&
1081 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1082 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) {
1083 result |= 0x01;
1084 } else {
1085 RF_DBG(dm, DBG_RF_IQK, "S1 RXIQK STEP1 FAIL\n");
1086 #if 1
1087 /*Restore GNT_WL/GNT_BT and path owner*/
1088 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
1089 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
1090 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
1091 #endif
1092 /*reload RF path*/
1093 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
1094 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1095
1096 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1097 ODM_delay_us(10);
1098
1099 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
1100 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
1101 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
1102 return result;
1103 }
1104
1105 u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
1106 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, u4tmp);
1107 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe40 = 0x%x u4tmp = 0x%x\n",
1108 odm_get_bb_reg(dm, R_0xe40, MASKDWORD), u4tmp);
1109
1110 RF_DBG(dm, DBG_RF_IQK, "[IQK]path S1 RXIQK STEP2!!\n");
1111 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S1 RXIQK2 = 0x%x\n",
1112 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
1113 #if 0
1114 /*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S1 RXIQK2 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6)); */
1115 #endif
1116 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
1117
1118 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x38008c1c);
1119 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x18008c1c);
1120 odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
1121 odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
1122
1123 odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82170000);
1124 odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28171400);
1125
1126 /*LO calibration setting*/
1127 odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a8d1);
1128
1129 /*modify RXIQK mode table*/
1130 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1131
1132 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1133 ODM_delay_us(10);
1134
1135 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
1136 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00007);
1137 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
1138 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xb3fdb);
1139 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
1140
1141 RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S1 RXIQK2 = 0x%x\n",
1142 odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
1143 RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S1 RXIQK2 = 0x%x\n",
1144 odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
1145
1146 /*enter IQK mode*/
1147 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1148
1149 #if 1
1150 /*backup path & GNT value */
1151 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
1152 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
1153
1154 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1155 ODM_delay_us(10);
1156
1157 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
1158 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
1159
1160 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
1161 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
1162 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
1163 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
1164 #endif
1165 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
1166
1167 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1168 ODM_delay_us(10);
1169
1170 RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S1 RXIQK2 = 0x%x\n",
1171 odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
1172 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S1 RXIQK2 = 0x%x\n",
1173 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
1174
1175 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
1176 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
1177
1178 /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
1179
1180 ktime = 0;
1181 while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
1182 ODM_delay_us(10);
1183 ktime++;
1184 }
1185
1186 #if 1
1187 /*Restore GNT_WL/GNT_BT and path owner*/
1188 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
1189 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
1190 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
1191 #endif
1192 /*reload RF path*/
1193 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
1194
1195 /*leave IQK mode*/
1196 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1197
1198 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1199 ODM_delay_us(10);
1200
1201 /* PA/PAD controlled by 0x0*/
1202 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
1203 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
1204 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
1205
1206 reg_eac = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
1207 reg_ea4 = odm_get_bb_reg(dm, R_0xea4, MASKDWORD);
1208 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
1209 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", reg_ea4,
1210 reg_eac);
1211
1212 RF_DBG(dm, DBG_RF_IQK,
1213 "[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
1214 odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
1215 odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
1216
1217 tmp = (reg_eac & 0x03FF0000) >> 16;
1218 if ((tmp & 0x200) > 0)
1219 tmp = 0x400 - tmp;
1220
1221 if (!(reg_eac & BIT(27)) && /*if Tx is OK, check whether Rx is OK*/
1222 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1223 (((reg_eac & 0x03FF0000) >> 16) != 0x36) &&
1224 (((reg_ea4 & 0x03FF0000) >> 16) < 0x11a) &&
1225 (((reg_ea4 & 0x03FF0000) >> 16) > 0xe6) &&
1226 tmp < 0x1a)
1227 result |= 0x02;
1228 else
1229 RF_DBG(dm, DBG_RF_IQK, "S1 RXIQK STEP2 FAIL\n");
1230 return result;
1231 }
1232
1233 u8 phy_path_s0_iqk_8723d(struct dm_struct *dm)
1234 {
1235 u32 reg_e94_s0, reg_e9c_s0, reg_eac_s0, path_sel_bb;
1236 u8 result = 0x00, cnt;
1237 u16 ktime;
1238 u32 original_path, original_gnt;
1239
1240 RF_DBG(dm, DBG_RF_IQK, "path S0 TXIQK!\n");
1241 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S0 TXIQK = 0x%x\n",
1242 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
1243 path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
1244
1245 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000280); /*10 od 0x948 0x1 [7] ; WL:S1 to S0;BT:S0 to S1;*/
1246 #if 0
1247 /*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S0 TXIQK = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
1248 #endif
1249
1250 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1251
1252 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1253 ODM_delay_us(10);
1254
1255 /*modify TXIQK mode table*/
1256 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x80000);
1257 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00004);
1258 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005d);
1259 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xBFFE0);
1260 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x00000);
1261
1262 /*path-A IQK setting*/
1263 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x08008c0c);
1264 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
1265 odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x8214018a);
1266 odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160200);
1267 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
1268 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
1269
1270 /*LO calibration setting*/
1271 odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x00462911);
1272
1273 /*PA, PAD setting*/
1274 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x1);
1275 odm_set_rf_reg(dm, RF_PATH_A, RF_0x66, 0x600, 0x0);
1276 odm_set_rf_reg(dm, RF_PATH_A, RF_0x66, 0x1E0, 0x3);
1277 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8d, 0x1F, 0xf);
1278
1279 /*LOK setting added for 8723D*/
1280 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x10, 0x1);
1281 odm_set_rf_reg(dm, RF_PATH_A, RF_0x64, 0x1, 0x1);
1282
1283 #if 1
1284 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe6d);
1285 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x66d);
1286 #endif
1287
1288 RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S0 TXIQK = 0x%x\n",
1289 odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
1290 RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S0 TXIQK = 0x%x\n",
1291 odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
1292 /*enter IQK mode*/
1293 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1294 #if 1
1295 /*backup path & GNT value */
1296 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
1297 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
1298
1299 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1300 ODM_delay_us(10);
1301
1302 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
1303 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
1304
1305 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
1306 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
1307 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
1308 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
1309 #endif
1310 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
1311
1312 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1313 ODM_delay_us(10);
1314
1315 RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S0 TXIQK = 0x%x\n",
1316 odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
1317 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S0 TXIQK = 0x%x\n",
1318 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
1319
1320 /*One shot, path S1 LOK & IQK*/
1321 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
1322 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
1323
1324 /*delay x ms*/
1325 #if 0
1326 /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
1327 #endif
1328
1329 ktime = 0;
1330 while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
1331 ODM_delay_us(10);
1332 ktime++;
1333 }
1334 #if 1
1335 /*Restore GNT_WL/GNT_BT and path owner*/
1336 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
1337 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
1338 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
1339 #endif
1340 /*reload RF path*/
1341 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
1342 /*leave IQK mode*/
1343 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1344
1345 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1346 ODM_delay_us(10);
1347
1348 /*PA/PAD controlled by 0x0*/
1349 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x0);
1350 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
1351 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
1352 /* Check failed*/
1353 reg_eac_s0 = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
1354 reg_e94_s0 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
1355 reg_e9c_s0 = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
1356 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac_s0 = 0x%x\n", reg_eac_s0);
1357 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n",
1358 reg_e94_s0, reg_e9c_s0);
1359 /*monitor image power before & after IQK*/
1360 RF_DBG(dm, DBG_RF_IQK,
1361 "[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n",
1362 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
1363 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
1364 if (!(reg_eac_s0 & BIT(28)) &&
1365 (((reg_e94_s0 & 0x03FF0000) >> 16) != 0x142) &&
1366 (((reg_e9c_s0 & 0x03FF0000) >> 16) != 0x42))
1367
1368 result |= 0x01;
1369 else
1370 RF_DBG(dm, DBG_RF_IQK, "S0 TXIQK FAIL\n");
1371
1372 return result;
1373 }
1374
1375 u8 phy_path_s0_rx_iqk_8723d(struct dm_struct *dm, boolean config_path_s0)
1376 {
1377 u32 reg_e94_s0, reg_e9c_s0, reg_ea4_s0, reg_eac_s0, tmp, u4tmp;
1378 u32 path_sel_bb;
1379 u8 result = 0x00, cnt;
1380 u16 ktime;
1381 u32 original_path, original_gnt;
1382
1383 path_sel_bb = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
1384 RF_DBG(dm, DBG_RF_IQK, "path S0 RxIQK Step1!!\n");
1385 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S0 RXIQK1 = 0x%x\n",
1386 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
1387 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x99000280);
1388 #if 0
1389 /*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S0 RXIQK1 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
1390 #endif
1391
1392 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1393
1394 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
1395 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
1396
1397 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x18008c1c);
1398 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x38008c1c);
1399 odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
1400 odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
1401
1402 odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82160000);
1403 odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28160000);
1404
1405 odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a911);
1406
1407 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x80000);
1408 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00006);
1409 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
1410 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xa7ffb);
1411 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x00000);
1412
1413 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x1);
1414 odm_set_rf_reg(dm, RF_PATH_A, RF_0x66, 0x600, 0x0);
1415
1416 #if 1
1417 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, 0xe6d);
1418 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK, 0x66d);
1419 #endif
1420
1421 RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S0 RXIQK1 = 0x%x\n",
1422 odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
1423 RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S0 RXIQK1 = 0x%x\n",
1424 odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
1425
1426 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1427
1428 #if 1
1429 /*backup path & GNT value */
1430 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
1431 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
1432
1433 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1434 ODM_delay_us(10);
1435
1436 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
1437 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
1438
1439 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
1440 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
1441 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
1442 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
1443 #endif
1444 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
1445
1446 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1447 ODM_delay_us(10);
1448
1449 RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S0 RXIQK1 = 0x%x\n",
1450 odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
1451 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S0 RXIQK1 = 0x%x\n",
1452 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
1453
1454 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
1455 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
1456
1457 #if 0
1458 /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
1459 #endif
1460 ktime = 0;
1461 while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
1462 ODM_delay_us(10);
1463 ktime++;
1464 }
1465 reg_eac_s0 = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
1466 reg_e94_s0 = odm_get_bb_reg(dm, R_0xe94, MASKDWORD);
1467 reg_e9c_s0 = odm_get_bb_reg(dm, R_0xe9c, MASKDWORD);
1468 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac_s0 = 0x%x\n", reg_eac_s0);
1469 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94_s0 = 0x%x, 0xe9c_s0 = 0x%x\n",
1470 reg_e94_s0, reg_e9c_s0);
1471 /*monitor image power before & after IQK*/
1472 RF_DBG(dm, DBG_RF_IQK,
1473 "[IQK]0xe90_s0(before IQK)= 0x%x, 0xe98_s0(afer IQK) = 0x%x\n",
1474 odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
1475 odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
1476
1477 tmp = (reg_e9c_s0 & 0x03FF0000) >> 16;
1478 if ((tmp & 0x200) > 0)
1479 tmp = 0x400 - tmp;
1480
1481 if (!(reg_eac_s0 & BIT(28)) &&
1482 (((reg_e94_s0 & 0x03FF0000) >> 16) != 0x142) &&
1483 (((reg_e9c_s0 & 0x03FF0000) >> 16) != 0x42)) {
1484 result |= 0x01;
1485 } else {
1486 RF_DBG(dm, DBG_RF_IQK, "S0 RXIQK STEP1 FAIL\n");
1487 #if 1
1488 /*Restore GNT_WL/GNT_BT and path owner*/
1489 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
1490 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
1491 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
1492 #endif
1493 /*reload RF path*/
1494 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
1495 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1496
1497 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1498 ODM_delay_us(10);
1499
1500 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x0);
1501 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
1502 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
1503 return result;
1504 }
1505
1506 u4tmp = 0x80007C00 | (reg_e94_s0 & 0x3FF0000) | ((reg_e9c_s0 & 0x3FF0000) >> 16);
1507 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, u4tmp);
1508 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe40_s0 = 0x%x u4tmp = 0x%x\n",
1509 odm_get_bb_reg(dm, R_0xe40, MASKDWORD), u4tmp);
1510
1511 RF_DBG(dm, DBG_RF_IQK, "[IQK]path S0 RXIQK STEP2!!\n\n");
1512 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x67 @S0 RXIQK2 = 0x%x\n",
1513 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
1514 #if 0
1515 /*RF_DBG(dm,DBG_RF_INIT, "[IQK]0x1e6@S0 RXIQK2 = 0x%x\n", platform_efio_read_1byte(adapter, 0x1e6));*/
1516 #endif
1517 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
1518
1519 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x38008c1c);
1520 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x18008c1c);
1521 odm_set_bb_reg(dm, R_0xe50, MASKDWORD, 0x38008c1c);
1522 odm_set_bb_reg(dm, R_0xe54, MASKDWORD, 0x38008c1c);
1523
1524 odm_set_bb_reg(dm, R_0xe38, MASKDWORD, 0x82170000);
1525 odm_set_bb_reg(dm, R_0xe3c, MASKDWORD, 0x28171400);
1526
1527 odm_set_bb_reg(dm, R_0xe4c, MASKDWORD, 0x0046a8d1);
1528
1529 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1530
1531 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1532 ODM_delay_us(10);
1533
1534 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, 0x80000, 0x1);
1535 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00007);
1536 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0005f);
1537 odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xb3fdb);
1538 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x00000);
1539
1540 RF_DBG(dm, DBG_RF_IQK, "RF0x1 @S0 RXIQK2 = 0x%x\n",
1541 odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
1542 RF_DBG(dm, DBG_RF_IQK, "RF0x2 @S0 RXIQK2 = 0x%x\n",
1543 odm_get_rf_reg(dm, RF_PATH_A, RF_0x2, RFREGOFFSETMASK));
1544 /*enter IQK mode*/
1545 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1546 #if 1
1547 /*backup path & GNT value */
1548 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
1549 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
1550
1551 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1552 ODM_delay_us(10);
1553
1554 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
1555 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n", original_gnt);
1556
1557 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
1558 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
1559 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
1560 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
1561 #endif
1562 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0054);
1563
1564 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1565 ODM_delay_us(10);
1566
1567 RF_DBG(dm, DBG_RF_IQK, "[IQK]GNT_BT @S0 RXIQK2 = 0x%x\n",
1568 odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD));
1569 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x948 @S0 RXIQK2 = 0x%x\n",
1570 odm_get_bb_reg(dm, R_0x948, MASKDWORD));
1571
1572 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf9000000);
1573 odm_set_bb_reg(dm, R_0xe48, MASKDWORD, 0xf8000000);
1574
1575 #if 0
1576 /*ODM_delay_ms(IQK_DELAY_TIME_8723D);*/
1577 #endif
1578 ktime = 0;
1579 while ((!odm_get_bb_reg(dm, R_0xeac, BIT(26))) && ktime < 1000) {
1580 ODM_delay_us(1);
1581 ktime++;
1582 }
1583 #if 1
1584 /*Restore GNT_WL/GNT_BT and path owner*/
1585 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
1586 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
1587 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
1588 #endif
1589 /*reload RF path*/
1590 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb);
1591
1592 /*leave IQK mode*/
1593 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1594
1595 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1596 ODM_delay_us(10);
1597
1598 odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, 0x800, 0x0);
1599 odm_set_rf_reg(dm, RF_PATH_A, RF_0x2, BIT(0), 0x0);
1600 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, BIT(0), 0x0);
1601
1602 reg_eac_s0 = odm_get_bb_reg(dm, R_0xeac, MASKDWORD);
1603 reg_ea4_s0 = odm_get_bb_reg(dm, R_0xea4, MASKDWORD);
1604 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac_s0 = 0x%x\n", reg_eac_s0);
1605 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xea4_s0 = 0x%x, 0xeac_s0 = 0x%x\n",
1606 reg_ea4_s0, reg_eac_s0);
1607
1608 RF_DBG(dm, DBG_RF_IQK,
1609 "[IQK]0xea0_s0(before IQK)= 0x%x, 0xea8_s0(afer IQK) = 0x%x\n",
1610 odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
1611 odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
1612
1613 tmp = (reg_eac_s0 & 0x03FF0000) >> 16;
1614 if ((tmp & 0x200) > 0)
1615 tmp = 0x400 - tmp;
1616
1617 if (!(reg_eac_s0 & BIT(27)) && /*if Tx is OK, check whether Rx is OK*/
1618 (((reg_ea4_s0 & 0x03FF0000) >> 16) != 0x132) &&
1619 (((reg_eac_s0 & 0x03FF0000) >> 16) != 0x36) &&
1620 (((reg_ea4_s0 & 0x03FF0000) >> 16) < 0x11a) &&
1621 (((reg_ea4_s0 & 0x03FF0000) >> 16) > 0xe6) &&
1622 tmp < 0x1a)
1623 result |= 0x02;
1624 else
1625 RF_DBG(dm, DBG_RF_IQK, "S0 RXIQK STEP2 FAIL\n");
1626 return result;
1627 }
1628
1629 void _phy_path_s1_fill_iqk_matrix_8723d(struct dm_struct *dm, boolean is_iqk_ok,
1630 s32 result[][8], u8 final_candidate,
1631 boolean is_tx_only)
1632 {
1633 u32 oldval_1, X, TX1_A, reg;
1634 s32 Y, TX1_C;
1635 RF_DBG(dm, DBG_RF_IQK, "path S1 IQ Calibration %s !\n",
1636 (is_iqk_ok) ? "Success" : "Failed");
1637
1638 if (final_candidate == 0xFF)
1639 return;
1640
1641 if (is_iqk_ok) {
1642 oldval_1 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
1643
1644 X = result[final_candidate][0];
1645
1646 if ((X & 0x00000200) != 0)
1647 X = X | 0xFFFFFC00;
1648 TX1_A = (X * oldval_1) >> 8;
1649 RF_DBG(dm, DBG_RF_IQK,
1650 "X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", X, TX1_A,
1651 oldval_1);
1652 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x3FF, TX1_A);
1653
1654 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(31), ((X * oldval_1 >> 7) & 0x1));
1655
1656 Y = result[final_candidate][1];
1657 if ((Y & 0x00000200) != 0)
1658 Y = Y | 0xFFFFFC00;
1659
1660 TX1_C = (Y * oldval_1) >> 8;
1661 RF_DBG(dm, DBG_RF_IQK, "Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C);
1662 odm_set_bb_reg(dm, R_0xc94, 0xF0000000, ((TX1_C & 0x3C0) >> 6));
1663 odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x003F0000, (TX1_C & 0x3F));
1664
1665 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, BIT(29), ((Y * oldval_1 >> 7) & 0x1));
1666
1667 if (is_tx_only) {
1668 RF_DBG(dm, DBG_RF_IQK, "%s only Tx OK\n", __func__);
1669 return;
1670 }
1671 reg = result[final_candidate][2];
1672 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1673 if (RTL_ABS(reg, 0x100) >= 16)
1674 reg = 0x100;
1675 #endif
1676 odm_set_bb_reg(dm, R_0xc14, 0x3FF, reg);
1677
1678 reg = result[final_candidate][3] & 0x3F;
1679 odm_set_bb_reg(dm, R_0xc14, 0xFC00, reg);
1680
1681 reg = (result[final_candidate][3] >> 6) & 0xF;
1682 odm_set_bb_reg(dm, R_0xca0, 0xF0000000, reg);
1683
1684 /* 10 os 7201 10
1685 * 10 id ea4 [25:16] p
1686 * 10 os 7202 10
1687 * 10 od c14 VarFromTmp [9:0] p
1688 *
1689 * 10 os 7201 11
1690 * 10 id eac [25:22] p
1691 * 10 os 7202 11
1692 * 10 od ca0 VarFromTmp [31:28] p
1693 *
1694 * 10 os 7201 12
1695 * 10 id eac [21:16] p
1696 * 10 os 7202 12
1697 * 10 od c14 VarFromTmp [15:10] p
1698 */
1699 }
1700 }
1701
1702 void _phy_path_s0_fill_iqk_matrix_8723d(struct dm_struct *dm, boolean is_iqk_ok,
1703 s32 result[][8], u8 final_candidate,
1704 boolean is_tx_only)
1705 {
1706 u32 oldval_0, X, TX0_A, reg;
1707 s32 Y, TX0_C;
1708 RF_DBG(dm, DBG_RF_IQK, "path S0 IQ Calibration %s !\n",
1709 (is_iqk_ok) ? "Success" : "Failed");
1710
1711 if (final_candidate == 0xFF)
1712 return;
1713
1714 if (is_iqk_ok) {
1715 oldval_0 = (odm_get_bb_reg(dm, R_0xcd4, MASKDWORD) >> 13) & 0x3FF;
1716
1717 X = result[final_candidate][4];
1718 if ((X & 0x00000200) != 0)
1719 X = X | 0xFFFFFC00;
1720 TX0_A = (X * oldval_0) >> 8;
1721 RF_DBG(dm, DBG_RF_IQK,
1722 "X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A,
1723 oldval_0);
1724 odm_set_bb_reg(dm, R_0xcd0, 0x7FE, TX0_A);
1725
1726 odm_set_bb_reg(dm, R_0xcd0, BIT(0), ((X * oldval_0 >> 7) & 0x1));
1727
1728 Y = result[final_candidate][5];
1729 if ((Y & 0x00000200) != 0)
1730 Y = Y | 0xFFFFFC00;
1731
1732 TX0_C = (Y * oldval_0) >> 8;
1733 RF_DBG(dm, DBG_RF_IQK, "Y = 0x%x, TX0_C = 0x%x\n", Y, TX0_C);
1734 odm_set_bb_reg(dm, R_0xcd4, 0x7FE, (TX0_C & 0x3FF));
1735
1736 odm_set_bb_reg(dm, R_0xcd4, BIT(0), ((Y * oldval_0 >> 7) & 0x1));
1737
1738 if (is_tx_only)
1739 return;
1740
1741 reg = result[final_candidate][6];
1742 odm_set_bb_reg(dm, R_0xcd8, 0x3FF, reg);
1743
1744 reg = result[final_candidate][7];
1745 odm_set_bb_reg(dm, R_0xcd8, 0x003FF000, reg);
1746
1747 /*10 os 7201 10
1748 *10 id ea4 [25:16] p
1749 *10 os 7202 10
1750 *10 od cd8 VarFromTmp [9:0] p
1751 *
1752 *10 os 7201 11
1753 *10 id eac [25:16] p
1754 *10 os 7202 11
1755 *10 od cd8 VarFromTmp [21:12] p
1756 * rege94_s1 = result[i][0];
1757 * rege9c_s1 = result[i][1];
1758 * regea4_s1 = result[i][2];
1759 * regeac_s1 = result[i][3];
1760 * rege94_s0 = result[i][4];
1761 * rege9c_s0 = result[i][5];
1762 * regea4_s0 = result[i][6];
1763 * regeac_s0 = result[i][7];
1764 */
1765 }
1766 }
1767
1768 void _phy_save_adda_registers_8723d(struct dm_struct *dm, u32 *adda_reg,
1769 u32 *adda_backup, u32 register_num)
1770 {
1771 u32 i;
1772
1773 for (i = 0; i < register_num; i++)
1774 adda_backup[i] = odm_get_bb_reg(dm, adda_reg[i], MASKDWORD);
1775 }
1776
1777 void _phy_save_mac_registers_8723d(struct dm_struct *dm, u32 *mac_reg,
1778 u32 *mac_backup)
1779 {
1780 u32 i;
1781
1782 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1783 mac_backup[i] = odm_read_1byte(dm, mac_reg[i]);
1784 mac_backup[i] = odm_read_4byte(dm, mac_reg[i]);
1785 }
1786
1787 void _phy_reload_adda_registers_8723d(struct dm_struct *dm, u32 *adda_reg,
1788 u32 *adda_backup, u32 regiester_num)
1789 {
1790 u32 i;
1791
1792 RF_DBG(dm, DBG_RF_IQK, "Reload ADDA power saving parameters !\n");
1793 for (i = 0; i < regiester_num; i++)
1794 odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, adda_backup[i]);
1795 }
1796
1797 void _phy_reload_mac_registers_8723d(struct dm_struct *dm, u32 *mac_reg,
1798 u32 *mac_backup)
1799 {
1800 u32 i;
1801
1802 RF_DBG(dm, DBG_RF_IQK, "Reload MAC parameters !\n");
1803 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1804 odm_write_1byte(dm, mac_reg[i], (u8)mac_backup[i]);
1805 odm_write_4byte(dm, mac_reg[i], mac_backup[i]);
1806 }
1807
1808 void _phy_path_adda_on_8723d(struct dm_struct *dm, u32 *adda_reg,
1809 boolean is_path_a_on, boolean is2T)
1810 {
1811 u32 path_on;
1812 u32 i;
1813
1814 path_on = is_path_a_on ? 0x03c00016 : 0x03c00016;
1815
1816 if (!is2T) {
1817 path_on = 0x03c00016;
1818 odm_set_bb_reg(dm, adda_reg[0], MASKDWORD, 0x03c00016);
1819 } else {
1820 odm_set_bb_reg(dm, adda_reg[0], MASKDWORD, path_on);
1821 }
1822
1823 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1824 odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, path_on);
1825 }
1826
1827 void _phy_mac_setting_calibration_8723d(struct dm_struct *dm, u32 *mac_reg,
1828 u32 *mac_backup)
1829 {
1830 #if 0
1831 /*
1832 odm_write_1byte(dm, mac_reg[i], 0x3F);
1833
1834 for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
1835 odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i]&(~BIT(3))));
1836 }
1837 odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i]&(~BIT(5))));
1838 */
1839
1840 /*odm_set_bb_reg(dm, R_0x522, MASKBYTE0, 0x7f);*/
1841 /*odm_set_bb_reg(dm, R_0x550, MASKBYTE0, 0x15);*/
1842 /*odm_set_bb_reg(dm, R_0x551, MASKBYTE0, 0x00);*/
1843 #endif
1844 odm_set_bb_reg(dm, R_0x520, 0x00ff0000, 0xff);
1845 }
1846
1847 void _phy_path_a_stand_by_8723d(struct dm_struct *dm)
1848 {
1849 u8 cnt;
1850
1851 RF_DBG(dm, DBG_RF_IQK, "path-S1 standby mode!\n");
1852 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1853 #if 0
1854 /* odm_set_bb_reg(dm, R_0x840, MASKDWORD, 0x00010000);*/
1855 #endif
1856
1857 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1858 ODM_delay_us(10);
1859
1860 odm_set_rf_reg(dm, (enum rf_path)0x0, RF_0x0, RFREGOFFSETMASK, 0x10000);
1861 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1862 }
1863
1864 void _phy_path_b_stand_by_8723d(struct dm_struct *dm)
1865 {
1866 u8 cnt;
1867
1868 RF_DBG(dm, DBG_RF_IQK, "path-S0 standby mode!\n");
1869 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
1870
1871 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
1872 ODM_delay_us(10);
1873
1874 odm_set_rf_reg(dm, (enum rf_path)0x1, RF_0x0, RFREGOFFSETMASK, 0x10000);
1875 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
1876 }
1877
1878 void _phy_pi_mode_switch_8723d(struct dm_struct *dm, boolean pi_mode)
1879 {
1880 u32 mode;
1881
1882 mode = pi_mode ? 0x01000100 : 0x01000000;
1883 odm_set_bb_reg(dm, R_0x820, MASKDWORD, mode);
1884 odm_set_bb_reg(dm, R_0x828, MASKDWORD, mode);
1885 }
1886
1887 boolean
1888 phy_simularity_compare_8723d(struct dm_struct *dm, s32 result[][8], u8 c1,
1889 u8 c2, boolean is2t)
1890 {
1891 u32 i, j, diff, simularity_bit_map, bound = 0;
1892 u8 final_candidate[2] = {0xFF, 0xFF};
1893 boolean is_result = true;
1894 #if 0
1895 /*#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)*/
1896 /* bool is2T = IS_92C_SERIAL( hal_data->version_id);*/
1897 /*#else*/
1898 #endif
1899 #if 0
1900 /*#endif*/
1901 #endif
1902
1903 s32 tmp1 = 0, tmp2 = 0;
1904
1905 if (is2t)
1906 bound = 8;
1907 else
1908 bound = 4;
1909
1910 RF_DBG(dm, DBG_RF_IQK, "===> IQK:%s c1 %d c2 %d!!!\n", __func__, c1,
1911 c2);
1912
1913 simularity_bit_map = 0;
1914
1915 for (i = 0; i < bound; i++) {
1916 if (i == 1 || i == 3 || i == 5 || i == 7) {
1917 if ((result[c1][i] & 0x00000200) != 0)
1918 tmp1 = result[c1][i] | 0xFFFFFC00;
1919 else
1920 tmp1 = result[c1][i];
1921
1922 if ((result[c2][i] & 0x00000200) != 0)
1923 tmp2 = result[c2][i] | 0xFFFFFC00;
1924 else
1925 tmp2 = result[c2][i];
1926 } else {
1927 tmp1 = result[c1][i];
1928 tmp2 = result[c2][i];
1929 }
1930
1931 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1932
1933 if (diff > MAX_TOLERANCE) {
1934 RF_DBG(dm, DBG_RF_IQK,
1935 "IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",
1936 diff, i, result[c1][i], result[c2][i]);
1937
1938 if ((i == 2 || i == 6) && !simularity_bit_map) {
1939 if (result[c1][i] + result[c1][i + 1] == 0)
1940 final_candidate[(i / 4)] = c2;
1941 else if (result[c2][i] + result[c2][i + 1] == 0)
1942 final_candidate[(i / 4)] = c1;
1943 else
1944 simularity_bit_map = simularity_bit_map | (1 << i);
1945 } else {
1946 simularity_bit_map = simularity_bit_map | (1 << i);
1947 }
1948 }
1949 }
1950
1951 RF_DBG(dm, DBG_RF_IQK, "IQK:%s simularity_bit_map %x !!!\n", __func__,
1952 simularity_bit_map);
1953
1954 if (simularity_bit_map == 0) {
1955 for (i = 0; i < (bound / 4); i++) {
1956 if (final_candidate[i] != 0xFF) {
1957 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1958 result[3][j] = result[final_candidate[i]][j];
1959 is_result = false;
1960 }
1961 }
1962 return is_result;
1963 }
1964
1965 if (!(simularity_bit_map & 0x03)) {
1966 for (i = 0; i < 2; i++)
1967 result[3][i] = result[c1][i];
1968 }
1969
1970 if (!(simularity_bit_map & 0x0c)) {
1971 for (i = 2; i < 4; i++)
1972 result[3][i] = result[c1][i];
1973 }
1974
1975 if (!(simularity_bit_map & 0x30)) {
1976 for (i = 4; i < 6; i++)
1977 result[3][i] = result[c1][i];
1978 }
1979
1980 if (!(simularity_bit_map & 0xc0)) {
1981 for (i = 6; i < 8; i++)
1982 result[3][i] = result[c1][i];
1983 }
1984
1985 return false;
1986 }
1987
1988 void _phy_check_coex_status_8723d(struct dm_struct *dm, boolean beforek)
1989 {
1990 #if MP_DRIVER != 1
1991 u8 u1b_tmp;
1992 u16 count = 0;
1993 u8 h2c_parameter;
1994
1995 if (beforek) {
1996 /* Set H2C cmd to inform FW (enable). */
1997 h2c_parameter = 1;
1998 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1999 /* Check 0x1e6 or 100ms timeout*/
2000 count = 0;
2001 u1b_tmp = odm_read_1byte(dm, 0x1e6);
2002 while (u1b_tmp != 0x1 && count < 5000) {
2003 ODM_delay_us(20);
2004 u1b_tmp = odm_read_1byte(dm, 0x1e6);
2005 count++;
2006 }
2007
2008 if (count >= 5000)
2009 RF_DBG(dm, DBG_RF_INIT,
2010 "[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)",
2011 count);
2012
2013 /* Wait BT IQK finished. */
2014 /* polling 0x1e7[0]=1 or 600ms timeout */
2015 count = 0;
2016 u1b_tmp = odm_read_1byte(dm, 0x1e7);
2017 while ((!(u1b_tmp & BIT(0))) && count < 30000) {
2018 ODM_delay_us(20);
2019 u1b_tmp = odm_read_1byte(dm, 0x1e7);
2020 count++;
2021 }
2022
2023 if (count >= 30000)
2024 RF_DBG(dm, DBG_RF_INIT,
2025 "[IQK]Waiting BT IQK finish time out! count(%d)",
2026 count);
2027 } else {
2028 /* Set H2C cmd to inform FW (disable). */
2029 h2c_parameter = 0;
2030 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
2031 /* Check 0x1e6 or 100ms timeout*/
2032 count = 0;
2033 u1b_tmp = odm_read_1byte(dm, 0x1e6);
2034 while (u1b_tmp != 0 && count < 5000) {
2035 ODM_delay_us(20);
2036 u1b_tmp = odm_read_1byte(dm, 0x1e6);
2037 count++;
2038 }
2039
2040 if (count >= 1000)
2041 RF_DBG(dm, DBG_RF_INIT,
2042 "[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)",
2043 count);
2044 }
2045 #endif
2046 }
2047
2048 void _phy_iq_calibrate_8723d(struct dm_struct *dm, s32 result[][8], u8 t,
2049 boolean is2T)
2050 {
2051 u32 i;
2052 u8 path_s1_ok = 0x0, path_s0_ok = 0x0, cnt;
2053 u8 tmp0xc50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
2054 u8 tmp0xc58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
2055 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
2056 R_0x85c, R_0xe6c,
2057 R_0xe70, R_0xe74,
2058 R_0xe78, R_0xe7c,
2059 R_0xe80, R_0xe84,
2060 R_0xe88, R_0xe8c,
2061 R_0xed0, R_0xed4,
2062 R_0xed8, R_0xedc,
2063 R_0xee0, R_0xeec};
2064 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
2065 R_0x522, R_0x550,
2066 R_0x551, R_0x40};
2067
2068 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
2069 R_0xc04, R_0xc08,
2070 R_0x874, R_0xb68, R_0xb6c,
2071 R_0x870, R_0x860,
2072 R_0x864, R_0xa04};
2073 u32 cnt_iqk_fail = 0;
2074 u32 retry_count;
2075
2076 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2077 retry_count = 2;
2078 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2079 #if MP_DRIVER
2080 retry_count = 9;
2081 #else
2082 retry_count = 2;
2083 #endif
2084 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
2085 if (*dm->mp_mode)
2086 retry_count = 9;
2087 else
2088 retry_count = 2;
2089 #endif
2090
2091 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2092 #ifdef MP_TEST
2093 if (*dm->mp_mode)
2094 retry_count = 9;
2095 #endif
2096 #endif
2097
2098 if (t == 0) {
2099 _phy_save_adda_registers_8723d(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
2100 _phy_save_mac_registers_8723d(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
2101 _phy_save_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
2102 }
2103 RF_DBG(dm, DBG_RF_IQK, "IQ Calibration for 1T1R_S0/S1 for %d times\n",
2104 t);
2105
2106 _phy_path_adda_on_8723d(dm, ADDA_REG, true, is2T);
2107 #if 0
2108 if (t == 0)
2109 dm->rf_calibrate_info.is_rf_pi_enable = (u8)odm_get_bb_reg(dm, R_0x820, BIT(8));
2110
2111 if (!dm->rf_calibrate_info.is_rf_pi_enable) {
2112 /* Switch BB to PI mode to do IQ Calibration. */
2113 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2114 _phy_pi_mode_switch_8723d(adapter, true);
2115 #else
2116 _phy_pi_mode_switch_8723d(dm, true);
2117 #endif
2118 }
2119 #endif
2120 _phy_mac_setting_calibration_8723d(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
2121 /*BB setting*/
2122 #if 0
2123 /*odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT24, 0x00);*/
2124 #endif
2125 odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0xf);
2126 odm_set_bb_reg(dm, R_0xc04, MASKDWORD, 0x03a05611);
2127 odm_set_bb_reg(dm, R_0xc08, MASKDWORD, 0x000800e4);
2128 odm_set_bb_reg(dm, R_0x874, MASKDWORD, 0x25204200);
2129
2130 /*IQ calibration setting*/
2131 #if 0
2132 /*RF_DBG(dm,DBG_RF_IQK, "IQK setting!\n"); */
2133 #endif
2134 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
2135 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
2136 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
2137
2138 if (is2T) {
2139 _phy_path_b_stand_by_8723d(dm);
2140 _phy_path_adda_on_8723d(dm, ADDA_REG, false, is2T);
2141 }
2142
2143 #if 1
2144 for (i = 0; i < retry_count; i++) {
2145 path_s1_ok = phy_path_s1_iqk_8723d(dm, is2T);
2146 if (path_s1_ok == 0x01) {
2147 RF_DBG(dm, DBG_RF_IQK, "path S1 Tx IQK Success!!\n");
2148 result[t][0] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD) & 0x3FF0000) >> 16;
2149 result[t][1] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
2150 break;
2151 }
2152
2153 RF_DBG(dm, DBG_RF_IQK, "path S1 Tx IQK Fail!!\n");
2154 result[t][0] = 0x100;
2155 result[t][1] = 0x0;
2156 cnt_iqk_fail++;
2157 #if 0
2158 else if (i == (retry_count - 1) && path_s1_ok == 0x01) {
2159 RT_DISP(FINIT, INIT_IQK, ("path S1 IQK Only Tx Success!!\n"));
2160
2161 result[t][0] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD) & 0x3FF0000) >> 16;
2162 result[t][1] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
2163 }
2164 #endif
2165 }
2166 #endif
2167 #if 1
2168 for (i = 0; i < retry_count; i++) {
2169 path_s1_ok = phy_path_s1_rx_iqk_8723d(dm, is2T);
2170 if (path_s1_ok == 0x03) {
2171 RF_DBG(dm, DBG_RF_IQK, "path S1 Rx IQK Success!!\n");
2172 result[t][2] = (odm_get_bb_reg(dm, R_0xea4, MASKDWORD) & 0x3FF0000) >> 16;
2173 result[t][3] = (odm_get_bb_reg(dm, R_0xeac, MASKDWORD) & 0x3FF0000) >> 16;
2174 break;
2175 }
2176
2177 RF_DBG(dm, DBG_RF_IQK, "path S1 Rx IQK Fail!!\n");
2178 result[t][2] = 0x100;
2179 result[t][3] = 0x0;
2180 cnt_iqk_fail++;
2181 }
2182
2183 if (path_s1_ok == 0x00)
2184 RF_DBG(dm, DBG_RF_IQK, "path S1 IQK failed!!\n");
2185 #endif
2186 if (is2T) {
2187 _phy_path_a_stand_by_8723d(dm);
2188 _phy_path_adda_on_8723d(dm, ADDA_REG, false, is2T);
2189
2190 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x808000);
2191 odm_set_bb_reg(dm, R_0xe40, MASKDWORD, 0x01007c00);
2192 odm_set_bb_reg(dm, R_0xe44, MASKDWORD, 0x01004800);
2193
2194 #if 1
2195 for (i = 0; i < retry_count; i++) {
2196 path_s0_ok = phy_path_s0_iqk_8723d(dm);
2197 if (path_s0_ok == 0x01) {
2198 RF_DBG(dm, DBG_RF_IQK,
2199 "path S0 Tx IQK Success!!\n");
2200 result[t][4] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD) & 0x3FF0000) >> 16;
2201 result[t][5] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
2202 break;
2203 }
2204
2205 RF_DBG(dm, DBG_RF_IQK, "path S0 Tx IQK Fail!!\n");
2206 result[t][4] = 0x100;
2207 result[t][5] = 0x0;
2208 cnt_iqk_fail++;
2209 #if 0
2210 else if (i == (retry_count - 1) && path_s1_ok == 0x01) {
2211 RT_DISP(FINIT, INIT_IQK, ("path S0 IQK Only Tx Success!!\n"));
2212
2213 result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
2214 result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
2215 }
2216 #endif
2217 }
2218 #endif
2219
2220 #if 1
2221 for (i = 0; i < retry_count; i++) {
2222 path_s0_ok = phy_path_s0_rx_iqk_8723d(dm, is2T);
2223 if (path_s0_ok == 0x03) {
2224 RF_DBG(dm, DBG_RF_IQK,
2225 "path S0 Rx IQK Success!!\n");
2226 #if 0
2227 /* result[t][0] = (odm_get_bb_reg(dm, R_0xe94, MASKDWORD)&0x3FF0000)>>16;*/
2228 /* result[t][1] = (odm_get_bb_reg(dm, R_0xe9c, MASKDWORD)&0x3FF0000)>>16;*/
2229 #endif
2230 result[t][6] = (odm_get_bb_reg(dm, R_0xea4, MASKDWORD) & 0x3FF0000) >> 16;
2231 result[t][7] = (odm_get_bb_reg(dm, R_0xeac, MASKDWORD) & 0x3FF0000) >> 16;
2232 break;
2233 }
2234
2235 RF_DBG(dm, DBG_RF_IQK, "path S0 Rx IQK Fail!!\n");
2236 result[t][6] = 0x100;
2237 result[t][7] = 0x0;
2238 cnt_iqk_fail++;
2239 }
2240
2241 if (path_s0_ok == 0x00)
2242 RF_DBG(dm, DBG_RF_IQK, "path S0 IQK failed!!\n");
2243 #endif
2244 }
2245 RF_DBG(dm, DBG_RF_IQK, "IQK:Back to BB mode, load original value!\n");
2246 odm_set_bb_reg(dm, R_0xe28, 0xffffff00, 0x000000);
2247
2248 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
2249 ODM_delay_us(10);
2250
2251 if (t != 0) {
2252 _phy_reload_adda_registers_8723d(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
2253 /* Reload MAC parameters*/
2254 _phy_reload_mac_registers_8723d(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
2255 _phy_reload_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
2256
2257 odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, 0x50);
2258 odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, tmp0xc50);
2259 if (is2T) {
2260 odm_set_bb_reg(dm, R_0xc58, MASKBYTE0, 0x50);
2261 odm_set_bb_reg(dm, R_0xc58, MASKBYTE0, tmp0xc58);
2262 }
2263 odm_set_bb_reg(dm, R_0xe30, MASKDWORD, 0x01008c00);
2264 odm_set_bb_reg(dm, R_0xe34, MASKDWORD, 0x01008c00);
2265 }
2266 dm->n_iqk_cnt++;
2267 if (cnt_iqk_fail == 0)
2268 dm->n_iqk_ok_cnt++;
2269 else
2270 dm->n_iqk_fail_cnt = dm->n_iqk_fail_cnt + cnt_iqk_fail;
2271 RF_DBG(dm, DBG_RF_IQK, "%s <==\n", __func__);
2272 }
2273
2274 void _phy_lc_calibrate_8723d(struct dm_struct *dm, boolean is2T)
2275 {
2276 u8 tmp_reg;
2277 u32 lc_cal, cnt;
2278 u16 i;
2279
2280 tmp_reg = odm_read_1byte(dm, 0xd03);
2281 if ((tmp_reg & 0x70) != 0)
2282 odm_write_1byte(dm, 0xd03, tmp_reg & 0x8F);
2283 else
2284 odm_write_1byte(dm, REG_TXPAUSE, 0xFF);
2285 /*backup RF0x18*/
2286 lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
2287 /*Start LCK*/
2288 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
2289 for (cnt = 0; cnt < 100; cnt++) {
2290 if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
2291 break;
2292 for (i = 0; i < 1000; i++) /*delay 10ms*/
2293 ODM_delay_us(10);
2294 }
2295 if (cnt == 100)
2296 RF_DBG(dm, DBG_RF_LCK, "LCK time out\n");
2297 /* Recover channel number*/
2298 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
2299 /*Restore original situation*/
2300 if ((tmp_reg & 0x70) != 0)
2301 odm_write_1byte(dm, 0xd03, tmp_reg);
2302 else
2303 odm_write_1byte(dm, REG_TXPAUSE, 0x00);
2304 }
2305
2306 /* IQK version:0x2 20171109*/
2307
2308 void phy_iq_calibrate_8723d(void *dm_void, boolean is_recovery)
2309 {
2310 struct dm_struct *dm = (struct dm_struct *)dm_void;
2311 s32 result[4][8];
2312 u8 i, final_candidate, indexforchannel, cnt;
2313 boolean is_path_s1_ok, is_path_s0_ok;
2314 s32 rege94_s1, rege9c_s1, regea4_s1, regeac_s1, rege94_s0, rege9c_s0, regea4_s0, regeac_s0, reg_tmp = 0;
2315 s32 regc80, regc94, regc14, regca0, regcd0, regcd4, regcd8;
2316 boolean is12simular, is13simular, is23simular;
2317 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
2318 R_0xc14, R_0xc1c,
2319 R_0xc4c, R_0xc78,
2320 R_0xc80, R_0xc88,
2321 R_0xc94, R_0xc9c,
2322 R_0xca0};
2323 u32 path_sel_bb_phy_iqk;
2324 u32 original_path, original_gnt, ori_path_ctrl;
2325 u32 iqk_fail_b, iqk_fail_a;
2326
2327 #if 1
2328 RF_DBG(dm, DBG_RF_IQK,
2329 "================ IQK Start ===================\n");
2330
2331 iqk_fail_b = dm->n_iqk_fail_cnt;
2332
2333 RF_DBG(dm, DBG_RF_INIT, "=====>%s\n", __func__);
2334
2335 path_sel_bb_phy_iqk = odm_get_bb_reg(dm, R_0x948, MASKDWORD);
2336
2337 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
2338 if (is_recovery) {
2339 #else
2340 if (is_recovery && !dm->is_in_hct_test) {
2341 #endif
2342 RF_DBG(dm, DBG_RF_INIT, "%s: Return due to is_recovery!\n",
2343 __func__);
2344 _phy_reload_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, 9);
2345 return;
2346 }
2347 /*Check & wait if BT is doing IQK*/
2348 if (!(*dm->mp_mode))
2349 _phy_check_coex_status_8723d(dm, true);
2350
2351 RF_DBG(dm, DBG_RF_IQK, "IQK:Start!!!\n");
2352 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2353 dm->rf_calibrate_info.is_iqk_in_progress = true;
2354 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2355
2356 for (i = 0; i < 8; i++) {
2357 result[0][i] = 0;
2358 result[1][i] = 0;
2359 result[2][i] = 0;
2360 result[3][i] = 0;
2361 }
2362
2363 final_candidate = 0xff;
2364 is_path_s1_ok = false;
2365 is_path_s0_ok = false;
2366 is12simular = false;
2367 is23simular = false;
2368 is13simular = false;
2369
2370 for (i = 0; i < 3; i++) {
2371 #if 1
2372 /*set path control to WL*/
2373 ori_path_ctrl = odm_get_mac_reg(dm, R_0x64, MASKBYTE3); /*save 0x67*/
2374 RF_DBG(dm, DBG_RF_IQK, "[IQK]original 0x67 = 0x%x\n",
2375 ori_path_ctrl);
2376 odm_set_mac_reg(dm, R_0x64, BIT(31), 0x1);
2377 RF_DBG(dm, DBG_RF_IQK, "[IQK]set 0x67 = 0x%x\n",
2378 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
2379 /*backup path & GNT value */
2380 original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
2381 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
2382
2383 for (cnt = 0; cnt < 100; cnt++) /*delay 1ms*/
2384 ODM_delay_us(10);
2385
2386 original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
2387 RF_DBG(dm, DBG_RF_IQK, "[IQK]OriginalGNT = 0x%x\n",
2388 original_gnt);
2389 /*set GNT_WL=1/GNT_BT=1 and path owner to WiFi for pause BT traffic*/
2390 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x0000ff00);
2391 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
2392 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);
2393 #endif
2394 _phy_iq_calibrate_8723d(dm, result, i, true);
2395 #if 1
2396 /*Restore GNT_WL/GNT_BT and path owner*/
2397 odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
2398 odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
2399 odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
2400 /*Restore path control owner*/
2401 odm_set_mac_reg(dm, R_0x64, MASKBYTE3, ori_path_ctrl);
2402 RF_DBG(dm, DBG_RF_IQK, "[IQK]restore 0x67 = 0x%x\n",
2403 odm_get_mac_reg(dm, R_0x64, MASKBYTE3));
2404 #endif
2405 if (i == 1) {
2406 is12simular = phy_simularity_compare_8723d(dm, result, 0, 1, true);
2407 if (is12simular) {
2408 final_candidate = 0;
2409 RF_DBG(dm, DBG_RF_IQK,
2410 "IQK: is12simular final_candidate is %x\n",
2411 final_candidate);
2412 break;
2413 }
2414 }
2415
2416 if (i == 2) {
2417 is13simular = phy_simularity_compare_8723d(dm, result, 0, 2, true);
2418 if (is13simular) {
2419 final_candidate = 0;
2420 RF_DBG(dm, DBG_RF_IQK,
2421 "IQK: is13simular final_candidate is %x\n",
2422 final_candidate);
2423
2424 break;
2425 }
2426 is23simular = phy_simularity_compare_8723d(dm, result, 1, 2, true);
2427 if (is23simular) {
2428 final_candidate = 1;
2429 RF_DBG(dm, DBG_RF_IQK,
2430 "IQK: is23simular final_candidate is %x\n",
2431 final_candidate);
2432 } else {
2433 for (i = 0; i < 8; i++)
2434 reg_tmp += result[3][i];
2435
2436 if (reg_tmp != 0)
2437 final_candidate = 3;
2438 else
2439 final_candidate = 0xFF;
2440 }
2441 }
2442 }
2443
2444 for (i = 0; i < 4; i++) {
2445 rege94_s1 = result[i][0];
2446 rege9c_s1 = result[i][1];
2447 regea4_s1 = result[i][2];
2448 regeac_s1 = result[i][3];
2449 rege94_s0 = result[i][4];
2450 rege9c_s0 = result[i][5];
2451 regea4_s0 = result[i][6];
2452 regeac_s0 = result[i][7];
2453 RF_DBG(dm, DBG_RF_IQK,
2454 "[IQK] rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x\n ",
2455 rege94_s1, rege9c_s1, regea4_s1, regeac_s1, rege94_s0,
2456 rege9c_s0, regea4_s0, regeac_s0);
2457 }
2458
2459 if (final_candidate != 0xff) {
2460 dm->rf_calibrate_info.rege94 = result[final_candidate][0];
2461 rege94_s1 = result[final_candidate][0];
2462 dm->rf_calibrate_info.rege9c = result[final_candidate][1];
2463 rege9c_s1 = result[final_candidate][1];
2464 regea4_s1 = result[final_candidate][2];
2465 regeac_s1 = result[final_candidate][3];
2466 dm->rf_calibrate_info.regeb4 = result[final_candidate][4];
2467 rege94_s0 = result[final_candidate][4];
2468 dm->rf_calibrate_info.regebc = result[final_candidate][5];
2469 rege9c_s0 = result[final_candidate][5];
2470 regea4_s0 = result[final_candidate][6];
2471 regeac_s0 = result[final_candidate][7];
2472 RF_DBG(dm, DBG_RF_IQK, "[IQK] final_candidate is %x\n",
2473 final_candidate);
2474 RF_DBG(dm, DBG_RF_IQK,
2475 "[IQK] TX1_X=%x TX1_Y=%x RX1_X=%x RX1_Y=%x TX0_X=%x TX0_Y=%x RX0_X=%x RX0_Y=%x\n ",
2476 rege94_s1, rege9c_s1, regea4_s1, regeac_s1, rege94_s0,
2477 rege9c_s0, regea4_s0, regeac_s0);
2478 is_path_s1_ok = true;
2479 is_path_s0_ok = true;
2480 } else {
2481 RF_DBG(dm, DBG_RF_IQK, "[IQK] FAIL use default value\n");
2482 dm->rf_calibrate_info.rege94 = 0x100;
2483 dm->rf_calibrate_info.regeb4 = 0x100;
2484 dm->rf_calibrate_info.rege9c = 0x0;
2485 dm->rf_calibrate_info.regebc = 0x0;
2486 }
2487
2488 if (rege94_s1 != 0)
2489 _phy_path_s1_fill_iqk_matrix_8723d(dm, is_path_s1_ok, result, final_candidate, (regea4_s1 == 0));
2490 if (rege94_s0 != 0)
2491 _phy_path_s0_fill_iqk_matrix_8723d(dm, is_path_s0_ok, result, final_candidate, (regea4_s0 == 0));
2492
2493 iqk_fail_a = dm->n_iqk_fail_cnt;
2494 if (iqk_fail_a - iqk_fail_b > 0)
2495 RF_DBG(dm, DBG_RF_IQK,
2496 "[8723dIQK]n_iqk_fail_cnt+,IQK restore to default value !\n");
2497
2498 regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
2499 regc94 = odm_get_bb_reg(dm, R_0xc94, MASKDWORD);
2500 regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
2501 regca0 = odm_get_bb_reg(dm, R_0xca0, MASKDWORD);
2502 RF_DBG(dm, DBG_RF_IQK,
2503 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
2504 regc80, regc94, regc14, regca0);
2505
2506 regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
2507 regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
2508 regcd8 = odm_get_bb_reg(dm, R_0xcd8, MASKDWORD);
2509 RF_DBG(dm, DBG_RF_IQK, "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
2510 regcd0, regcd4, regcd8);
2511 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2512 indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
2513 #else
2514 indexforchannel = 0;
2515 #endif
2516
2517 if (final_candidate < 4) {
2518 for (i = 0; i < iqk_matrix_reg_num; i++)
2519 dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].value[0][i] = result[final_candidate][i];
2520 dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].is_iqk_done = true;
2521 }
2522 RF_DBG(dm, DBG_RF_IQK, "\nIQK OK indexforchannel %d.\n",
2523 indexforchannel);
2524 _phy_save_adda_registers_8723d(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
2525
2526 if (!(*dm->mp_mode))
2527 _phy_check_coex_status_8723d(dm, false);
2528
2529 odm_set_bb_reg(dm, R_0x948, MASKDWORD, path_sel_bb_phy_iqk);
2530 RF_DBG(dm, DBG_RF_IQK, "IQK finished\n");
2531 #endif
2532 }
2533
2534 void phy_lc_calibrate_8723d(void *dm_void)
2535 {
2536 struct dm_struct *dm = (struct dm_struct *)dm_void;
2537
2538 _phy_lc_calibrate_8723d(dm, false);
2539 }
2540
2541 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
2542 void _phy_set_rf_path_switch_8723d(struct dm_struct *dm,
2543 #else
2544 void _phy_set_rf_path_switch_8723d(void *adapter,
2545 #endif
2546 boolean is_main, boolean is2T)
2547 {
2548 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2549 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2550 struct dm_struct *dm = &hal_data->DM_OutSrc;
2551 #endif
2552
2553 if (is_main)
2554 odm_set_mac_reg(dm, R_0x7c4, MASKLWORD, 0x7700);
2555 else
2556 odm_set_mac_reg(dm, R_0x7c4, MASKLWORD, 0xDD00);
2557
2558 odm_set_mac_reg(dm, R_0x7c0, MASKDWORD, 0xC00F0038);
2559 odm_set_mac_reg(dm, R_0x70, BIT(26), 1);
2560 odm_set_mac_reg(dm, R_0x64, BIT(31), 1);
2561 }
2562
2563
2564 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
2565 void phy_set_rf_path_switch_8723d(struct dm_struct *dm,
2566 #else
2567 void phy_set_rf_path_switch_8723d(void *adapter,
2568 #endif
2569 boolean is_main)
2570 {
2571 #if DISABLE_BB_RF
2572 return;
2573 #endif
2574
2575 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2576 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2577 _phy_set_rf_path_switch_8723d(dm, is_main, true);
2578 #else
2579 _phy_set_rf_path_switch_8723d(adapter, is_main, true);
2580 #endif
2581 #endif
2582 }
2583
2584 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2585 boolean _phy_query_rf_path_switch_8723d(
2586 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2587 struct dm_struct *dm,
2588 #else
2589 ADAPTER *adapter,
2590 #endif
2591 boolean is2T)
2592 {
2593 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2594 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2595 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2596 struct dm_struct *dm = &hal_data->odmpriv;
2597 #endif
2598 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2599 struct dm_struct *dm = &hal_data->DM_OutSrc;
2600 #endif
2601 #endif
2602
2603 if (odm_get_bb_reg(dm, R_0x7c4, MASKLWORD) == 0x7700)
2604 return true;
2605 else
2606 return false;
2607 }
2608
2609 boolean phy_query_rf_path_switch_8723d(
2610 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2611 struct dm_struct *dm
2612 #else
2613 void *adapter
2614 #endif
2615 )
2616 {
2617 #if DISABLE_BB_RF
2618 return true;
2619 #endif
2620
2621 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2622 return _phy_query_rf_path_switch_8723d(adapter, false);
2623 #else
2624 return _phy_query_rf_path_switch_8723d(dm, false);
2625 #endif
2626 }
2627 #endif
2628
2629 #else
2630
2631 void phy_iq_calibrate_8723d(void *dm_void, boolean is_recovery) {}
2632 void phy_lc_calibrate_8723d(void *dm_void) {}
2633
2634 void odm_tx_pwr_track_set_pwr_8723d(struct dm_struct *dm,
2635 enum pwrtrack_method method, u8 rf_path,
2636 u8 channel_mapped_index) {}
2637 #endif
2638