1 /******************************************************************************
2 *
3 * Copyright(c) 2014 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include <drv_types.h>
17 #include <hal_data.h>
18
19 /* A mapping from HalData to ODM. */
boardType(u8 InterfaceSel)20 enum odm_board_type boardType(u8 InterfaceSel)
21 {
22 enum odm_board_type board = ODM_BOARD_DEFAULT;
23
24 #ifdef CONFIG_PCI_HCI
25 INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
26 switch (pcie) {
27 case INTF_SEL0_SOLO_MINICARD:
28 board |= ODM_BOARD_MINICARD;
29 break;
30 case INTF_SEL1_BT_COMBO_MINICARD:
31 board |= ODM_BOARD_BT;
32 board |= ODM_BOARD_MINICARD;
33 break;
34 default:
35 board = ODM_BOARD_DEFAULT;
36 break;
37 }
38
39 #elif defined(CONFIG_USB_HCI)
40 INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
41 switch (usb) {
42 case INTF_SEL1_USB_High_Power:
43 board |= ODM_BOARD_EXT_LNA;
44 board |= ODM_BOARD_EXT_PA;
45 break;
46 case INTF_SEL2_MINICARD:
47 board |= ODM_BOARD_MINICARD;
48 break;
49 case INTF_SEL4_USB_Combo:
50 board |= ODM_BOARD_BT;
51 break;
52 case INTF_SEL5_USB_Combo_MF:
53 board |= ODM_BOARD_BT;
54 break;
55 case INTF_SEL0_USB:
56 case INTF_SEL3_USB_Solo:
57 default:
58 board = ODM_BOARD_DEFAULT;
59 break;
60 }
61
62 #endif
63 /* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
64
65 return board;
66 }
67
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)68 void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
69 {
70 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
71 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
72
73 if (hal->RegIQKFWOffload) {
74 rtw_sctx_init(&hal->iqk_sctx, 0);
75 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
76 } else
77 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
78
79 RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
80
81 if (rtw_mi_check_status(adapter, MI_LINKED)) {
82 #ifdef CONFIG_LPS
83 LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
84 #endif
85 halrf_iqk_trigger(p_dm_odm, _FALSE);
86 }
87 }
88
89 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
90 || (RTL8723F_SUPPORT == 1))
rtw_phydm_iqk_trigger(_adapter * adapter)91 void rtw_phydm_iqk_trigger(_adapter *adapter)
92 {
93 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
94 u8 clear = _TRUE;
95 u8 segment = _FALSE;
96 u8 rfk_forbidden = _FALSE;
97
98 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
99 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8723F_SUPPORT == 1)
100 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
101 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
102 #else
103 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
104 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
105 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
106 #endif
107 }
108 #endif
109
rtw_phydm_iqk_trigger_all(_adapter * adapter)110 void rtw_phydm_iqk_trigger_all(_adapter *adapter)
111 {
112 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
113 u8 clear = _TRUE;
114 u8 segment = _FALSE;
115 u8 rfk_forbidden = _FALSE;
116
117 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
118 || (RTL8723F_SUPPORT == 1))
119 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
120 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8723F_SUPPORT == 1)
121 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
122 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
123 #else
124 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
125 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
126 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
127 #endif /* (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) (RTL8723F_SUPPORT == 1) */
128 #else
129 halrf_iqk_trigger(p_dm_odm, _FALSE);
130 #endif /* ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
131 (RTL8723F_SUPPORT == 1) */
132 }
133
rtw_phydm_iqk_trigger_dbg(_adapter * adapter,bool recovery,bool clear,bool segment)134 void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
135 {
136 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
137
138 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
139 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
140 #else
141 halrf_iqk_trigger(p_dm_odm, recovery);
142 #endif
143 }
rtw_phydm_lck_trigger(_adapter * adapter)144 void rtw_phydm_lck_trigger(_adapter *adapter)
145 {
146 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
147
148 halrf_lck_trigger(p_dm_odm);
149 }
150
rtw_hal_phydm_cal_trigger(_adapter * adapter)151 void rtw_hal_phydm_cal_trigger(_adapter *adapter)
152 {
153 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
154
155 rtw_ps_deny(adapter, PS_DENY_IOCTL);
156 LeaveAllPowerSaveModeDirect(adapter);
157
158 rtw_phydm_iqk_trigger_all(adapter);
159
160 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
161 }
162
163 #ifdef CONFIG_DBG_RF_CAL
rtw_hal_iqk_test(_adapter * adapter,bool recovery,bool clear,bool segment)164 void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
165 {
166 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
167
168 rtw_ps_deny(adapter, PS_DENY_IOCTL);
169 LeaveAllPowerSaveModeDirect(adapter);
170
171 rtw_phydm_ability_backup(adapter);
172 rtw_phydm_func_disable_all(adapter);
173
174 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
175
176 rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
177 rtw_phydm_ability_restore(adapter);
178
179 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
180 }
181
rtw_hal_lck_test(_adapter * adapter)182 void rtw_hal_lck_test(_adapter *adapter)
183 {
184 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
185
186 rtw_ps_deny(adapter, PS_DENY_IOCTL);
187 LeaveAllPowerSaveModeDirect(adapter);
188
189 rtw_phydm_ability_backup(adapter);
190 rtw_phydm_func_disable_all(adapter);
191
192 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
193
194 rtw_phydm_lck_trigger(adapter);
195
196 rtw_phydm_ability_restore(adapter);
197 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
198 }
199 #endif
200
201 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
rtw_hal_update_param_init_fw_offload_cap(_adapter * adapter)202 void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
203 {
204 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
205
206 if (adapter->registrypriv.fw_param_init)
207 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
208 else
209 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
210
211 RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
212 }
213 #endif
214
record_ra_info(void * p_dm_void,u8 macid,struct cmn_sta_info * p_sta,u64 ra_mask)215 void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
216 {
217 struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
218 _adapter *adapter = p_dm->adapter;
219 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
220 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
221
222 if (p_sta) {
223 rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
224 rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
225 rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
226 rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
227
228 rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
229 }
230 }
231
232 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
rtw_phydm_fill_desc_dpt(void * dm,u8 * desc,u8 dpt_lv)233 void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
234 {
235 struct dm_struct *p_dm = (struct dm_struct *)dm;
236 _adapter *adapter = p_dm->adapter;
237
238 switch (rtw_get_chip_type(adapter)) {
239 /*
240 #ifdef CONFIG_RTL8188F
241 case RTL8188F:
242 break;
243 #endif
244
245 #ifdef CONFIG_RTL8723B
246 case RTL8723B :
247 break;
248 #endif
249
250 #ifdef CONFIG_RTL8703B
251 case RTL8703B :
252 break;
253 #endif
254
255 #ifdef CONFIG_RTL8812A
256 case RTL8812 :
257 break;
258 #endif
259
260 #ifdef CONFIG_RTL8821A
261 case RTL8821:
262 break;
263 #endif
264
265 #ifdef CONFIG_RTL8814A
266 case RTL8814A :
267 break;
268 #endif
269
270 #ifdef CONFIG_RTL8192F
271 case RTL8192F :
272 break;
273 #endif
274 */
275 /*
276 #ifdef CONFIG_RTL8192E
277 case RTL8192E :
278 SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
279 break;
280 #endif
281 */
282 #ifdef CONFIG_RTL8822B
283 case RTL8822B :
284 SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
285 break;
286 #endif
287
288 #ifdef CONFIG_RTL8821C
289 case RTL8821C :
290 SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
291 break;
292 #endif
293
294 default :
295 RTW_ERR("%s IC not support dynamic tx power\n", __func__);
296 break;
297 }
298 }
rtw_phydm_set_dyntxpwr(_adapter * adapter,u8 * desc,u8 mac_id)299 void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
300 {
301 struct dm_struct *dm = adapter_to_phydm(adapter);
302
303 odm_set_dyntxpwr(dm, desc, mac_id);
304 }
305 #endif
306
307 #ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(_adapter * adapter,u8 state)308 void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
309 {
310 struct registry_priv *pregistrypriv = &adapter->registrypriv;
311 struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
312 struct dm_struct *dm = adapter_to_phydm(adapter);
313 u8 tdma_dig_en;
314
315 switch (state) {
316 case TDMADIG_INIT:
317 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
318 phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
319 break;
320 case TDMADIG_NON_INIT:
321 if(pregistrypriv->tdmadig_dynamic) {
322 if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
323 tdma_dig_en = 0;
324 else
325 tdma_dig_en = pregistrypriv->tdmadig_en;
326 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
327 }
328 break;
329 default:
330 break;
331
332 }
333 }
334 #endif/*CONFIG_TDMADIG*/
rtw_phydm_ops_func_init(struct dm_struct * p_phydm)335 void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
336 {
337 struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
338
339 p_ra_t->record_ra_info = record_ra_info;
340 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
341 p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
342 #endif
343 }
rtw_phydm_priv_init(_adapter * adapter)344 void rtw_phydm_priv_init(_adapter *adapter)
345 {
346 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
347 struct dm_struct *phydm = &(hal->odmpriv);
348
349 phydm->adapter = adapter;
350 odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
351 }
352
Init_ODM_ComInfo(_adapter * adapter)353 void Init_ODM_ComInfo(_adapter *adapter)
354 {
355 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
356 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
357 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
358 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
359 struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
360 int i;
361
362 /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
363 pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
364 rtw_odm_init_ic_type(adapter);
365
366 if (rtw_get_intf_type(adapter) == RTW_GSPI)
367 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
368 else
369 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
370
371 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
372
373 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
374
375 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
376
377 #ifdef CONFIG_ADVANCE_OTA
378 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
379 #endif
380 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
381
382 {
383 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
384 u8 odm_board_type = ODM_BOARD_DEFAULT;
385
386 if (pHalData->ExternalLNA_2G != 0) {
387 odm_board_type |= ODM_BOARD_EXT_LNA;
388 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
389 }
390 if (pHalData->external_lna_5g != 0) {
391 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
392 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
393 }
394 if (pHalData->ExternalPA_2G != 0) {
395 odm_board_type |= ODM_BOARD_EXT_PA;
396 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
397 }
398 if (pHalData->external_pa_5g != 0) {
399 odm_board_type |= ODM_BOARD_EXT_PA_5G;
400 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
401 }
402 if (pHalData->EEPROMBluetoothCoexist)
403 odm_board_type |= ODM_BOARD_BT;
404
405 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
406 /* 1 ============== End of BoardType ============== */
407 }
408
409 #ifdef CONFIG_DFS_MASTER
410 rtw_odm_update_dfs_region(dvobj);
411 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
412 #endif
413
414 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
415 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
416 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
417 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
418
419 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
420 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
421
422 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
423
424 /*Add by YuChen for kfree init*/
425 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
426 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
427
428 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
429 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
430 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
431
432 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
433 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
434 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
435
436 /* waiting for PhyDMV034 support*/
437 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability));
438
439 /*Add by YuChen for adaptivity init*/
440 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &rfctl->adaptivity_en);
441 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
442 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
443 rtw_odm_adaptivity_update(dvobj);
444
445 /*halrf info init*/
446 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
447 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
448 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_MP_POWER_TRACKING_TYPE, pHalData->txpwr_pg_mode);
449
450 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
451 rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
452
453 #ifdef CONFIG_IQK_PA_OFF
454 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
455 #endif
456 rtw_hal_update_iqk_fw_offload_cap(adapter);
457 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
458 rtw_hal_update_param_init_fw_offload_cap(adapter);
459 #endif
460
461 /* Pointer reference */
462 /*Antenna diversity relative parameters*/
463 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
464 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
465
466 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
467 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
468 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
469
470 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
471 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
472
473 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
474 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
475 #ifdef CONFIG_NARROWBAND_SUPPORTING
476 if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
477 || (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
478 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
479 }
480 else
481 #endif
482 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
483 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
484 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
485
486 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
487 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
488 /*Add by Yuchen for phydm beamforming*/
489 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
490 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
491 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
492 #ifdef CONFIG_RTL8723B
493 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
494 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
495 #endif /*CONFIG_RTL8723B*/
496 #ifdef CONFIG_USB_HCI
497 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
498 #endif
499
500 #ifdef CONFIG_DYNAMIC_SOML
501 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
502 #endif
503 #ifdef CONFIG_RTW_PATH_DIV
504 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
505 #endif
506 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
507
508 /*halrf info hook*/
509 /* waiting for PhyDMV034 support*/
510 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
511 #ifdef CONFIG_MP_INCLUDED
512 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
513 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
514 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
515 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
516 #endif/*CONFIG_MP_INCLUDED*/
517 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
518 phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
519
520 rtw_phydm_ops_func_init(pDM_Odm);
521 phydm_dm_early_init(pDM_Odm);
522 /* TODO */
523 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
524 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
525 }
526
527
528 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
529 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
530 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
531 { 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
532
533 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
534 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
535 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
536 { 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
537
538 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
539 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
540 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
541 { 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
542
543
544 struct turbo_edca_setting{
545 u32 edca_ul; /* uplink, tx */
546 u32 edca_dl; /* downlink, rx */
547 };
548
549 #define TURBO_EDCA_ENT(UL, DL) {UL, DL}
550
551 #if 0
552 #define TURBO_EDCA_MODE_NUM 18
553 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
554 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
555 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
556 TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */
557
558 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
559 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
560 TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */
561
562 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
563 TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
564 TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
565
566 TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
567 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
568 TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
569
570 TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
571 TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
572 TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
573
574 TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
575
576 TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
577
578 TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
579 };
580 #else
581 #define TURBO_EDCA_MODE_NUM 8
582 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
583 /* { UL, DL } */
584 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
585
586 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
587
588 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
589
590 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
591
592 TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
593
594 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
595
596 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
597
598 TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
599 };
600 #endif
601
rtw_hal_turbo_edca(_adapter * adapter)602 void rtw_hal_turbo_edca(_adapter *adapter)
603 {
604 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
605 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
606 struct recv_priv *precvpriv = &(adapter->recvpriv);
607 struct registry_priv *pregpriv = &adapter->registrypriv;
608 struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
609 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
610
611 /* Parameter suggested by Scott */
612 #if 0
613 u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
614 u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
615 #endif
616 u32 EDCA_BE_UL = 0x5ea42b;
617 u32 EDCA_BE_DL = 0x00a42b;
618 u8 ic_type = rtw_get_chip_type(adapter);
619
620 u8 iot_peer = 0;
621 u8 wireless_mode = 0xFF; /* invalid value */
622 u8 traffic_index;
623 u32 edca_param;
624 u64 cur_tx_bytes = 0;
625 u64 cur_rx_bytes = 0;
626 u8 bbtchange = _TRUE;
627 u8 is_bias_on_rx = _FALSE;
628 u8 is_linked = _FALSE;
629 u8 interface_type;
630
631 if (hal_data->dis_turboedca == 1)
632 return;
633
634 if (rtw_mi_check_status(adapter, MI_ASSOC))
635 is_linked = _TRUE;
636
637 if (is_linked != _TRUE) {
638 precvpriv->is_any_non_be_pkts = _FALSE;
639 return;
640 }
641
642 if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
643 precvpriv->is_any_non_be_pkts = _FALSE;
644 return;
645 }
646
647 interface_type = rtw_get_intf_type(adapter);
648 wireless_mode = pmlmeext->cur_wireless_mode;
649
650 iot_peer = pmlmeinfo->assoc_AP_vendor;
651
652 if (iot_peer >= HT_IOT_PEER_MAX) {
653 precvpriv->is_any_non_be_pkts = _FALSE;
654 return;
655 }
656
657 if (ic_type == RTL8188E) {
658 if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
659 is_bias_on_rx = _TRUE;
660 }
661
662 /* Check if the status needs to be changed. */
663 if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
664 cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
665 cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
666
667 /* traffic, TX or RX */
668 if (is_bias_on_rx) {
669 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
670 /* Uplink TP is present. */
671 traffic_index = UP_LINK;
672 } else {
673 /* Balance TP is present. */
674 traffic_index = DOWN_LINK;
675 }
676 } else {
677 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
678 /* Downlink TP is present. */
679 traffic_index = DOWN_LINK;
680 } else {
681 /* Balance TP is present. */
682 traffic_index = UP_LINK;
683 }
684 }
685 #if 0
686 if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
687 || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
688 #endif
689 {
690 if (interface_type == RTW_PCIE) {
691 EDCA_BE_UL = 0x6ea42b;
692 EDCA_BE_DL = 0x6ea42b;
693 }
694
695 /* 92D txop can't be set to 0x3e for cisco1250 */
696 if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
697 EDCA_BE_DL = edca_setting_DL[iot_peer];
698 EDCA_BE_UL = edca_setting_UL[iot_peer];
699 }
700 /* merge from 92s_92c_merge temp*/
701 else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
702 EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
703 else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
704 EDCA_BE_DL = 0xa630;
705 else if (iot_peer == HT_IOT_PEER_MARVELL) {
706 EDCA_BE_DL = edca_setting_DL[iot_peer];
707 EDCA_BE_UL = edca_setting_UL[iot_peer];
708 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
709 /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
710 /* Suggested by SD3 Wilson for ASUS TP issue.*/
711 EDCA_BE_DL = edca_setting_DL[iot_peer];
712 }
713
714 if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
715 EDCA_BE_UL = 0x5ea42b;
716 EDCA_BE_DL = 0x5ea42b;
717
718 RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
719 }
720
721 if (interface_type == RTW_PCIE &&
722 ((ic_type == RTL8822B)
723 || (ic_type == RTL8822C)
724 || (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
725 EDCA_BE_UL = 0x6ea42b;
726 EDCA_BE_DL = 0x6ea42b;
727 }
728
729 if ((ic_type == RTL8822B)
730 && (interface_type == RTW_SDIO))
731 EDCA_BE_DL = 0x00431c;
732
733 #ifdef CONFIG_RTW_TPT_MODE
734 if ( dvobj->tpt_mode > 0 ) {
735 EDCA_BE_UL = dvobj->edca_be_ul;
736 EDCA_BE_DL = dvobj->edca_be_dl;
737 }
738 #endif /* CONFIG_RTW_TPT_MODE */
739
740 /* keep this condition at last check */
741 if (hal_data->dis_turboedca == 2) {
742
743 if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
744
745 struct turbo_edca_setting param;
746
747 param = rtw_turbo_edca[hal_data->edca_param_mode];
748
749 EDCA_BE_UL = param.edca_ul;
750 EDCA_BE_DL = param.edca_dl;
751
752 } else {
753
754 EDCA_BE_UL = hal_data->edca_param_mode;
755 EDCA_BE_DL = hal_data->edca_param_mode;
756 }
757 }
758
759 if (traffic_index == DOWN_LINK)
760 edca_param = EDCA_BE_DL;
761 else
762 edca_param = EDCA_BE_UL;
763
764 #ifdef CONFIG_EXTEND_LOWRATE_TXOP
765 #define TXOP_CCK1M 0x01A6
766 #define TXOP_CCK2M 0x00E6
767 #define TXOP_CCK5M 0x006B
768 #define TXOP_OFD6M 0x0066
769 #define TXOP_MCS6M 0x0061
770 {
771 struct sta_info *psta;
772 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
773 u8 mac_id, role, current_rate_id;
774
775 /* search all used & connect2AP macid */
776 for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
777 if (rtw_macid_is_used(macid_ctl, mac_id)) {
778 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
779 if (role != H2C_MSR_ROLE_AP)
780 continue;
781
782 psta = macid_ctl->sta[mac_id];
783 current_rate_id = rtw_get_current_tx_rate(adapter, psta);
784 /* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */
785 switch (current_rate_id) {
786 case DESC_RATE1M:
787 edca_param &= 0x0000FFFF;
788 edca_param |= (TXOP_CCK1M<<16);
789 break;
790 case DESC_RATE2M:
791 edca_param &= 0x0000FFFF;
792 edca_param |= (TXOP_CCK2M<<16);
793 break;
794 case DESC_RATE5_5M:
795 edca_param &= 0x0000FFFF;
796 edca_param |= (TXOP_CCK5M<<16);
797 break;
798 case DESC_RATE6M:
799 edca_param &= 0x0000FFFF;
800 edca_param |= (TXOP_OFD6M<<16);
801 break;
802 case DESC_RATEMCS0:
803 edca_param &= 0x0000FFFF;
804 edca_param |= (TXOP_MCS6M<<16);
805 break;
806 default:
807 break;
808 }
809 }
810 }
811 }
812 #endif /* CONFIG_EXTEND_LOWRATE_TXOP */
813
814 #ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
815 edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
816 #endif
817
818 if ( edca_param != hal_data->ac_param_be) {
819
820 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
821
822 RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
823 }
824
825 hal_data->prv_traffic_idx = traffic_index;
826 }
827
828 hal_data->is_turbo_edca = _TRUE;
829 } else {
830 /* */
831 /* Turn Off EDCA turbo here. */
832 /* Restore original EDCA according to the declaration of AP. */
833 /* */
834 if (hal_data->is_turbo_edca) {
835 edca_param = hal_data->ac_param_be;
836 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
837 hal_data->is_turbo_edca = _FALSE;
838 }
839 }
840
841 }
842
rtw_dm_get_min_rssi(_adapter * adapter)843 s8 rtw_dm_get_min_rssi(_adapter *adapter)
844 {
845 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
846 struct sta_info *sta;
847 s8 min_rssi = 127, rssi;
848 int i;
849
850 for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
851 sta = macid_ctl->sta[i];
852 if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
853 || is_broadcast_mac_addr(sta->cmn.mac_addr))
854 continue;
855 rssi = sta->cmn.rssi_stat.rssi;
856 if (rssi >= 0 && min_rssi > rssi)
857 min_rssi = rssi;
858 }
859
860 return min_rssi == 127 ? 0 : min_rssi;
861 }
862
rtw_phydm_get_min_rssi(_adapter * adapter)863 s8 rtw_phydm_get_min_rssi(_adapter *adapter)
864 {
865 struct dm_struct *phydm = adapter_to_phydm(adapter);
866 s8 rssi_min = 0;
867
868 rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
869 return rssi_min;
870 }
871
rtw_phydm_get_cur_igi(_adapter * adapter)872 u8 rtw_phydm_get_cur_igi(_adapter *adapter)
873 {
874 struct dm_struct *phydm = adapter_to_phydm(adapter);
875 u8 cur_igi = 0;
876
877 cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
878 return cur_igi;
879 }
880
rtw_phydm_get_edcca_flag(_adapter * adapter)881 bool rtw_phydm_get_edcca_flag(_adapter *adapter)
882 {
883 struct dm_struct *phydm = adapter_to_phydm(adapter);
884 bool cur_edcca_flag = 0;
885
886 cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
887 return cur_edcca_flag;
888 }
889
rtw_phydm_get_phy_cnt(_adapter * adapter,enum phy_cnt cnt)890 u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
891 {
892 struct dm_struct *phydm = adapter_to_phydm(adapter);
893
894 if (cnt == FA_OFDM)
895 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
896 else if (cnt == FA_CCK)
897 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
898 else if (cnt == FA_TOTAL)
899 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
900 else if (cnt == CCA_OFDM)
901 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
902 else if (cnt == CCA_CCK)
903 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
904 else if (cnt == CCA_ALL)
905 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
906 else if (cnt == CRC32_OK_VHT)
907 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
908 else if (cnt == CRC32_OK_HT)
909 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
910 else if (cnt == CRC32_OK_LEGACY)
911 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
912 else if (cnt == CRC32_OK_CCK)
913 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
914 else if (cnt == CRC32_ERROR_VHT)
915 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
916 else if (cnt == CRC32_ERROR_HT)
917 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
918 else if (cnt == CRC32_ERROR_LEGACY)
919 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
920 else if (cnt == CRC32_ERROR_CCK)
921 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
922 else
923 return 0;
924 }
925
rtw_phydm_is_iqk_in_progress(_adapter * adapter)926 u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
927 {
928 u8 rts = _FALSE;
929 struct dm_struct *podmpriv = adapter_to_phydm(adapter);
930
931 odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
932 if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
933 RTW_ERR("IQK InProgress\n");
934 rts = _TRUE;
935 }
936 odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
937
938 return rts;
939 }
940
SetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)941 void SetHalODMVar(
942 PADAPTER Adapter,
943 HAL_ODM_VARIABLE eVariable,
944 void *pValue1,
945 BOOLEAN bSet)
946 {
947 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
948 /* _irqL irqL; */
949 switch (eVariable) {
950 case HAL_ODM_STA_INFO: {
951 struct sta_info *psta = (struct sta_info *)pValue1;
952
953 if (bSet) {
954 RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
955 psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
956 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
957 } else {
958 RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
959 /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
960 psta->cmn.dm_ctrl = 0;
961 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
962
963 /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
964 }
965 }
966 break;
967 case HAL_ODM_P2P_STATE:
968 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
969 break;
970 case HAL_ODM_WIFI_DISPLAY_STATE:
971 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
972 break;
973 case HAL_ODM_INITIAL_GAIN: {
974 u8 rx_gain = *((u8 *)(pValue1));
975 /*printk("rx_gain:%x\n",rx_gain);*/
976 if (rx_gain == 0xff) {/*restore rx gain*/
977 /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
978 odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
979 } else {
980 /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
981 /*odm_write_dig(podmpriv,rx_gain);*/
982 odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
983 }
984 }
985 break;
986 case HAL_ODM_RX_INFO_DUMP: {
987 u8 cur_igi = 0;
988 s8 rssi_min;
989 void *sel;
990
991 sel = pValue1;
992 cur_igi = rtw_phydm_get_cur_igi(Adapter);
993 rssi_min = rtw_phydm_get_min_rssi(Adapter);
994
995 _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
996 _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
997 , podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
998 _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
999 rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
1000 rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
1001 rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
1002
1003 if (podmpriv->is_linked) {
1004 _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
1005 if (IS_HARDWARE_TYPE_8814A(Adapter))
1006 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
1007 podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
1008 else
1009 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
1010 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1011 rtw_dump_raw_rssi_info(Adapter, sel);
1012 #endif
1013 }
1014 }
1015 break;
1016 case HAL_ODM_RX_Dframe_INFO: {
1017 void *sel;
1018
1019 sel = pValue1;
1020
1021 /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
1022 #ifdef DBG_RX_DFRAME_RAW_DATA
1023 rtw_dump_rx_dframe_info(Adapter, sel);
1024 #endif
1025 }
1026 break;
1027
1028 #ifdef CONFIG_ANTENNA_DIVERSITY
1029 case HAL_ODM_ANTDIV_SELECT: {
1030 u8 antenna = (*(u8 *)pValue1);
1031 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1032 /*switch antenna*/
1033 odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
1034 /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
1035
1036 }
1037 break;
1038 #endif
1039
1040 default:
1041 break;
1042 }
1043 }
1044
GetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)1045 void GetHalODMVar(
1046 PADAPTER Adapter,
1047 HAL_ODM_VARIABLE eVariable,
1048 void *pValue1,
1049 void *pValue2)
1050 {
1051 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
1052
1053 switch (eVariable) {
1054 #ifdef CONFIG_ANTENNA_DIVERSITY
1055 case HAL_ODM_ANTDIV_SELECT: {
1056 struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
1057 *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
1058 }
1059 break;
1060 #endif
1061 case HAL_ODM_INITIAL_GAIN:
1062 *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
1063 break;
1064 default:
1065 break;
1066 }
1067 }
1068
1069 #ifdef RTW_HALMAC
1070 #include "../hal_halmac.h"
1071 #endif
rtw_phydm_rfe_ctrl_gpio(_adapter * adapter,u8 gpio_num)1072 bool rtw_phydm_rfe_ctrl_gpio(
1073 _adapter *adapter,
1074 u8 gpio_num
1075 )
1076 {
1077 #ifdef RTW_HALMAC
1078 if(rtw_halmac_rfe_ctrl_cfg(adapter_to_dvobj(adapter), gpio_num))
1079 return _TRUE;
1080 else
1081 #endif/*RTW_HALMAC*/
1082 return _FALSE;
1083 }
1084
1085 enum hal_status
rtw_phydm_fw_iqk(struct dm_struct * p_dm_odm,u8 clear,u8 segment)1086 rtw_phydm_fw_iqk(
1087 struct dm_struct *p_dm_odm,
1088 u8 clear,
1089 u8 segment
1090 )
1091 {
1092 #ifdef RTW_HALMAC
1093 struct _ADAPTER *adapter = p_dm_odm->adapter;
1094
1095 if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
1096 return HAL_STATUS_SUCCESS;
1097 #endif
1098 return HAL_STATUS_FAILURE;
1099 }
1100
1101 enum hal_status
rtw_phydm_cfg_phy_para(struct dm_struct * p_dm_odm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)1102 rtw_phydm_cfg_phy_para(
1103 struct dm_struct *p_dm_odm,
1104 enum phydm_halmac_param config_type,
1105 u32 offset,
1106 u32 data,
1107 u32 mask,
1108 enum rf_path e_rf_path,
1109 u32 delay_time)
1110 {
1111 #ifdef RTW_HALMAC
1112 struct _ADAPTER *adapter = p_dm_odm->adapter;
1113 struct rtw_phy_parameter para;
1114
1115 switch (config_type) {
1116 case PHYDM_HALMAC_CMD_MAC_W8:
1117 para.cmd = 0; /* MAC register */
1118 para.data.mac.offset = offset;
1119 para.data.mac.value = data;
1120 para.data.mac.msk = mask;
1121 para.data.mac.msk_en = (mask) ? 1 : 0;
1122 para.data.mac.size = 1;
1123 break;
1124 case PHYDM_HALMAC_CMD_MAC_W16:
1125 para.cmd = 0; /* MAC register */
1126 para.data.mac.offset = offset;
1127 para.data.mac.value = data;
1128 para.data.mac.msk = mask;
1129 para.data.mac.msk_en = (mask) ? 1 : 0;
1130 para.data.mac.size = 2;
1131 break;
1132 case PHYDM_HALMAC_CMD_MAC_W32:
1133 para.cmd = 0; /* MAC register */
1134 para.data.mac.offset = offset;
1135 para.data.mac.value = data;
1136 para.data.mac.msk = mask;
1137 para.data.mac.msk_en = (mask) ? 1 : 0;
1138 para.data.mac.size = 4;
1139 break;
1140 case PHYDM_HALMAC_CMD_BB_W8:
1141 para.cmd = 1; /* BB register */
1142 para.data.bb.offset = offset;
1143 para.data.bb.value = data;
1144 para.data.bb.msk = mask;
1145 para.data.bb.msk_en = (mask) ? 1 : 0;
1146 para.data.bb.size = 1;
1147 break;
1148 case PHYDM_HALMAC_CMD_BB_W16:
1149 para.cmd = 1; /* BB register */
1150 para.data.bb.offset = offset;
1151 para.data.bb.value = data;
1152 para.data.bb.msk = mask;
1153 para.data.bb.msk_en = (mask) ? 1 : 0;
1154 para.data.bb.size = 2;
1155 break;
1156 case PHYDM_HALMAC_CMD_BB_W32:
1157 para.cmd = 1; /* BB register */
1158 para.data.bb.offset = offset;
1159 para.data.bb.value = data;
1160 para.data.bb.msk = mask;
1161 para.data.bb.msk_en = (mask) ? 1 : 0;
1162 para.data.bb.size = 4;
1163 break;
1164 case PHYDM_HALMAC_CMD_RF_W:
1165 para.cmd = 2; /* RF register */
1166 para.data.rf.offset = offset;
1167 para.data.rf.value = data;
1168 para.data.rf.msk = mask;
1169 para.data.rf.msk_en = (mask) ? 1 : 0;
1170 if (e_rf_path == RF_PATH_A)
1171 para.data.rf.path = 0;
1172 else if (e_rf_path == RF_PATH_B)
1173 para.data.rf.path = 1;
1174 else if (e_rf_path == RF_PATH_C)
1175 para.data.rf.path = 2;
1176 else if (e_rf_path == RF_PATH_D)
1177 para.data.rf.path = 3;
1178 else
1179 para.data.rf.path = 0;
1180 break;
1181 case PHYDM_HALMAC_CMD_DELAY_US:
1182 para.cmd = 3; /* Delay */
1183 para.data.delay.unit = 0; /* microsecond */
1184 para.data.delay.value = delay_time;
1185 break;
1186 case PHYDM_HALMAC_CMD_DELAY_MS:
1187 para.cmd = 3; /* Delay */
1188 para.data.delay.unit = 1; /* millisecond */
1189 para.data.delay.value = delay_time;
1190 break;
1191 case PHYDM_HALMAC_CMD_END:
1192 para.cmd = 0xFF; /* End command */
1193 break;
1194 default:
1195 return HAL_STATUS_FAILURE;
1196 }
1197
1198 if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
1199 return HAL_STATUS_FAILURE;
1200 #endif /*RTW_HALMAC*/
1201 return HAL_STATUS_SUCCESS;
1202 }
1203
1204
1205 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_phydm_wd_lps_lclk_hdl(_adapter * adapter)1206 void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
1207 {
1208 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1209 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1210 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1211 struct sta_priv *pstapriv = &adapter->stapriv;
1212 struct sta_info *psta = NULL;
1213 bool is_linked = _FALSE;
1214
1215 if (!rtw_is_hw_init_completed(adapter))
1216 return;
1217
1218 if (rtw_mi_check_status(adapter, MI_ASSOC))
1219 is_linked = _TRUE;
1220
1221 if (is_linked == _FALSE)
1222 return;
1223
1224 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1225 if (psta == NULL)
1226 return;
1227
1228 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
1229
1230 phydm_watchdog_lps_32k(&pHalData->odmpriv);
1231
1232 #ifdef CONFIG_LPS_PG
1233 if (pwrpriv->lps_level == LPS_PG) {
1234 if (rtw_hal_set_lps_pg_info_cmd(adapter) == _FAIL)
1235 RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n",
1236 FUNC_ADPT_ARG(adapter));
1237 }
1238 #endif /* CONFIG_LPS_PG */
1239 }
1240
rtw_phydm_watchdog_in_lps_lclk(_adapter * adapter)1241 void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
1242 {
1243 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1244 struct sta_priv *pstapriv = &adapter->stapriv;
1245 u8 cur_igi = 0;
1246 s8 min_rssi = 0;
1247
1248 if (!rtw_is_hw_init_completed(adapter))
1249 return;
1250
1251 cur_igi = rtw_phydm_get_cur_igi(adapter);
1252 min_rssi = rtw_dm_get_min_rssi(adapter);
1253 /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
1254
1255 if (min_rssi <= 0)
1256 return;
1257
1258 if ((cur_igi > min_rssi + 5) ||
1259 (cur_igi < min_rssi - 5)) {
1260 #ifdef CONFIG_LPS
1261 rtw_dm_in_lps_wk_cmd(adapter);
1262 #endif
1263 }
1264 }
1265 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1266
dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)1267 void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
1268 {
1269 struct ra_sta_info *ra_info;
1270 u8 curr_sgi = _FALSE;
1271 u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
1272
1273 if (!psta)
1274 return;
1275 RTW_PRINT_SEL(sel, "\n");
1276 RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
1277 psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
1278
1279 if (is_client_associated_to_ap(psta->padapter))
1280 RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
1281 rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
1282
1283 ra_info = &psta->cmn.ra_info;
1284 curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
1285 RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
1286 , HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
1287 , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
1288 );
1289
1290 if (0) {
1291 RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
1292 , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
1293 , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
1294 );
1295 RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
1296 , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
1297 , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
1298 );
1299 RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
1300 , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
1301 , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
1302 );
1303 RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
1304 , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
1305 , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
1306 );
1307 }
1308
1309 _RTW_PRINT_SEL(sel, "RTW: [TP] ");
1310 tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
1311 rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
1312 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1313
1314 if (tx_tp_mbips)
1315 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1316 else
1317 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
1318
1319 if (rx_tp_mbips)
1320 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1321 else
1322 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
1323
1324 if (bi_tp_mbips)
1325 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1326 else
1327 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1328
1329
1330 _RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
1331 tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
1332 rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
1333 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1334 if (tx_tp_mbips)
1335 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1336 else
1337 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
1338
1339 if (rx_tp_mbips)
1340 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1341 else
1342 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
1343
1344 if (bi_tp_mbips)
1345 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1346 else
1347 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1348
1349 #if 0
1350 RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
1351 (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
1352 (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
1353 #endif
1354 }
1355
dump_sta_info(void * sel,struct sta_info * psta)1356 void dump_sta_info(void *sel, struct sta_info *psta)
1357 {
1358 struct ra_sta_info *ra_info;
1359 u8 curr_tx_sgi = _FALSE;
1360 u8 curr_tx_rate = 0;
1361
1362 if (!psta)
1363 return;
1364
1365 ra_info = &psta->cmn.ra_info;
1366
1367 RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
1368 MAC_ARG(psta->cmn.mac_addr));
1369 RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
1370 RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
1371 RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
1372 RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
1373 RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
1374 ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
1375 RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
1376 RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
1377 RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
1378 (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
1379 RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
1380 (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
1381 RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
1382 RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
1383
1384 curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
1385 curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
1386 RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
1387 HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
1388 RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
1389 RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
1390 RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
1391 }
1392
rtw_phydm_ra_registed(_adapter * adapter,struct sta_info * psta)1393 void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
1394 {
1395 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1396 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1397 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
1398
1399 if (psta == NULL) {
1400 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
1401 rtw_warn_on(1);
1402 return;
1403 }
1404
1405 if (psta->cmn.mac_id >= macid_ctl->num)
1406 return;
1407
1408 phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
1409 dump_sta_info(RTW_DBGDUMP, psta);
1410 }
1411
init_phydm_info(_adapter * adapter)1412 static void init_phydm_info(_adapter *adapter)
1413 {
1414 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1415 struct dm_struct *phydm = &(hal_data->odmpriv);
1416
1417 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
1418 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
1419 }
1420
1421 #ifdef CONFIG_CTRL_TXSS_BY_TP
rtw_phydm_trx_cfg(_adapter * adapter,bool tx_1ss)1422 void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
1423 {
1424 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1425 enum bb_path txpath = BB_PATH_AB;
1426 enum bb_path rxpath = BB_PATH_AB;
1427 /*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
1428 enum bb_path txpath_1ss = BB_PATH_A;
1429
1430 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1431 txpath = (tx_1ss) ? BB_PATH_A : txpath;
1432
1433 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
1434 RTW_ERR("%s failed\n", __func__);
1435 }
1436 #endif
1437
rtw_hal_runtime_trx_path_decision(_adapter * adapter)1438 u8 rtw_hal_runtime_trx_path_decision(_adapter *adapter)
1439 {
1440 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1441 enum bb_path txpath;
1442 enum bb_path rxpath;
1443 int i;
1444 u8 rst = _FAIL;
1445
1446 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1447 if (!txpath) {
1448 RTW_ERR("%s tx_path_bmp is empty\n", __func__);
1449 rtw_warn_on(1);
1450 goto exit;
1451 }
1452 if (!rxpath) {
1453 RTW_ERR("%s rx_path_bmp is empty\n", __func__);
1454 rtw_warn_on(1);
1455 goto exit;
1456 }
1457
1458 tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
1459 , GET_HAL_TX_PATH_BMP(adapter));
1460
1461 #if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
1462 {
1463 enum bb_path txpath_1ss;
1464
1465 if (txpath == BB_PATH_AB) {
1466 switch (hal_data->max_tx_cnt) {
1467 case 2:
1468 #ifdef CONFIG_RTW_TX_NPATH_EN
1469 if (adapter->registrypriv.tx_npath == 1)
1470 txpath_1ss = BB_PATH_AB;
1471 else
1472 #endif
1473 #ifdef CONFIG_RTW_PATH_DIV
1474 if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
1475 txpath_1ss = BB_PATH_AUTO;
1476 else
1477 #endif
1478 txpath_1ss = BB_PATH_A;
1479 break;
1480 case 1:
1481 #ifdef CONFIG_RTW_PATH_DIV
1482 if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
1483 txpath = txpath_1ss = BB_PATH_AUTO;
1484 else
1485 #endif
1486 txpath = txpath_1ss = BB_PATH_A;
1487 break;
1488 default:
1489 RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
1490 , hal_data->max_tx_cnt);
1491 rtw_warn_on(1);
1492 goto exit;
1493 }
1494 } else
1495 txpath_1ss = txpath;
1496
1497 if (hal_data->txpath_nss[0] != txpath_1ss) {
1498 hal_data->txpath_nss[0] = txpath_1ss;
1499 if (txpath_1ss == BB_PATH_AUTO)
1500 hal_data->txpath_num_nss[0] = 1;
1501 else {
1502 hal_data->txpath_num_nss[0] = 0;
1503 for (i = 0; i < RF_PATH_MAX; i++) {
1504 if (txpath_1ss & BIT(i))
1505 hal_data->txpath_num_nss[0]++;
1506 }
1507 }
1508 }
1509 }
1510 #elif defined(CONFIG_RTL8814B)
1511 {
1512 /* 8814B is always full-TX */
1513 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1514 }
1515 #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
1516 {
1517 #ifdef CONFIG_RTW_TX_NPATH_EN
1518 if (adapter->registrypriv.tx_npath == 1)
1519 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1520 #endif
1521 }
1522 #endif
1523
1524 hal_data->txpath = txpath;
1525 hal_data->rxpath = rxpath;
1526 dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
1527 rst = _SUCCESS;
1528
1529 exit:
1530 return rst;
1531 }
1532
1533 /*
1534 * trx_mode init - 8822B / 8822C / 8192F
1535 * 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
1536 * Path-diversity - 8822B / 8822C / 8192F
1537 * PHYDM API - phydm_api_trx_mode
1538 */
rtw_phydm_config_trx_path(_adapter * adapter)1539 static u8 rtw_phydm_config_trx_path(_adapter *adapter)
1540 {
1541 u8 rst = _SUCCESS;
1542
1543 #if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
1544 {
1545 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1546 enum bb_path txpath = hal_data->txpath;
1547 enum bb_path rxpath = hal_data->rxpath;
1548 enum bb_path txpath_1ss = hal_data->txpath_nss[0];
1549
1550 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
1551 RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
1552 , txpath, rxpath, txpath_1ss);
1553 rtw_warn_on(1);
1554 rst = _FAIL;
1555 }
1556 }
1557 #elif defined(CONFIG_RTL8814B)
1558 {
1559 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1560 enum bb_path txpath = hal_data->txpath;
1561 enum bb_path rxpath = hal_data->rxpath;
1562
1563 if (txpath == BB_PATH_ABCD && rxpath == BB_PATH_ABCD)
1564 rst = config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath);
1565 else
1566 rst = config_phydm_trx_mode_ext_8814b(adapter_to_phydm(adapter), txpath,
1567 rxpath,
1568 txpath, txpath, txpath);
1569 if (rst == FALSE) {
1570 RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
1571 , txpath, rxpath);
1572 rtw_warn_on(1);
1573 rst = _FAIL;
1574 }
1575 }
1576 #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
1577 {
1578 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1579
1580 if (hal_data->txpath_num_nss[0] == 2)
1581 phydm_tx_2path(adapter_to_phydm(adapter));
1582 }
1583 #endif
1584
1585 return rst;
1586 }
1587
rtw_phydm_init(_adapter * adapter)1588 void rtw_phydm_init(_adapter *adapter)
1589 {
1590 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1591 struct dm_struct *phydm = &(hal_data->odmpriv);
1592
1593 rtw_phydm_config_trx_path(adapter);
1594 init_phydm_info(adapter);
1595 hal_data->phydm_init_result = odm_dm_init(phydm);
1596
1597 #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
1598 phydm_pathb_q_matrix_rotate_en(phydm);
1599 #endif
1600 }
1601
rtw_phydm_set_crystal_cap(_adapter * adapter,u8 crystal_cap)1602 bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
1603 {
1604 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1605 struct dm_struct *phydm = &(hal_data->odmpriv);
1606
1607 return phydm_set_crystal_cap_reg(phydm, crystal_cap);
1608 }
1609
1610 #ifdef CONFIG_LPS_PG
1611 /*
1612 static void _lps_pg_state_update(_adapter *adapter)
1613 {
1614 u8 is_in_lpspg = _FALSE;
1615 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1616 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1617 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1618 struct sta_priv *pstapriv = &adapter->stapriv;
1619 struct sta_info *psta = NULL;
1620
1621 if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
1622 is_in_lpspg = _TRUE;
1623 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1624
1625 if (psta)
1626 psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
1627 }
1628 */
rtw_phydm_lps_pg_hdl(_adapter * adapter,struct sta_info * sta,bool in_lpspg)1629 void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
1630 {
1631 struct dm_struct *phydm = adapter_to_phydm(adapter);
1632 /*u8 rate_id;*/
1633
1634 if(sta == NULL) {
1635 RTW_ERR("%s sta is null\n", __func__);
1636 rtw_warn_on(1);
1637 return;
1638 }
1639
1640 if (in_lpspg) {
1641 sta->cmn.ra_info.disable_ra = _TRUE;
1642 sta->cmn.ra_info.disable_pt = _TRUE;
1643 /*TODO : DRV fix tx rate*/
1644 /*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
1645 } else {
1646 sta->cmn.ra_info.disable_ra = _FALSE;
1647 sta->cmn.ra_info.disable_pt = _FALSE;
1648 }
1649
1650 rtw_phydm_ra_registed(adapter, sta);
1651 }
1652 #endif
1653
1654 /*#define DBG_PHYDM_STATE_CHK*/
1655
1656
_rtw_phydm_rfk_condition_check(_adapter * adapter,u8 is_scaning,u8 ifs_linked)1657 static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
1658 {
1659 u8 rfk_allowed = _TRUE;
1660
1661 #ifdef CONFIG_SKIP_RFK_IN_DM
1662 rfk_allowed = _FALSE;
1663 if (0)
1664 RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
1665 return rfk_allowed;
1666 #endif
1667
1668 #ifdef CONFIG_MCC_MODE
1669 /*not in MCC State*/
1670 if (MCC_EN(adapter) &&
1671 rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
1672 rfk_allowed = _FALSE;
1673 if (0)
1674 RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
1675 return rfk_allowed;
1676 }
1677 #endif
1678
1679 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1680
1681 #endif
1682
1683 if (ifs_linked) {
1684 if (is_scaning) {
1685 rfk_allowed = _FALSE;
1686 RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
1687 }
1688 else {
1689 rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
1690 if (rfk_allowed == _FALSE)
1691 RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
1692 }
1693 }
1694
1695 return rfk_allowed;
1696 }
1697
1698 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
_rtw_phydm_iqk_segment_chk(_adapter * adapter,u8 ifs_linked)1699 static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
1700 {
1701 u8 iqk_sgt = _FALSE;
1702
1703 #if 0
1704 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1705 if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
1706 rst = _TRUE;
1707 #else
1708 if (ifs_linked)
1709 iqk_sgt = _TRUE;
1710 #endif
1711 return iqk_sgt;
1712 }
1713 #endif
1714
1715 /*check the tx low rate while unlinked to any AP;for pwr tracking */
_rtw_phydm_pwr_tracking_rate_check(_adapter * adapter)1716 static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
1717 {
1718 int i;
1719 _adapter *iface;
1720 u8 if_tx_rate = 0xFF;
1721 u8 tx_rate = 0xFF;
1722 struct mlme_ext_priv *pmlmeext = NULL;
1723 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1724 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1725 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
1726
1727 for (i = 0; i < dvobj->iface_nums; i++) {
1728 iface = dvobj->padapters[i];
1729 pmlmeext = &(iface->mlmeextpriv);
1730 if ((iface) && rtw_is_adapter_up(iface)) {
1731 #ifdef CONFIG_P2P
1732 if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
1733 if_tx_rate = IEEE80211_OFDM_RATE_6MB;
1734 else
1735 #endif
1736 if_tx_rate = pmlmeext->tx_rate;
1737
1738 if (if_tx_rate < tx_rate) {
1739 /*5G limit ofdm rate*/
1740 if (pHalData->current_channel > 14) {
1741 if (!IS_CCK_RATE(if_tx_rate))
1742 tx_rate = if_tx_rate;
1743 } else {
1744 tx_rate = if_tx_rate;
1745 }
1746 }
1747 RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
1748 }
1749 }
1750
1751 /*suggest by RF James,unlinked setting ofdm rate*/
1752 if (tx_rate == 0xFF)
1753 tx_rate = IEEE80211_OFDM_RATE_6MB;
1754
1755 RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
1756 return tx_rate;
1757 }
1758
1759 #ifdef CONFIG_DYNAMIC_SOML
rtw_dyn_soml_byte_update(_adapter * adapter,u8 data_rate,u32 size)1760 void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
1761 {
1762 struct dm_struct *phydm = adapter_to_phydm(adapter);
1763
1764 phydm_soml_bytes_acq(phydm, data_rate, size);
1765 }
1766
rtw_dyn_soml_para_set(_adapter * adapter,u8 train_num,u8 intvl,u8 period,u8 delay)1767 void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
1768 u8 period, u8 delay)
1769 {
1770 struct dm_struct *phydm = adapter_to_phydm(adapter);
1771
1772 phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
1773 RTW_INFO("%s.\n", __func__);
1774 }
1775
rtw_dyn_soml_config(_adapter * adapter)1776 void rtw_dyn_soml_config(_adapter *adapter)
1777 {
1778 RTW_INFO("%s.\n", __func__);
1779
1780 if (adapter->registrypriv.dyn_soml_en == 1) {
1781 /* Must after phydm_adaptive_soml_init() */
1782 rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
1783 RTW_INFO("dyn_soml_en = 1\n");
1784 } else {
1785 if (adapter->registrypriv.dyn_soml_en == 2) {
1786 rtw_dyn_soml_para_set(adapter,
1787 adapter->registrypriv.dyn_soml_train_num,
1788 adapter->registrypriv.dyn_soml_interval,
1789 adapter->registrypriv.dyn_soml_period,
1790 adapter->registrypriv.dyn_soml_delay);
1791 RTW_INFO("dyn_soml_en = 2\n");
1792 RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
1793 adapter->registrypriv.dyn_soml_train_num,
1794 adapter->registrypriv.dyn_soml_interval,
1795 adapter->registrypriv.dyn_soml_period,
1796 adapter->registrypriv.dyn_soml_delay);
1797 } else if (adapter->registrypriv.dyn_soml_en == 0) {
1798 RTW_INFO("dyn_soml_en = 0\n");
1799 } else
1800 RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
1801 adapter->registrypriv.dyn_soml_en);
1802 }
1803 }
1804 #endif
1805
rtw_phydm_set_rrsr(_adapter * adapter,u32 rrsr_value,bool write_rrsr)1806 void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
1807 {
1808 struct dm_struct *phydm = adapter_to_phydm(adapter);
1809 u32 temp_rrsr =0xFFFFFFFF;
1810
1811 if (adapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
1812 temp_rrsr = adapter->registrypriv.set_rrsr_value;
1813 else
1814 temp_rrsr = rrsr_value;
1815
1816 odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, temp_rrsr);
1817 if(write_rrsr)
1818 phydm_rrsr_set_register(phydm, temp_rrsr);
1819 }
rtw_phydm_dyn_rrsr_en(_adapter * adapter,bool en_rrsr)1820 void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr)
1821 {
1822 struct dm_struct *phydm = adapter_to_phydm(adapter);
1823
1824 phydm_rrsr_en(phydm, en_rrsr);
1825 }
rtw_phydm_read_efuse(_adapter * adapter)1826 void rtw_phydm_read_efuse(_adapter *adapter)
1827 {
1828 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1829 struct dm_struct *phydm = &(hal_data->odmpriv);
1830
1831 /*PHYDM API - thermal trim*/
1832 phydm_get_thermal_trim_offset(phydm);
1833 /*PHYDM API - power trim*/
1834 phydm_get_power_trim_offset(phydm);
1835 }
1836
1837 #ifdef CONFIG_LPS_PWR_TRACKING
rtw_phydm_pwr_tracking_directly(_adapter * adapter)1838 void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
1839 {
1840 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1841 u8 rfk_forbidden = _TRUE;
1842 u8 is_linked = _FALSE;
1843
1844 if (rtw_mi_check_status(adapter, MI_ASSOC))
1845 is_linked = _TRUE;
1846
1847 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
1848 halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1849
1850 odm_txpowertracking_direct_ce(&hal_data->odmpriv);
1851 }
1852 #endif
1853
rtw_phydm_watchdog(_adapter * adapter,bool in_lps)1854 void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
1855 {
1856 u8 bLinked = _FALSE;
1857 u8 bsta_state = _FALSE;
1858 u8 bBtDisabled = _TRUE;
1859 u8 rfk_forbidden = _FALSE;
1860 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1861 u8 segment_iqk = _FALSE;
1862 #endif
1863 u8 tx_unlinked_low_rate = 0xFF;
1864 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1865
1866 if (!rtw_is_hw_init_completed(adapter)) {
1867 RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
1868 return;
1869 }
1870 if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY))
1871 pHalData->bScanInProcess = _TRUE;
1872 else
1873 pHalData->bScanInProcess = _FALSE;
1874
1875 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
1876 bLinked = _TRUE;
1877 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
1878 bsta_state = _TRUE;
1879 }
1880
1881 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
1882 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
1883
1884 #ifdef CONFIG_BT_COEXIST
1885 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
1886 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
1887 (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
1888 #else
1889 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
1890 #endif /* CONFIG_BT_COEXIST */
1891
1892 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
1893 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1894
1895 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1896 segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
1897 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
1898 #endif
1899 #ifdef DBG_PHYDM_STATE_CHK
1900 RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
1901 __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
1902 #endif
1903
1904 if (bLinked == _FALSE) {
1905 tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
1906 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
1907 }
1908
1909 /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
1910 #ifdef DBG_PHYDM_STATE_CHK
1911 RTW_ERR("Not stay in union band, skip phydm\n");
1912 #endif
1913 goto _exit;
1914 }*/
1915
1916 #ifdef CONFIG_TDMADIG
1917 rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
1918 #endif/*CONFIG_TDMADIG*/
1919
1920 if (in_lps)
1921 phydm_watchdog_lps(&pHalData->odmpriv);
1922 else
1923 phydm_watchdog(&pHalData->odmpriv);
1924
1925 #ifdef CONFIG_RTW_ACS
1926 rtw_acs_update_current_info(adapter);
1927 #endif
1928
1929 return;
1930 }
1931
1932
1933