1 /******************************************************************************
2 *
3 * Copyright(c) 2013 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include <rtw_odm.h>
17 #include <hal_data.h>
18
rtw_phydm_ability_ops(_adapter * adapter,HAL_PHYDM_OPS ops,u32 ability)19 u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
20 {
21 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
22 struct dm_struct *podmpriv = &pHalData->odmpriv;
23 u32 result = 0;
24
25 switch (ops) {
26 case HAL_PHYDM_DIS_ALL_FUNC:
27 podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
28 halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
29 break;
30 case HAL_PHYDM_FUNC_SET:
31 podmpriv->support_ability |= ability;
32 break;
33 case HAL_PHYDM_FUNC_CLR:
34 podmpriv->support_ability &= ~(ability);
35 break;
36 case HAL_PHYDM_ABILITY_BK:
37 /* dm flag backup*/
38 podmpriv->bk_support_ability = podmpriv->support_ability;
39 pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
40 break;
41 case HAL_PHYDM_ABILITY_RESTORE:
42 /* restore dm flag */
43 podmpriv->support_ability = podmpriv->bk_support_ability;
44 halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
45 break;
46 case HAL_PHYDM_ABILITY_SET:
47 podmpriv->support_ability = ability;
48 break;
49 case HAL_PHYDM_ABILITY_GET:
50 result = podmpriv->support_ability;
51 break;
52 }
53 return result;
54 }
55
56 /* set ODM_CMNINFO_IC_TYPE based on chip_type */
rtw_odm_init_ic_type(_adapter * adapter)57 void rtw_odm_init_ic_type(_adapter *adapter)
58 {
59 struct dm_struct *odm = adapter_to_phydm(adapter);
60 u32 ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
61
62 rtw_warn_on(!ic_type);
63
64 odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
65 }
66
rtw_odm_adaptivity_ver_msg(void * sel,_adapter * adapter)67 void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
68 {
69 RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
70 }
71
72 #define RTW_ADAPTIVITY_EN_DISABLE 0
73 #define RTW_ADAPTIVITY_EN_ENABLE 1
74 #define RTW_ADAPTIVITY_EN_AUTO 2
75
rtw_odm_adaptivity_en_msg(void * sel,_adapter * adapter)76 void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
77 {
78 struct registry_priv *regsty = &adapter->registrypriv;
79
80 RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
81
82 if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
83 _RTW_PRINT_SEL(sel, "DISABLE\n");
84 else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
85 _RTW_PRINT_SEL(sel, "ENABLE\n");
86 else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO)
87 _RTW_PRINT_SEL(sel, "AUTO\n");
88 else
89 _RTW_PRINT_SEL(sel, "INVALID\n");
90 }
91
92 #define RTW_ADAPTIVITY_MODE_NORMAL 0
93 #define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
94
rtw_odm_adaptivity_mode_msg(void * sel,_adapter * adapter)95 void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
96 {
97 struct registry_priv *regsty = &adapter->registrypriv;
98
99 if (regsty->adaptivity_en != RTW_ADAPTIVITY_EN_ENABLE)
100 return;
101
102 RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
103
104 if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
105 _RTW_PRINT_SEL(sel, "NORMAL\n");
106 else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
107 _RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
108 else
109 _RTW_PRINT_SEL(sel, "INVALID\n");
110 }
111
rtw_odm_adaptivity_config_msg(void * sel,_adapter * adapter)112 void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
113 {
114 rtw_odm_adaptivity_ver_msg(sel, adapter);
115 rtw_odm_adaptivity_en_msg(sel, adapter);
116 rtw_odm_adaptivity_mode_msg(sel, adapter);
117 }
118
rtw_odm_adaptivity_needed(_adapter * adapter)119 bool rtw_odm_adaptivity_needed(_adapter *adapter)
120 {
121 struct registry_priv *regsty = &adapter->registrypriv;
122 bool ret = _FALSE;
123
124 if (regsty->adaptivity_en)
125 ret = _TRUE;
126
127 return ret;
128 }
129
rtw_odm_adaptivity_update(struct dvobj_priv * dvobj)130 void rtw_odm_adaptivity_update(struct dvobj_priv *dvobj)
131 {
132 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(dvobj_get_primary_adapter(dvobj));
133 struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
134 struct dm_struct *odm = dvobj_to_phydm(dvobj);
135 u8 edcca_mode = RTW_EDCCA_NORMAL;
136
137 if (hal_data->current_band_type == BAND_ON_2_4G)
138 edcca_mode = rfctl->edcca_mode_2g;
139 #if CONFIG_IEEE80211_BAND_5GHZ
140 else if (hal_data->current_band_type == BAND_ON_5G)
141 edcca_mode = rfctl->edcca_mode_5g;
142 #endif
143
144 rfctl->adaptivity_en = (edcca_mode == RTW_EDCCA_NORMAL || edcca_mode == RTW_EDCCA_MODE_NUM) ? 0 : 1;
145 phydm_adaptivity_info_init(odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, edcca_mode == RTW_EDCCA_CS ? TRUE : FALSE);
146 }
147
rtw_odm_adaptivity_parm_msg(void * sel,_adapter * adapter)148 void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
149 {
150 struct dm_struct *odm = adapter_to_phydm(adapter);
151
152 rtw_odm_adaptivity_config_msg(sel, adapter);
153
154 RTW_PRINT_SEL(sel, "%10s %16s\n"
155 , "th_l2h_ini", "th_edcca_hl_diff");
156 RTW_PRINT_SEL(sel, "0x%-8x %-16d\n"
157 , (u8)odm->th_l2h_ini
158 , odm->th_edcca_hl_diff
159 );
160 }
161
rtw_odm_adaptivity_parm_set(_adapter * adapter,s8 th_l2h_ini,s8 th_edcca_hl_diff)162 void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)
163 {
164 struct dm_struct *odm = adapter_to_phydm(adapter);
165
166 odm->th_l2h_ini = th_l2h_ini;
167 odm->th_edcca_hl_diff = th_edcca_hl_diff;
168 }
169
rtw_odm_get_perpkt_rssi(void * sel,_adapter * adapter)170 void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
171 {
172 struct dm_struct *odm = adapter_to_phydm(adapter);
173
174 RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
175 HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
176 }
177
178
rtw_odm_acquirespinlock(_adapter * adapter,enum rt_spinlock_type type)179 void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type)
180 {
181 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
182 _irqL irqL;
183
184 switch (type) {
185 case RT_IQK_SPINLOCK:
186 _enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
187 default:
188 break;
189 }
190 }
191
rtw_odm_releasespinlock(_adapter * adapter,enum rt_spinlock_type type)192 void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type)
193 {
194 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
195 _irqL irqL;
196
197 switch (type) {
198 case RT_IQK_SPINLOCK:
199 _exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
200 default:
201 break;
202 }
203 }
204
rtw_odm_get_tx_power_mbm(struct dm_struct * dm,u8 rfpath,u8 rate,u8 bw,u8 cch)205 s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch)
206 {
207 return phy_get_txpwr_single_mbm(dm->adapter, rfpath, mgn_rate_to_rs(rate), rate, bw, cch, 0, 0, 0, NULL);
208 }
209
210 #ifdef CONFIG_DFS_MASTER
rtw_odm_radar_detect_reset(_adapter * adapter)211 inline void rtw_odm_radar_detect_reset(_adapter *adapter)
212 {
213 phydm_radar_detect_reset(adapter_to_phydm(adapter));
214 }
215
rtw_odm_radar_detect_disable(_adapter * adapter)216 inline void rtw_odm_radar_detect_disable(_adapter *adapter)
217 {
218 phydm_radar_detect_disable(adapter_to_phydm(adapter));
219 }
220
221 /* called after ch, bw is set */
rtw_odm_radar_detect_enable(_adapter * adapter)222 inline void rtw_odm_radar_detect_enable(_adapter *adapter)
223 {
224 phydm_radar_detect_enable(adapter_to_phydm(adapter));
225 }
226
rtw_odm_radar_detect(_adapter * adapter)227 inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
228 {
229 return phydm_radar_detect(adapter_to_phydm(adapter));
230 }
231
232 static enum phydm_dfs_region_domain _rtw_dfs_regd_to_phydm[] = {
233 [RTW_DFS_REGD_NONE] = PHYDM_DFS_DOMAIN_UNKNOWN,
234 [RTW_DFS_REGD_FCC] = PHYDM_DFS_DOMAIN_FCC,
235 [RTW_DFS_REGD_MKK] = PHYDM_DFS_DOMAIN_MKK,
236 [RTW_DFS_REGD_ETSI] = PHYDM_DFS_DOMAIN_ETSI,
237 };
238
239 #define rtw_dfs_regd_to_phydm(region) (((region) >= RTW_DFS_REGD_NUM) ? _rtw_dfs_regd_to_phydm[RTW_DFS_REGD_NONE] : _rtw_dfs_regd_to_phydm[(region)])
240
rtw_odm_update_dfs_region(struct dvobj_priv * dvobj)241 void rtw_odm_update_dfs_region(struct dvobj_priv *dvobj)
242 {
243 odm_cmn_info_init(dvobj_to_phydm(dvobj), ODM_CMNINFO_DFS_REGION_DOMAIN, rtw_dfs_regd_to_phydm(rtw_rfctl_get_dfs_domain(dvobj_to_rfctl(dvobj))));
244 }
245
rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv * dvobj)246 inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
247 {
248 return phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
249 }
250 #endif /* CONFIG_DFS_MASTER */
251
rtw_odm_parse_rx_phy_status_chinfo(union recv_frame * rframe,u8 * phys)252 void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
253 {
254 #ifndef DBG_RX_PHYSTATUS_CHINFO
255 #define DBG_RX_PHYSTATUS_CHINFO 0
256 #endif
257
258 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
259 _adapter *adapter = rframe->u.hdr.adapter;
260 struct dm_struct *phydm = adapter_to_phydm(adapter);
261 struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
262 u8 *wlanhdr = get_recvframe_data(rframe);
263
264 if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
265 /*
266 * 8723D:
267 * type_0(CCK)
268 * l_rxsc
269 * is filled with primary channel SC, not real rxsc.
270 * 0:LSC, 1:USC
271 * type_1(OFDM)
272 * rf_mode
273 * RF bandwidth when RX
274 * l_rxsc(legacy), ht_rxsc
275 * see below RXSC N-series
276 * type_2(Not used)
277 */
278 /*
279 * 8821C, 8822B:
280 * type_0(CCK)
281 * l_rxsc
282 * is filled with primary channel SC, not real rxsc.
283 * 0:LSC, 1:USC
284 * type_1(OFDM)
285 * rf_mode
286 * RF bandwidth when RX
287 * l_rxsc(legacy), ht_rxsc
288 * see below RXSC AC-series
289 * type_2(Not used)
290 */
291
292 if ((*phys & 0xf) == 0) {
293 struct phy_sts_rpt_jgr2_type0 *phys_t0 = (struct phy_sts_rpt_jgr2_type0 *)phys;
294
295 if (DBG_RX_PHYSTATUS_CHINFO) {
296 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
297 , *phys & 0xf
298 , MAC_ARG(get_ta(wlanhdr))
299 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
300 , HDATA_RATE(attrib->data_rate)
301 , phys_t0->band, phys_t0->channel, phys_t0->rxsc
302 );
303 }
304
305 } else if ((*phys & 0xf) == 1) {
306 struct phy_sts_rpt_jgr2_type1 *phys_t1 = (struct phy_sts_rpt_jgr2_type1 *)phys;
307 u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
308 u8 pkt_cch = 0;
309 u8 pkt_bw = CHANNEL_WIDTH_20;
310
311 #if ODM_IC_11N_SERIES_SUPPORT
312 if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
313 /* RXSC N-series */
314 #define RXSC_DUP 0
315 #define RXSC_LSC 1
316 #define RXSC_USC 2
317 #define RXSC_40M 3
318
319 static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
320
321 if (phys_t1->rf_mode == 0) {
322 pkt_cch = phys_t1->channel;
323 pkt_bw = CHANNEL_WIDTH_20;
324 } else if (phys_t1->rf_mode == 1) {
325 if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
326 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
327 pkt_bw = CHANNEL_WIDTH_20;
328 } else if (rxsc == RXSC_40M) {
329 pkt_cch = phys_t1->channel;
330 pkt_bw = CHANNEL_WIDTH_40;
331 }
332 } else
333 rtw_warn_on(1);
334
335 goto type1_end;
336 }
337 #endif /* ODM_IC_11N_SERIES_SUPPORT */
338
339 #if ODM_IC_11AC_SERIES_SUPPORT
340 if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
341 /* RXSC AC-series */
342 #define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */
343
344 #define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */
345 #define RXSC_L20M_OF_160M 6
346 #define RXSC_L20M_OF_80M 4
347 #define RXSC_L20M_OF_40M 2
348 #define RXSC_U20M_OF_40M 1
349 #define RXSC_U20M_OF_80M 3
350 #define RXSC_U20M_OF_160M 5
351 #define RXSC_UU20M_OF_160M 7
352
353 #define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */
354 #define RXSC_L40M_OF_80M 10
355 #define RXSC_U40M_OF_80M 9
356 #define RXSC_U40M_OF_160M 11
357
358 #define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */
359 #define RXSC_U80M_OF_160M 13
360
361 static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
362
363 if (phys_t1->rf_mode == 0) {
364 /* RF 20MHz */
365 pkt_cch = phys_t1->channel;
366 pkt_bw = CHANNEL_WIDTH_20;
367 goto type1_end;
368 }
369
370 if (rxsc == 0) {
371 /* RF and RX with same BW */
372 if (attrib->data_rate >= DESC_RATEMCS0) {
373 pkt_cch = phys_t1->channel;
374 pkt_bw = phys_t1->rf_mode;
375 }
376 goto type1_end;
377 }
378
379 if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
380 || (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
381 || (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
382 ) {
383 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
384 pkt_bw = CHANNEL_WIDTH_20;
385 } else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
386 || (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
387 ) {
388 if (attrib->data_rate >= DESC_RATEMCS0) {
389 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
390 pkt_bw = CHANNEL_WIDTH_40;
391 }
392 } else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
393 ) {
394 if (attrib->data_rate >= DESC_RATEMCS0) {
395 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
396 pkt_bw = CHANNEL_WIDTH_80;
397 }
398 } else
399 rtw_warn_on(1);
400
401 }
402 #endif /* ODM_IC_11AC_SERIES_SUPPORT */
403
404 type1_end:
405 if (DBG_RX_PHYSTATUS_CHINFO) {
406 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
407 , *phys & 0xf
408 , MAC_ARG(get_ta(wlanhdr))
409 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
410 , HDATA_RATE(attrib->data_rate)
411 , phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
412 , pkt_cch, pkt_bw
413 );
414 }
415
416 /* for now, only return cneter channel of 20MHz packet */
417 if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
418 attrib->ch = pkt_cch;
419
420 } else {
421 struct phy_sts_rpt_jgr2_type2 *phys_t2 = (struct phy_sts_rpt_jgr2_type2 *)phys;
422
423 if (DBG_RX_PHYSTATUS_CHINFO) {
424 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
425 , *phys & 0xf
426 , MAC_ARG(get_ta(wlanhdr))
427 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
428 , HDATA_RATE(attrib->data_rate)
429 , phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
430 );
431 }
432 }
433 }
434 #endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
435
436 }
437
438 #if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
439 void
debug_DACK(struct dm_struct * dm)440 debug_DACK(
441 struct dm_struct *dm
442 )
443 {
444 //P_PHYDM_FUNC dm;
445 //dm = &(SysMib.ODM.Phydm);
446 //PIQK_OFFLOAD_PARM pIQK_info;
447 //pIQK_info= &(SysMib.ODM.IQKParm);
448 u8 i;
449 u32 temp1, temp2, temp3;
450
451 temp1 = odm_get_bb_reg(dm, 0x1860, bMaskDWord);
452 temp2 = odm_get_bb_reg(dm, 0x4160, bMaskDWord);
453 temp3 = odm_get_bb_reg(dm, 0x9b4, bMaskDWord);
454
455 odm_set_bb_reg(dm, 0x9b4, bMaskDWord, 0xdb66db00);
456
457 //pathA
458 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
459 odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
460
461 RTW_INFO("path A i\n");
462 //i
463 for (i = 0; i < 0xf; i++) {
464 odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
465 RTW_INFO("[0][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000));
466 //pIQK_info->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
467 }
468 RTW_INFO("path A q\n");
469 //q
470 for (i = 0; i < 0xf; i++) {
471 odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
472 RTW_INFO("[0][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000));
473 //pIQK_info->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
474 }
475 //pathB
476 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
477 odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
478
479 RTW_INFO("\npath B i\n");
480 //i
481 for (i = 0; i < 0xf; i++) {
482 odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
483 RTW_INFO("[1][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x4510,0x7fc0000));
484 //pIQK_info->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
485 }
486 RTW_INFO("path B q\n");
487 //q
488 for (i = 0; i < 0xf; i++) {
489 odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
490 RTW_INFO("[1][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x453c,0x7fc0000));
491 //pIQK_info->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
492 }
493
494 //restore to normal
495 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
496 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
497 odm_set_bb_reg(dm, 0x1860, bMaskDWord, temp1);
498 odm_set_bb_reg(dm, 0x4160, bMaskDWord, temp2);
499 odm_set_bb_reg(dm, 0x9b4, bMaskDWord, temp3);
500
501
502 }
503
504 void
debug_IQK(struct dm_struct * dm,IN u8 idx,IN u8 path)505 debug_IQK(
506 struct dm_struct *dm,
507 IN u8 idx,
508 IN u8 path
509 )
510 {
511 u8 i, ch;
512 u32 tmp;
513 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
514
515 RTW_INFO("idx = %d, path = %d\n", idx, path);
516
517 odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);
518
519 if (idx == TX_IQK) {//TXCFIR
520 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
521 } else {//RXCFIR
522 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
523 }
524 odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
525 odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
526 for (i = 0; i <= 16; i++) {
527 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
528 tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
529 RTW_INFO("iqk_cfir_real[%d][%d][%d] = 0x%x\n", path, idx, i, ((tmp & 0x0fff0000) >> 16));
530 //iqk_info->iqk_cfir_real[ch][path][idx][i] =
531 // (tmp & 0x0fff0000) >> 16;
532 RTW_INFO("iqk_cfir_imag[%d][%d][%d] = 0x%x\n", path, idx, i, (tmp & 0x0fff));
533 //iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0x0fff;
534 }
535 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
536 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
537 }
538
539 __odm_func__ void
debug_information_8822c(struct dm_struct * dm)540 debug_information_8822c(
541 struct dm_struct *dm)
542 {
543 struct dm_dpk_info *dpk_info = &dm->dpk_info;
544
545 u32 reg_rf18;
546
547 if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
548 dpk_info->is_tssi_mode = true;
549 else
550 dpk_info->is_tssi_mode = false;
551
552 reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
553
554 dpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
555 dpk_info->dpk_ch = (u8)reg_rf18 & 0xff;
556 dpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
557
558 RTW_INFO("[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
559 dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? "2G" : "5G",
560 dpk_info->dpk_ch,
561 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
562 }
563
564 extern void _dpk_get_coef_8822c(void *dm_void, u8 path);
565
566 __odm_func__ void
debug_reload_data_8822c(void * dm_void)567 debug_reload_data_8822c(
568 void *dm_void)
569 {
570 struct dm_struct *dm = (struct dm_struct *)dm_void;
571 struct dm_dpk_info *dpk_info = &dm->dpk_info;
572
573 u8 path;
574 u32 u32tmp;
575
576 debug_information_8822c(dm);
577
578 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
579
580 RTW_INFO("[DPK] Reload path: 0x%x\n", path);
581
582 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
583
584 /*txagc bnd*/
585 if (dpk_info->dpk_band == 0x0)
586 u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
587 else
588 u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
589
590 RTW_INFO("[DPK] txagc bnd = 0x%08x\n", u32tmp);
591
592 u32tmp = odm_get_bb_reg(dm, R_0x1b64, MASKBYTE3);
593 RTW_INFO("[DPK] dpk_txagc = 0x%08x\n", u32tmp);
594
595 //debug_coef_write_8822c(dm, path, dpk_info->dpk_path_ok & BIT(path) >> path);
596 _dpk_get_coef_8822c(dm, path);
597
598 //debug_one_shot_8822c(dm, path, DPK_ON);
599
600 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
601
602 if (path == RF_PATH_A)
603 u32tmp = odm_get_bb_reg(dm, R_0x1b04, 0x0fffffff);
604 else
605 u32tmp = odm_get_bb_reg(dm, R_0x1b5c, 0x0fffffff);
606
607 RTW_INFO("[DPK] dpk_gs = 0x%08x\n", u32tmp);
608
609 }
610 }
611
odm_lps_pg_debug_8822c(void * dm_void)612 void odm_lps_pg_debug_8822c(void *dm_void)
613 {
614 struct dm_struct *dm = (struct dm_struct *)dm_void;
615
616 debug_DACK(dm);
617 debug_IQK(dm, TX_IQK, RF_PATH_A);
618 debug_IQK(dm, RX_IQK, RF_PATH_A);
619 debug_IQK(dm, TX_IQK, RF_PATH_B);
620 debug_IQK(dm, RX_IQK, RF_PATH_B);
621 debug_reload_data_8822c(dm);
622 }
623 #endif /* defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG) */
624
625