1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8188E_SPEC_H__ 16 #define __RTL8188E_SPEC_H__ 17 18 19 /* ************************************************************ 20 * 8188E Regsiter offset definition 21 * ************************************************************ */ 22 23 24 /* ************************************************************ 25 * 26 * ************************************************************ */ 27 28 /* ----------------------------------------------------- 29 * 30 * 0x0000h ~ 0x00FFh System Configuration 31 * 32 * ----------------------------------------------------- */ 33 #define REG_BB_PAD_CTRL 0x0064 34 #define REG_HMEBOX_E0 0x0088 35 #define REG_HMEBOX_E1 0x008A 36 #define REG_HMEBOX_E2 0x008C 37 #define REG_HMEBOX_E3 0x008E 38 #define REG_HMEBOX_EXT_0 0x01F0 39 #define REG_HMEBOX_EXT_1 0x01F4 40 #define REG_HMEBOX_EXT_2 0x01F8 41 #define REG_HMEBOX_EXT_3 0x01FC 42 #define REG_HIMR_88E 0x00B0 /* RTL8188E */ 43 #define REG_HISR_88E 0x00B4 /* RTL8188E */ 44 #define REG_HIMRE_88E 0x00B8 /* RTL8188E */ 45 #define REG_HISRE_88E 0x00BC /* RTL8188E */ 46 47 #define REG_DBI_WDATA_8188E 0x0348 /* DBI Write data */ 48 #define REG_DBI_RDATA_8188E 0x034C /* DBI Read data */ 49 #define REG_DBI_ADDR_8188E 0x0350 /* DBI Address */ 50 #define REG_DBI_FLAG_8188E 0x0352 /* DBI Read/Write Flag */ 51 #define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */ 52 #define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */ 53 #define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */ 54 55 #define REG_MACID_NO_LINK_0 0x0484 56 #define REG_MACID_NO_LINK_1 0x0488 57 #define REG_MACID_PAUSE_0 0x048c 58 #define REG_MACID_PAUSE_1 0x0490 59 60 /* ----------------------------------------------------- 61 * 62 * 0x0100h ~ 0x01FFh MACTOP General Configuration 63 * 64 * ----------------------------------------------------- */ 65 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 66 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 67 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 68 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 69 70 /* ----------------------------------------------------- 71 * 72 * 0x0200h ~ 0x027Fh TXDMA Configuration 73 * 74 * ----------------------------------------------------- */ 75 76 /* ----------------------------------------------------- 77 * 78 * 0x0280h ~ 0x02FFh RXDMA Configuration 79 * 80 * ----------------------------------------------------- */ 81 82 /* ----------------------------------------------------- 83 * 84 * 0x0300h ~ 0x03FFh PCIe 85 * 86 * ----------------------------------------------------- */ 87 #define REG_PCIE_HRPWM_8188E 0x0361 /* PCIe RPWM */ 88 #define REG_PCIE_HCPWM_8188E 0x0363 /* PCIe CPWM */ 89 90 /* ----------------------------------------------------- 91 * 92 * 0x0400h ~ 0x047Fh Protocol Configuration 93 * 94 * ----------------------------------------------------- */ 95 #ifdef CONFIG_WOWLAN 96 #define REG_TXPKTBUF_IV_LOW 0x01a4 97 #define REG_TXPKTBUF_IV_HIGH 0x01a8 98 #endif 99 100 /* ----------------------------------------------------- 101 * 102 * 0x0500h ~ 0x05FFh EDCA Configuration 103 * 104 * ----------------------------------------------------- */ 105 106 /* ----------------------------------------------------- 107 * 108 * 0x0600h ~ 0x07FFh WMAC Configuration 109 * 110 * ----------------------------------------------------- */ 111 #ifdef CONFIG_RF_POWER_TRIM 112 #define EEPROM_RF_GAIN_OFFSET 0xC1 113 #define EEPROM_RF_GAIN_VAL 0xF6 114 #define EEPROM_THERMAL_OFFSET 0xF5 115 #endif /*CONFIG_RF_POWER_TRIM*/ 116 /* ---------------------------------------------------------------------------- 117 * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) 118 * ---------------------------------------------------------------------------- 119 * IOL config for REG_FDHM0(Reg0x88) */ 120 #define CMD_INIT_LLT BIT0 121 #define CMD_READ_EFUSE_MAP BIT1 122 #define CMD_EFUSE_PATCH BIT2 123 #define CMD_IOCONFIG BIT3 124 #define CMD_INIT_LLT_ERR BIT4 125 #define CMD_READ_EFUSE_MAP_ERR BIT5 126 #define CMD_EFUSE_PATCH_ERR BIT6 127 #define CMD_IOCONFIG_ERR BIT7 128 129 /* ----------------------------------------------------- 130 * 131 * Redifine register definition for compatibility 132 * 133 * ----------------------------------------------------- */ 134 135 /* TODO: use these definition when using REG_xxx naming rule. 136 * NOTE: DO NOT Remove these definition. Use later. */ 137 #define ISR_88E REG_HISR_88E 138 139 #ifdef CONFIG_PCI_HCI 140 /* #define IMR_RX_MASK (IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */ 141 #define IMR_TX_MASK (IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E) 142 143 #ifdef CONFIG_CONCURRENT_MODE 144 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E) 145 #else 146 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E) 147 #endif 148 149 #define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E) 150 #endif 151 152 /* ---------------------------------------------------------------------------- 153 * 8192C EEPROM/EFUSE share register definition. 154 * ---------------------------------------------------------------------------- */ 155 156 #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ 157 #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ 158 159 #endif /* __RTL8188E_SPEC_H__ */ 160