1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_INIT_C_
16
17 #include <rtl8188f_hal.h>
18 #include "hal_com_h2c.h"
19 #include "hal8188f_fw.h"
20
21 #if 0 /* FW tx packet write */
22 #define FW_DOWNLOAD_SIZE_8188F 8192
23 #endif
24
25 static void
_FWDownloadEnable(PADAPTER padapter,BOOLEAN enable)26 _FWDownloadEnable(
27 PADAPTER padapter,
28 BOOLEAN enable
29 )
30 {
31 u8 tmp, count = 0;
32
33 if (enable) {
34 /* 8051 enable */
35 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
36 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
37
38 tmp = rtw_read8(padapter, REG_MCUFWDL);
39 rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
40
41 do {
42 tmp = rtw_read8(padapter, REG_MCUFWDL);
43 if (tmp & 0x01)
44 break;
45 rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
46 rtw_msleep_os(1);
47 } while (count++ < 100);
48 if (count > 0)
49 RTW_INFO("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count);
50
51 /* 8051 reset */
52 tmp = rtw_read8(padapter, REG_MCUFWDL + 2);
53 rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
54 } else {
55 /* MCU firmware download disable. */
56 tmp = rtw_read8(padapter, REG_MCUFWDL);
57 rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
58 }
59 }
60
61 static int
_BlockWrite(PADAPTER padapter,void * buffer,u32 buffSize)62 _BlockWrite(
63 PADAPTER padapter,
64 void *buffer,
65 u32 buffSize
66 )
67 {
68 int ret = _SUCCESS;
69
70 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
71 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
72 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
73 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
74 u32 remainSize_p1 = 0, remainSize_p2 = 0;
75 u8 *bufferPtr = (u8 *)buffer;
76 u32 i = 0, offset = 0;
77 #ifdef CONFIG_PCI_HCI
78 u8 remainFW[4] = {0, 0, 0, 0};
79 u8 *p = NULL;
80 #endif
81
82 #ifdef CONFIG_USB_HCI
83 blockSize_p1 = 196; /* the same as 8188e */
84 #endif
85
86 /*printk("====>%s %d\n", __func__, __LINE__); */
87
88 /*3 Phase #1 */
89 blockCount_p1 = buffSize / blockSize_p1;
90 remainSize_p1 = buffSize % blockSize_p1;
91
92
93
94 for (i = 0; i < blockCount_p1; i++) {
95 #ifdef CONFIG_USB_HCI
96 ret = rtw_writeN(padapter, (FW_8188F_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
97 #else
98 ret = rtw_write32(padapter, (FW_8188F_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32 *)(bufferPtr + i * blockSize_p1))));
99 #endif
100 if (ret == _FAIL) {
101 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
102 goto exit;
103 }
104 }
105
106 #ifdef CONFIG_PCI_HCI
107 p = (u8 *)((u32 *)(bufferPtr + blockCount_p1 * blockSize_p1));
108 if (remainSize_p1) {
109 switch (remainSize_p1) {
110 case 0:
111 break;
112 case 3:
113 remainFW[2] = *(p + 2);
114 case 2:
115 remainFW[1] = *(p + 1);
116 case 1:
117 remainFW[0] = *(p);
118 ret = rtw_write32(padapter, (FW_8188F_START_ADDRESS + blockCount_p1 * blockSize_p1),
119 le32_to_cpu(*(u32 *)remainFW));
120 }
121 return ret;
122 }
123 #endif
124
125 /*3 Phase #2 */
126 if (remainSize_p1) {
127 offset = blockCount_p1 * blockSize_p1;
128
129 blockCount_p2 = remainSize_p1 / blockSize_p2;
130 remainSize_p2 = remainSize_p1 % blockSize_p2;
131
132
133
134 #ifdef CONFIG_USB_HCI
135 for (i = 0; i < blockCount_p2; i++) {
136 ret = rtw_writeN(padapter, (FW_8188F_START_ADDRESS + offset + i * blockSize_p2), blockSize_p2, (bufferPtr + offset + i * blockSize_p2));
137
138 if (ret == _FAIL)
139 goto exit;
140 }
141 #endif
142 }
143
144 /*3 Phase #3 */
145 if (remainSize_p2) {
146 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
147
148 blockCount_p3 = remainSize_p2 / blockSize_p3;
149
150
151 for (i = 0; i < blockCount_p3; i++) {
152 ret = rtw_write8(padapter, (FW_8188F_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
153
154 if (ret == _FAIL) {
155 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
156 goto exit;
157 }
158 }
159 }
160 exit:
161 return ret;
162 }
163
164 static int
_PageWrite(PADAPTER padapter,u32 page,void * buffer,u32 size)165 _PageWrite(
166 PADAPTER padapter,
167 u32 page,
168 void *buffer,
169 u32 size
170 )
171 {
172 u8 value8;
173 u8 u8Page = (u8)(page & 0x07);
174
175 value8 = (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
176 rtw_write8(padapter, REG_MCUFWDL + 2, value8);
177
178 return _BlockWrite(padapter, buffer, size);
179 }
180
181 #ifdef CONFIG_PCI_HCI
182 static void
_FillDummy(u8 * pFwBuf,u32 * pFwLen)183 _FillDummy(
184 u8 *pFwBuf,
185 u32 *pFwLen
186 )
187 {
188 u32 FwLen = *pFwLen;
189 u8 remain = (u8)(FwLen % 4);
190
191 remain = (remain == 0) ? 0 : (4 - remain);
192
193 while (remain > 0) {
194 pFwBuf[FwLen] = 0;
195 FwLen++;
196 remain--;
197 }
198
199 *pFwLen = FwLen;
200 }
201 #endif
202 static int
_WriteFW(PADAPTER padapter,void * buffer,u32 size)203 _WriteFW(
204 PADAPTER padapter,
205 void *buffer,
206 u32 size
207 )
208 {
209 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
210 int ret = _SUCCESS;
211 u32 pageNums, remainSize;
212 u32 page, offset;
213 u8 *bufferPtr = (u8 *)buffer;
214
215 #ifdef CONFIG_PCI_HCI
216 /* 20100120 Joseph: Add for 88CE normal chip. */
217 /* Fill in zero to make firmware image to dword alignment. */
218 _FillDummy(bufferPtr, &size);
219 #endif
220
221 pageNums = size / MAX_DLFW_PAGE_SIZE;
222 /*RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */
223 remainSize = size % MAX_DLFW_PAGE_SIZE;
224
225 for (page = 0; page < pageNums; page++) {
226 offset = page * MAX_DLFW_PAGE_SIZE;
227 ret = _PageWrite(padapter, page, bufferPtr + offset, MAX_DLFW_PAGE_SIZE);
228
229 if (ret == _FAIL) {
230 printk("====>%s %d\n", __func__, __LINE__);
231 goto exit;
232 }
233 }
234 if (remainSize) {
235 offset = pageNums * MAX_DLFW_PAGE_SIZE;
236 page = pageNums;
237 ret = _PageWrite(padapter, page, bufferPtr + offset, remainSize);
238
239 if (ret == _FAIL) {
240 printk("====>%s %d\n", __func__, __LINE__);
241 goto exit;
242 }
243 }
244
245 exit:
246 return ret;
247 }
248
_8051Reset8188(PADAPTER padapter)249 void _8051Reset8188(PADAPTER padapter)
250 {
251 u8 cpu_rst;
252 u8 io_rst;
253
254 #if 0
255 io_rst = rtw_read8(padapter, REG_RSV_CTRL);
256 rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1));
257 #endif
258
259 /* Reset 8051(WLMCU) IO wrapper */
260 /* 0x1c[8] = 0 */
261 /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */
262 io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
263 io_rst &= ~BIT(0);
264 rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
265
266 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
267 cpu_rst &= ~BIT(2);
268 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
269
270 #if 0
271 io_rst = rtw_read8(padapter, REG_RSV_CTRL);
272 rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1));
273 #endif
274
275 /* Enable 8051 IO wrapper */
276 /* 0x1c[8] = 1 */
277 io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
278 io_rst |= BIT(0);
279 rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
280
281 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
282 cpu_rst |= BIT(2);
283 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
284
285 RTW_INFO("%s: Finish\n", __func__);
286 }
287
polling_fwdl_chksum(_adapter * adapter,u32 min_cnt,u32 timeout_ms)288 static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
289 {
290 s32 ret = _FAIL;
291 u32 value32;
292 systime start = rtw_get_current_time();
293 u32 cnt = 0;
294
295 /* polling CheckSum report */
296 do {
297 cnt++;
298 value32 = rtw_read32(adapter, REG_MCUFWDL);
299 if (value32 & FWDL_ChkSum_rpt || RTW_CANNOT_IO(adapter))
300 break;
301 rtw_yield_os();
302 } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
303
304 if (!(value32 & FWDL_ChkSum_rpt))
305 goto exit;
306
307 if (rtw_fwdl_test_trigger_chksum_fail())
308 goto exit;
309
310 ret = _SUCCESS;
311
312 exit:
313 RTW_INFO("%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __func__
314 , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
315
316 return ret;
317 }
318
_FWFreeToGo(_adapter * adapter,u32 min_cnt,u32 timeout_ms)319 static s32 _FWFreeToGo(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
320 {
321 s32 ret = _FAIL;
322 u32 value32;
323 systime start = rtw_get_current_time();
324 u32 cnt = 0;
325 u32 value_to_check = 0;
326 u32 value_expected = (MCUFWDL_RDY | FWDL_ChkSum_rpt | WINTINI_RDY | RAM_DL_SEL);
327
328 value32 = rtw_read32(adapter, REG_MCUFWDL);
329 value32 |= MCUFWDL_RDY;
330 value32 &= ~WINTINI_RDY;
331 rtw_write32(adapter, REG_MCUFWDL, value32);
332
333 _8051Reset8188(adapter);
334
335 /* polling for FW ready */
336 do {
337 cnt++;
338 value32 = rtw_read32(adapter, REG_MCUFWDL);
339 value_to_check = value32 & value_expected;
340 if ((value_to_check == value_expected) || RTW_CANNOT_IO(adapter))
341 break;
342 rtw_yield_os();
343 } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
344
345 if (value_to_check != value_expected)
346 goto exit;
347
348 if (rtw_fwdl_test_trigger_wintint_rdy_fail())
349 goto exit;
350
351 ret = _SUCCESS;
352
353 exit:
354 RTW_INFO("%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __func__
355 , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
356
357 return ret;
358 }
359
360 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
361
rtl8188f_FirmwareSelfReset(PADAPTER padapter)362 void rtl8188f_FirmwareSelfReset(PADAPTER padapter)
363 {
364 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
365 u8 u1bTmp;
366 u8 Delay = 100;
367
368 if (!(IS_FW_81xxC(padapter) &&
369 ((pHalData->firmware_version < 0x21) ||
370 (pHalData->firmware_version == 0x21 &&
371 pHalData->firmware_sub_version < 0x01)))) { /* after 88C Fw v33.1 */
372 /*0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
373 rtw_write8(padapter, REG_HMETFR + 3, 0x20);
374
375 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
376 while (u1bTmp & BIT2) {
377 Delay--;
378 if (Delay == 0)
379 break;
380 rtw_udelay_os(50);
381 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
382 }
383
384 if (Delay == 0) {
385 /*force firmware reset */
386 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
387 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp & (~BIT2));
388 }
389 }
390 }
391
392 #ifdef CONFIG_FILE_FWIMG
393 extern char *rtw_fw_file_path;
394 extern char *rtw_fw_wow_file_path;
395 #ifdef CONFIG_MP_INCLUDED
396 extern char *rtw_fw_mp_bt_file_path;
397 #endif /* CONFIG_MP_INCLUDED */
398 u8 FwBuffer[FW_8188F_SIZE];
399 #endif /* CONFIG_FILE_FWIMG */
400
401 #ifdef CONFIG_MP_INCLUDED
_WriteBTFWtoTxPktBuf8188F(PADAPTER Adapter,void * buffer,u32 FwBufLen,u8 times)402 int _WriteBTFWtoTxPktBuf8188F(
403 PADAPTER Adapter,
404 void *buffer,
405 u32 FwBufLen,
406 u8 times
407 )
408 {
409 int rtStatus = _SUCCESS;
410 /*u32 value32; */
411 /*u8 numHQ, numLQ, numPubQ;//, txpktbuf_bndy; */
412 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
413 /*PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
414 u8 BcnValidReg;
415 u8 count = 0, DLBcnCount = 0;
416 u8 *FwbufferPtr = (u8 *)buffer;
417 /*PRT_TCB pTcb, ptempTcb; */
418 /*PRT_TX_LOCAL_BUFFER pBuf; */
419
420 u8 *ReservedPagePacket = NULL;
421 u8 *pGenBufReservedPagePacket = NULL;
422 u32 TotalPktLen, txpktbuf_bndy;
423 /*u8 tmpReg422; */
424 /*u8 u1bTmp; */
425 u8 *pframe;
426 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
427 struct xmit_frame *pmgntframe;
428 struct pkt_attrib *pattrib;
429 u8 txdesc_offset = TXDESC_OFFSET;
430 u8 val8;
431 #ifdef CONFIG_PCI_HCI
432 u8 u1bTmp;
433 #endif
434
435 #if 1/*#ifdef CONFIG_PCI_HCI */
436 TotalPktLen = FwBufLen;
437 #else
438 TotalPktLen = FwBufLen + pHalData->HWDescHeadLength;
439 #endif
440
441 if ((TotalPktLen + TXDESC_OFFSET) > MAX_CMDBUF_SZ) {
442 RTW_INFO(" WARNING %s => Total packet len = %d > MAX_CMDBUF_SZ:%d\n"
443 , __func__, (TotalPktLen + TXDESC_OFFSET), MAX_CMDBUF_SZ);
444 return _FAIL;
445 }
446
447 pGenBufReservedPagePacket = rtw_zmalloc(TotalPktLen);/*GetGenTempBuffer (Adapter, TotalPktLen); */
448 if (!pGenBufReservedPagePacket)
449 return _FAIL;
450
451 ReservedPagePacket = (u8 *)pGenBufReservedPagePacket;
452
453 _rtw_memset(ReservedPagePacket, 0, TotalPktLen);
454
455 #if 1/*#ifdef CONFIG_PCI_HCI*/
456 _rtw_memcpy(ReservedPagePacket, FwbufferPtr, FwBufLen);
457
458 #else
459 PlatformMoveMemory(ReservedPagePacket + Adapter->HWDescHeadLength , FwbufferPtr, FwBufLen);
460 #endif
461
462 /*--------------------------------------------------------- */
463 /* 1. Pause BCN */
464 /*--------------------------------------------------------- */
465 /*Set REG_CR bit 8. DMA beacon by SW. */
466 #ifdef CONFIG_PCI_HCI
467 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
468 PlatformEFIOWrite1Byte(Adapter, REG_CR + 1, (u1bTmp | BIT0));
469 #else
470 /* Remove for temparaily because of the code on v2002 is not sync to MERGE_TMEP for USB/SDIO. */
471 /* De not remove this part on MERGE_TEMP. by tynli. */
472 #endif
473
474 /* Disable Hw protection for a time which revserd for Hw sending beacon. */
475 /* Fix download reserved page packet fail that access collision with the protection time. */
476 /* 2010.05.11. Added by tynli. */
477 val8 = rtw_read8(Adapter, REG_BCN_CTRL);
478 val8 &= ~EN_BCN_FUNCTION;
479 val8 |= DIS_TSF_UDT;
480 rtw_write8(Adapter, REG_BCN_CTRL, val8);
481
482 #if 0/*#ifdef CONFIG_PCI_HCI*/
483 tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
484 if (tmpReg422 & BIT6)
485 bRecover = TRUE;
486 PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, tmpReg422 & (~BIT6));
487 #else
488 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
489 PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2,
490 PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6));
491 #endif
492
493 /*--------------------------------------------------------- */
494 /* 2. Adjust LLT table to an even boundary. */
495 /*--------------------------------------------------------- */
496 #if 0/*#ifdef CONFIG_SDIO_HCI*/
497 txpktbuf_bndy = 10; /* rsvd page start address should be an even value. */
498 rtStatus = InitLLTTable8188FS(Adapter, txpktbuf_bndy);
499 if (RT_STATUS_SUCCESS != rtStatus) {
500 RTW_INFO("_CheckWLANFwPatchBTFwReady_8188F(): Failed to init LLT!\n");
501 return RT_STATUS_FAILURE;
502 }
503
504 /* Init Tx boundary. */
505 PlatformEFIOWrite1Byte(Adapter, REG_DWBCN0_CTRL_8188F + 1, (u8)txpktbuf_bndy);
506 #endif
507
508
509 /*--------------------------------------------------------- */
510 /* 3. Write Fw to Tx packet buffer by reseverd page. */
511 /*--------------------------------------------------------- */
512 do {
513 /* download rsvd page. */
514 /* Clear beacon valid check bit. */
515 BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
516 PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg & (~BIT(0)));
517
518 /*BT patch is big, we should set 0x209 < 0x40 suggested from Gimmy */
519
520 PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 1, (0x90 - 0x20 * (times - 1)));
521 RTW_INFO("0x209:0x%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1));
522
523 #if 0
524 /* Acquice TX spin lock before GetFwBuf and send the packet to prevent system deadlock. */
525 /* Advertised by Roger. Added by tynli. 2010.02.22. */
526 PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
527 if (MgntGetFWBuffer(Adapter, &pTcb, &pBuf)) {
528 PlatformMoveMemory(pBuf->Buffer.VirtualAddress, ReservedPagePacket, TotalPktLen);
529 CmdSendPacket(Adapter, pTcb, pBuf, TotalPktLen, DESC_PACKET_TYPE_NORMAL, FALSE);
530 } else
531 dbgdump("SetFwRsvdPagePkt(): MgntGetFWBuffer FAIL!!!!!!!!.\n");
532 PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
533 #else
534 /*---------------------------------------------------------
535 tx reserved_page_packet
536 ----------------------------------------------------------*/
537 pmgntframe = rtw_alloc_cmdxmitframe(pxmitpriv);
538 if (pmgntframe == NULL) {
539 rtStatus = _FAIL;
540 goto exit;
541 }
542 /*update attribute */
543 pattrib = &pmgntframe->attrib;
544 update_mgntframe_attrib(Adapter, pattrib);
545
546 pattrib->qsel = QSLT_BEACON;
547 pattrib->pktlen = pattrib->last_txcmdsz = FwBufLen;
548
549 /*_rtw_memset(pmgntframe->buf_addr, 0, TotalPktLen+txdesc_size); */
550 /*pmgntframe->buf_addr = ReservedPagePacket; */
551
552 _rtw_memcpy((u8 *)(pmgntframe->buf_addr + txdesc_offset), ReservedPagePacket, FwBufLen);
553 RTW_INFO("[%d]===>TotalPktLen + TXDESC_OFFSET TotalPacketLen:%d\n", DLBcnCount, (FwBufLen + txdesc_offset));
554
555 #ifdef CONFIG_PCI_HCI
556 dump_mgntframe(Adapter, pmgntframe);
557 #else
558 dump_mgntframe_and_wait(Adapter, pmgntframe, 100);
559 #endif
560
561 #endif
562 #if 1
563 /* check rsvd page download OK. */
564 BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
565 while (!(BcnValidReg & BIT(0)) && count < 200) {
566 count++;
567 /*PlatformSleepUs(10); */
568 rtw_msleep_os(1);
569 BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
570 }
571 DLBcnCount++;
572 /*RTW_INFO("##0x208:%08x,0x210=%08x\n",PlatformEFIORead4Byte(Adapter, REG_TDECTRL),PlatformEFIORead4Byte(Adapter, 0x210)); */
573
574 PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg);
575
576 } while ((!(BcnValidReg & BIT(0))) && DLBcnCount < 5);
577
578
579 #endif
580 if (DLBcnCount >= 5) {
581 RTW_INFO(" check rsvd page download OK DLBcnCount =%d\n", DLBcnCount);
582 rtStatus = _FAIL;
583 goto exit;
584 }
585
586 if (!(BcnValidReg & BIT(0))) {
587 RTW_INFO("_WriteFWtoTxPktBuf(): 1 Download RSVD page failed!\n");
588 rtStatus = _FAIL;
589 goto exit;
590 }
591
592 /*--------------------------------------------------------- */
593 /* 4. Set Tx boundary to the initial value */
594 /*--------------------------------------------------------- */
595
596
597 /*--------------------------------------------------------- */
598 /* 5. Reset beacon setting to the initial value. */
599 /* After _CheckWLANFwPatchBTFwReady(). */
600 /*--------------------------------------------------------- */
601
602 exit:
603
604 if (pGenBufReservedPagePacket) {
605 RTW_INFO("_WriteBTFWtoTxPktBuf8188F => rtw_mfree pGenBufReservedPagePacket!\n");
606 rtw_mfree((u8 *)pGenBufReservedPagePacket, TotalPktLen);
607 }
608 return rtStatus;
609 }
610
611
612
613 /* */
614 /* Description: Determine the contents of H2C BT_FW_PATCH Command sent to FW. */
615 /* 2011.10.20 by tynli */
616 /* */
617 void
SetFwBTFwPatchCmd(PADAPTER Adapter,u16 FwSize)618 SetFwBTFwPatchCmd(
619 PADAPTER Adapter,
620 u16 FwSize
621 )
622 {
623 u8 u1BTFwPatchParm[H2C_BT_FW_PATCH_LEN] = {0};
624 u8 addr0 = 0;
625 u8 addr1 = 0xa0;
626 u8 addr2 = 0x10;
627 u8 addr3 = 0x80;
628
629
630 SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(u1BTFwPatchParm, FwSize);
631 SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(u1BTFwPatchParm, addr0);
632 SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(u1BTFwPatchParm, addr1);
633 SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(u1BTFwPatchParm, addr2);
634 SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(u1BTFwPatchParm, addr3);
635
636 FillH2CCmd8188F(Adapter, H2C_8188F_BT_FW_PATCH, H2C_BT_FW_PATCH_LEN, u1BTFwPatchParm);
637
638 }
639
640 void
SetFwBTPwrCmd(PADAPTER Adapter,u8 PwrIdx)641 SetFwBTPwrCmd(
642 PADAPTER Adapter,
643 u8 PwrIdx
644 )
645 {
646 u8 u1BTPwrIdxParm[H2C_FORCE_BT_TXPWR_LEN] = {0};
647
648 SET_8188F_H2CCMD_BT_PWR_IDX(u1BTPwrIdxParm, PwrIdx);
649
650
651 FillH2CCmd8188F(Adapter, H2C_8188F_FORCE_BT_TXPWR, H2C_FORCE_BT_TXPWR_LEN, u1BTPwrIdxParm);
652 }
653
654 /* */
655 /* Description: WLAN Fw will write BT Fw to BT XRAM and signal driver. */
656 /* */
657 /* 2011.10.20. by tynli. */
658 /* */
659 int
_CheckWLANFwPatchBTFwReady(PADAPTER Adapter,BOOLEAN bRecover)660 _CheckWLANFwPatchBTFwReady(
661 PADAPTER Adapter,
662 BOOLEAN bRecover
663 )
664 {
665 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
666 u32 count = 0;
667 u8 u1bTmp;
668 int ret = _FAIL;
669
670 /*--------------------------------------------------------- */
671 /* Check if BT FW patch procedure is ready. */
672 /*--------------------------------------------------------- */
673 do {
674 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_HMEBOX_DBG_0_8188F);
675 if ((u1bTmp & BIT6) || (u1bTmp & BIT7)) {
676 ret = _SUCCESS;
677 break;
678 }
679
680 count++;
681 rtw_msleep_os(50); /* 50ms */
682 } while (!((u1bTmp & BIT6) || (u1bTmp & BIT7)) && count < 50);
683
684
685
686
687 /*--------------------------------------------------------- */
688 /* Reset beacon setting to the initial value. */
689 /*--------------------------------------------------------- */
690 #if 0/*#ifdef CONFIG_PCI_HCI*/
691 if (LLT_table_init(Adapter, FALSE, 0) == RT_STATUS_FAILURE) {
692 dbgdump("Init self define for BT Fw patch LLT table fail.\n");
693 /*return RT_STATUS_FAILURE; */
694 }
695 #endif
696 u1bTmp = rtw_read8(Adapter, REG_BCN_CTRL);
697 u1bTmp |= EN_BCN_FUNCTION;
698 u1bTmp &= ~DIS_TSF_UDT;
699 rtw_write8(Adapter, REG_BCN_CTRL, u1bTmp);
700
701 /* To make sure that if there exists an adapter which would like to send beacon. */
702 /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
703 /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
704 /* the beacon cannot be sent by HW. */
705 /* 2010.06.23. Added by tynli. */
706
707 if (bRecover) {
708 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
709 PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (u1bTmp | BIT6));
710 }
711
712
713 /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
714 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8188F + 1);
715 PlatformEFIOWrite1Byte(Adapter, REG_CR_8188F + 1, (u1bTmp & (~BIT0)));
716
717 return ret;
718 }
719
ReservedPage_Compare(PADAPTER Adapter,PRT_MP_FIRMWARE pFirmware,u32 BTPatchSize)720 int ReservedPage_Compare(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware, u32 BTPatchSize)
721 {
722 u8 temp, ret, lastBTsz;
723 u32 u1bTmp = 0, address_start = 0, count = 0, i = 0;
724 u8 *myBTFwBuffer = NULL;
725
726 myBTFwBuffer = rtw_zmalloc(BTPatchSize);
727 if (myBTFwBuffer == NULL) {
728 RTW_INFO("%s can't be executed due to the failed malloc.\n", __func__);
729 Adapter->mppriv.bTxBufCkFail = _TRUE;
730 return _FALSE;
731 }
732
733 temp = rtw_read8(Adapter, 0x209);
734
735 address_start = (temp * 128) / 8;
736
737 rtw_write32(Adapter, 0x140, 0x00000000);
738 rtw_write32(Adapter, 0x144, 0x00000000);
739 rtw_write32(Adapter, 0x148, 0x00000000);
740
741 rtw_write8(Adapter, 0x106, 0x69);
742
743 for (i = 0; i < (BTPatchSize / 8); i++) {
744 rtw_write32(Adapter, 0x140, address_start + 5 + i);
745
746 /*polling until reg 0x140[23]=1; */
747 do {
748 u1bTmp = rtw_read32(Adapter, 0x140);
749 if (u1bTmp & BIT(23)) {
750 ret = _SUCCESS;
751 break;
752 }
753 count++;
754 RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
755 rtw_msleep_os(10); /* 10ms */
756 } while (!(u1bTmp & BIT(23)) && count < 50);
757
758 myBTFwBuffer[i * 8 + 0] = rtw_read8(Adapter, 0x144);
759 myBTFwBuffer[i * 8 + 1] = rtw_read8(Adapter, 0x145);
760 myBTFwBuffer[i * 8 + 2] = rtw_read8(Adapter, 0x146);
761 myBTFwBuffer[i * 8 + 3] = rtw_read8(Adapter, 0x147);
762 myBTFwBuffer[i * 8 + 4] = rtw_read8(Adapter, 0x148);
763 myBTFwBuffer[i * 8 + 5] = rtw_read8(Adapter, 0x149);
764 myBTFwBuffer[i * 8 + 6] = rtw_read8(Adapter, 0x14a);
765 myBTFwBuffer[i * 8 + 7] = rtw_read8(Adapter, 0x14b);
766 }
767
768 rtw_write32(Adapter, 0x140, address_start + 5 + BTPatchSize / 8);
769
770 lastBTsz = BTPatchSize % 8;
771
772 /*polling until reg 0x140[23]=1; */
773 u1bTmp = 0;
774 count = 0;
775 do {
776 u1bTmp = rtw_read32(Adapter, 0x140);
777 if (u1bTmp & BIT(23)) {
778 ret = _SUCCESS;
779 break;
780 }
781 count++;
782 RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
783 rtw_msleep_os(10); /* 10ms */
784 } while (!(u1bTmp & BIT(23)) && count < 50);
785
786 for (i = 0; i < lastBTsz; i++)
787 myBTFwBuffer[(BTPatchSize / 8) * 8 + i] = rtw_read8(Adapter, (0x144 + i));
788
789
790 for (i = 0; i < BTPatchSize; i++) {
791 if (myBTFwBuffer[i] != pFirmware->szFwBuffer[i]) {
792 RTW_INFO(" In direct myBTFwBuffer[%d]=%x , pFirmware->szFwBuffer=%x\n", i, myBTFwBuffer[i], pFirmware->szFwBuffer[i]);
793 Adapter->mppriv.bTxBufCkFail = _TRUE;
794 break;
795 }
796 }
797
798 if (myBTFwBuffer != NULL)
799 rtw_mfree(myBTFwBuffer, BTPatchSize);
800
801 return _TRUE;
802 }
803
804 #ifdef CONFIG_BT_COEXIST
805 /* As the size of bt firmware is more than 16k which is too big for some platforms, we divide it
806 * into four parts to transfer. The last parameter of _WriteBTFWtoTxPktBuf8188F is used to indicate
807 * the location of every part. We call the first 4096 byte of bt firmware as part 1, the second 4096
808 * part as part 2, the third 4096 part as part 3, the remain as part 4. First we transform the part
809 * 4 and set the register 0x209 to 0x90, then the 32 bytes description are added to the head of part
810 * 4, and those bytes are putted at the location 0x90. Second we transform the part 3 and set the
811 * register 0x209 to 0x70. The 32 bytes description and part 3(4196 bytes) are putted at the location
812 * 0x70. It can contain 4196 bytes between 0x70 and 0x90. So the last 32 bytes os part 3 will cover the
813 * 32 bytes description of part4. Using this method, we can put the whole bt firmware to 0x30 and only
814 * has 32 bytes descrption at the head of part 1.
815 */
FirmwareDownloadBT(PADAPTER padapter,PRT_MP_FIRMWARE pFirmware)816 s32 FirmwareDownloadBT(PADAPTER padapter, PRT_MP_FIRMWARE pFirmware)
817 {
818 s32 rtStatus;
819 u8 *pBTFirmwareBuf;
820 u32 BTFirmwareLen;
821 u8 download_time;
822 s8 i;
823 u8 RegFwHwTxQCtrl = 0;
824 BOOLEAN bRecover = _FALSE;
825
826
827 rtStatus = _SUCCESS;
828 pBTFirmwareBuf = NULL;
829 BTFirmwareLen = 0;
830
831 /* */
832 /* Patch BT Fw. Download BT RAM code to Tx packet buffer. */
833 /* */
834 if (padapter->bBTFWReady) {
835 RTW_INFO("%s: BT Firmware is ready!!\n", __func__);
836 return _FAIL;
837 }
838
839 #ifdef CONFIG_FILE_FWIMG
840 if (rtw_is_file_readable(rtw_fw_mp_bt_file_path) == _TRUE) {
841 RTW_INFO("%s: acquire MP BT FW from file:%s\n", __func__, rtw_fw_mp_bt_file_path);
842
843 rtStatus = rtw_retrieve_from_file(rtw_fw_mp_bt_file_path, FwBuffer, FW_8188F_SIZE);
844 BTFirmwareLen = rtStatus >= 0 ? rtStatus : 0;
845 pBTFirmwareBuf = FwBuffer;
846 } else
847 #endif /* CONFIG_FILE_FWIMG */
848 {
849 #ifdef CONFIG_EMBEDDED_FWIMG
850 RTW_INFO("%s: Download MP BT FW from header\n", __func__);
851
852 pBTFirmwareBuf = (u8 *)Rtl8188FFwBTImgArray;
853 BTFirmwareLen = Rtl8188FFwBTImgArrayLength;
854 pFirmware->szFwBuffer = pBTFirmwareBuf;
855 pFirmware->ulFwLength = BTFirmwareLen;
856 #endif /* CONFIG_EMBEDDED_FWIMG */
857 }
858
859 RTW_INFO("%s: MP BT Firmware size=%d\n", __func__, BTFirmwareLen);
860
861 /* for h2c cam here should be set to true */
862 GET_HAL_DATA(padapter)->bFWReady = _TRUE;
863
864 download_time = (BTFirmwareLen + 4095) / 4096;
865 RTW_INFO("%s: download_time is %d\n", __func__, download_time);
866 RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2);
867
868 if (RegFwHwTxQCtrl & BIT(6))
869 bRecover = _TRUE;
870
871 /* Download BT patch Fw. */
872 for (i = (download_time - 1); i >= 0; i--) {
873 if (i == (download_time - 1)) {
874 rtStatus = _WriteBTFWtoTxPktBuf8188F(padapter, pBTFirmwareBuf + (4096 * i), (BTFirmwareLen - (4096 * i)), 1);
875 RTW_INFO("%s: start %d, len %d, time 1\n", __func__, 4096 * i, BTFirmwareLen - (4096 * i));
876 } else {
877 rtStatus = _WriteBTFWtoTxPktBuf8188F(padapter, pBTFirmwareBuf + (4096 * i), 4096, (download_time - i));
878 RTW_INFO("%s: start %d, len 4096, time %d\n", __func__, 4096 * i, download_time - i);
879 }
880
881 if (rtStatus != _SUCCESS) {
882 RTW_INFO("%s: BT Firmware download to Tx packet buffer fail!\n", __func__);
883 padapter->bBTFWReady = _FALSE;
884 return rtStatus;
885 }
886 }
887
888 ReservedPage_Compare(padapter, pFirmware, BTFirmwareLen);
889
890 padapter->bBTFWReady = _TRUE;
891 SetFwBTFwPatchCmd(padapter, (u16)BTFirmwareLen);
892 rtStatus = _CheckWLANFwPatchBTFwReady(padapter, bRecover);
893
894 RTW_INFO("<===%s: return %s!\n", __func__, rtStatus == _SUCCESS ? "SUCCESS" : "FAIL");
895
896 return rtStatus;
897 }
898 #endif /* CONFIG_BT_COEXIST */
899 #endif /* CONFIG_MP_INCLUDED */
900
901 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
rtl8188f_cal_txdesc_chksum(struct tx_desc * ptxdesc)902 void rtl8188f_cal_txdesc_chksum(struct tx_desc *ptxdesc)
903 {
904 u16 *usPtr = (u16 *)ptxdesc;
905 u32 count;
906 u32 index;
907 u16 checksum = 0;
908
909
910 /* Clear first */
911 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
912
913 /* checksume is always calculated by first 32 bytes, */
914 /* and it doesn't depend on TX DESC length. */
915 /* Thomas,Lucas@SD4,20130515 */
916 count = 16;
917
918 for (index = 0; index < count; index++)
919 checksum ^= le16_to_cpu(*(usPtr + index));
920
921 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
922 }
923 #endif
924
925 #if 0 /* FW tx packet write */
926 u8 send_fw_packet(PADAPTER padapter, u8 *pRam_code, u32 length)
927 {
928 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
929 struct xmit_buf xmit_buf_tmp;
930 struct submit_ctx sctx_tmp;
931 u8 *pTx_data_buffer = NULL;
932 u8 *pTmp_buffer = NULL;
933 u32 modify_ram_size;
934 u32 tmp_size, tmp_value;
935 u8 value8;
936 u32 i, counter;
937 u8 bRet;
938 u32 dwDataLength, writeLength;
939
940 /* Due to SDIO can not send 32K packet */
941 if (FW_DOWNLOAD_SIZE_8188F == length)
942 length--;
943
944 modify_ram_size = length << 2;
945 pTx_data_buffer = rtw_zmalloc(modify_ram_size);
946
947 if (NULL == pTx_data_buffer) {
948 RTW_INFO("Allocate buffer fail!!\n");
949 return _FALSE;
950 }
951
952 _rtw_memset(pTx_data_buffer, 0, modify_ram_size);
953
954 /* Transfer to new format */
955 tmp_size = length >> 1;
956 for (i = 0; i <= tmp_size; i++) {
957 *(pTx_data_buffer + i * 8) = *(pRam_code + i * 2);
958 *(pTx_data_buffer + i * 8 + 1) = *(pRam_code + i * 2 + 1);
959 }
960
961 /* Gen TX_DESC */
962 _rtw_memset(pTx_data_buffer, 0, TXDESC_SIZE);
963 pTmp_buffer = pTx_data_buffer;
964 #if 0
965 pTmp_buffer->qsel = BcnQsel;
966 pTmp_buffer->txpktsize = modify_ram_size - TXDESC_SIZE;
967 pTmp_buffer->offset = TXDESC_SIZE;
968 #else
969 SET_TX_DESC_QUEUE_SEL_8188F(pTmp_buffer, QSLT_BEACON);
970 SET_TX_DESC_PKT_SIZE_8188F(pTmp_buffer, modify_ram_size - TXDESC_SIZE);
971 SET_TX_DESC_OFFSET_8188F(pTmp_buffer, TXDESC_SIZE);
972 #endif
973 rtl8188f_cal_txdesc_chksum((struct tx_desc *)pTmp_buffer);
974
975
976 /* Send packet */
977 #if 0
978 dwDataLength = modify_ram_size;
979 overlap.Offset = 0;
980 overlap.OffsetHigh = 0;
981 overlap.hEvent = CreateEvent(NULL, FALSE, FALSE, NULL);
982 bRet = WriteFile(HalVari.hFile_Queue[TX_BCNQ]->handle, pTx_data_buffer, dwDataLength, &writeLength, &overlap);
983 if (WaitForSingleObject(overlap.hEvent, INFINITE) == WAIT_OBJECT_0) {
984
985 GetOverlappedResult(HalVari.hFile_Queue[TX_BCNQ]->handle, &overlap, &writeLength, FALSE);
986 if (writeLength != dwDataLength) {
987 TCHAR editbuf[100];
988
989 sprintf(editbuf, "DL FW Length Err: Write length error:bRet %d writeLength %ld dwDataLength %ld, Error Code:%ld", bRet, writeLength, dwDataLength, GetLastError());
990 AfxMessageBox(editbuf, MB_OK | MB_ICONERROR);
991 return FALSE;
992 }
993 }
994 CloseHandle(overlap.hEvent);
995 #else
996 xmit_buf_tmp.pdata = pTx_data_buffer;
997 xmit_buf_tmp.len = modify_ram_size;
998 rtw_sctx_init(&sctx_tmp, 10);
999 xmit_buf_tmp.sctx = &sctx_tmp;
1000 if (rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[BCN_QUEUE_INX], xmit_buf_tmp.len, (u8 *)&xmit_buf_tmp) == _FAIL) {
1001 RTW_INFO("rtw_write_port fail\n");
1002 return _FAIL;
1003 }
1004 #endif
1005
1006 /* check if DMA is OK */
1007 counter = 100;
1008 do {
1009 if (0 == counter) {
1010 RTW_INFO("DMA time out!!\n");
1011 return _FALSE;
1012 }
1013 value8 = rtw_read8(padapter, REG_DWBCN0_CTRL_8188F + 2);
1014 counter--;
1015 } while (0 == (value8 & BIT(0)));
1016
1017 rtw_write8(padapter, REG_DWBCN0_CTRL_8188F + 2, value8);
1018
1019 /* Modify ram code by IO method */
1020 tmp_value = rtw_read8(padapter, REG_MCUFWDL + 1);
1021 /* Disable DMA */
1022 rtw_write8(padapter, REG_MCUFWDL + 1, (u8)tmp_value & ~(BIT(5)));
1023 tmp_value = (tmp_value >> 6) << 1;
1024 /* Set page start address */
1025 rtw_write8(padapter, REG_MCUFWDL + 2, (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | tmp_value);
1026 tmp_size = TXDESC_SIZE >> 2; /* 10bytes */
1027 #if 0
1028 IO_Func.WriteRegister(0x1000, (u16)tmp_size, pRam_code);
1029 #else
1030 _BlockWrite(padapter, pRam_code, tmp_size);
1031 #endif
1032
1033 if (pTmp_buffer != NULL)
1034 rtw_mfree((u8 *)pTmp_buffer, modify_ram_size);
1035
1036 return _TRUE;
1037 }
1038 #endif
1039
1040 /* */
1041 /* Description: */
1042 /* Download 8192C firmware code. */
1043 /* */
1044 /* */
rtl8188f_FirmwareDownload(PADAPTER padapter,BOOLEAN bUsedWoWLANFw)1045 s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw)
1046 {
1047 s32 rtStatus = _SUCCESS;
1048 u8 write_fw = 0;
1049 systime fwdl_start_time;
1050 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1051 u8 *FwImage;
1052 u32 FwImageLen;
1053 u8 *pFwImageFileName;
1054 #ifdef CONFIG_WOWLAN
1055 u8 *FwImageWoWLAN;
1056 u32 FwImageWoWLANLen;
1057 #endif
1058 u8 *pucMappedFile = NULL;
1059 PRT_FIRMWARE_8188F pFirmware = NULL;
1060 PRT_8188F_FIRMWARE_HDR pFwHdr = NULL;
1061 u8 *pFirmwareBuf;
1062 u32 FirmwareLen;
1063 #ifdef CONFIG_FILE_FWIMG
1064 u8 *fwfilepath;
1065 #endif /* CONFIG_FILE_FWIMG */
1066 u8 value8;
1067 struct dvobj_priv *psdpriv = padapter->dvobj;
1068 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1069 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
1070
1071
1072 pFirmware = (PRT_FIRMWARE_8188F)rtw_zmalloc(sizeof(RT_FIRMWARE_8188F));
1073
1074 if (!pFirmware) {
1075 rtStatus = _FAIL;
1076 goto exit;
1077 }
1078
1079 {
1080 u8 tmp_ps = 0, tmp_rf = 0;
1081
1082 tmp_ps = rtw_read8(padapter, 0xa3);
1083 tmp_ps &= 0xf8;
1084 tmp_ps |= 0x02;
1085 /*1. write 0xA3[:2:0] = 3b'010 */
1086 rtw_write8(padapter, 0xa3, tmp_ps);
1087 /*2. read power_state = 0xA0[1:0] */
1088 tmp_ps = rtw_read8(padapter, 0xa0);
1089 tmp_ps &= 0x03;
1090 if (tmp_ps != 0x01) {
1091 RTW_INFO(FUNC_ADPT_FMT" tmp_ps=%x\n", FUNC_ADPT_ARG(padapter), tmp_ps);
1092 pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
1093 }
1094 }
1095
1096 #ifdef CONFIG_BT_COEXIST
1097 rtw_btcoex_PreLoadFirmware(padapter);
1098 #endif
1099
1100 #ifdef CONFIG_FILE_FWIMG
1101 #ifdef CONFIG_WOWLAN
1102 if (bUsedWoWLANFw)
1103 fwfilepath = rtw_fw_wow_file_path;
1104 else
1105 #endif /* CONFIG_WOWLAN */
1106 {
1107 fwfilepath = rtw_fw_file_path;
1108 }
1109 #endif /* CONFIG_FILE_FWIMG */
1110
1111 #ifdef CONFIG_FILE_FWIMG
1112 if (rtw_is_file_readable(fwfilepath) == _TRUE) {
1113 RTW_INFO("%s acquire FW from file:%s\n", __func__, fwfilepath);
1114 pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
1115 } else
1116 #endif /* CONFIG_FILE_FWIMG */
1117 {
1118 #ifdef CONFIG_EMBEDDED_FWIMG
1119 pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
1120 #else /* !CONFIG_EMBEDDED_FWIMG */
1121 pFirmware->eFWSource = FW_SOURCE_IMG_FILE; /* We should decided by Reg. */
1122 #endif /* !CONFIG_EMBEDDED_FWIMG */
1123 }
1124
1125 switch (pFirmware->eFWSource) {
1126 case FW_SOURCE_IMG_FILE:
1127 #ifdef CONFIG_FILE_FWIMG
1128 rtStatus = rtw_retrieve_from_file(fwfilepath, FwBuffer, FW_8188F_SIZE);
1129 pFirmware->ulFwLength = rtStatus >= 0 ? rtStatus : 0;
1130 pFirmware->szFwBuffer = FwBuffer;
1131 #endif /* CONFIG_FILE_FWIMG */
1132 break;
1133
1134 case FW_SOURCE_HEADER_FILE:
1135 if (bUsedWoWLANFw) {
1136 #ifdef CONFIG_WOWLAN
1137 if (pwrpriv->wowlan_mode) {
1138 pFirmware->szFwBuffer = array_mp_8188f_fw_wowlan;
1139 pFirmware->ulFwLength = array_length_mp_8188f_fw_wowlan;
1140
1141 RTW_INFO(" ===> %s fw: %s, size: %d\n",
1142 __func__, "WoWLAN",
1143 pFirmware->ulFwLength);
1144 }
1145 #endif /* CONFIG_WOWLAN */
1146
1147 #ifdef CONFIG_AP_WOWLAN
1148 if (pwrpriv->wowlan_ap_mode) {
1149 pFirmware->szFwBuffer = array_mp_8188f_fw_ap;
1150 pFirmware->ulFwLength = array_length_mp_8188f_fw_ap;
1151
1152 RTW_INFO(" ===> %s fw: %s, size: %d\n",
1153 __func__, "AP_WoWLAN",
1154 pFirmware->ulFwLength);
1155 }
1156 #endif /* CONFIG_AP_WOWLAN */
1157 } else {
1158 /* CONFIG_FW_WoWLAN functions of NIC is included in WoWLAN */
1159 /* functions of NIC is separated from WoWLAN starting from V0200 */
1160 pFirmware->szFwBuffer = array_mp_8188f_fw_nic;
1161 pFirmware->ulFwLength = array_length_mp_8188f_fw_nic;
1162 RTW_INFO("%s fw: %s, size: %d\n", __func__
1163 /*, "FW_WoWLAN" */
1164 , "FW_NIC"
1165 , pFirmware->ulFwLength);
1166 }
1167 break;
1168 }
1169
1170 if ((pFirmware->ulFwLength - 32) > FW_8188F_SIZE) {
1171 rtStatus = _FAIL;
1172 RTW_ERR("Firmware size:%u exceed %u\n", pFirmware->ulFwLength, FW_8188F_SIZE);
1173 goto exit;
1174 }
1175
1176 pFirmwareBuf = pFirmware->szFwBuffer;
1177 FirmwareLen = pFirmware->ulFwLength;
1178
1179 /* To Check Fw header. Added by tynli. 2009.12.04. */
1180 pFwHdr = (PRT_8188F_FIRMWARE_HDR)pFirmwareBuf;
1181
1182 pHalData->firmware_version = le16_to_cpu(pFwHdr->Version);
1183 pHalData->firmware_sub_version = le16_to_cpu(pFwHdr->Subversion);
1184 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
1185
1186 RTW_INFO("%s: fw_ver=%x fw_subver=%04x sig=0x%x, Month=%02x, Date=%02x, Hour=%02x, Minute=%02x\n",
1187 __func__, pHalData->firmware_version, pHalData->firmware_sub_version, pHalData->FirmwareSignature
1188 , pFwHdr->Month, pFwHdr->Date, pFwHdr->Hour, pFwHdr->Minute);
1189
1190 if (IS_FW_HEADER_EXIST_8188F(pFwHdr)) {
1191 RTW_INFO("%s(): Shift for fw header!\n", __func__);
1192 /* Shift 32 bytes for FW header */
1193 pFirmwareBuf = pFirmwareBuf + 32;
1194 FirmwareLen = FirmwareLen - 32;
1195 }
1196
1197 fwdl_start_time = rtw_get_current_time();
1198
1199 #if 1
1200 RTW_INFO("%s by IO write!\n", __func__);
1201
1202 /*
1203 * Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself,
1204 * or it will cause download Fw fail. 2010.02.01. by tynli.
1205 */
1206 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
1207 rtw_write8(padapter, REG_MCUFWDL, 0x00);
1208 _8051Reset8188(padapter);
1209 }
1210
1211 _FWDownloadEnable(padapter, _TRUE);
1212
1213 while (!RTW_CANNOT_IO(padapter)
1214 && (write_fw++ < 3 || rtw_get_passing_time_ms(fwdl_start_time) < 500)) {
1215 /* reset FWDL chksum */
1216 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
1217
1218 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
1219 if (rtStatus != _SUCCESS)
1220 continue;
1221
1222 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
1223 if (rtStatus == _SUCCESS)
1224 break;
1225 }
1226 #else
1227 RTW_INFO("%s by Tx pkt write!\n", __func__);
1228
1229 if ((rtw_read8(padapter, REG_MCUFWDL) & MCUFWDL_RDY) == 0) {
1230 /* DLFW use HIQ only */
1231 value32 = 0xFF | BIT(31);
1232 rtw_write32(padapter, REG_RQPN, value32);
1233
1234 /* Set beacon boundary to TXFIFO header */
1235 rtw_write8(padapter, REG_BCNQ_BDNY, 0);
1236 rtw_write16(padapter, REG_DWBCN0_CTRL_8188F + 1, BIT(8));
1237
1238 /* SDIO need read this register before send packet */
1239 rtw_read32(padapter, 0x10250020);
1240
1241 _FWDownloadEnable(padapter, _TRUE);
1242
1243 /* Get original check sum */
1244 new_chk_sum = *(pFirmwareBuf + FirmwareLen - 2) | ((u16) *(pFirmwareBuf + FirmwareLen - 1) << 8);
1245
1246 /* Send ram code flow */
1247 dma_iram_sel = 0;
1248 mem_offset = 0;
1249 pkt_size_tmp = FirmwareLen;
1250 while (0 != pkt_size_tmp) {
1251 if (pkt_size_tmp >= FW_DOWNLOAD_SIZE_8188F) {
1252 send_pkt_size = FW_DOWNLOAD_SIZE_8188F;
1253 /* Modify check sum value */
1254 new_chk_sum = (u16)(new_chk_sum ^ (((send_pkt_size - 1) << 2) - TXDESC_SIZE));
1255 } else {
1256 send_pkt_size = pkt_size_tmp;
1257 new_chk_sum = (u16)(new_chk_sum ^ ((send_pkt_size << 2) - TXDESC_SIZE));
1258
1259 }
1260
1261 if (send_pkt_size == pkt_size_tmp) {
1262 /* last partition packet, write new check sum to ram code file */
1263 *(pFirmwareBuf + FirmwareLen - 2) = new_chk_sum & 0xFF;
1264 *(pFirmwareBuf + FirmwareLen - 1) = (new_chk_sum & 0xFF00) >> 8;
1265 }
1266
1267 /* IRAM select */
1268 rtw_write8(padapter, REG_MCUFWDL + 1, (rtw_read8(padapter, REG_MCUFWDL + 1) & 0x3F) | (dma_iram_sel << 6));
1269 /* Enable DMA */
1270 rtw_write8(padapter, REG_MCUFWDL + 1, rtw_read8(padapter, REG_MCUFWDL + 1) | BIT(5));
1271
1272 if (_FALSE == send_fw_packet(padapter, pFirmwareBuf + mem_offset, send_pkt_size)) {
1273 RTW_INFO("%s: Send FW fail !\n", __func__);
1274 rtStatus = _FAIL;
1275 goto DLFW_FAIL;
1276 }
1277
1278 dma_iram_sel++;
1279 mem_offset += send_pkt_size;
1280 pkt_size_tmp -= send_pkt_size;
1281 }
1282 } else {
1283 RTW_INFO("%s: Download FW fail since MCUFWDL_RDY is not set!\n", __func__);
1284 rtStatus = _FAIL;
1285 goto DLFW_FAIL;
1286 }
1287 #endif
1288
1289 _FWDownloadEnable(padapter, _FALSE);
1290
1291 rtStatus = _FWFreeToGo(padapter, 10, 200);
1292 if (_SUCCESS != rtStatus)
1293 goto DLFW_FAIL;
1294
1295 RTW_INFO("%s: DLFW OK !\n", __func__);
1296
1297 DLFW_FAIL:
1298 if (rtStatus == _FAIL) {
1299 /* Disable FWDL_EN */
1300 value8 = rtw_read8(padapter, REG_MCUFWDL);
1301 value8 = (value8 & ~(BIT(0)) & ~(BIT(1)));
1302 rtw_write8(padapter, REG_MCUFWDL, value8);
1303 }
1304
1305 RTW_INFO("%s %s. write_fw:%u, %dms\n"
1306 , __func__, (rtStatus == _SUCCESS) ? "success" : "fail"
1307 , write_fw
1308 , rtw_get_passing_time_ms(fwdl_start_time)
1309 );
1310
1311 exit:
1312 if (pFirmware)
1313 rtw_mfree((u8 *)pFirmware, sizeof(RT_FIRMWARE_8188F));
1314
1315 rtl8188f_InitializeFirmwareVars(padapter);
1316
1317 RTW_INFO(" <=== %s()\n", __func__);
1318
1319 return rtStatus;
1320 }
1321
rtl8188f_InitializeFirmwareVars(PADAPTER padapter)1322 void rtl8188f_InitializeFirmwareVars(PADAPTER padapter)
1323 {
1324 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1325
1326 /* Init Fw LPS related. */
1327 adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE;
1328
1329 /*Init H2C cmd. */
1330 rtw_write8(padapter, REG_HMETFR, 0x0f);
1331
1332 /* Init H2C counter. by tynli. 2009.12.09. */
1333 pHalData->LastHMEBoxNum = 0;
1334 /*pHalData->H2CQueueHead = 0; */
1335 /*pHalData->H2CQueueTail = 0; */
1336 /*pHalData->H2CStopInsertQueue = _FALSE; */
1337 }
1338
1339 /*=========================================================== */
1340 /* Efuse related code */
1341 /*=========================================================== */
1342 static u8
hal_EfuseSwitchToBank(PADAPTER padapter,u8 bank,u8 bPseudoTest)1343 hal_EfuseSwitchToBank(
1344 PADAPTER padapter,
1345 u8 bank,
1346 u8 bPseudoTest)
1347 {
1348 u8 bRet = _FALSE;
1349 u32 value32 = 0;
1350 #ifdef HAL_EFUSE_MEMORY
1351 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1352 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1353 #endif
1354
1355
1356 RTW_INFO("%s: Efuse switch bank to %d\n", __func__, bank);
1357 if (bPseudoTest) {
1358 #ifdef HAL_EFUSE_MEMORY
1359 pEfuseHal->fakeEfuseBank = bank;
1360 #else
1361 fakeEfuseBank = bank;
1362 #endif
1363 bRet = _TRUE;
1364 } else {
1365 value32 = rtw_read32(padapter, EFUSE_TEST);
1366 bRet = _TRUE;
1367 switch (bank) {
1368 case 0:
1369 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1370 break;
1371 case 1:
1372 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
1373 break;
1374 case 2:
1375 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
1376 break;
1377 case 3:
1378 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
1379 break;
1380 default:
1381 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1382 bRet = _FALSE;
1383 break;
1384 }
1385 rtw_write32(padapter, EFUSE_TEST, value32);
1386 }
1387
1388 return bRet;
1389 }
1390
1391 static void
Hal_GetEfuseDefinition(PADAPTER padapter,u8 efuseType,u8 type,void * pOut,u8 bPseudoTest)1392 Hal_GetEfuseDefinition(
1393 PADAPTER padapter,
1394 u8 efuseType,
1395 u8 type,
1396 void *pOut,
1397 u8 bPseudoTest)
1398 {
1399 switch (type) {
1400 case TYPE_EFUSE_MAX_SECTION: {
1401 u8 *pMax_section;
1402
1403 pMax_section = (u8 *)pOut;
1404
1405 if (efuseType == EFUSE_WIFI)
1406 *pMax_section = EFUSE_MAX_SECTION_8188F;
1407 else
1408 *pMax_section = EFUSE_BT_MAX_SECTION;
1409 }
1410 break;
1411
1412 case TYPE_EFUSE_REAL_CONTENT_LEN: {
1413 u16 *pu2Tmp;
1414
1415 pu2Tmp = (u16 *)pOut;
1416
1417 if (efuseType == EFUSE_WIFI)
1418 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8188F;
1419 else
1420 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
1421 }
1422 break;
1423
1424 case TYPE_AVAILABLE_EFUSE_BYTES_BANK: {
1425 u16 *pu2Tmp;
1426
1427 pu2Tmp = (u16 *)pOut;
1428
1429 if (efuseType == EFUSE_WIFI)
1430 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8188F - EFUSE_OOB_PROTECT_BYTES);
1431 else
1432 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);
1433 }
1434 break;
1435
1436 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: {
1437 u16 *pu2Tmp;
1438
1439 pu2Tmp = (u16 *)pOut;
1440
1441 if (efuseType == EFUSE_WIFI)
1442 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8188F - EFUSE_OOB_PROTECT_BYTES);
1443 else
1444 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN - (EFUSE_PROTECT_BYTES_BANK * 3));
1445 }
1446 break;
1447
1448 case TYPE_EFUSE_MAP_LEN: {
1449 u16 *pu2Tmp;
1450
1451 pu2Tmp = (u16 *)pOut;
1452
1453 if (efuseType == EFUSE_WIFI)
1454 *pu2Tmp = EFUSE_MAP_LEN_8188F;
1455 else
1456 *pu2Tmp = EFUSE_BT_MAP_LEN;
1457 }
1458 break;
1459
1460 case TYPE_EFUSE_PROTECT_BYTES_BANK: {
1461 u8 *pu1Tmp;
1462
1463 pu1Tmp = (u8 *)pOut;
1464
1465 if (efuseType == EFUSE_WIFI)
1466 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
1467 else
1468 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
1469 }
1470 break;
1471
1472 case TYPE_EFUSE_CONTENT_LEN_BANK: {
1473 u16 *pu2Tmp;
1474
1475 pu2Tmp = (u16 *)pOut;
1476
1477 if (efuseType == EFUSE_WIFI)
1478 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8188F;
1479 else
1480 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
1481 }
1482 break;
1483
1484 default: {
1485 u8 *pu1Tmp;
1486
1487 pu1Tmp = (u8 *)pOut;
1488 *pu1Tmp = 0;
1489 }
1490 break;
1491 }
1492 }
1493
1494 #define VOLTAGE_V25 0x03
1495 #define LDOE25_SHIFT 28
1496
1497 /*================================================================= */
1498 /* The following is for compile ok */
1499 /* That should be merged with the original in the future */
1500 /*================================================================= */
1501 #define EFUSE_ACCESS_ON_8188 0x69 /* For RTL8188 only. */
1502 #define EFUSE_ACCESS_OFF_8188 0x00 /* For RTL8188 only. */
1503 #define REG_EFUSE_ACCESS_8188 0x00CF /* Efuse access protection for RTL8188 */
1504
1505 /*================================================================= */
Hal_BT_EfusePowerSwitch(PADAPTER padapter,u8 bWrite,u8 PwrState)1506 static void Hal_BT_EfusePowerSwitch(
1507 PADAPTER padapter,
1508 u8 bWrite,
1509 u8 PwrState)
1510 {
1511 u8 tempval;
1512 if (PwrState == _TRUE) {
1513 /* enable BT power cut */
1514 /* 0x6A[14] = 1 */
1515 tempval = rtw_read8(padapter, 0x6B);
1516 tempval |= BIT(6);
1517 rtw_write8(padapter, 0x6B, tempval);
1518
1519 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
1520 /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together! */
1521 rtw_usleep_os(100);
1522 /* disable BT output isolation */
1523 /* 0x6A[15] = 0 */
1524 tempval = rtw_read8(padapter, 0x6B);
1525 tempval &= ~BIT(7);
1526 rtw_write8(padapter, 0x6B, tempval);
1527 } else {
1528 /* enable BT output isolation */
1529 /* 0x6A[15] = 1 */
1530 tempval = rtw_read8(padapter, 0x6B);
1531 tempval |= BIT(7);
1532 rtw_write8(padapter, 0x6B, tempval);
1533
1534 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
1535 /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together! */
1536
1537 /* disable BT power cut */
1538 /* 0x6A[14] = 1 */
1539 tempval = rtw_read8(padapter, 0x6B);
1540 tempval &= ~BIT(6);
1541 rtw_write8(padapter, 0x6B, tempval);
1542 }
1543
1544 }
1545 static void
Hal_EfusePowerSwitch(PADAPTER padapter,u8 bWrite,u8 PwrState)1546 Hal_EfusePowerSwitch(
1547 PADAPTER padapter,
1548 u8 bWrite,
1549 u8 PwrState)
1550 {
1551 u8 tempval;
1552 u16 tmpV16;
1553
1554
1555 if (PwrState == _TRUE) {
1556 #ifdef CONFIG_SDIO_HCI
1557 /* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */
1558 /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */
1559 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
1560 if (tempval & BIT(0)) { /* SDIO local register is suspend */
1561 u8 count = 0;
1562
1563
1564 tempval &= ~BIT(0);
1565 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL, tempval);
1566
1567 /* check 0x86[1:0]=10'2h, wait power state to leave suspend */
1568 do {
1569 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
1570 tempval &= 0x3;
1571 if (tempval == 0x02)
1572 break;
1573
1574 count++;
1575 if (count >= 100)
1576 break;
1577
1578 rtw_mdelay_os(10);
1579 } while (1);
1580
1581 if (count >= 100) {
1582 RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86=%#X\n",
1583 FUNC_ADPT_ARG(padapter), tempval);
1584 } else {
1585 RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86=%#X\n",
1586 FUNC_ADPT_ARG(padapter), tempval);
1587 }
1588 }
1589 #endif /* CONFIG_SDIO_HCI */
1590
1591 rtw_write8(padapter, REG_EFUSE_ACCESS_8188, EFUSE_ACCESS_ON_8188);
1592
1593 /* Reset: 0x0000h[28], default valid */
1594 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
1595 if (!(tmpV16 & FEN_ELDR)) {
1596 tmpV16 |= FEN_ELDR;
1597 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
1598 }
1599
1600 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
1601 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
1602 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
1603 tmpV16 |= (LOADER_CLK_EN | ANA8M);
1604 rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
1605 }
1606
1607 if (bWrite == _TRUE) {
1608 /* Enable LDO 2.5V before read/write action */
1609 tempval = rtw_read8(padapter, EFUSE_TEST + 3);
1610 rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80));
1611 }
1612 } else {
1613 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
1614
1615 if (bWrite == _TRUE) {
1616 /* Disable LDO 2.5V after read/write action */
1617 tempval = rtw_read8(padapter, EFUSE_TEST + 3);
1618 rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F));
1619 }
1620
1621 }
1622 }
1623
1624 static void
hal_ReadEFuse_WiFi(PADAPTER padapter,u16 _offset,u16 _size_byte,u8 * pbuf,u8 bPseudoTest)1625 hal_ReadEFuse_WiFi(
1626 PADAPTER padapter,
1627 u16 _offset,
1628 u16 _size_byte,
1629 u8 *pbuf,
1630 u8 bPseudoTest)
1631 {
1632 #ifdef HAL_EFUSE_MEMORY
1633 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1634 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1635 #endif
1636 u8 *efuseTbl = NULL;
1637 u16 eFuse_Addr = 0;
1638 u8 offset, wden;
1639 u8 efuseHeader, efuseExtHdr, efuseData;
1640 u16 i, total, used;
1641 u8 efuse_usage = 0;
1642
1643 /*RTW_INFO("YJ: ====>%s():_offset=%d _size_byte=%d bPseudoTest=%d\n", __func__, _offset, _size_byte, bPseudoTest); */
1644 /* */
1645 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
1646 /* */
1647 if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN) {
1648 RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte);
1649 return;
1650 }
1651
1652 efuseTbl = (u8 *)rtw_malloc(EFUSE_MAX_MAP_LEN);
1653 if (efuseTbl == NULL) {
1654 RTW_INFO("%s: alloc efuseTbl fail!\n", __func__);
1655 return;
1656 }
1657 /* 0xff will be efuse default value instead of 0x00. */
1658 _rtw_memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
1659
1660
1661 #ifdef CONFIG_RTW_DEBUG
1662 if (0) {
1663 for (i = 0; i < 256; i++)
1664 /*ReadEFuseByte(padapter, i, &efuseTbl[i], _FALSE); */
1665 efuse_OneByteRead(padapter, i, &efuseTbl[i], _FALSE);
1666 RTW_INFO("Efuse Content:\n");
1667 for (i = 0; i < 256; i++)
1668 printk("%02X%s", efuseTbl[i], (((i + 1) % 16) == 0) ? "\n" : " ");
1669 }
1670 #endif
1671
1672
1673 /* switch bank back to bank 0 for later BT and wifi use. */
1674 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1675
1676 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
1677 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
1678 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1679 if (efuseHeader == 0xFF) {
1680 RTW_INFO("%s: data end at address=%#x\n", __func__, eFuse_Addr - 1);
1681 break;
1682 }
1683 /*RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __func__, eFuse_Addr-1, efuseHeader); */
1684
1685 /* Check PG header for section num. */
1686 if (EXT_HEADER(efuseHeader)) { /*extended header */
1687 offset = GET_HDR_OFFSET_2_0(efuseHeader);
1688 /*RTW_INFO("%s: extended header offset=0x%X\n", __func__, offset); */
1689
1690 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
1691 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1692 /*RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __func__, eFuse_Addr-1, efuseExtHdr); */
1693 if (ALL_WORDS_DISABLED(efuseExtHdr))
1694 continue;
1695
1696 offset |= ((efuseExtHdr & 0xF0) >> 1);
1697 wden = (efuseExtHdr & 0x0F);
1698 } else {
1699 offset = ((efuseHeader >> 4) & 0x0f);
1700 wden = (efuseHeader & 0x0f);
1701 }
1702 /*RTW_INFO("%s: Offset=%d Worden=0x%X\n", __func__, offset, wden); */
1703
1704 if (offset < EFUSE_MAX_SECTION_8188F) {
1705 u16 addr;
1706 /* Get word enable value from PG header */
1707 /*RTW_INFO("%s: Offset=%d Worden=0x%X\n", __func__, offset, wden); */
1708
1709 addr = offset * PGPKT_DATA_SIZE;
1710 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1711 /* Check word enable condition in the section */
1712 if (!(wden & (0x01 << i))) {
1713 efuseData = 0;
1714 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1715 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1716 /*RTW_INFO("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr-1, efuseData); */
1717 efuseTbl[addr] = efuseData;
1718
1719 efuseData = 0;
1720 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1721 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1722 /*RTW_INFO("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr-1, efuseData); */
1723 efuseTbl[addr + 1] = efuseData;
1724 }
1725 addr += 2;
1726 }
1727 } else {
1728 RTW_ERR("%s: offset(%d) is illegal!!\n", __func__, offset);
1729 eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
1730 }
1731 }
1732
1733 /* Copy from Efuse map to output pointer memory!!! */
1734 for (i = 0; i < _size_byte; i++)
1735 pbuf[i] = efuseTbl[_offset + i];
1736
1737 /* Calculate Efuse utilization */
1738 total = 0;
1739 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
1740 used = eFuse_Addr - 1;
1741 if (total)
1742 efuse_usage = (u8)((used * 100) / total);
1743 else
1744 efuse_usage = 100;
1745 if (bPseudoTest) {
1746 #ifdef HAL_EFUSE_MEMORY
1747 pEfuseHal->fakeEfuseUsedBytes = used;
1748 #else
1749 fakeEfuseUsedBytes = used;
1750 #endif
1751 } else {
1752 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
1753 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
1754 }
1755
1756 if (efuseTbl)
1757 rtw_mfree(efuseTbl, EFUSE_MAX_MAP_LEN);
1758 }
1759
1760 static void
hal_ReadEFuse_BT(PADAPTER padapter,u16 _offset,u16 _size_byte,u8 * pbuf,u8 bPseudoTest)1761 hal_ReadEFuse_BT(
1762 PADAPTER padapter,
1763 u16 _offset,
1764 u16 _size_byte,
1765 u8 *pbuf,
1766 u8 bPseudoTest
1767 )
1768 {
1769 #ifdef HAL_EFUSE_MEMORY
1770 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1771 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1772 #endif
1773 u8 *efuseTbl;
1774 u8 bank;
1775 u16 eFuse_Addr;
1776 u8 efuseHeader, efuseExtHdr, efuseData;
1777 u8 offset, wden;
1778 u16 i, total, used;
1779 u8 efuse_usage;
1780
1781
1782 /* */
1783 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
1784 /* */
1785 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
1786 RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte);
1787 return;
1788 }
1789
1790 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
1791 if (efuseTbl == NULL) {
1792 RTW_INFO("%s: efuseTbl malloc fail!\n", __func__);
1793 return;
1794 }
1795 /* 0xff will be efuse default value instead of 0x00. */
1796 _rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
1797
1798 total = 0;
1799 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
1800
1801 for (bank = 1; bank < 3; bank++) { /* 8188F Max bake 0~2 */
1802 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
1803 RTW_INFO("%s: hal_EfuseSwitchToBank Fail!!\n", __func__);
1804 goto exit;
1805 }
1806
1807 eFuse_Addr = 0;
1808
1809 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
1810 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
1811 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1812 if (efuseHeader == 0xFF)
1813 break;
1814 RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __func__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8188F) + eFuse_Addr - 1), efuseHeader);
1815
1816 /* Check PG header for section num. */
1817 if (EXT_HEADER(efuseHeader)) { /*extended header */
1818 offset = GET_HDR_OFFSET_2_0(efuseHeader);
1819 RTW_INFO("%s: extended header offset_2_0=0x%X\n", __func__, offset);
1820
1821 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
1822 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1823 RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __func__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8188F) + eFuse_Addr - 1), efuseExtHdr);
1824 if (ALL_WORDS_DISABLED(efuseExtHdr))
1825 continue;
1826
1827 offset |= ((efuseExtHdr & 0xF0) >> 1);
1828 wden = (efuseExtHdr & 0x0F);
1829 } else {
1830 offset = ((efuseHeader >> 4) & 0x0f);
1831 wden = (efuseHeader & 0x0f);
1832 }
1833
1834 if (offset < EFUSE_BT_MAX_SECTION) {
1835 u16 addr;
1836
1837 /* Get word enable value from PG header */
1838 RTW_INFO("%s: Offset=%d Worden=%#X\n", __func__, offset, wden);
1839
1840 addr = offset * PGPKT_DATA_SIZE;
1841 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1842 /* Check word enable condition in the section */
1843 if (!(wden & (0x01 << i))) {
1844 efuseData = 0;
1845 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1846 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1847 RTW_INFO("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr - 1, efuseData);
1848 efuseTbl[addr] = efuseData;
1849
1850 efuseData = 0;
1851 /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1852 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1853 RTW_INFO("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr - 1, efuseData);
1854 efuseTbl[addr + 1] = efuseData;
1855 }
1856 addr += 2;
1857 }
1858 } else {
1859 RTW_INFO("%s: offset(%d) is illegal!!\n", __func__, offset);
1860 eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
1861 }
1862 }
1863
1864 if ((eFuse_Addr - 1) < total) {
1865 RTW_INFO("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr - 1);
1866 break;
1867 }
1868 }
1869
1870 /* switch bank back to bank 0 for later BT and wifi use. */
1871 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1872
1873 /* Copy from Efuse map to output pointer memory!!! */
1874 for (i = 0; i < _size_byte; i++)
1875 pbuf[i] = efuseTbl[_offset + i];
1876
1877 /* */
1878 /* Calculate Efuse utilization. */
1879 /* */
1880 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
1881 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
1882 RTW_INFO("%s: bank(%d) data end at %#x ,used =%d\n", __func__, bank, eFuse_Addr - 1, used);
1883 efuse_usage = (u8)((used * 100) / total);
1884 if (bPseudoTest) {
1885 #ifdef HAL_EFUSE_MEMORY
1886 pEfuseHal->fakeBTEfuseUsedBytes = used;
1887 #else
1888 fakeBTEfuseUsedBytes = used;
1889 #endif
1890 } else {
1891 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
1892 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
1893 }
1894
1895 exit:
1896 if (efuseTbl)
1897 rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
1898 }
1899
1900 static void
Hal_ReadEFuse(PADAPTER padapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,u8 bPseudoTest)1901 Hal_ReadEFuse(
1902 PADAPTER padapter,
1903 u8 efuseType,
1904 u16 _offset,
1905 u16 _size_byte,
1906 u8 *pbuf,
1907 u8 bPseudoTest)
1908 {
1909 if (efuseType == EFUSE_WIFI)
1910 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1911 else
1912 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1913 }
1914
1915 static u16
hal_EfuseGetCurrentSize_WiFi(PADAPTER padapter,u8 bPseudoTest)1916 hal_EfuseGetCurrentSize_WiFi(
1917 PADAPTER padapter,
1918 u8 bPseudoTest)
1919 {
1920 #ifdef HAL_EFUSE_MEMORY
1921 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1922 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1923 #endif
1924 u16 efuse_addr = 0;
1925 u16 start_addr = 0; /* for debug */
1926 u8 hoffset = 0, hworden = 0;
1927 u8 efuse_data, word_cnts = 0;
1928 u32 count = 0; /* for debug */
1929
1930
1931 if (bPseudoTest) {
1932 #ifdef HAL_EFUSE_MEMORY
1933 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
1934 #else
1935 efuse_addr = (u16)fakeEfuseUsedBytes;
1936 #endif
1937 } else
1938 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1939 start_addr = efuse_addr;
1940 RTW_INFO("%s: start_efuse_addr=0x%X\n", __func__, efuse_addr);
1941
1942 /* switch bank back to bank 0 for later BT and wifi use. */
1943 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1944
1945 #if 0 /* for debug test */
1946 efuse_OneByteRead(padapter, 0x1FF, &efuse_data, bPseudoTest);
1947 RTW_INFO(FUNC_ADPT_FMT ": efuse raw 0x1FF=0x%02X\n",
1948 FUNC_ADPT_ARG(padapter), efuse_data);
1949 efuse_data = 0xFF;
1950 #endif /* for debug test */
1951
1952 count = 0;
1953 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1954 #if 1
1955 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
1956 RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __func__, efuse_addr);
1957 goto error;
1958 }
1959 #else
1960 ReadEFuseByte(padapter, efuse_addr, &efuse_data, bPseudoTest);
1961 #endif
1962
1963 if (efuse_data == 0xFF)
1964 break;
1965
1966 if ((start_addr != 0) && (efuse_addr == start_addr)) {
1967 count++;
1968 RTW_INFO(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X=0x%02X not 0xFF!!(%d times)\n",
1969 FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count);
1970
1971 efuse_data = 0xFF;
1972 if (count < 4) {
1973 /* try again! */
1974
1975 if (count > 2) {
1976 /* try again form address 0 */
1977 efuse_addr = 0;
1978 start_addr = 0;
1979 }
1980
1981 continue;
1982 }
1983
1984 goto error;
1985 }
1986
1987 if (EXT_HEADER(efuse_data)) {
1988 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1989 efuse_addr++;
1990 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1991 if (ALL_WORDS_DISABLED(efuse_data))
1992 continue;
1993
1994 hoffset |= ((efuse_data & 0xF0) >> 1);
1995 hworden = efuse_data & 0x0F;
1996 } else {
1997 hoffset = (efuse_data >> 4) & 0x0F;
1998 hworden = efuse_data & 0x0F;
1999 }
2000
2001 word_cnts = Efuse_CalculateWordCnts(hworden);
2002 efuse_addr += (word_cnts * 2) + 1;
2003 }
2004
2005 if (bPseudoTest) {
2006 #ifdef HAL_EFUSE_MEMORY
2007 pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
2008 #else
2009 fakeEfuseUsedBytes = efuse_addr;
2010 #endif
2011 } else
2012 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
2013
2014 goto exit;
2015
2016 error:
2017 /* report max size to prevent write efuse */
2018 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
2019
2020 exit:
2021 RTW_INFO("%s: CurrentSize=%d\n", __func__, efuse_addr);
2022
2023 return efuse_addr;
2024 }
2025
2026 static u16
hal_EfuseGetCurrentSize_BT(PADAPTER padapter,u8 bPseudoTest)2027 hal_EfuseGetCurrentSize_BT(
2028 PADAPTER padapter,
2029 u8 bPseudoTest)
2030 {
2031 #ifdef HAL_EFUSE_MEMORY
2032 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2033 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
2034 #endif
2035 u16 btusedbytes;
2036 u16 efuse_addr;
2037 u8 bank, startBank;
2038 u8 hoffset = 0, hworden = 0;
2039 u8 efuse_data, word_cnts = 0;
2040 u16 retU2 = 0;
2041 u8 bContinual = _TRUE;
2042
2043
2044 if (bPseudoTest) {
2045 #ifdef HAL_EFUSE_MEMORY
2046 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
2047 #else
2048 btusedbytes = fakeBTEfuseUsedBytes;
2049 #endif
2050 } else {
2051 btusedbytes = 0;
2052 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
2053 }
2054 efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
2055 startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
2056
2057 RTW_INFO("%s: start from bank=%d addr=0x%X\n", __func__, startBank, efuse_addr);
2058
2059 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
2060
2061 for (bank = startBank; bank < 3; bank++) {
2062 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
2063 RTW_ERR("%s: switch bank(%d) Fail!!\n", __func__, bank);
2064 /*bank = EFUSE_MAX_BANK; */
2065 break;
2066 }
2067
2068 /* only when bank is switched we have to reset the efuse_addr. */
2069 if (bank != startBank)
2070 efuse_addr = 0;
2071 #if 1
2072
2073 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
2074 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
2075 RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __func__, efuse_addr);
2076 /*bank = EFUSE_MAX_BANK; */
2077 break;
2078 }
2079 RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank);
2080
2081 if (efuse_data == 0xFF)
2082 break;
2083
2084 if (EXT_HEADER(efuse_data)) {
2085 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
2086 efuse_addr++;
2087 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
2088 RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank);
2089
2090 if (ALL_WORDS_DISABLED(efuse_data)) {
2091 efuse_addr++;
2092 continue;
2093 }
2094
2095 /*hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
2096 hoffset |= ((efuse_data & 0xF0) >> 1);
2097 hworden = efuse_data & 0x0F;
2098 } else {
2099 hoffset = (efuse_data >> 4) & 0x0F;
2100 hworden = efuse_data & 0x0F;
2101 }
2102
2103 RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
2104 FUNC_ADPT_ARG(padapter), hoffset, hworden);
2105
2106 word_cnts = Efuse_CalculateWordCnts(hworden);
2107 /*read next header */
2108 efuse_addr += (word_cnts * 2) + 1;
2109 }
2110 #else
2111 while (bContinual &&
2112 efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest) &&
2113 AVAILABLE_EFUSE_ADDR(efuse_addr)) {
2114 if (efuse_data != 0xFF) {
2115 if ((efuse_data & 0x1F) == 0x0F) { /*extended header */
2116 hoffset = efuse_data;
2117 efuse_addr++;
2118 efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest);
2119 if ((efuse_data & 0x0F) == 0x0F) {
2120 efuse_addr++;
2121 continue;
2122 } else {
2123 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2124 hworden = efuse_data & 0x0F;
2125 }
2126 } else {
2127 hoffset = (efuse_data >> 4) & 0x0F;
2128 hworden = efuse_data & 0x0F;
2129 }
2130 word_cnts = Efuse_CalculateWordCnts(hworden);
2131 /*read next header */
2132 efuse_addr = efuse_addr + (word_cnts * 2) + 1;
2133 } else
2134 bContinual = _FALSE;
2135 }
2136 #endif
2137
2138
2139 /* Check if we need to check next bank efuse */
2140 if (efuse_addr < retU2) {
2141 /* don't need to check next bank. */
2142 break;
2143 }
2144 }
2145 #if 0
2146 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
2147 if (bPseudoTest) {
2148 #ifdef HAL_EFUSE_MEMORY
2149 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
2150 #else
2151 fakeBTEfuseUsedBytes = retU2;
2152 #endif
2153 } else
2154 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&retU2);
2155 #else
2156 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
2157 if (bPseudoTest) {
2158 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
2159 /*RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */
2160 } else {
2161 pEfuseHal->BTEfuseUsedBytes = retU2;
2162 /*RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */
2163 }
2164 #endif
2165
2166 RTW_INFO("%s: CurrentSize=%d\n", __func__, retU2);
2167 return retU2;
2168 }
2169
2170 static u16
Hal_EfuseGetCurrentSize(PADAPTER pAdapter,u8 efuseType,u8 bPseudoTest)2171 Hal_EfuseGetCurrentSize(
2172 PADAPTER pAdapter,
2173 u8 efuseType,
2174 u8 bPseudoTest)
2175 {
2176 u16 ret = 0;
2177
2178 if (efuseType == EFUSE_WIFI)
2179 ret = hal_EfuseGetCurrentSize_WiFi(pAdapter, bPseudoTest);
2180 else
2181 ret = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
2182
2183 return ret;
2184 }
2185
2186 static u8
Hal_EfuseWordEnableDataWrite(PADAPTER padapter,u16 efuse_addr,u8 word_en,u8 * data,u8 bPseudoTest)2187 Hal_EfuseWordEnableDataWrite(
2188 PADAPTER padapter,
2189 u16 efuse_addr,
2190 u8 word_en,
2191 u8 *data,
2192 u8 bPseudoTest)
2193 {
2194 u16 tmpaddr = 0;
2195 u16 start_addr = efuse_addr;
2196 u8 badworden = 0x0F;
2197 u8 tmpdata[PGPKT_DATA_SIZE];
2198
2199
2200 /*RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __func__, efuse_addr, word_en); */
2201 _rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
2202
2203 if (!(word_en & BIT(0))) {
2204 tmpaddr = start_addr;
2205 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
2206 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
2207 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2208 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
2209 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[1], bPseudoTest);
2210 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2211 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
2212 badworden &= (~BIT(0));
2213 }
2214 if (!(word_en & BIT(1))) {
2215 tmpaddr = start_addr;
2216 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
2217 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
2218 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2219 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
2220 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[3], bPseudoTest);
2221 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2222 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
2223 badworden &= (~BIT(1));
2224 }
2225 if (!(word_en & BIT(2))) {
2226 tmpaddr = start_addr;
2227 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
2228 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
2229 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2230 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
2231 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[5], bPseudoTest);
2232 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2233 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
2234 badworden &= (~BIT(2));
2235 }
2236 if (!(word_en & BIT(3))) {
2237 tmpaddr = start_addr;
2238 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
2239 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
2240 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2241 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
2242 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[7], bPseudoTest);
2243 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2244 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
2245 badworden &= (~BIT(3));
2246 }
2247
2248 return badworden;
2249 }
2250
2251 static s32
Hal_EfusePgPacketRead(PADAPTER padapter,u8 offset,u8 * data,u8 bPseudoTest)2252 Hal_EfusePgPacketRead(
2253 PADAPTER padapter,
2254 u8 offset,
2255 u8 *data,
2256 u8 bPseudoTest)
2257 {
2258 u8 bDataEmpty = _TRUE;
2259 u8 efuse_data, word_cnts = 0;
2260 u16 efuse_addr = 0;
2261 u8 hoffset = 0, hworden = 0;
2262 u8 i;
2263 u8 max_section = 0;
2264 s32 ret;
2265
2266
2267 if (data == NULL)
2268 return _FALSE;
2269
2270 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest);
2271 if (offset > max_section) {
2272 RTW_INFO("%s: Packet offset(%d) is illegal(>%d)!\n", __func__, offset, max_section);
2273 return _FALSE;
2274 }
2275
2276 _rtw_memset(data, 0xFF, PGPKT_DATA_SIZE);
2277 ret = _TRUE;
2278
2279 /* */
2280 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
2281 /* Skip dummy parts to prevent unexpected data read from Efuse. */
2282 /* By pass right now. 2009.02.19. */
2283 /* */
2284 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
2285 if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == _FALSE) {
2286 ret = _FALSE;
2287 break;
2288 }
2289
2290 if (efuse_data == 0xFF)
2291 break;
2292
2293 if (EXT_HEADER(efuse_data)) {
2294 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
2295 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
2296 if (ALL_WORDS_DISABLED(efuse_data)) {
2297 RTW_INFO("%s: Error!! All words disabled!\n", __func__);
2298 continue;
2299 }
2300
2301 hoffset |= ((efuse_data & 0xF0) >> 1);
2302 hworden = efuse_data & 0x0F;
2303 } else {
2304 hoffset = (efuse_data >> 4) & 0x0F;
2305 hworden = efuse_data & 0x0F;
2306 }
2307
2308 if (hoffset == offset) {
2309 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2310 /* Check word enable condition in the section */
2311 if (!(hworden & (0x01 << i))) {
2312 /*ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
2313 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
2314 /*RTW_INFO("%s: efuse[%#X]=0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */
2315 data[i * 2] = efuse_data;
2316
2317 /*ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
2318 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
2319 /*RTW_INFO("%s: efuse[%#X]=0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */
2320 data[(i * 2) + 1] = efuse_data;
2321 }
2322 }
2323 } else {
2324 word_cnts = Efuse_CalculateWordCnts(hworden);
2325 efuse_addr += word_cnts * 2;
2326 }
2327 }
2328
2329 return ret;
2330 }
2331
2332 static u8
hal_EfusePgCheckAvailableAddr(PADAPTER pAdapter,u8 efuseType,u8 bPseudoTest)2333 hal_EfusePgCheckAvailableAddr(
2334 PADAPTER pAdapter,
2335 u8 efuseType,
2336 u8 bPseudoTest)
2337 {
2338 u16 max_available = 0;
2339 u16 current_size;
2340
2341
2342 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest);
2343 /*RTW_INFO("%s: max_available=%d\n", __func__, max_available); */
2344
2345 current_size = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
2346 if (current_size >= max_available) {
2347 RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __func__, current_size, max_available);
2348 return _FALSE;
2349 }
2350 return _TRUE;
2351 }
2352
2353 static void
hal_EfuseConstructPGPkt(u8 offset,u8 word_en,u8 * pData,PPGPKT_STRUCT pTargetPkt)2354 hal_EfuseConstructPGPkt(
2355 u8 offset,
2356 u8 word_en,
2357 u8 *pData,
2358 PPGPKT_STRUCT pTargetPkt)
2359 {
2360 _rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
2361 pTargetPkt->offset = offset;
2362 pTargetPkt->word_en = word_en;
2363 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
2364 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2365 }
2366
2367 #if 0
2368 static u8
2369 wordEnMatched(
2370 PPGPKT_STRUCT pTargetPkt,
2371 PPGPKT_STRUCT pCurPkt,
2372 u8 *pWden)
2373 {
2374 u8 match_word_en = 0x0F; /* default all words are disabled */
2375 u8 i;
2376
2377 /* check if the same words are enabled both target and current PG packet */
2378 if (((pTargetPkt->word_en & BIT(0)) == 0) &&
2379 ((pCurPkt->word_en & BIT(0)) == 0)) {
2380 match_word_en &= ~BIT(0); /* enable word 0 */
2381 }
2382 if (((pTargetPkt->word_en & BIT(1)) == 0) &&
2383 ((pCurPkt->word_en & BIT(1)) == 0)) {
2384 match_word_en &= ~BIT(1); /* enable word 1 */
2385 }
2386 if (((pTargetPkt->word_en & BIT(2)) == 0) &&
2387 ((pCurPkt->word_en & BIT(2)) == 0)) {
2388 match_word_en &= ~BIT(2); /* enable word 2 */
2389 }
2390 if (((pTargetPkt->word_en & BIT(3)) == 0) &&
2391 ((pCurPkt->word_en & BIT(3)) == 0)) {
2392 match_word_en &= ~BIT(3); /* enable word 3 */
2393 }
2394
2395 *pWden = match_word_en;
2396
2397 if (match_word_en != 0xf)
2398 return _TRUE;
2399 else
2400 return _FALSE;
2401 }
2402
2403 static u8
2404 hal_EfuseCheckIfDatafollowed(
2405 PADAPTER pAdapter,
2406 u8 word_cnts,
2407 u16 startAddr,
2408 u8 bPseudoTest)
2409 {
2410 u8 bRet = _FALSE;
2411 u8 i, efuse_data;
2412
2413 for (i = 0; i < (word_cnts * 2); i++) {
2414 if (efuse_OneByteRead(pAdapter, (startAddr + i) , &efuse_data, bPseudoTest) == _FALSE) {
2415 RTW_INFO("%s: efuse_OneByteRead FAIL!!\n", __func__);
2416 bRet = _TRUE;
2417 break;
2418 }
2419
2420 if (efuse_data != 0xFF) {
2421 bRet = _TRUE;
2422 break;
2423 }
2424 }
2425
2426 return bRet;
2427 }
2428 #endif
2429
2430 static u8
hal_EfusePartialWriteCheck(PADAPTER padapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2431 hal_EfusePartialWriteCheck(
2432 PADAPTER padapter,
2433 u8 efuseType,
2434 u16 *pAddr,
2435 PPGPKT_STRUCT pTargetPkt,
2436 u8 bPseudoTest)
2437 {
2438 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2439 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
2440 u8 bRet = _FALSE;
2441 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
2442 u8 efuse_data = 0;
2443 #if 0
2444 u8 i, cur_header = 0;
2445 u8 new_wden = 0, matched_wden = 0, badworden = 0;
2446 PGPKT_STRUCT curPkt;
2447 #endif
2448
2449
2450 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest);
2451 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest);
2452
2453 if (efuseType == EFUSE_WIFI) {
2454 if (bPseudoTest) {
2455 #ifdef HAL_EFUSE_MEMORY
2456 startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
2457 #else
2458 startAddr = (u16)fakeEfuseUsedBytes;
2459 #endif
2460 } else
2461 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
2462 } else {
2463 if (bPseudoTest) {
2464 #ifdef HAL_EFUSE_MEMORY
2465 startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
2466 #else
2467 startAddr = (u16)fakeBTEfuseUsedBytes;
2468 #endif
2469 } else
2470 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
2471 }
2472 startAddr %= efuse_max;
2473 RTW_INFO("%s: startAddr=%#X\n", __func__, startAddr);
2474
2475 while (1) {
2476 if (startAddr >= efuse_max_available_len) {
2477 bRet = _FALSE;
2478 RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
2479 __func__, startAddr, efuse_max_available_len);
2480 break;
2481 }
2482
2483 if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
2484 #if 1
2485 bRet = _FALSE;
2486 RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
2487 __func__, startAddr, efuse_data);
2488 break;
2489 #else
2490 if (EXT_HEADER(efuse_data)) {
2491 cur_header = efuse_data;
2492 startAddr++;
2493 efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest);
2494 if (ALL_WORDS_DISABLED(efuse_data)) {
2495 RTW_INFO("%s: Error condition, all words disabled!", __func__);
2496 bRet = _FALSE;
2497 break;
2498 } else {
2499 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2500 curPkt.word_en = efuse_data & 0x0F;
2501 }
2502 } else {
2503 cur_header = efuse_data;
2504 curPkt.offset = (cur_header >> 4) & 0x0F;
2505 curPkt.word_en = cur_header & 0x0F;
2506 }
2507
2508 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
2509 /* if same header is found but no data followed */
2510 /* write some part of data followed by the header. */
2511 if ((curPkt.offset == pTargetPkt->offset) &&
2512 (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr + 1, bPseudoTest) == _FALSE) &&
2513 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == _TRUE) {
2514 RTW_INFO("%s: Need to partial write data by the previous wrote header\n", __func__);
2515 /* Here to write partial data */
2516 badworden = Efuse_WordEnableDataWrite(padapter, startAddr + 1, matched_wden, pTargetPkt->data, bPseudoTest);
2517 if (badworden != 0x0F) {
2518 u32 PgWriteSuccess = 0;
2519 /* if write fail on some words, write these bad words again */
2520 if (efuseType == EFUSE_WIFI)
2521 PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2522 else
2523 PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2524
2525 if (!PgWriteSuccess) {
2526 bRet = _FALSE; /* write fail, return */
2527 break;
2528 }
2529 }
2530 /* partial write ok, update the target packet for later use */
2531 for (i = 0; i < 4; i++) {
2532 if ((matched_wden & (0x1 << i)) == 0) { /* this word has been written */
2533 pTargetPkt->word_en |= (0x1 << i); /* disable the word */
2534 }
2535 }
2536 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2537 }
2538 /* read from next header */
2539 startAddr = startAddr + (curPkt.word_cnts * 2) + 1;
2540 #endif
2541 } else {
2542 /* not used header, 0xff */
2543 *pAddr = startAddr;
2544 /*RTW_INFO("%s: Started from unused header offset=%d\n", __func__, startAddr)); */
2545 bRet = _TRUE;
2546 break;
2547 }
2548 }
2549
2550 return bRet;
2551 }
2552
2553 BOOLEAN
hal_EfuseFixHeaderProcess(PADAPTER pAdapter,u8 efuseType,PPGPKT_STRUCT pFixPkt,u16 * pAddr,BOOLEAN bPseudoTest)2554 hal_EfuseFixHeaderProcess(
2555 PADAPTER pAdapter,
2556 u8 efuseType,
2557 PPGPKT_STRUCT pFixPkt,
2558 u16 *pAddr,
2559 BOOLEAN bPseudoTest
2560 )
2561 {
2562 u8 originaldata[8], badworden=0;
2563 u16 efuse_addr=*pAddr;
2564 u32 PgWriteSuccess=0;
2565
2566 _rtw_memset((void *)originaldata, 0xff, 8);
2567
2568 if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) {
2569 badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
2570
2571 if (badworden != 0xf) {
2572
2573 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
2574 if (!PgWriteSuccess)
2575 return FALSE;
2576 else
2577 efuse_addr = Hal_EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
2578 } else {
2579 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
2580 }
2581 } else {
2582 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
2583 }
2584
2585 *pAddr = efuse_addr;
2586 return TRUE;
2587 }
2588
2589 static u8
hal_EfusePgPacketWrite1ByteHeader(PADAPTER pAdapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2590 hal_EfusePgPacketWrite1ByteHeader(
2591 PADAPTER pAdapter,
2592 u8 efuseType,
2593 u16 *pAddr,
2594 PPGPKT_STRUCT pTargetPkt,
2595 u8 bPseudoTest)
2596 {
2597 u8 bRet = _FALSE;
2598 u8 pg_header = 0, tmp_header = 0;
2599 u16 efuse_addr = *pAddr;
2600 u8 repeatcnt = 0;
2601
2602
2603 /* RTW_INFO("%s\n", __FUNCTION__); */
2604 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
2605
2606 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2607
2608 phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0);
2609
2610 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2611
2612 phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1);
2613
2614 while (tmp_header == 0xFF || pg_header != tmp_header) {
2615 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2616 RTW_ERR("retry %d times fail!!\n", repeatcnt);
2617 return _FALSE;
2618 }
2619 efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
2620 efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
2621 RTW_ERR("===>%s: Keep %d-th retrying,pg_header = 0x%X tmp_header = 0x%X\n", __FUNCTION__,repeatcnt, pg_header, tmp_header);
2622 }
2623
2624 if (pg_header == tmp_header)
2625 bRet = _TRUE;
2626 else {
2627 PGPKT_STRUCT fixPkt;
2628
2629 RTW_ERR(" pg_header(0x%X) != tmp_header(0x%X)\n", pg_header, tmp_header);
2630 RTW_ERR("Error condition for fixed PG packet, need to cover the existed data: (Addr, Data) = (0x%X, 0x%X)\n",
2631 efuse_addr, tmp_header);
2632 fixPkt.offset = (tmp_header>>4) & 0x0F;
2633 fixPkt.word_en = tmp_header & 0x0F;
2634 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2635 if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2636 return _FALSE;
2637 }
2638
2639 *pAddr = efuse_addr;
2640
2641 return _TRUE;
2642 }
2643
2644 static u8
hal_EfusePgPacketWrite2ByteHeader(PADAPTER padapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2645 hal_EfusePgPacketWrite2ByteHeader(
2646 PADAPTER padapter,
2647 u8 efuseType,
2648 u16 *pAddr,
2649 PPGPKT_STRUCT pTargetPkt,
2650 u8 bPseudoTest)
2651 {
2652 u16 efuse_addr, efuse_max_available_len = 0;
2653 u8 pg_header = 0, tmp_header = 0, pg_header_temp = 0;
2654 u8 repeatcnt = 0;
2655
2656
2657 /* RTW_INFO("%s\n", __FUNCTION__); */
2658 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest);
2659
2660 efuse_addr = *pAddr;
2661
2662 if (efuse_addr >= efuse_max_available_len) {
2663 RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
2664 return _FALSE;
2665 }
2666
2667 while (efuse_addr < efuse_max_available_len) {
2668 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
2669 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2670 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2671 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2672 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2673
2674 while (tmp_header == 0xFF || pg_header != tmp_header) {
2675 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2676 RTW_INFO("%s, Repeat over limit for pg_header!!\n", __FUNCTION__);
2677 return _FALSE;
2678 }
2679
2680 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2681 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2682 }
2683
2684 /*to write ext_header*/
2685 if (tmp_header == pg_header) {
2686 efuse_addr++;
2687 pg_header_temp = pg_header;
2688 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
2689
2690 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2691 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2692 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2693 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2694
2695 while (tmp_header == 0xFF || pg_header != tmp_header) {
2696 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2697 RTW_INFO("%s, Repeat over limit for ext_header!!\n", __FUNCTION__);
2698 return _FALSE;
2699 }
2700
2701 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2702 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2703 }
2704
2705 if ((tmp_header & 0x0F) == 0x0F) {
2706 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2707 RTW_INFO("Repeat over limit for word_en!!\n");
2708 return _FALSE;
2709 } else {
2710 efuse_addr++;
2711 continue;
2712 }
2713 } else if (pg_header != tmp_header) {
2714 PGPKT_STRUCT fixPkt;
2715 RTW_ERR("Error, efuse_PgPacketWrite2ByteHeader(), offset PG fail, need to cover the existed data!!\n");
2716 RTW_ERR("Error condition for offset PG fail, need to cover the existed data\n");
2717 fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
2718 fixPkt.word_en = tmp_header & 0x0F;
2719 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2720 if (!hal_EfuseFixHeaderProcess(padapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2721 return _FALSE;
2722 } else
2723 break;
2724 } else if ((tmp_header & 0x1F) == 0x0F) {/*wrong extended header*/
2725 efuse_addr += 2;
2726 continue;
2727 }
2728 }
2729
2730 *pAddr = efuse_addr;
2731
2732 return _TRUE;
2733 }
2734
2735 static u8
hal_EfusePgPacketWriteHeader(PADAPTER padapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2736 hal_EfusePgPacketWriteHeader(
2737 PADAPTER padapter,
2738 u8 efuseType,
2739 u16 *pAddr,
2740 PPGPKT_STRUCT pTargetPkt,
2741 u8 bPseudoTest)
2742 {
2743 u8 bRet = _FALSE;
2744
2745 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
2746 bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2747 else
2748 bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2749
2750 return bRet;
2751 }
2752
2753 static u8
hal_EfusePgPacketWriteData(PADAPTER pAdapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2754 hal_EfusePgPacketWriteData(
2755 PADAPTER pAdapter,
2756 u8 efuseType,
2757 u16 *pAddr,
2758 PPGPKT_STRUCT pTargetPkt,
2759 u8 bPseudoTest)
2760 {
2761 u16 efuse_addr;
2762 u8 badworden;
2763 u8 PgWriteSuccess = 0;
2764
2765
2766 efuse_addr = *pAddr;
2767 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
2768 if (badworden == 0x0F) {
2769 RTW_INFO("%s: OK!!\n", __FUNCTION__);
2770 return _TRUE;
2771 } else { /* Reorganize other pg packet */
2772 RTW_ERR ("Error, efuse_PgPacketWriteData(), wirte data fail!!\n");
2773 RTW_ERR ("efuse_PgPacketWriteData Fail!!\n");
2774 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2775 if (!PgWriteSuccess)
2776 return FALSE;
2777 else
2778 return TRUE;
2779 }
2780
2781 return _TRUE;
2782 }
2783
2784 static s32
Hal_EfusePgPacketWrite(PADAPTER padapter,u8 offset,u8 word_en,u8 * pData,u8 bPseudoTest)2785 Hal_EfusePgPacketWrite(
2786 PADAPTER padapter,
2787 u8 offset,
2788 u8 word_en,
2789 u8 *pData,
2790 u8 bPseudoTest)
2791 {
2792 PGPKT_STRUCT targetPkt;
2793 u16 startAddr = 0;
2794 u8 efuseType = EFUSE_WIFI;
2795
2796 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
2797 return _FALSE;
2798
2799 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
2800
2801 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2802 return _FALSE;
2803
2804 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2805 return _FALSE;
2806
2807 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2808 return _FALSE;
2809
2810 return _TRUE;
2811 }
2812
2813 static u8
Hal_EfusePgPacketWrite_BT(PADAPTER pAdapter,u8 offset,u8 word_en,u8 * pData,u8 bPseudoTest)2814 Hal_EfusePgPacketWrite_BT(
2815 PADAPTER pAdapter,
2816 u8 offset,
2817 u8 word_en,
2818 u8 *pData,
2819 u8 bPseudoTest)
2820 {
2821 PGPKT_STRUCT targetPkt;
2822 u16 startAddr = 0;
2823 u8 efuseType = EFUSE_BT;
2824
2825 if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
2826 return _FALSE;
2827
2828 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
2829
2830 if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2831 return _FALSE;
2832
2833 if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2834 return _FALSE;
2835
2836 if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2837 return _FALSE;
2838
2839 return _TRUE;
2840 }
2841
2842
rtl8188f_read_chip_version(PADAPTER padapter)2843 static void rtl8188f_read_chip_version(PADAPTER padapter)
2844 {
2845 u32 value32;
2846 HAL_DATA_TYPE *pHalData;
2847 u8 tmpvdr;
2848 pHalData = GET_HAL_DATA(padapter);
2849
2850 value32 = rtw_read32(padapter, REG_SYS_CFG);
2851 pHalData->version_id.ICType = CHIP_8188F;
2852 pHalData->version_id.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
2853 pHalData->version_id.RFType = RF_TYPE_1T1R;
2854
2855 tmpvdr = (value32 & EXT_VENDOR_ID) >> EXT_VENDOR_ID_SHIFT;
2856 if (tmpvdr == 0x00)
2857 pHalData->version_id.VendorType = CHIP_VENDOR_TSMC;
2858 else if (tmpvdr == 0x01)
2859 pHalData->version_id.VendorType = CHIP_VENDOR_SMIC;
2860 else if (tmpvdr == 0x02)
2861 pHalData->version_id.VendorType = CHIP_VENDOR_UMC;
2862
2863 pHalData->version_id.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
2864
2865 #if 0
2866 /* For regulator mode. by tynli. 2011.01.14 */
2867 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
2868 #endif
2869
2870 #if 0
2871 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
2872 pHalData->version_id.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */
2873 #endif
2874
2875 #if 0
2876 /* For multi-function consideration. Added by Roger, 2010.10.06. */
2877 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
2878 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
2879 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
2880 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
2881 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
2882 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
2883 #endif
2884
2885
2886 #if 0 /* mark for chage to use efuse */
2887 if (IS_B_CUT(pHalData->version_id) || IS_C_CUT(pHalData->version_id)) {
2888 RTW_INFO(" IS_B/C_CUT SWR up 1 level !!!!!!!!!!!!!!!!!\n");
2889 phy_set_mac_reg(padapter, 0x14, BIT23 | BIT22 | BIT21 | BIT20, 0x5); /* MAC reg 0x14[23:20] = 4b'0101 (SWR 1.220V) */
2890 } else if (IS_D_CUT(pHalData->version_id))
2891 RTW_INFO(" IS_D_CUT SKIP SWR !!!!!!!!!!!!!!!!!\n");
2892 #endif /* mark for chage to use efuse */
2893
2894 #if 1
2895 dump_chip_info(pHalData->version_id);
2896 #endif
2897
2898 }
2899
2900
rtl8188f_InitBeaconParameters(PADAPTER padapter)2901 void rtl8188f_InitBeaconParameters(PADAPTER padapter)
2902 {
2903 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2904 u16 val16;
2905 u8 val8;
2906
2907
2908 val8 = DIS_TSF_UDT;
2909 val16 = val8 | (val8 << 8); /* port0 and port1 */
2910 #ifdef CONFIG_BT_COEXIST
2911 /* Enable prot0 beacon function for PSTDMA */
2912 val16 |= EN_BCN_FUNCTION;
2913 #endif
2914 rtw_write16(padapter, REG_BCN_CTRL, val16);
2915
2916 /* TBTT setup time */
2917 rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
2918
2919 /* TBTT hold time: 0x540[19:8] */
2920 rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
2921 rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
2922 (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
2923
2924 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
2925 /* so don't set this register on STA mode. */
2926 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE)
2927 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8188F); /* 5ms */
2928 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8188F); /* 2ms */
2929
2930 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
2931 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
2932 rtw_write16(padapter, REG_BCNTCFG, 0x4413);
2933
2934 }
2935
rtl8188f_InitBeaconMaxError(PADAPTER padapter,u8 InfraMode)2936 void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode)
2937 {
2938 #ifdef CONFIG_ADHOC_WORKAROUND_SETTING
2939 rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF);
2940 #else
2941 /*rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10)); */
2942 #endif
2943 }
2944
_InitBurstPktLen_8188FS(PADAPTER Adapter)2945 void _InitBurstPktLen_8188FS(PADAPTER Adapter)
2946 {
2947 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2948
2949 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7) | BIT(7)); /*enable single pkt ampdu */
2950 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8188F, 0x18); /*for VHT packet length 11K */
2951 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8188F, 0x1F);
2952 rtw_write8(Adapter, REG_PIFS_8188F, 0x00);
2953 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8188F, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL) & (~BIT(7)));
2954 if (pHalData->AMPDUBurstMode)
2955 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8188F, 0x5F);
2956 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8188F, 0x70);
2957
2958 /* ARFB table 9 for 11ac 5G 2SS */
2959 rtw_write32(Adapter, REG_ARFR0_8188F, 0x00000010);
2960 if (IS_NORMAL_CHIP(pHalData->version_id))
2961 rtw_write32(Adapter, REG_ARFR0_8188F + 4, 0xfffff000);
2962 else
2963 rtw_write32(Adapter, REG_ARFR0_8188F + 4, 0x3e0ff000);
2964
2965 /* ARFB table 10 for 11ac 5G 1SS */
2966 rtw_write32(Adapter, REG_ARFR1_8188F, 0x00000010);
2967 rtw_write32(Adapter, REG_ARFR1_8188F + 4, 0x003ff000);
2968 }
2969
2970
_BeaconFunctionEnable(PADAPTER padapter,u8 Enable,u8 Linked)2971 static void _BeaconFunctionEnable(PADAPTER padapter, u8 Enable, u8 Linked)
2972 {
2973 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
2974 rtw_write8(padapter, REG_RD_CTRL + 1, 0x6F);
2975 }
2976
rtl8188f_SetBeaconRelatedRegisters(PADAPTER padapter)2977 static void rtl8188f_SetBeaconRelatedRegisters(PADAPTER padapter)
2978 {
2979 u8 val8;
2980 u32 value32;
2981 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2982 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2983 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2984 u32 bcn_ctrl_reg;
2985
2986 /*reset TSF, enable update TSF, correcting TSF On Beacon */
2987
2988 /*REG_MBSSID_BCN_SPACE */
2989 /*REG_BCNDMATIM */
2990 /*REG_ATIMWND */
2991 /*REG_TBTT_PROHIBIT */
2992 /*REG_DRVERLYINT */
2993 /*REG_BCN_MAX_ERR */
2994 /*REG_BCNTCFG //(0x510) */
2995 /*REG_DUAL_TSF_RST */
2996 /*REG_BCN_CTRL //(0x550) */
2997
2998
2999 bcn_ctrl_reg = REG_BCN_CTRL;
3000 #ifdef CONFIG_CONCURRENT_MODE
3001 if (padapter->hw_port == HW_PORT1)
3002 bcn_ctrl_reg = REG_BCN_CTRL_1;
3003 #endif
3004
3005 /* */
3006 /* ATIM window */
3007 /* */
3008 rtw_write16(padapter, REG_ATIMWND, 2);
3009
3010 /* */
3011 /* Beacon interval (in unit of TU). */
3012 /* */
3013 rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
3014
3015 rtl8188f_InitBeaconParameters(padapter);
3016
3017 rtw_write8(padapter, REG_SLOT, 0x09);
3018
3019 /* */
3020 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
3021 /* */
3022 value32 = rtw_read32(padapter, REG_TCR);
3023 value32 &= ~TSFRST;
3024 rtw_write32(padapter, REG_TCR, value32);
3025
3026 value32 |= TSFRST;
3027 rtw_write32(padapter, REG_TCR, value32);
3028
3029 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
3030 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _TRUE) {
3031 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
3032 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
3033 }
3034
3035 _BeaconFunctionEnable(padapter, _TRUE, _TRUE);
3036
3037 ResumeTxBeacon(padapter);
3038 val8 = rtw_read8(padapter, bcn_ctrl_reg);
3039 val8 |= DIS_BCNQ_SUB;
3040 rtw_write8(padapter, bcn_ctrl_reg, val8);
3041 }
3042
hal_notch_filter_8188f(_adapter * adapter,bool enable)3043 void hal_notch_filter_8188f(_adapter *adapter, bool enable)
3044 {
3045 if (enable) {
3046 RTW_INFO("Enable notch filter\n");
3047 rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) | BIT1);
3048 } else {
3049 RTW_INFO("Disable notch filter\n");
3050 rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) & ~BIT1);
3051 }
3052 }
3053
3054 /* */
3055 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
3056 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
3057 /* Fw can tell Hw to send these packet derectly. */
3058 /* Added by tynli. 2009.10.15. */
3059 /* */
3060 /*type1:pspoll, type2:null */
rtl8188f_fill_fake_txdesc(PADAPTER padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)3061 void rtl8188f_fill_fake_txdesc(
3062 PADAPTER padapter,
3063 u8 *pDesc,
3064 u32 BufferLen,
3065 u8 IsPsPoll,
3066 u8 IsBTQosNull,
3067 u8 bDataFrame)
3068 {
3069 /* Clear all status */
3070 _rtw_memset(pDesc, 0, TXDESC_SIZE);
3071
3072 SET_TX_DESC_FIRST_SEG_8188F(pDesc, 1); /*bFirstSeg; */
3073 SET_TX_DESC_LAST_SEG_8188F(pDesc, 1); /*bLastSeg; */
3074
3075 SET_TX_DESC_OFFSET_8188F(pDesc, 0x28); /* Offset = 32 */
3076
3077 SET_TX_DESC_PKT_SIZE_8188F(pDesc, BufferLen); /* Buffer size + command header */
3078 SET_TX_DESC_QUEUE_SEL_8188F(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
3079
3080 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
3081 if (_TRUE == IsPsPoll) {
3082 /* Nothing */
3083 SET_TX_DESC_NAV_USE_HDR_8188F(pDesc, 1);
3084 } else {
3085 SET_TX_DESC_HWSEQ_EN_8188F(pDesc, 1); /* Hw set sequence number */
3086 SET_TX_DESC_HWSEQ_SEL_8188F(pDesc, 0);
3087 }
3088
3089 if (_TRUE == IsBTQosNull)
3090 SET_TX_DESC_BT_INT_8188F(pDesc, 1);
3091
3092 SET_TX_DESC_USE_RATE_8188F(pDesc, 1); /* use data rate which is set by Sw */
3093 SET_TX_DESC_OWN_8188F((u8 *)pDesc, 1);
3094
3095 SET_TX_DESC_TX_RATE_8188F(pDesc, DESC8188F_RATE1M);
3096
3097 /* */
3098 /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */
3099 /* */
3100 if (_TRUE == bDataFrame) {
3101 u32 EncAlg;
3102
3103 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
3104 switch (EncAlg) {
3105 case _NO_PRIVACY_:
3106 SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x0);
3107 break;
3108 case _WEP40_:
3109 case _WEP104_:
3110 case _TKIP_:
3111 SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x1);
3112 break;
3113 case _SMS4_:
3114 SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x2);
3115 break;
3116 case _AES_:
3117 SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x3);
3118 break;
3119 default:
3120 SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x0);
3121 break;
3122 }
3123 }
3124
3125 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
3126 /* USB interface drop packet if the checksum of descriptor isn't correct. */
3127 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
3128 rtl8188f_cal_txdesc_chksum((struct tx_desc *)pDesc);
3129 #endif
3130 }
3131
rtl8188f_InitAntenna_Selection(PADAPTER padapter)3132 void rtl8188f_InitAntenna_Selection(PADAPTER padapter)
3133 {
3134 #ifdef CONFIG_ANTENNA_DIVERSITY
3135 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3136
3137 if (pHalData->AntDivCfg == 0)
3138 return;
3139
3140 /* LED(GPIO4) disable for AntDiv */
3141 phy_set_mac_reg(padapter, 0x4C, BIT21, 0x0);
3142 #endif
3143 }
3144
rtl8188f_CheckAntenna_Selection(PADAPTER padapter)3145 void rtl8188f_CheckAntenna_Selection(PADAPTER padapter)
3146 {
3147 PHAL_DATA_TYPE pHalData;
3148 u8 val;
3149
3150
3151 pHalData = GET_HAL_DATA(padapter);
3152
3153 val = rtw_read8(padapter, REG_LEDCFG2);
3154 /* Let 8051 take control antenna stetting */
3155 if (!(val & BIT(7))) {
3156 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
3157 rtw_write8(padapter, REG_LEDCFG2, val);
3158 }
3159 }
rtl8188f_DeinitAntenna_Selection(PADAPTER padapter)3160 void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter)
3161 {
3162 PHAL_DATA_TYPE pHalData;
3163 u8 val;
3164
3165
3166 pHalData = GET_HAL_DATA(padapter);
3167 val = rtw_read8(padapter, REG_LEDCFG2);
3168 /* Let 8051 take control antenna stetting */
3169 val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
3170 rtw_write8(padapter, REG_LEDCFG2, val);
3171
3172 }
3173
init_hal_spec_8188f(_adapter * adapter)3174 void init_hal_spec_8188f(_adapter *adapter)
3175 {
3176 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3177
3178 hal_spec->ic_name = "rtl8188f";
3179 hal_spec->macid_num = 16;
3180 hal_spec->sec_cam_ent_num = 16;
3181 hal_spec->sec_cap = 0;
3182 hal_spec->wow_cap = WOW_CAP_TKIP_OL;
3183 hal_spec->macid_cap = MACID_DROP_INDIRECT;
3184 hal_spec->macid_txrpt = 0x8100;
3185 hal_spec->macid_txrpt_pgsz = 16;
3186
3187 hal_spec->rfpath_num_2g = 1;
3188 hal_spec->rfpath_num_5g = 0;
3189 hal_spec->rf_reg_path_num = hal_spec->rf_reg_path_avail_num = 1;
3190 hal_spec->rf_reg_trx_path_bmp = 0x11;
3191 hal_spec->max_tx_cnt = 1;
3192
3193 hal_spec->tx_nss_num = 1;
3194 hal_spec->rx_nss_num = 1;
3195 hal_spec->band_cap = BAND_CAP_2G;
3196 hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M;
3197 hal_spec->port_num = 2;
3198 hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N;
3199
3200 hal_spec->txgi_max = 63;
3201 hal_spec->txgi_pdbm = 2;
3202
3203 hal_spec->wl_func = 0
3204 | WL_FUNC_P2P
3205 | WL_FUNC_MIRACAST
3206 | WL_FUNC_TDLS
3207 ;
3208
3209 hal_spec->tx_aclt_unit_factor = 1;
3210
3211 hal_spec->pg_txpwr_saddr = 0x10;
3212 hal_spec->pg_txgi_diff_factor = 1;
3213
3214 rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)
3215 , REG_MACID_SLEEP, 0, 0, 0);
3216 }
3217
rtl8188f_init_default_value(PADAPTER padapter)3218 void rtl8188f_init_default_value(PADAPTER padapter)
3219 {
3220 PHAL_DATA_TYPE pHalData;
3221 u8 i;
3222 pHalData = GET_HAL_DATA(padapter);
3223
3224 /* init default value */
3225 pHalData->fw_ractrl = _FALSE;
3226 if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
3227 pHalData->LastHMEBoxNum = 0;
3228
3229
3230 /*init phydm default value */
3231 pHalData->bIQKInitialized = _FALSE;
3232
3233 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
3234 pHalData->IntrMask[0] = (u32)(
3235 /* IMR_ROK | */
3236 /* IMR_RDU | */
3237 /* IMR_VODOK | */
3238 /* IMR_VIDOK | */
3239 /* IMR_BEDOK | */
3240 /* IMR_BKDOK | */
3241 /* IMR_MGNTDOK | */
3242 /* IMR_HIGHDOK | */
3243 /* IMR_CPWM | */
3244 /* IMR_CPWM2 | */
3245 /* IMR_C2HCMD | */
3246 /* IMR_HISR1_IND_INT | */
3247 /* IMR_ATIMEND | */
3248 /* IMR_BCNDMAINT_E | */
3249 /* IMR_HSISR_IND_ON_INT | */
3250 /* IMR_BCNDOK0 | */
3251 /* IMR_BCNDMAINT0 | */
3252 /* IMR_TSF_BIT32_TOGGLE | */
3253 /* IMR_TXBCN0OK | */
3254 /* IMR_TXBCN0ERR | */
3255 /* IMR_GTINT3 | */
3256 /* IMR_GTINT4 | */
3257 /* IMR_TXCCK | */
3258 0);
3259
3260 pHalData->IntrMask[1] = (u32)(
3261 /* IMR_RXFOVW | */
3262 /* IMR_TXFOVW | */
3263 /* IMR_RXERR | */
3264 /* IMR_TXERR | */
3265 /* IMR_ATIMEND_E | */
3266 /* IMR_BCNDOK1 | */
3267 /* IMR_BCNDOK2 | */
3268 /* IMR_BCNDOK3 | */
3269 /* IMR_BCNDOK4 | */
3270 /* IMR_BCNDOK5 | */
3271 /* IMR_BCNDOK6 | */
3272 /* IMR_BCNDOK7 | */
3273 /* IMR_BCNDMAINT1 | */
3274 /* IMR_BCNDMAINT2 | */
3275 /* IMR_BCNDMAINT3 | */
3276 /* IMR_BCNDMAINT4 | */
3277 /* IMR_BCNDMAINT5 | */
3278 /* IMR_BCNDMAINT6 | */
3279 /* IMR_BCNDMAINT7 | */
3280 0);
3281 #endif
3282
3283 /* init Efuse variables */
3284 pHalData->EfuseUsedBytes = 0;
3285 pHalData->EfuseUsedPercentage = 0;
3286 #ifdef HAL_EFUSE_MEMORY
3287 pHalData->EfuseHal.fakeEfuseBank = 0;
3288 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
3289 _rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
3290 _rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
3291 _rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
3292 pHalData->EfuseHal.BTEfuseUsedBytes = 0;
3293 pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
3294 _rtw_memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
3295 _rtw_memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3296 _rtw_memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3297 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
3298 _rtw_memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
3299 _rtw_memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3300 _rtw_memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3301 #endif
3302 }
3303
GetEEPROMSize8188F(PADAPTER padapter)3304 u8 GetEEPROMSize8188F(PADAPTER padapter)
3305 {
3306 u8 size = 0;
3307 u32 cr;
3308
3309 cr = rtw_read16(padapter, REG_9346CR);
3310 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
3311 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
3312
3313 RTW_INFO("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
3314
3315 return size;
3316 }
3317
3318 /*------------------------------------------------------------------------- */
3319 /* */
3320 /* LLT R/W/Init function */
3321 /* */
3322 /*------------------------------------------------------------------------- */
rtl8188f_InitLLTTable(PADAPTER padapter)3323 s32 rtl8188f_InitLLTTable(PADAPTER padapter)
3324 {
3325 systime start;
3326 u32 passing_time;
3327 u32 val32;
3328 s32 ret;
3329
3330
3331 ret = _FAIL;
3332
3333 val32 = rtw_read32(padapter, REG_AUTO_LLT);
3334 val32 |= BIT_AUTO_INIT_LLT;
3335 rtw_write32(padapter, REG_AUTO_LLT, val32);
3336
3337 start = rtw_get_current_time();
3338
3339 do {
3340 val32 = rtw_read32(padapter, REG_AUTO_LLT);
3341 if (!(val32 & BIT_AUTO_INIT_LLT)) {
3342 ret = _SUCCESS;
3343 break;
3344 }
3345
3346 passing_time = rtw_get_passing_time_ms(start);
3347 if (passing_time > 1000) {
3348 RTW_INFO("%s: FAIL!! REG_AUTO_LLT(0x%X)=%08x\n",
3349 __func__, REG_AUTO_LLT, val32);
3350 break;
3351 }
3352
3353 rtw_usleep_os(2);
3354 } while (1);
3355
3356 return ret;
3357 }
3358
3359 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
_DisableGPIO(PADAPTER padapter)3360 void _DisableGPIO(PADAPTER padapter)
3361 {
3362 /*
3363 * j. GPIO_PIN_CTRL 0x44[31:0]=0x000
3364 * k.Value = GPIO_PIN_CTRL[7:0]
3365 * l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
3366 * m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
3367 * n. LEDCFG 0x4C[15:0] = 0x8080
3368 */
3369 u8 value8;
3370 u16 value16;
3371 u32 value32;
3372 u32 u4bTmp;
3373
3374
3375 /*1. Disable GPIO[7:0] */
3376 rtw_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
3377 value32 = rtw_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
3378 u4bTmp = value32 & 0x000000FF;
3379 value32 |= ((u4bTmp << 8) | 0x00FF0000);
3380 rtw_write32(padapter, REG_GPIO_PIN_CTRL, value32);
3381
3382
3383 /*2. Disable GPIO[10:8] */
3384 rtw_write8(padapter, REG_MAC_PINMUX_CFG, 0x00);
3385 value16 = rtw_read16(padapter, REG_GPIO_IO_SEL) & 0xFF0F;
3386 value8 = (u8)(value16 & 0x000F);
3387 value16 |= ((value8 << 4) | 0x0780);
3388 rtw_write16(padapter, REG_GPIO_IO_SEL, value16);
3389
3390
3391 /*3. Disable LED0 & 1 */
3392 rtw_write16(padapter, REG_LEDCFG0, 0x8080);
3393
3394 } /*end of _DisableGPIO() */
3395
_DisableRFAFEAndResetBB8188F(PADAPTER padapter)3396 void _DisableRFAFEAndResetBB8188F(PADAPTER padapter)
3397 {
3398 /*
3399 * a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
3400 * b. RF path 0 offset 0x00 = 0x00 disable RF
3401 * c. APSD_CTRL 0x600[7:0] = 0x40
3402 * d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
3403 * e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
3404 */
3405 enum rf_path eRFPath = RF_PATH_A, value8 = 0;
3406
3407 rtw_write8(padapter, REG_TXPAUSE, 0xFF);
3408
3409 phy_set_rf_reg(padapter, eRFPath, 0x0, bMaskByte0, 0x0);
3410
3411 value8 |= APSDOFF;
3412 rtw_write8(padapter, REG_APSD_CTRL, value8);/*0x40 */
3413
3414 /* Set BB reset at first */
3415 value8 = 0;
3416 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
3417 rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /*0x16 */
3418
3419 /* Set global reset. */
3420 value8 &= ~FEN_BB_GLB_RSTn;
3421 rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /*0x14 */
3422
3423 /* 2010/08/12 MH We need to set BB/GLBAL reset to save power for SS mode. */
3424
3425 }
3426
_DisableRFAFEAndResetBB(PADAPTER padapter)3427 void _DisableRFAFEAndResetBB(PADAPTER padapter)
3428 {
3429 _DisableRFAFEAndResetBB8188F(padapter);
3430 }
3431
_ResetDigitalProcedure1_8188F(PADAPTER padapter,BOOLEAN bWithoutHWSM)3432 void _ResetDigitalProcedure1_8188F(PADAPTER padapter, BOOLEAN bWithoutHWSM)
3433 {
3434 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3435
3436 if (IS_FW_81xxC(padapter) && (pHalData->firmware_version <= 0x20)) {
3437 #if 0
3438 /*
3439 * f. SYS_FUNC_EN 0x03[7:0]=0x54 reset MAC register, DCORE
3440 * g. MCUFWDL 0x80[7:0]=0 reset MCU ready status
3441 */
3442 u32 value32 = 0;
3443
3444 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
3445 rtw_write8(padapter, REG_MCUFWDL, 0);
3446 #else
3447 /*
3448 * f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
3449 * g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset)
3450 * h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE
3451 * i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register, (8051 enable)
3452 */
3453 u16 valu16 = 0;
3454
3455 rtw_write8(padapter, REG_MCUFWDL, 0);
3456
3457 valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
3458 rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/*reset MCU ,8051 */
3459
3460 valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
3461 rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /*reset MAC */
3462
3463 valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
3464 rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/*enable MCU ,8051 */
3465 #endif
3466 } else {
3467 u8 retry_cnts = 0;
3468
3469 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we are trying to */
3470 /* enter IPS/HW&SW radio off. For S3/S4/S5/Disable, we can stop 8051 because */
3471 /* we will init FW when power on again. */
3472 /*if(!pDevice->RegUsbSS) */
3473 {
3474 /* If we want to SS mode, we can not reset 8051. */
3475 if (rtw_read8(padapter, REG_MCUFWDL) & BIT1) {
3476 /*IF fw in RAM code, do reset */
3477
3478
3479 if (pHalData->bFWReady) {
3480 /* 2010/08/25 MH According to RD alfred's suggestion, we need to disable other */
3481 /* HRCV INT to influence 8051 reset. */
3482 rtw_write8(padapter, REG_FWIMR, 0x20);
3483 /* 2011/02/15 MH According to Alex's suggestion, close mask to prevent incorrect FW write operation. */
3484 rtw_write8(padapter, REG_FTIMR, 0x00);
3485 rtw_write8(padapter, REG_FSIMR, 0x00);
3486
3487 rtw_write8(padapter, REG_HMETFR + 3, 0x20); /*8051 reset by self */
3488
3489 while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(padapter, REG_SYS_FUNC_EN))) {
3490 rtw_udelay_os(50);/*us */
3491 /* 2010/08/25 For test only We keep on reset 5051 to prevent fail. */
3492 /*rtw_write8(padapter, REG_HMETFR+3, 0x20);//8051 reset by self */
3493 }
3494 /*RT_ASSERT((retry_cnts < 100), ("8051 reset failed!\n")); */
3495
3496 if (retry_cnts >= 100) {
3497 /* if 8051 reset fail we trigger GPIO 0 for LA */
3498 /*rtw_write32( padapter, */
3499 /* REG_GPIO_PIN_CTRL, */
3500 /* 0x00010100); */
3501 /* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */
3502 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x50); /*Reset MAC and Enable 8051 */
3503 rtw_mdelay_os(10);
3504 }
3505 }
3506 }
3507 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54); /*Reset MAC and Enable 8051 */
3508 rtw_write8(padapter, REG_MCUFWDL, 0);
3509 }
3510 }
3511
3512 /*if(pDevice->RegUsbSS) */
3513 /*bWithoutHWSM = TRUE; // Sugest by Filen and Issau. */
3514
3515 if (bWithoutHWSM) {
3516 /*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */
3517 /*
3518 * Without HW auto state machine
3519 * SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
3520 * h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
3521 * i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
3522 * j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
3523 */
3524 /*rtw_write16(padapter, REG_SYS_CLKR, 0x30A3); */
3525 /*if(!pDevice->RegUsbSS) */
3526 /* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
3527 rtw_write16(padapter, REG_SYS_CLKR, 0x70A3); /*modify to 0x70A3 by Scott. */
3528 rtw_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
3529 rtw_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
3530 /*if(!pDevice->RegUsbSS) */
3531 rtw_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
3532 } else {
3533 /* Disable all RF/BB power */
3534 rtw_write8(padapter, REG_RF_CTRL, 0x00);
3535 }
3536
3537 }
3538
_ResetDigitalProcedure1(PADAPTER padapter,BOOLEAN bWithoutHWSM)3539 void _ResetDigitalProcedure1(PADAPTER padapter, BOOLEAN bWithoutHWSM)
3540 {
3541 _ResetDigitalProcedure1_8188F(padapter, bWithoutHWSM);
3542 }
3543
_ResetDigitalProcedure2(PADAPTER padapter)3544 void _ResetDigitalProcedure2(PADAPTER padapter)
3545 {
3546 /*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */
3547 /*
3548 * k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
3549 * l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
3550 * m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
3551 */
3552 /*rtw_write8(padapter, REG_SYS_FUNC_EN+1, 0x44); //marked by Scott. */
3553 /* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
3554 rtw_write16(padapter, REG_SYS_CLKR, 0x70a3); /*modify to 0x70a3 by Scott. */
3555 rtw_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82); /*modify to 0x82 by Scott. */
3556 }
3557
_DisableAnalog(PADAPTER padapter,BOOLEAN bWithoutHWSM)3558 void _DisableAnalog(PADAPTER padapter, BOOLEAN bWithoutHWSM)
3559 {
3560 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3561 u16 value16 = 0;
3562 u8 value8 = 0;
3563
3564
3565 if (bWithoutHWSM) {
3566 /*
3567 * n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
3568 * o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
3569 * r. When driver call disable, the ASIC will turn off remaining clock automatically
3570 */
3571
3572 rtw_write8(padapter, REG_LDOA15_CTRL, 0x04);
3573 /*rtw_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
3574
3575 value8 = rtw_read8(padapter, REG_LDOV12D_CTRL);
3576 value8 &= (~LDV12_EN);
3577 rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
3578 }
3579
3580 /*
3581 * h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
3582 * i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
3583 */
3584 value8 = 0x23;
3585
3586 rtw_write8(padapter, REG_SPS0_CTRL, value8);
3587
3588 if (bWithoutHWSM) {
3589 /*value16 |= (APDM_HOST | PFM_ALDN); */
3590 /* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */
3591 /* Because suspend operation need the asistance of 8051 to wait for 3ms. */
3592 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
3593 } else
3594 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
3595
3596 rtw_write16(padapter, REG_APS_FSMCO, value16);/*0x4802 */
3597
3598 rtw_write8(padapter, REG_RSV_CTRL, 0x0e);
3599
3600 #if 0
3601 /*tynli_test for suspend mode. */
3602 if (!bWithoutHWSM)
3603 rtw_write8(padapter, 0xfe10, 0x19);
3604 #endif
3605
3606 }
3607
3608 /* HW Auto state machine */
CardDisableHWSM(PADAPTER padapter,u8 resetMCU)3609 s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU)
3610 {
3611 int rtStatus = _SUCCESS;
3612
3613
3614 if (RTW_CANNOT_RUN(padapter))
3615 return rtStatus;
3616 /*==== RF Off Sequence ==== */
3617 _DisableRFAFEAndResetBB(padapter);
3618
3619 /* ==== Reset digital sequence ====== */
3620 _ResetDigitalProcedure1(padapter, _FALSE);
3621
3622 /* ==== Pull GPIO PIN to balance level and LED control ====== */
3623 _DisableGPIO(padapter);
3624
3625 /* ==== Disable analog sequence === */
3626 _DisableAnalog(padapter, _FALSE);
3627
3628
3629 return rtStatus;
3630 }
3631
3632 /* without HW Auto state machine */
CardDisableWithoutHWSM(PADAPTER padapter)3633 s32 CardDisableWithoutHWSM(PADAPTER padapter)
3634 {
3635 s32 rtStatus = _SUCCESS;
3636
3637
3638 if (RTW_CANNOT_RUN(padapter))
3639 return rtStatus;
3640
3641 /*==== RF Off Sequence ==== */
3642 _DisableRFAFEAndResetBB(padapter);
3643
3644 /* ==== Reset digital sequence ====== */
3645 _ResetDigitalProcedure1(padapter, _TRUE);
3646
3647 /* ==== Pull GPIO PIN to balance level and LED control ====== */
3648 _DisableGPIO(padapter);
3649
3650 /* ==== Reset digital sequence ====== */
3651 _ResetDigitalProcedure2(padapter);
3652
3653 /* ==== Disable analog sequence === */
3654 _DisableAnalog(padapter, _TRUE);
3655
3656 return rtStatus;
3657 }
3658 #endif /* CONFIG_USB_HCI || CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
3659
3660 void
Hal_InitPGData(PADAPTER padapter,u8 * PROMContent)3661 Hal_InitPGData(
3662 PADAPTER padapter,
3663 u8 *PROMContent)
3664 {
3665
3666 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3667 u32 i;
3668 u16 value16;
3669
3670 if (_FALSE == pHalData->bautoload_fail_flag) {
3671 /* autoload OK. */
3672 /*if (IS_BOOT_FROM_EEPROM(padapter)) */
3673 if (_TRUE == pHalData->EepromOrEfuse) {
3674 /* Read all Content from EEPROM or EFUSE. */
3675 for (i = 0; i < HWSET_MAX_SIZE_8188F; i += 2) {
3676 /*value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1))); */
3677 /**((u16*)(&PROMContent[i])) = value16; */
3678 }
3679 } else {
3680 /* Read EFUSE real map to shadow. */
3681 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
3682 _rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_8188F);
3683 }
3684 } else {
3685 /*autoload fail */
3686 /*pHalData->AutoloadFailFlag = _TRUE; */
3687 /*update to default value 0xFF */
3688 if (_FALSE == pHalData->EepromOrEfuse)
3689 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
3690 _rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_8188F);
3691 }
3692
3693 #ifdef CONFIG_EFUSE_CONFIG_FILE
3694 if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
3695 if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS)
3696 RTW_ERR("invalid phy efuse and read from file fail, will use driver default!!\n");
3697 }
3698 #endif
3699 }
3700
3701 void
Hal_EfuseParseIDCode(PADAPTER padapter,u8 * hwinfo)3702 Hal_EfuseParseIDCode(
3703 PADAPTER padapter,
3704 u8 *hwinfo
3705 )
3706 {
3707 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3708 u16 EEPROMId;
3709
3710
3711 /* Checl 0x8129 again for making sure autoload status!! */
3712 EEPROMId = le16_to_cpu(*((u16 *)hwinfo));
3713 if (EEPROMId != RTL_EEPROM_ID) {
3714 RTW_INFO("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
3715 pHalData->bautoload_fail_flag = _TRUE;
3716 } else
3717 pHalData->bautoload_fail_flag = _FALSE;
3718
3719 }
3720 void
Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter,u8 * PROMContent,BOOLEAN AutoLoadFail)3721 Hal_EfuseParseTxPowerInfo_8188F(
3722 PADAPTER padapter,
3723 u8 *PROMContent,
3724 BOOLEAN AutoLoadFail
3725 )
3726 {
3727 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3728
3729 pHalData->txpwr_pg_mode = TXPWR_PG_WITH_PWR_IDX;
3730
3731 /* 2010/10/19 MH Add Regulator recognize for CU. */
3732 if (!AutoLoadFail) {
3733 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8188F] & 0x7); /*bit0~2 */
3734 if (PROMContent[EEPROM_RF_BOARD_OPTION_8188F] == 0xFF)
3735 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7); /*bit0~2 */
3736 } else
3737 pHalData->EEPROMRegulatory = 0;
3738 }
3739
3740 void
Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3741 Hal_EfuseParseEEPROMVer_8188F(
3742 PADAPTER padapter,
3743 u8 *hwinfo,
3744 BOOLEAN AutoLoadFail
3745 )
3746 {
3747 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3748
3749 if (!AutoLoadFail)
3750 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8188F];
3751 else
3752 pHalData->EEPROMVersion = 1;
3753 }
3754
3755 #if 0 /* Do not need for rtl8188f */
3756 void
3757 Hal_EfuseParseVoltage_8188F(
3758 PADAPTER pAdapter,
3759 u8 *hwinfo,
3760 BOOLEAN AutoLoadFail
3761 )
3762 {
3763 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3764
3765 /*_rtw_memcpy(pEEPROM->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8188F], 1); */
3766 RTW_INFO("%s hwinfo[EEPROM_Voltage_ADDR_8188F] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8188F]);
3767 pHalData->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8188F] & 0xf0) >> 4;
3768 RTW_INFO("%s pHalData->adjuseVoltageVal =%x\n", __func__, pHalData->adjuseVoltageVal);
3769 }
3770 #endif
3771
3772 void
Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3773 Hal_EfuseParseChnlPlan_8188F(
3774 PADAPTER padapter,
3775 u8 *hwinfo,
3776 BOOLEAN AutoLoadFail
3777 )
3778 {
3779 hal_com_config_channel_plan(
3780 padapter
3781 , hwinfo ? &hwinfo[EEPROM_COUNTRY_CODE_8188F] : NULL
3782 , hwinfo ? hwinfo[EEPROM_ChannelPlan_8188F] : 0xFF
3783 , padapter->registrypriv.alpha2
3784 , padapter->registrypriv.channel_plan
3785 , AutoLoadFail
3786 );
3787 }
3788
3789 void
Hal_EfuseParseCustomerID_8188F(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3790 Hal_EfuseParseCustomerID_8188F(
3791 PADAPTER padapter,
3792 u8 *hwinfo,
3793 BOOLEAN AutoLoadFail
3794 )
3795 {
3796 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3797
3798 if (!AutoLoadFail)
3799 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8188F];
3800 else
3801 pHalData->EEPROMCustomerID = 0;
3802 }
3803
3804 void
Hal_EfuseParsePowerSavingMode_8188F(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3805 Hal_EfuseParsePowerSavingMode_8188F(
3806 PADAPTER padapter,
3807 u8 *hwinfo,
3808 BOOLEAN AutoLoadFail
3809 )
3810 {
3811 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3812 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
3813 u8 tmpvalue;
3814
3815 if (AutoLoadFail) {
3816 pwrctl->bHWPowerdown = _FALSE;
3817 pwrctl->bSupportRemoteWakeup = _FALSE;
3818 } else {
3819
3820 /* hw power down mode selection , 0:rf-off ; 1:power down */
3821
3822 if (padapter->registrypriv.hwpdn_mode == 2)
3823 pwrctl->bHWPowerdown = (hwinfo[EEPROM_FEATURE_OPTION_8188F] & BIT4);
3824 else
3825 pwrctl->bHWPowerdown = padapter->registrypriv.hwpdn_mode;
3826
3827 /* decide hw if support remote wakeup function */
3828 /* if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume */
3829 #ifdef CONFIG_USB_HCI
3830 pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0_8188FU] & BIT1) ? _TRUE : _FALSE;
3831 #endif /* CONFIG_USB_HCI */
3832
3833 RTW_INFO("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n"
3834 , __FUNCTION__, pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup);
3835
3836 RTW_INFO("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n"
3837 , padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable);
3838
3839 }
3840 }
3841
3842 void
Hal_EfuseParseAntennaDiversity_8188F(PADAPTER pAdapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3843 Hal_EfuseParseAntennaDiversity_8188F(
3844 PADAPTER pAdapter,
3845 u8 *hwinfo,
3846 BOOLEAN AutoLoadFail
3847 )
3848 {
3849 #ifdef CONFIG_ANTENNA_DIVERSITY
3850 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
3851 struct registry_priv *registry_par = &pAdapter->registrypriv;
3852
3853 /* default:rtw_antdiv_cfg, 0:OFF, 1:ON, 2:By EFUSE */
3854 if (registry_par->antdiv_cfg == 2) {
3855 if (0x01 == hwinfo[EEPROM_RF_ANTENNA_OPT_8188F])
3856 pHalData->AntDivCfg = 1;
3857 else
3858 pHalData->AntDivCfg = 0;
3859 } else if (registry_par->antdiv_cfg == 1)
3860 pHalData->AntDivCfg = 1;
3861 else
3862 pHalData->AntDivCfg = 0;
3863
3864 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
3865 /* default:rtw_antdiv_type */
3866 if (registry_par->antdiv_type == 0) {
3867 #if 0
3868 pHalData->TRxAntDivType = hwinfo[EEPROM_RFE_OPTION_8188F];
3869 if (pHalData->TRxAntDivType == 0xFF)
3870 pHalData->TRxAntDivType = S0S1_SW_ANTDIV;
3871 else
3872 RTW_INFO("%s: efuse[0x%x]=0x%02x is unknown type\n",
3873 __func__, EEPROM_RFE_OPTION_8188F, pHalData->TRxAntDivType);
3874 #else
3875 /* 8188F only intrnal switch S0S1 */
3876 pHalData->TRxAntDivType = S0S1_SW_ANTDIV;
3877 #endif
3878 } else {
3879 /* 8188F only intrnal switch S0S1 */
3880 pHalData->TRxAntDivType = S0S1_SW_ANTDIV;
3881 }
3882
3883 RTW_INFO("%s: AntDivCfg=%d, AntDivType=%d\n",
3884 __func__, pHalData->AntDivCfg, pHalData->TRxAntDivType);
3885 #endif
3886 }
3887
3888 void
Hal_EfuseParseXtal_8188F(PADAPTER pAdapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3889 Hal_EfuseParseXtal_8188F(
3890 PADAPTER pAdapter,
3891 u8 *hwinfo,
3892 BOOLEAN AutoLoadFail
3893 )
3894 {
3895 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3896
3897 if (!AutoLoadFail) {
3898 pHalData->crystal_cap = hwinfo[EEPROM_XTAL_8188F];
3899 if (pHalData->crystal_cap == 0xFF)
3900 pHalData->crystal_cap = EEPROM_Default_CrystalCap_8188F; /*what value should 8812 set? */
3901 } else
3902 pHalData->crystal_cap = EEPROM_Default_CrystalCap_8188F;
3903 }
3904
3905
3906 void
Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter,u8 * PROMContent,u8 AutoLoadFail)3907 Hal_EfuseParseThermalMeter_8188F(
3908 PADAPTER padapter,
3909 u8 *PROMContent,
3910 u8 AutoLoadFail
3911 )
3912 {
3913 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
3914
3915 /* */
3916 /* ThermalMeter from EEPROM */
3917 /* */
3918 if (_FALSE == AutoLoadFail)
3919 pHalData->eeprom_thermal_meter = PROMContent[EEPROM_THERMAL_METER_8188F];
3920 else
3921 pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8188F;
3922
3923 if ((pHalData->eeprom_thermal_meter == 0xff) || (_TRUE == AutoLoadFail)) {
3924 pHalData->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;
3925 pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8188F;
3926 }
3927
3928 }
3929
3930
Hal_EfuseParseKFreeData_8188F(PADAPTER Adapter,u8 * PROMContent,BOOLEAN AutoloadFail)3931 void Hal_EfuseParseKFreeData_8188F(
3932 PADAPTER Adapter,
3933 u8 *PROMContent,
3934 BOOLEAN AutoloadFail)
3935 {
3936 #ifdef CONFIG_RF_POWER_TRIM
3937 #define THERMAL_K_MEAN_OFFSET_8188F 5 /* 8188F FT thermal K mean value has +5 offset, it's special case */
3938
3939 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3940 struct kfree_data_t *kfree_data = &pHalData->kfree_data;
3941 u8 pg_pwrtrim = 0xFF, pg_therm = 0xFF;
3942
3943 efuse_OneByteRead(Adapter, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim, _FALSE);
3944 efuse_OneByteRead(Adapter, PPG_THERMAL_OFFSET_8188F ,&pg_therm ,_FALSE);
3945
3946 if (pg_pwrtrim != 0xFF) {
3947 kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]
3948 = KFREE_BB_GAIN_2G_TX_OFFSET(pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK);
3949 kfree_data->flag |= KFREE_FLAG_ON;
3950 }
3951
3952 if (pg_therm != 0xFF) {
3953 kfree_data->thermal
3954 = KFREE_THERMAL_OFFSET(pg_therm & PPG_THERMAL_OFFSET_MASK) - THERMAL_K_MEAN_OFFSET_8188F;
3955 if (GET_PG_KFREE_THERMAL_K_ON_8188F(PROMContent))
3956 kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
3957 }
3958
3959 if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
3960 pHalData->eeprom_thermal_meter -= kfree_data->thermal;
3961
3962 RTW_INFO("kfree Pwr Trim flag:%u\n", kfree_data->flag);
3963 if (kfree_data->flag & KFREE_FLAG_ON)
3964 RTW_INFO("bb_gain:%d\n", kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]);
3965 if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
3966 RTW_INFO("thermal:%d\n", kfree_data->thermal);
3967
3968 #endif /*CONFIG_RF_POWER_TRIM */
3969 }
3970
3971 u8
BWMapping_8188F(PADAPTER Adapter,struct pkt_attrib * pattrib)3972 BWMapping_8188F(
3973 PADAPTER Adapter,
3974 struct pkt_attrib *pattrib
3975 )
3976 {
3977 u8 BWSettingOfDesc = 0;
3978 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
3979
3980 /*RTW_INFO("BWMapping pHalData->current_channel_bw %d, pattrib->bwmode %d\n",pHalData->current_channel_bw,pattrib->bwmode); */
3981
3982 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
3983 if (pattrib->bwmode == CHANNEL_WIDTH_80)
3984 BWSettingOfDesc = 2;
3985 else if (pattrib->bwmode == CHANNEL_WIDTH_40)
3986 BWSettingOfDesc = 1;
3987 else
3988 BWSettingOfDesc = 0;
3989 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
3990 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
3991 BWSettingOfDesc = 1;
3992 else
3993 BWSettingOfDesc = 0;
3994 } else
3995 BWSettingOfDesc = 0;
3996
3997 /*if(pTcb->bBTTxPacket) */
3998 /* BWSettingOfDesc = 0; */
3999
4000 return BWSettingOfDesc;
4001 }
4002
SCMapping_8188F(PADAPTER Adapter,struct pkt_attrib * pattrib)4003 u8 SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib)
4004 {
4005 u8 SCSettingOfDesc = 0;
4006 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
4007
4008 /*RTW_INFO("SCMapping: pHalData->current_channel_bw %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC); */
4009
4010 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
4011 if (pattrib->bwmode == CHANNEL_WIDTH_80)
4012 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4013 else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
4014 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
4015 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
4016 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
4017 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
4018 else
4019 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
4020 } else {
4021 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
4022 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
4023 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
4024 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
4025 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
4026 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
4027 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
4028 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
4029 else
4030 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
4031 }
4032 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
4033 /*RTW_INFO("SCMapping: HT Case: pHalData->current_channel_bw %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur40MhzPrimeSC); */
4034
4035 if (pattrib->bwmode == CHANNEL_WIDTH_40)
4036 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4037 else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
4038 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
4039 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
4040 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
4041 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
4042 else
4043 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4044 }
4045 } else
4046 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4047
4048 return SCSettingOfDesc;
4049 }
4050
fill_txdesc_force_bmc_camid(struct pkt_attrib * pattrib,u8 * ptxdesc)4051 void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
4052 {
4053 if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
4054 && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
4055
4056 SET_TX_DESC_EN_DESC_ID_8188F(ptxdesc, 1);
4057 SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->bmc_camid);
4058 }
4059 }
4060
fill_txdesc_sectype(struct pkt_attrib * pattrib)4061 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
4062 {
4063 u8 sectype = 0;
4064 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
4065 switch (pattrib->encrypt) {
4066 /* SEC_TYPE */
4067 case _WEP40_:
4068 case _WEP104_:
4069 case _TKIP_:
4070 case _TKIP_WTMIC_:
4071 sectype = 1;
4072 break;
4073
4074 #ifdef CONFIG_WAPI_SUPPORT
4075 case _SMS4_:
4076 sectype = 2;
4077 break;
4078 #endif
4079 case _AES_:
4080 sectype = 3;
4081 break;
4082
4083 case _NO_PRIVACY_:
4084 default:
4085 break;
4086 }
4087 }
4088 return sectype;
4089 }
4090
fill_txdesc_vcs_8188f(PADAPTER padapter,struct pkt_attrib * pattrib,u8 * ptxdesc)4091 static void fill_txdesc_vcs_8188f(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
4092 {
4093 /*RTW_INFO("cvs_mode=%d\n", pattrib->vcs_mode); */
4094
4095 SET_TX_DESC_HW_RTS_ENABLE_8188F(ptxdesc, 0);
4096
4097 switch (pattrib->vcs_mode) {
4098 case RTS_CTS:
4099 SET_TX_DESC_RTS_ENABLE_8188F(ptxdesc, 1);
4100 break;
4101 case CTS_TO_SELF:
4102 SET_TX_DESC_CTS2SELF_8188F(ptxdesc, 1);
4103 break;
4104 case NONE_VCS:
4105 default:
4106 break;
4107 }
4108
4109 #if 1 /* TODO: */
4110 /* Protection mode related */
4111 if (pattrib->vcs_mode) {
4112 /* SET_TX_DESC_CCA_RTS_8188F(ptxdesc, pTcb->RTSCCA); */
4113 SET_TX_DESC_RTS_RATE_8188F(ptxdesc, 8); /*TODO: Hardcode?, RTS Rate=24M (8) */
4114 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF); /* TODO: PROTECTION_MODE ?? */
4115
4116 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
4117 SET_TX_DESC_RTS_SHORT_8188F(ptxdesc, 1);
4118
4119 /* Set RTS BW */
4120 if (pattrib->ht_en)
4121 SET_TX_DESC_RTS_SC_8188F(ptxdesc, SCMapping_8188F(padapter, pattrib));
4122 }
4123 #endif
4124 }
4125
fill_txdesc_phy_8188f(PADAPTER padapter,struct pkt_attrib * pattrib,u8 * ptxdesc)4126 static void fill_txdesc_phy_8188f(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
4127 {
4128 /*RTW_INFO("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */
4129
4130 if (pattrib->ht_en) {
4131 SET_TX_DESC_DATA_BW_8188F(ptxdesc, BWMapping_8188F(padapter, pattrib));
4132 SET_TX_DESC_DATA_SC_8188F(ptxdesc, SCMapping_8188F(padapter, pattrib));
4133 }
4134 }
4135
rtl8188f_fill_default_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)4136 static void rtl8188f_fill_default_txdesc(
4137 struct xmit_frame *pxmitframe,
4138 u8 *pbuf)
4139 {
4140 PADAPTER padapter;
4141 HAL_DATA_TYPE *pHalData;
4142 struct mlme_ext_priv *pmlmeext;
4143 struct mlme_ext_info *pmlmeinfo;
4144 struct pkt_attrib *pattrib;
4145 s32 bmcst;
4146
4147 _rtw_memset(pbuf, 0, TXDESC_SIZE);
4148
4149 padapter = pxmitframe->padapter;
4150 pHalData = GET_HAL_DATA(padapter);
4151 pmlmeext = &padapter->mlmeextpriv;
4152 pmlmeinfo = &(pmlmeext->mlmext_info);
4153
4154 pattrib = &pxmitframe->attrib;
4155 bmcst = IS_MCAST(pattrib->ra);
4156
4157 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
4158 u8 drv_userate = 0;
4159
4160 SET_TX_DESC_MACID_8188F(pbuf, pattrib->mac_id);
4161 SET_TX_DESC_RATE_ID_8188F(pbuf, pattrib->raid);
4162 SET_TX_DESC_QUEUE_SEL_8188F(pbuf, pattrib->qsel);
4163 SET_TX_DESC_SEQ_8188F(pbuf, pattrib->seqnum);
4164
4165 SET_TX_DESC_SEC_TYPE_8188F(pbuf, fill_txdesc_sectype(pattrib));
4166
4167 if (bmcst)
4168 fill_txdesc_force_bmc_camid(pattrib, pbuf);
4169
4170 fill_txdesc_vcs_8188f(padapter, pattrib, pbuf);
4171
4172 #ifdef CONFIG_P2P
4173 if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
4174 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
4175 drv_userate = 1;
4176 }
4177 #endif
4178
4179 if ((pattrib->ether_type != 0x888e) &&
4180 (pattrib->ether_type != 0x0806) &&
4181 (pattrib->ether_type != 0x88B4) &&
4182 (pattrib->dhcp_pkt != 1) &&
4183 (drv_userate != 1)
4184 #ifdef CONFIG_AUTO_AP_MODE
4185 && (pattrib->pctrl != _TRUE)
4186 #endif
4187 ) {
4188 /* Non EAP & ARP & DHCP type data packet */
4189
4190 if (pattrib->ampdu_en == _TRUE) {
4191 SET_TX_DESC_AGG_ENABLE_8188F(pbuf, 1);
4192 SET_TX_DESC_MAX_AGG_NUM_8188F(pbuf, 0x1F);
4193 SET_TX_DESC_AMPDU_DENSITY_8188F(pbuf, pattrib->ampdu_spacing);
4194 } else
4195 SET_TX_DESC_AGG_BREAK_8188F(pbuf, 1);
4196
4197 fill_txdesc_phy_8188f(padapter, pattrib, pbuf);
4198
4199 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(pbuf, 0x1F);
4200
4201 if (pHalData->fw_ractrl == _FALSE) {
4202 SET_TX_DESC_USE_RATE_8188F(pbuf, 1);
4203
4204 if (pHalData->INIDATA_RATE[pattrib->mac_id] & BIT(7))
4205 SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1);
4206
4207 SET_TX_DESC_TX_RATE_8188F(pbuf, pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F);
4208 }
4209 if (bmcst) {
4210 SET_TX_DESC_USE_RATE_8188F(pbuf, 1);
4211 SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pattrib->rate));
4212 SET_TX_DESC_DISABLE_FB_8188F(pbuf, 1);
4213 }
4214 /* modify data rate by iwpriv */
4215 if (padapter->fix_rate != 0xFF) {
4216 SET_TX_DESC_USE_RATE_8188F(pbuf, 1);
4217 if (padapter->fix_rate & BIT(7))
4218 SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1);
4219 SET_TX_DESC_TX_RATE_8188F(pbuf, padapter->fix_rate & 0x7F);
4220 if (!padapter->data_fb)
4221 SET_TX_DESC_DISABLE_FB_8188F(pbuf, 1);
4222 }
4223
4224 if (pattrib->ldpc)
4225 SET_TX_DESC_DATA_LDPC_8188F(pbuf, 1);
4226
4227 if (pattrib->stbc)
4228 SET_TX_DESC_DATA_STBC_8188F(pbuf, 1);
4229
4230 #ifdef CONFIG_CMCC_TEST
4231 SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1); /* use cck short premble */
4232 #endif
4233 } else {
4234 /* EAP data packet and ARP packet. */
4235 /* Use the 1M data rate to send the EAP/ARP packet. */
4236 /* This will maybe make the handshake smooth. */
4237
4238 SET_TX_DESC_AGG_BREAK_8188F(pbuf, 1);
4239 SET_TX_DESC_USE_RATE_8188F(pbuf, 1);
4240 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
4241 SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1);
4242 #ifdef CONFIG_IP_R_MONITOR
4243 if((pattrib->ether_type == ETH_P_ARP) &&
4244 (IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)))
4245 SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(IEEE80211_OFDM_RATE_6MB));
4246 else
4247 #endif/*CONFIG_IP_R_MONITOR*/
4248 SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pmlmeext->tx_rate));
4249
4250 RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x SeqNum = %d\n",
4251 FUNC_ADPT_ARG(padapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);
4252 }
4253
4254 #if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4255 SET_TX_DESC_USB_TXAGG_NUM_8188F(pbuf, pxmitframe->agg_num);
4256 #endif
4257
4258 #ifdef CONFIG_TDLS
4259 #ifdef CONFIG_XMIT_ACK
4260 /* CCX-TXRPT ack for xmit mgmt frames. */
4261 if (pxmitframe->ack_report) {
4262 #ifdef DBG_CCX
4263 RTW_INFO("%s set spe_rpt\n", __func__);
4264 #endif
4265 SET_TX_DESC_SPE_RPT_8188F(pbuf, 1);
4266 SET_TX_DESC_SW_DEFINE_8188F(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
4267 }
4268 #endif /* CONFIG_XMIT_ACK */
4269 #endif
4270 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
4271
4272 SET_TX_DESC_MACID_8188F(pbuf, pattrib->mac_id);
4273 SET_TX_DESC_QUEUE_SEL_8188F(pbuf, pattrib->qsel);
4274 SET_TX_DESC_RATE_ID_8188F(pbuf, pattrib->raid);
4275 SET_TX_DESC_SEQ_8188F(pbuf, pattrib->seqnum);
4276 SET_TX_DESC_USE_RATE_8188F(pbuf, 1);
4277
4278 SET_TX_DESC_MBSSID_8188F(pbuf, pattrib->mbssid & 0xF);
4279
4280 SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(pbuf, 1);
4281 if (pattrib->retry_ctrl == _TRUE) {
4282 /* Nothing */
4283 SET_TX_DESC_DATA_RETRY_LIMIT_8188F(pbuf, 6);
4284 } else {
4285 /* Nothing */
4286 SET_TX_DESC_DATA_RETRY_LIMIT_8188F(pbuf, 12);
4287 }
4288
4289 SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pattrib->rate));
4290
4291 #ifdef CONFIG_XMIT_ACK
4292 /* CCX-TXRPT ack for xmit mgmt frames. */
4293 if (pxmitframe->ack_report) {
4294 #ifdef DBG_CCX
4295 RTW_INFO("%s set spe_rpt\n", __func__);
4296 #endif
4297 SET_TX_DESC_SPE_RPT_8188F(pbuf, 1);
4298 SET_TX_DESC_SW_DEFINE_8188F(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
4299 }
4300 #endif /* CONFIG_XMIT_ACK */
4301 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
4302 }
4303 #ifdef CONFIG_MP_INCLUDED
4304 else if (pxmitframe->frame_tag == MP_FRAMETAG) {
4305 fill_txdesc_for_mp(padapter, pbuf);
4306 }
4307 #endif
4308 else {
4309
4310 SET_TX_DESC_MACID_8188F(pbuf, pattrib->mac_id);
4311 SET_TX_DESC_RATE_ID_8188F(pbuf, pattrib->raid);
4312 SET_TX_DESC_QUEUE_SEL_8188F(pbuf, pattrib->qsel);
4313 SET_TX_DESC_SEQ_8188F(pbuf, pattrib->seqnum);
4314 SET_TX_DESC_USE_RATE_8188F(pbuf, 1);
4315 SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pmlmeext->tx_rate));
4316 }
4317
4318 SET_TX_DESC_PKT_SIZE_8188F(pbuf, pattrib->last_txcmdsz);
4319
4320 {
4321 u8 pkt_offset, offset;
4322
4323 pkt_offset = 0;
4324 offset = TXDESC_SIZE;
4325 #ifdef CONFIG_USB_HCI
4326 pkt_offset = pxmitframe->pkt_offset;
4327 offset += (pxmitframe->pkt_offset >> 3);
4328 #endif /* CONFIG_USB_HCI */
4329
4330 #ifdef CONFIG_TX_EARLY_MODE
4331 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
4332 pkt_offset = 1;
4333 offset += EARLY_MODE_INFO_SIZE;
4334 }
4335 #endif /* CONFIG_TX_EARLY_MODE */
4336
4337 SET_TX_DESC_PKT_OFFSET_8188F(pbuf, pkt_offset);
4338 SET_TX_DESC_OFFSET_8188F(pbuf, offset);
4339 }
4340
4341 if (bmcst)
4342 SET_TX_DESC_BMC_8188F(pbuf, 1);
4343
4344 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
4345 /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
4346 /* mgnt frame should be controlled by Hw because Fw will also send null data */
4347 /* which we cannot control when Fw LPS enable. */
4348 /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
4349 /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
4350 /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
4351 /* 2010.06.23. Added by tynli. */
4352 if (!pattrib->qos_en)
4353 SET_TX_DESC_HWSEQ_EN_8188F(pbuf, 1);
4354
4355 #ifdef CONFIG_ANTENNA_DIVERSITY
4356 if (!bmcst && pattrib->psta)
4357 odm_set_tx_ant_by_tx_info(adapter_to_phydm(padapter), pbuf, pattrib->psta->cmn.mac_id);
4358 #endif
4359 }
4360
4361 /*
4362 * Description:
4363 *
4364 * Parameters:
4365 * pxmitframe xmitframe
4366 * pbuf where to fill tx desc
4367 */
rtl8188f_update_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)4368 void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
4369 {
4370 rtl8188f_fill_default_txdesc(pxmitframe, pbuf);
4371
4372 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4373 rtl8188f_cal_txdesc_chksum((struct tx_desc *)pbuf);
4374 #endif
4375 }
4376
hw_var_set_monitor(PADAPTER adapter,u8 variable,u8 * val)4377 static void hw_var_set_monitor(PADAPTER adapter, u8 variable, u8 *val)
4378 {
4379 #ifdef CONFIG_WIFI_MONITOR
4380 u32 tmp_32bit;
4381 struct net_device *ndev = adapter->pnetdev;
4382 struct mon_reg_backup *mon = &GET_HAL_DATA(adapter)->mon_backup;
4383
4384 mon->known_rcr = 1;
4385 rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)& mon->rcr);
4386
4387 /* Receive all type */
4388 tmp_32bit = RCR_AAP | RCR_APP_PHYST_RXFF;
4389
4390 if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
4391 /* Append FCS */
4392 tmp_32bit |= RCR_APPFCS;
4393 }
4394
4395 rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)& tmp_32bit);
4396
4397 /* Receive all data frames */
4398 mon->known_rxfilter = 1;
4399 mon->rxfilter0 = rtw_read16(adapter, REG_RXFLTMAP0_8188F);
4400 mon->rxfilter1 = rtw_read16(adapter, REG_RXFLTMAP1_8188F);
4401 mon->rxfilter2 = rtw_read16(adapter, REG_RXFLTMAP2_8188F);
4402 rtw_write16(adapter, REG_RXFLTMAP0_8188F, 0xFFFF);
4403 rtw_write16(adapter, REG_RXFLTMAP1_8188F, 0xFFFF);
4404 rtw_write16(adapter, REG_RXFLTMAP2_8188F, 0xFFFF);
4405 #endif /* CONFIG_WIFI_MONITOR */
4406 }
4407
hw_var_set_opmode(PADAPTER padapter,u8 variable,u8 * val)4408 static void hw_var_set_opmode(PADAPTER padapter, u8 variable, u8 *val)
4409 {
4410 u8 val8;
4411 u8 mode = *((u8 *)val);
4412 static u8 isMonitor = _FALSE;
4413
4414 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
4415
4416 if (isMonitor == _TRUE) {
4417 #ifdef CONFIG_WIFI_MONITOR
4418 struct mon_reg_backup *backup = &GET_HAL_DATA(padapter)->mon_backup;
4419
4420 if (backup->known_rcr) {
4421 backup->known_rcr = 0;
4422 rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&backup->rcr);
4423 rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
4424 }
4425 if (backup->known_rxfilter) {
4426 backup->known_rxfilter = 0;
4427 rtw_write16(padapter, REG_RXFLTMAP0_8188F, backup->rxfilter0);
4428 rtw_write16(padapter, REG_RXFLTMAP1_8188F, backup->rxfilter1);
4429 rtw_write16(padapter, REG_RXFLTMAP2_8188F, backup->rxfilter2);
4430 }
4431 #endif /* CONFIG_WIFI_MONITOR */
4432 isMonitor = _FALSE;
4433 }
4434
4435 if (mode == _HW_STATE_MONITOR_) {
4436 isMonitor = _TRUE;
4437 /* set net_type */
4438 Set_MSR(padapter, _HW_STATE_NOLINK_);
4439
4440 hw_var_set_monitor(padapter, variable, val);
4441 return;
4442 }
4443 rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
4444
4445 #ifdef CONFIG_CONCURRENT_MODE
4446 if (padapter->hw_port == HW_PORT1) {
4447
4448 /* disable Port1 TSF update */
4449 rtw_iface_disable_tsf_update(padapter);
4450
4451 Set_MSR(padapter, mode);
4452
4453 RTW_INFO("#### %s()-%d hw_port(%d) mode=%d ####\n",
4454 __func__, __LINE__, padapter->hw_port, mode);
4455
4456 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
4457 if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter)) {
4458 StopTxBeacon(padapter);
4459 #ifdef CONFIG_PCI_HCI
4460 UpdateInterruptMask8188FE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
4461 #else /* !CONFIG_PCI_HCI */
4462 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4463
4464 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4465 rtw_write8(padapter, REG_DRVERLYINT, 0x05);/*restore early int time to 5ms */
4466 UpdateInterruptMask8188FU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8188F);
4467 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4468
4469 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4470 UpdateInterruptMask8188FU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F));
4471 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4472
4473 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4474 #endif /* !CONFIG_PCI_HCI */
4475 }
4476
4477 /* disable atim wnd and disable beacon function */
4478 rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_ATIM);
4479 } else if (mode == _HW_STATE_ADHOC_) {
4480 ResumeTxBeacon(padapter);
4481 rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
4482 } else if (mode == _HW_STATE_AP_) {
4483 #ifdef CONFIG_PCI_HCI
4484 UpdateInterruptMask8188FE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
4485 #else /* !CONFIG_PCI_HCI */
4486 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4487
4488 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4489 UpdateInterruptMask8188FU(padapter, _TRUE, IMR_BCNDMAINT0_8188F, 0);
4490 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4491
4492 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4493 UpdateInterruptMask8188FU(padapter, _TRUE, (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F), 0);
4494 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4495
4496 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4497 #endif /* !CONFIG_PCI_HCI */
4498
4499 rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_BCNQ_SUB);
4500
4501 /* enable to rx data frame */
4502 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
4503 /* enable to rx ps-poll */
4504 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
4505
4506 /* Beacon Control related register for first time */
4507 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
4508
4509 /*rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
4510 rtw_write8(padapter, REG_ATIMWND_1, 0x0a); /* 10ms for port1 */
4511
4512 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
4513
4514 /* reset TSF2 */
4515 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1));
4516
4517 /* enable BCN1 Function for if2 */
4518 /* don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) */
4519 rtw_write8(padapter, REG_BCN_CTRL_1, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
4520
4521 /*SW_BCN_SEL - Port1 */
4522 /*rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2)|BIT4); */
4523 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
4524
4525 /* select BCN on port 1 */
4526 rtw_write8(padapter, REG_CCK_CHECK_8188F,
4527 (rtw_read8(padapter, REG_CCK_CHECK_8188F) | BIT_BCN_PORT_SEL));
4528
4529 if (!rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_ASSOC_SUCCESS)) {
4530 val8 = rtw_read8(padapter, REG_BCN_CTRL);
4531 val8 &= ~EN_BCN_FUNCTION;
4532 rtw_write8(padapter, REG_BCN_CTRL, val8);
4533 }
4534
4535 /*BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked */
4536 /*rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1)|BIT(5)); */
4537 /*rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(3)); */
4538
4539 /*dis BCN0 ATIM WND if if1 is station */
4540 rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | DIS_ATIM);
4541
4542 #ifdef CONFIG_TSF_RESET_OFFLOAD
4543 /* Reset TSF for STA+AP concurrent mode */
4544 if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
4545 if (rtw_hal_reset_tsf(padapter, HW_PORT1) == _FAIL)
4546 RTW_INFO("ERROR! %s()-%d: Reset port1 TSF fail\n",
4547 __func__, __LINE__);
4548 }
4549 #endif /* CONFIG_TSF_RESET_OFFLOAD */
4550 }
4551 } else /*else for port0 */
4552 #endif /* CONFIG_CONCURRENT_MODE */
4553 {
4554 #ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
4555 hw_var_set_opmode_mbid(padapter, mode);
4556 #else
4557 /* disable Port0 TSF update */
4558 rtw_iface_disable_tsf_update(padapter);
4559
4560 /* set net_type */
4561 Set_MSR(padapter, mode);
4562 RTW_INFO("#### %s() -%d hw_port(0) mode = %d ####\n", __func__, __LINE__, mode);
4563
4564 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
4565 #ifdef CONFIG_CONCURRENT_MODE
4566 if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter))
4567 /* suspect code indent for conditional statements */
4568 #endif /* CONFIG_CONCURRENT_MODE */
4569 {
4570
4571 StopTxBeacon(padapter);
4572 #ifdef CONFIG_PCI_HCI
4573 UpdateInterruptMask8188FE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
4574 #else /* !CONFIG_PCI_HCI */
4575 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4576 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4577 rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */
4578 UpdateInterruptMask8812AU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8188F);
4579 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4580
4581 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4582 UpdateInterruptMask8812AU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F));
4583 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4584
4585 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4586 #endif /* !CONFIG_PCI_HCI */
4587 }
4588
4589 /* disable atim wnd */
4590 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);
4591 /*rtw_write8(padapter,REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION); */
4592 } else if (mode == _HW_STATE_ADHOC_) {
4593 ResumeTxBeacon(padapter);
4594 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
4595 } else if (mode == _HW_STATE_AP_) {
4596 #ifdef CONFIG_PCI_HCI
4597 UpdateInterruptMask8188FE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
4598 #else /* !CONFIG_PCI_HCI */
4599 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4600 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4601 UpdateInterruptMask8188FU(padapter, _TRUE , IMR_BCNDMAINT0_8188F, 0);
4602 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4603
4604 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4605 UpdateInterruptMask8188FU(padapter, _TRUE , (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F), 0);
4606 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4607
4608 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4609 #endif
4610
4611 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
4612
4613 /*enable to rx data frame */
4614 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
4615 /*enable to rx ps-poll */
4616 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
4617
4618 /*Beacon Control related register for first time */
4619 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
4620
4621 /*rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
4622 rtw_write8(padapter, REG_ATIMWND, 0x0c); /* 12ms */
4623
4624 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
4625
4626 /*reset TSF */
4627 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
4628
4629 /*enable BCN0 Function for if1 */
4630 /*don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
4631 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
4632
4633 /*SW_BCN_SEL - Port0 */
4634 /*rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */
4635 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
4636
4637 /* select BCN on port 0 */
4638 rtw_write8(padapter, REG_CCK_CHECK_8188F,
4639 (rtw_read8(padapter, REG_CCK_CHECK_8188F) & ~BIT_BCN_PORT_SEL));
4640
4641 #ifdef CONFIG_CONCURRENT_MODE
4642 if (!rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_ASSOC_SUCCESS)) {
4643 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
4644 val8 &= ~EN_BCN_FUNCTION;
4645 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
4646 }
4647 #endif /* CONFIG_CONCURRENT_MODE */
4648
4649 /* dis BCN1 ATIM WND if if2 is station */
4650 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
4651 val8 |= DIS_ATIM;
4652 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
4653 #ifdef CONFIG_TSF_RESET_OFFLOAD
4654 /* Reset TSF for STA+AP concurrent mode */
4655 if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
4656 if (rtw_hal_reset_tsf(padapter, HW_PORT0) == _FAIL)
4657 RTW_INFO("ERROR! %s()-%d: Reset port0 TSF fail\n",
4658 __func__, __LINE__);
4659 }
4660 #endif /* CONFIG_TSF_RESET_OFFLOAD */
4661 }
4662 #endif
4663 }
4664 }
4665
CCX_FwC2HTxRpt_8188f(PADAPTER padapter,u8 * pdata,u8 len)4666 void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len)
4667 {
4668 u8 seq_no;
4669
4670 #define GET_8188F_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
4671 #define GET_8188F_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
4672
4673 /*RTW_INFO("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, */
4674 /* *pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */
4675
4676 seq_no = *(pdata + 6);
4677
4678 #ifdef CONFIG_XMIT_ACK
4679 if (GET_8188F_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8188F_C2H_TX_RPT_LIFE_TIME_OVER(pdata))
4680 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
4681 /*
4682 else if(seq_no != padapter->xmitpriv.seq_no) {
4683 RTW_INFO("tx_seq_no=%d, rpt_seq_no=%d\n", padapter->xmitpriv.seq_no, seq_no);
4684 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
4685 }
4686 */
4687 else
4688 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
4689 #endif
4690 }
4691
c2h_handler_8188f(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)4692 static s32 c2h_handler_8188f(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
4693 {
4694 s32 ret = _SUCCESS;
4695
4696 switch (id) {
4697 case C2H_CCX_TX_RPT:
4698 CCX_FwC2HTxRpt_8188f(adapter, payload, plen);
4699 break;
4700 default:
4701 ret = _FAIL;
4702 break;
4703 }
4704 return ret;
4705 }
4706
rtl8188f_set_pll_ref_clk_sel(_adapter * adapter,u8 sel)4707 void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel)
4708 {
4709 u8 value8;
4710
4711 value8 = rtw_read8(adapter, REG_MAC_PLL_CTRL_EXT_8188F);
4712 if ((value8 & 0x0F) != (sel & 0x0F)) {
4713 u16 value16;
4714 u8 ori_bit_wlock_2c;
4715
4716 value16 = rtw_read16(adapter, REG_RSV_CTRL_8188F);
4717 ori_bit_wlock_2c = (value16 & BIT8) ? 1 : 0;
4718 if (ori_bit_wlock_2c) {
4719 value16 &= ~BIT8;
4720 rtw_write16(adapter, REG_RSV_CTRL_8188F, value16);
4721 }
4722
4723 RTW_PRINT("switch pll_ref_clk_sel from 0x%x to 0x%x\n"
4724 , (value8 & 0x0F), (sel & 0x0F));
4725 value8 = (value8 & 0xF0) | (sel & 0x0F);
4726 rtw_write8(adapter, REG_MAC_PLL_CTRL_EXT_8188F, value8);
4727
4728 if (ori_bit_wlock_2c) {
4729 value16 |= BIT8;
4730 rtw_write16(adapter, REG_RSV_CTRL_8188F, value16);
4731 }
4732 }
4733 }
4734
SetHwReg8188F(PADAPTER padapter,u8 variable,u8 * val)4735 u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val)
4736 {
4737 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
4738 u8 ret = _SUCCESS;
4739 u8 val8;
4740 u16 val16;
4741 u32 val32;
4742
4743
4744 switch (variable) {
4745
4746 case HW_VAR_SET_OPMODE:
4747 hw_var_set_opmode(padapter, variable, val);
4748 break;
4749
4750 case HW_VAR_BASIC_RATE:
4751 rtw_var_set_basic_rate(padapter, val);
4752 break;
4753
4754 case HW_VAR_TXPAUSE:
4755 rtw_write8(padapter, REG_TXPAUSE, *val);
4756 break;
4757
4758 case HW_VAR_SLOT_TIME:
4759 rtw_write8(padapter, REG_SLOT, *val);
4760 break;
4761
4762 case HW_VAR_RESP_SIFS:
4763 #ifdef RTW_SIFS_IOT_BY_CORE
4764 /*
4765 * set IOT value here or restore to default value:
4766 * hal_data->init_reg_0x428, init_reg_0x514, init_reg_0x63a, init_reg_0x63c
4767 */
4768 #endif
4769 break;
4770
4771 case HW_VAR_ACK_PREAMBLE: {
4772 u8 regTmp;
4773 u8 bShortPreamble = *val;
4774
4775 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
4776 /*regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */
4777 regTmp = rtw_read8(padapter, REG_WMAC_TRXPTCL_CTL + 2);
4778 if (bShortPreamble) {
4779 regTmp |= BIT(1);/*668[17]*/
4780 } else {
4781 regTmp &= ~BIT(1);
4782 }
4783 rtw_write8(padapter, REG_WMAC_TRXPTCL_CTL + 2, regTmp);
4784 }
4785 break;
4786
4787 case HW_VAR_CAM_INVALID_ALL:
4788 rtw_write32(padapter, REG_CAMCMD, BIT(31) | BIT(30));
4789 break;
4790
4791 case HW_VAR_AC_PARAM_VO:
4792 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
4793 break;
4794
4795 case HW_VAR_AC_PARAM_VI:
4796 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
4797 break;
4798
4799 case HW_VAR_AC_PARAM_BE:
4800 pHalData->ac_param_be = ((u32 *)(val))[0];
4801 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
4802 break;
4803
4804 case HW_VAR_AC_PARAM_BK:
4805 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
4806 break;
4807
4808 case HW_VAR_ACM_CTRL: {
4809 u8 ctrl = *((u8 *)val);
4810 u8 hwctrl = 0;
4811
4812 if (ctrl != 0) {
4813 hwctrl |= AcmHw_HwEn;
4814
4815 if (ctrl & BIT(3)) /* BE */
4816 hwctrl |= AcmHw_BeqEn;
4817
4818 if (ctrl & BIT(2)) /* VI */
4819 hwctrl |= AcmHw_ViqEn;
4820
4821 if (ctrl & BIT(1)) /* VO */
4822 hwctrl |= AcmHw_VoqEn;
4823 }
4824
4825 RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
4826 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
4827 }
4828 break;
4829
4830 #ifdef CONFIG_80211N_HT
4831 case HW_VAR_AMPDU_FACTOR: {
4832 u32 AMPDULen = (*((u8 *)val));
4833
4834 if (AMPDULen < HT_AGG_SIZE_32K)
4835 AMPDULen = (0x2000 << (*((u8 *)val))) - 1;
4836 else
4837 AMPDULen = 0x7fff;
4838
4839 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8188F, AMPDULen);
4840 }
4841 break;
4842 #endif /* CONFIG_80211N_HT */
4843 case HW_VAR_H2C_FW_PWRMODE: {
4844 u8 psmode = *val;
4845
4846 /*if (psmode != PS_MODE_ACTIVE) { */
4847 /* rtl8188f_set_lowpwr_lps_cmd(padapter, _TRUE); */
4848 /*} else { */
4849 /* rtl8188f_set_lowpwr_lps_cmd(padapter, _FALSE); */
4850 /*} */
4851 rtl8188f_set_FwPwrMode_cmd(padapter, psmode);
4852 }
4853 break;
4854 case HW_VAR_H2C_PS_TUNE_PARAM:
4855 rtl8188f_set_FwPsTuneParam_cmd(padapter);
4856 break;
4857
4858 case HW_VAR_H2C_FW_JOINBSSRPT:
4859 rtl8188f_set_FwJoinBssRpt_cmd(padapter, *val);
4860 break;
4861
4862 case HW_VAR_DL_RSVD_PAGE:
4863 #ifdef CONFIG_BT_COEXIST
4864 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
4865 rtl8188f_download_BTCoex_AP_mode_rsvd_page(padapter);
4866 else
4867 #endif /* CONFIG_BT_COEXIST */
4868 {
4869 rtl8188f_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
4870 }
4871 break;
4872
4873 #ifdef CONFIG_P2P
4874 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
4875 rtl8188f_set_p2p_ps_offload_cmd(padapter, *val);
4876 break;
4877 #endif /*CONFIG_P2P */
4878
4879 case HW_VAR_EFUSE_USAGE:
4880 pHalData->EfuseUsedPercentage = *val;
4881 break;
4882
4883 case HW_VAR_EFUSE_BYTES:
4884 pHalData->EfuseUsedBytes = *((u16 *)val);
4885 break;
4886
4887 case HW_VAR_EFUSE_BT_USAGE:
4888 #ifdef HAL_EFUSE_MEMORY
4889 pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
4890 #endif
4891 break;
4892
4893 case HW_VAR_EFUSE_BT_BYTES:
4894 #ifdef HAL_EFUSE_MEMORY
4895 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
4896 #else
4897 BTEfuseUsedBytes = *((u16 *)val);
4898 #endif
4899 break;
4900
4901 case HW_VAR_FIFO_CLEARN_UP: {
4902 #define RW_RELEASE_EN BIT(18)
4903 #define RXDMA_IDLE BIT(17)
4904
4905 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
4906 u8 trycnt = 100;
4907
4908 /* pause tx */
4909 rtw_write8(padapter, REG_TXPAUSE, 0xff);
4910
4911 /* keep sn */
4912 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
4913
4914 if (pwrpriv->bkeepfwalive != _TRUE) {
4915 /* RX DMA stop */
4916 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4917 val32 |= RW_RELEASE_EN;
4918 rtw_write32(padapter, REG_RXPKT_NUM, val32);
4919 do {
4920 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4921 val32 &= RXDMA_IDLE;
4922 if (val32)
4923 break;
4924
4925 RTW_INFO("%s: [HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", __func__, val32, trycnt);
4926 rtw_yield_os();
4927 } while (--trycnt);
4928 if (trycnt == 0)
4929 RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
4930
4931 /* RQPN Load 0 */
4932 rtw_write16(padapter, REG_RQPN_NPQ, 0);
4933 rtw_write32(padapter, REG_RQPN, 0x80000000);
4934 rtw_mdelay_os(2);
4935 }
4936 }
4937 break;
4938
4939 case HW_VAR_RESTORE_HW_SEQ:
4940 /* restore Sequence No. */
4941 rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
4942 break;
4943
4944 #ifdef CONFIG_CONCURRENT_MODE
4945 case HW_VAR_CHECK_TXBUF: {
4946 u32 i;
4947 u8 RetryLimit = 0x01;
4948 u32 reg_200, reg_204;
4949
4950 val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
4951 rtw_write16(padapter, REG_RETRY_LIMIT, val16);
4952
4953 for (i = 0; i < 200; i++) { /* polling 200x10=2000 msec */
4954 reg_200 = rtw_read32(padapter, 0x200);
4955 reg_204 = rtw_read32(padapter, 0x204);
4956 if (reg_200 != reg_204) {
4957 /*RTW_INFO("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(padapter, 0x204), rtw_read32(padapter, 0x200), i); */
4958 rtw_msleep_os(10);
4959 } else {
4960 RTW_INFO("[HW_VAR_CHECK_TXBUF] no packet in tx packet buffer (%d)\n", i);
4961 break;
4962 }
4963 }
4964
4965 if (reg_200 != reg_204)
4966 RTW_INFO("packets in tx buffer - 0x204=%x, 0x200=%x\n", reg_204, reg_200);
4967
4968 RetryLimit = RL_VAL_STA;
4969 val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
4970 rtw_write16(padapter, REG_RETRY_LIMIT, val16);
4971 }
4972 break;
4973 #endif /* CONFIG_CONCURRENT_MODE */
4974
4975 case HW_VAR_NAV_UPPER: {
4976 u32 usNavUpper = *((u32 *)val);
4977
4978 if (usNavUpper > HAL_NAV_UPPER_UNIT_8188F * 0xFF) {
4979 break;
4980 }
4981
4982 /* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT_8188F - 1) / HAL_NAV_UPPER_UNIT_8188F) */
4983 /* is getting the upper integer. */
4984 usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8188F - 1) / HAL_NAV_UPPER_UNIT_8188F;
4985 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
4986 }
4987 break;
4988
4989 case HW_VAR_BCN_VALID:
4990 #ifdef CONFIG_CONCURRENT_MODE
4991 if (padapter->hw_port == HW_PORT1) {
4992 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2);
4993 val8 |= BIT(0);
4994 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8);
4995 } else
4996 #endif /* CONFIG_CONCURRENT_MODE */
4997 {
4998 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
4999 val8 = rtw_read8(padapter, REG_TDECTRL + 2);
5000 val8 |= BIT(0);
5001 rtw_write8(padapter, REG_TDECTRL + 2, val8);
5002 }
5003 break;
5004
5005 case HW_VAR_DL_BCN_SEL:
5006 #ifdef CONFIG_CONCURRENT_MODE
5007 if (padapter->hw_port == HW_PORT1) {
5008 /* SW_BCN_SEL - Port1 */
5009 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2);
5010 val8 |= BIT(4);
5011 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8);
5012 } else
5013 #endif /* CONFIG_CONCURRENT_MODE */
5014 {
5015 /* SW_BCN_SEL - Port0 */
5016 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2);
5017 val8 &= ~BIT(4);
5018 rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8);
5019 }
5020 break;
5021
5022 #ifdef CONFIG_GPIO_WAKEUP
5023 case HW_SET_GPIO_WL_CTRL: {
5024 u8 enable = *val;
5025 u8 value = rtw_read8(padapter, 0x4e);
5026
5027 if (enable && (value & BIT(6))) {
5028 value &= ~BIT(6);
5029 rtw_write8(padapter, 0x4e, value);
5030 } else if (enable == _FALSE) {
5031 value |= BIT(6);
5032 rtw_write8(padapter, 0x4e, value);
5033 }
5034 RTW_INFO("%s: set WL control, 0x4E=0x%02X\n",
5035 __func__, rtw_read8(padapter, 0x4e));
5036 }
5037 break;
5038 #endif
5039 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
5040 case HW_VAR_TDLS_BCN_EARLY_C2H_RPT:
5041 rtl8188f_set_BcnEarly_C2H_Rpt_cmd(padapter, *val);
5042 break;
5043 #endif
5044 default:
5045 ret = SetHwReg(padapter, variable, val);
5046 break;
5047 }
5048
5049 return ret;
5050 }
5051
5052 #ifdef CONFIG_PROC_DEBUG
5053 struct qinfo_8188f {
5054 u32 head:8;
5055 u32 pkt_num:7;
5056 u32 tail:8;
5057 u32 ac:2;
5058 u32 macid:7;
5059 };
5060
5061 struct bcn_qinfo_8188f {
5062 u16 head:8;
5063 u16 pkt_num:8;
5064 };
5065
dump_qinfo_8188f(void * sel,struct qinfo_8188f * info,const char * tag)5066 void dump_qinfo_8188f(void *sel, struct qinfo_8188f *info, const char *tag)
5067 {
5068 /*if (info->pkt_num) */
5069 RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n"
5070 , tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac
5071 );
5072 }
5073
dump_bcn_qinfo_8188f(void * sel,struct bcn_qinfo_8188f * info,const char * tag)5074 void dump_bcn_qinfo_8188f(void *sel, struct bcn_qinfo_8188f *info, const char *tag)
5075 {
5076 /*if (info->pkt_num) */
5077 RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n"
5078 , tag ? tag : "", info->head, info->pkt_num
5079 );
5080 }
5081
dump_mac_qinfo_8188f(void * sel,_adapter * adapter)5082 void dump_mac_qinfo_8188f(void *sel, _adapter *adapter)
5083 {
5084 u32 q0_info;
5085 u32 q1_info;
5086 u32 q2_info;
5087 u32 q3_info;
5088 u32 q4_info;
5089 u32 q5_info;
5090 u32 q6_info;
5091 u32 q7_info;
5092 u32 mg_q_info;
5093 u32 hi_q_info;
5094 u16 bcn_q_info;
5095
5096 q0_info = rtw_read32(adapter, REG_Q0_INFO);
5097 q1_info = rtw_read32(adapter, REG_Q1_INFO);
5098 q2_info = rtw_read32(adapter, REG_Q2_INFO);
5099 q3_info = rtw_read32(adapter, REG_Q3_INFO);
5100 q4_info = rtw_read32(adapter, REG_Q4_INFO);
5101 q5_info = rtw_read32(adapter, REG_Q5_INFO);
5102 q6_info = rtw_read32(adapter, REG_Q6_INFO);
5103 q7_info = rtw_read32(adapter, REG_Q7_INFO);
5104 mg_q_info = rtw_read32(adapter, REG_MGQ_INFO);
5105 hi_q_info = rtw_read32(adapter, REG_HGQ_INFO);
5106 bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO);
5107
5108 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q0_info, "Q0 ");
5109 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q1_info, "Q1 ");
5110 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q2_info, "Q2 ");
5111 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q3_info, "Q3 ");
5112 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q4_info, "Q4 ");
5113 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q5_info, "Q5 ");
5114 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q6_info, "Q6 ");
5115 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q7_info, "Q7 ");
5116 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&mg_q_info, "MG ");
5117 dump_qinfo_8188f(sel, (struct qinfo_8188f *)&hi_q_info, "HI ");
5118 dump_bcn_qinfo_8188f(sel, (struct bcn_qinfo_8188f *)&bcn_q_info, "BCN ");
5119 }
5120
dump_mac_txfifo_8188f(void * sel,_adapter * adapter)5121 static void dump_mac_txfifo_8188f(void *sel, _adapter *adapter)
5122 {
5123 u32 rqpn, rqpn_npq;
5124 u32 hpq, lpq, npq, epq, pubq;
5125
5126 rqpn = rtw_read32(adapter, REG_FIFOPAGE);
5127 rqpn_npq = rtw_read32(adapter, REG_RQPN_NPQ);
5128
5129 hpq = (rqpn & 0xFF);
5130 lpq = ((rqpn & 0xFF00)>>8);
5131 pubq = ((rqpn & 0xFF0000)>>16);
5132 npq = ((rqpn_npq & 0xFF00)>>8);
5133 epq = ((rqpn_npq & 0xFF000000)>>24);
5134
5135 RTW_PRINT_SEL(sel, "Tx: available page num: ");
5136 if ((hpq == 0xEA) && (hpq == lpq) && (hpq == pubq))
5137 RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
5138 else
5139 RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
5140 , hpq, lpq, npq, epq, pubq);
5141 }
5142 #endif
5143
rtl8188f_read_wmmedca_reg(PADAPTER adapter,u16 * vo_params,u16 * vi_params,u16 * be_params,u16 * bk_params)5144 void rtl8188f_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params)
5145 {
5146 u8 vo_reg_params[4];
5147 u8 vi_reg_params[4];
5148 u8 be_reg_params[4];
5149 u8 bk_reg_params[4];
5150
5151 GetHwReg8188F(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params);
5152 GetHwReg8188F(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params);
5153 GetHwReg8188F(adapter, HW_VAR_AC_PARAM_BE, be_reg_params);
5154 GetHwReg8188F(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params);
5155
5156 vo_params[0] = vo_reg_params[0];
5157 vo_params[1] = vo_reg_params[1] & 0x0F;
5158 vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4;
5159 vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32;
5160
5161 vi_params[0] = vi_reg_params[0];
5162 vi_params[1] = vi_reg_params[1] & 0x0F;
5163 vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4;
5164 vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32;
5165
5166 be_params[0] = be_reg_params[0];
5167 be_params[1] = be_reg_params[1] & 0x0F;
5168 be_params[2] = (be_reg_params[1] & 0xF0) >> 4;
5169 be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32;
5170
5171 bk_params[0] = bk_reg_params[0];
5172 bk_params[1] = bk_reg_params[1] & 0x0F;
5173 bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4;
5174 bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32;
5175
5176 vo_params[1] = (1 << vo_params[1]) - 1;
5177 vo_params[2] = (1 << vo_params[2]) - 1;
5178 vi_params[1] = (1 << vi_params[1]) - 1;
5179 vi_params[2] = (1 << vi_params[2]) - 1;
5180 be_params[1] = (1 << be_params[1]) - 1;
5181 be_params[2] = (1 << be_params[2]) - 1;
5182 bk_params[1] = (1 << bk_params[1]) - 1;
5183 bk_params[2] = (1 << bk_params[2]) - 1;
5184 }
5185
GetHwReg8188F(PADAPTER padapter,u8 variable,u8 * val)5186 void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val)
5187 {
5188 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
5189 u8 val8;
5190 u16 val16;
5191 u32 val32;
5192
5193
5194 switch (variable) {
5195 case HW_VAR_TXPAUSE:
5196 *val = rtw_read8(padapter, REG_TXPAUSE);
5197 break;
5198
5199 case HW_VAR_BCN_VALID:
5200 #ifdef CONFIG_CONCURRENT_MODE
5201 if (padapter->hw_port == HW_PORT1) {
5202 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2);
5203 *val = (BIT(0) & val8) ? _TRUE : _FALSE;
5204 } else
5205 #endif
5206 {
5207 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
5208 val8 = rtw_read8(padapter, REG_TDECTRL + 2);
5209 *val = (BIT(0) & val8) ? _TRUE : _FALSE;
5210 }
5211 break;
5212
5213 case HW_VAR_AC_PARAM_VO:
5214 val32 = rtw_read32(padapter, REG_EDCA_VO_PARAM);
5215 val[0] = val32 & 0xFF;
5216 val[1] = (val32 >> 8) & 0xFF;
5217 val[2] = (val32 >> 16) & 0xFF;
5218 val[3] = (val32 >> 24) & 0x07;
5219 break;
5220
5221 case HW_VAR_AC_PARAM_VI:
5222 val32 = rtw_read32(padapter, REG_EDCA_VI_PARAM);
5223 val[0] = val32 & 0xFF;
5224 val[1] = (val32 >> 8) & 0xFF;
5225 val[2] = (val32 >> 16) & 0xFF;
5226 val[3] = (val32 >> 24) & 0x07;
5227 break;
5228
5229 case HW_VAR_AC_PARAM_BE:
5230 val32 = rtw_read32(padapter, REG_EDCA_BE_PARAM);
5231 val[0] = val32 & 0xFF;
5232 val[1] = (val32 >> 8) & 0xFF;
5233 val[2] = (val32 >> 16) & 0xFF;
5234 val[3] = (val32 >> 24) & 0x07;
5235 break;
5236
5237 case HW_VAR_AC_PARAM_BK:
5238 val32 = rtw_read32(padapter, REG_EDCA_BK_PARAM);
5239 val[0] = val32 & 0xFF;
5240 val[1] = (val32 >> 8) & 0xFF;
5241 val[2] = (val32 >> 16) & 0xFF;
5242 val[3] = (val32 >> 24) & 0x07;
5243 break;
5244
5245 case HW_VAR_EFUSE_USAGE:
5246 *val = pHalData->EfuseUsedPercentage;
5247 break;
5248
5249 case HW_VAR_EFUSE_BYTES:
5250 *((u16 *)val) = pHalData->EfuseUsedBytes;
5251 break;
5252
5253 case HW_VAR_EFUSE_BT_USAGE:
5254 #ifdef HAL_EFUSE_MEMORY
5255 *val = pHalData->EfuseHal.BTEfuseUsedPercentage;
5256 #endif
5257 break;
5258
5259 case HW_VAR_EFUSE_BT_BYTES:
5260 #ifdef HAL_EFUSE_MEMORY
5261 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
5262 #else
5263 *((u16 *)val) = BTEfuseUsedBytes;
5264 #endif
5265 break;
5266
5267 case HW_VAR_CHK_HI_QUEUE_EMPTY:
5268 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
5269 *val = (val16 & BIT(10)) ? _TRUE : _FALSE;
5270 break;
5271 case HW_VAR_CHK_MGQ_CPU_EMPTY:
5272 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
5273 *val = (val16 & BIT(8)) ? _TRUE : _FALSE;
5274 break;
5275 #ifdef CONFIG_WOWLAN
5276 case HW_VAR_RPWM_TOG:
5277 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1) & BIT7;
5278 break;
5279 case HW_VAR_WAKEUP_REASON:
5280 *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
5281 if (*val == 0xEA)
5282 *val = 0;
5283 break;
5284 case HW_VAR_SYS_CLKR:
5285 *val = rtw_read8(padapter, REG_SYS_CLKR);
5286 break;
5287 #endif
5288 #ifdef CONFIG_PROC_DEBUG
5289 case HW_VAR_DUMP_MAC_QUEUE_INFO:
5290 dump_mac_qinfo_8188f(val, padapter);
5291 break;
5292 case HW_VAR_DUMP_MAC_TXFIFO:
5293 dump_mac_txfifo_8188f(val, padapter);
5294 break;
5295 #endif
5296 default:
5297 GetHwReg(padapter, variable, val);
5298 break;
5299 }
5300 }
5301
5302 /*
5303 * Description:
5304 * Change default setting of specified variable.
5305 */
SetHalDefVar8188F(PADAPTER padapter,HAL_DEF_VARIABLE variable,void * pval)5306 u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
5307 {
5308 PHAL_DATA_TYPE pHalData;
5309 u8 bResult;
5310
5311
5312 pHalData = GET_HAL_DATA(padapter);
5313 bResult = _SUCCESS;
5314
5315 switch (variable) {
5316 default:
5317 bResult = SetHalDefVar(padapter, variable, pval);
5318 break;
5319 }
5320
5321 return bResult;
5322 }
5323
hal_ra_info_dump(_adapter * padapter,void * sel)5324 void hal_ra_info_dump(_adapter *padapter , void *sel)
5325 {
5326 int i;
5327 u8 mac_id;
5328 u32 cmd;
5329 u32 ra_info1, ra_info2, bw_set;
5330 u32 rate_mask1, rate_mask2;
5331 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
5332 HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter);
5333 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
5334 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
5335
5336 for (i = 0; i < macid_ctl->num; i++) {
5337
5338 if (rtw_macid_is_used(macid_ctl, i) && !rtw_macid_is_bmc(macid_ctl, i)) {
5339
5340 mac_id = (u8) i;
5341 _RTW_PRINT_SEL(sel , "============ RA status check Mac_id:%d ===================\n", mac_id);
5342
5343 cmd = 0x40000100 | mac_id;
5344 rtw_write32(padapter, REG_HMEBOX_DBG_2_8188F, cmd);
5345 rtw_msleep_os(10);
5346 ra_info1 = rtw_read32(padapter, 0x2F0);
5347 curr_tx_sgi = rtw_get_current_tx_sgi(padapter, macid_ctl->sta[mac_id]);
5348 curr_tx_rate = rtw_get_current_tx_rate(padapter, macid_ctl->sta[mac_id]);
5349
5350 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>cur_tx_rate= %s,cur_sgi:%d\n" , ra_info1 , HDATA_RATE(curr_tx_rate), curr_tx_sgi);
5351 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => PWRSTS = 0x%02x\n", ra_info1, (ra_info1 >> 8) & 0x07);
5352
5353 cmd = 0x40000400 | mac_id;
5354 rtw_write32(padapter, REG_HMEBOX_DBG_2_8188F, cmd);
5355 rtw_msleep_os(10);
5356 ra_info1 = rtw_read32(padapter, 0x2F0);
5357 ra_info2 = rtw_read32(padapter, 0x2F4);
5358 rate_mask1 = rtw_read32(padapter, 0x2F8);
5359 rate_mask2 = rtw_read32(padapter, 0x2FC);
5360 hight_rate = ra_info2 & 0xFF;
5361 lowest_rate = (ra_info2 >> 8) & 0xFF;
5362 bw_set = (ra_info1 >> 8) & 0xFF;
5363
5364 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => VHT_EN=0x%02x, ", ra_info1, (ra_info1 >> 24) & 0xFF);
5365
5366 switch (bw_set) {
5367
5368 case CHANNEL_WIDTH_20:
5369 _RTW_PRINT_SEL(sel , "BW_setting=20M\n");
5370 break;
5371
5372 case CHANNEL_WIDTH_40:
5373 _RTW_PRINT_SEL(sel , "BW_setting=40M\n");
5374 break;
5375
5376 case CHANNEL_WIDTH_80:
5377 _RTW_PRINT_SEL(sel , "BW_setting=80M\n");
5378 break;
5379
5380 case CHANNEL_WIDTH_160:
5381 _RTW_PRINT_SEL(sel , "BW_setting=160M\n");
5382 break;
5383
5384 default:
5385 _RTW_PRINT_SEL(sel , "BW_setting=0x%02x\n", bw_set);
5386 break;
5387
5388 }
5389
5390 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>RSSI=%d, DISRA=0x%02x\n",
5391 ra_info1,
5392 ra_info1 & 0xFF,
5393 (ra_info1 >> 16) & 0xFF);
5394
5395 _RTW_PRINT_SEL(sel , "[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n",
5396 ra_info2,
5397 HDATA_RATE(hight_rate),
5398 HDATA_RATE(lowest_rate),
5399 (ra_info2 >> 16) & 0xFF,
5400 (ra_info2 >> 24) & 0xFF);
5401
5402 _RTW_PRINT_SEL(sel , "rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1);
5403
5404
5405 }
5406 }
5407 }
5408
5409 /*
5410 * Description:
5411 * Query setting of specified variable.
5412 */
GetHalDefVar8188F(PADAPTER padapter,HAL_DEF_VARIABLE variable,void * pval)5413 u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
5414 {
5415 PHAL_DATA_TYPE pHalData;
5416 u8 bResult;
5417
5418
5419 pHalData = GET_HAL_DATA(padapter);
5420 bResult = _SUCCESS;
5421
5422 switch (variable) {
5423 case HAL_DEF_MAX_RECVBUF_SZ:
5424 *((u32 *)pval) = MAX_RECVBUF_SZ;
5425 break;
5426
5427 case HAL_DEF_RX_PACKET_OFFSET:
5428 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ * 8;
5429 break;
5430
5431 case HW_VAR_MAX_RX_AMPDU_FACTOR:
5432 /* Stanley@BB.SD3 suggests 16K can get stable performance */
5433 /* The experiment was done on SDIO interface */
5434 /* coding by Lucas@20130730 */
5435 *(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;
5436 break;
5437 case HW_VAR_BEST_AMPDU_DENSITY:
5438 *((u32 *)pval) = AMPDU_DENSITY_VALUE_7;
5439 break;
5440 case HAL_DEF_TX_LDPC:
5441 case HAL_DEF_RX_LDPC:
5442 *((u8 *)pval) = _FALSE;
5443 break;
5444 case HAL_DEF_RX_STBC:
5445 *((u8 *)pval) = 1;
5446 break;
5447 case HAL_DEF_EXPLICIT_BEAMFORMER:
5448 case HAL_DEF_EXPLICIT_BEAMFORMEE:
5449 *((u8 *)pval) = _FALSE;
5450 break;
5451
5452 case HW_DEF_RA_INFO_DUMP:
5453 hal_ra_info_dump(padapter, pval);
5454 break;
5455
5456 case HAL_DEF_TX_PAGE_BOUNDARY:
5457 if (!padapter->registrypriv.wifi_spec)
5458 *(u8 *)pval = TX_PAGE_BOUNDARY_8188F;
5459 else
5460 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F;
5461 break;
5462 case HAL_DEF_TX_PAGE_SIZE:
5463 *((u32 *)pval) = PAGE_SIZE_128;
5464 break;
5465 case HAL_DEF_RX_DMA_SZ_WOW:
5466 *(u32 *)pval = RX_DMA_SIZE_8188F - RESV_FMWF;
5467 break;
5468 case HAL_DEF_RX_DMA_SZ:
5469 *(u32 *)pval = RX_DMA_BOUNDARY_8188F + 1;
5470 break;
5471 case HAL_DEF_RX_PAGE_SIZE:
5472 *((u32 *)pval) = 8;
5473 break;
5474 default:
5475 bResult = GetHalDefVar(padapter, variable, pval);
5476 break;
5477 }
5478
5479 return bResult;
5480 }
5481
5482 #ifdef CONFIG_WOWLAN
Hal_DetectWoWMode(PADAPTER pAdapter)5483 void Hal_DetectWoWMode(PADAPTER pAdapter)
5484 {
5485 adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE;
5486 RTW_INFO("%s\n", __func__);
5487 }
5488 #endif /*CONFIG_WOWLAN */
5489
rtl8188f_start_thread(_adapter * padapter)5490 void rtl8188f_start_thread(_adapter *padapter)
5491 {
5492 #if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
5493 #ifndef CONFIG_SDIO_TX_TASKLET
5494 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
5495
5496 if (xmitpriv->SdioXmitThread == NULL) {
5497 RTW_INFO(FUNC_ADPT_FMT " start RTWHALXT\n", FUNC_ADPT_ARG(padapter));
5498 xmitpriv->SdioXmitThread = kthread_run(rtl8188fs_xmit_thread, padapter, "RTWHALXT");
5499 if (IS_ERR(xmitpriv->SdioXmitThread)) {
5500 RTW_ERR("%s: start rtl8188fs_xmit_thread FAIL!!\n", __func__);
5501 xmitpriv->SdioXmitThread = NULL;
5502 }
5503 }
5504 #endif
5505 #endif
5506 }
5507
rtl8188f_stop_thread(_adapter * padapter)5508 void rtl8188f_stop_thread(_adapter *padapter)
5509 {
5510 #if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
5511 #ifndef CONFIG_SDIO_TX_TASKLET
5512 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
5513
5514 /* stop xmit_buf_thread */
5515 if (xmitpriv->SdioXmitThread) {
5516 _rtw_up_sema(&xmitpriv->SdioXmitSema);
5517 #ifdef SDIO_FREE_XMIT_BUF_SEMA
5518 rtw_sdio_free_xmitbuf_sema_up(xmitpriv);
5519 rtw_sdio_free_xmitbuf_sema_down(xmitpriv);
5520 #endif
5521 rtw_thread_stop(xmitpriv->SdioXmitThread);
5522 xmitpriv->SdioXmitThread = NULL;
5523 }
5524 #endif
5525 #endif
5526 }
5527
5528 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
5529 extern void check_bt_status_work(void *data);
rtl8188fs_init_checkbthang_workqueue(_adapter * adapter)5530 void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter)
5531 {
5532 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
5533 adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0);
5534 #else
5535 adapter->priv_checkbt_wq = create_workqueue("sdio_wq");
5536 #endif
5537 INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work);
5538 }
5539
rtl8188fs_free_checkbthang_workqueue(_adapter * adapter)5540 void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter)
5541 {
5542 if (adapter->priv_checkbt_wq) {
5543 cancel_delayed_work_sync(&adapter->checkbt_work);
5544 flush_workqueue(adapter->priv_checkbt_wq);
5545 destroy_workqueue(adapter->priv_checkbt_wq);
5546 adapter->priv_checkbt_wq = NULL;
5547 }
5548 }
5549
rtl8188fs_cancle_checkbthang_workqueue(_adapter * adapter)5550 void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter)
5551 {
5552 if (adapter->priv_checkbt_wq)
5553 cancel_delayed_work_sync(&adapter->checkbt_work);
5554 }
5555
rtl8188fs_hal_check_bt_hang(_adapter * adapter)5556 void rtl8188fs_hal_check_bt_hang(_adapter *adapter)
5557 {
5558 if (adapter->priv_checkbt_wq)
5559 queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0);
5560 }
5561 #endif
5562
rtl8188f_set_hal_ops(struct hal_ops * pHalFunc)5563 void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc)
5564 {
5565 pHalFunc->dm_init = &rtl8188f_init_dm_priv;
5566 pHalFunc->dm_deinit = &rtl8188f_deinit_dm_priv;
5567
5568 pHalFunc->read_chip_version = &rtl8188f_read_chip_version;
5569
5570 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8188F;
5571
5572 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8188F;
5573 pHalFunc->set_txpwr_done = rtl8188f_set_txpwr_done;
5574 pHalFunc->set_tx_power_index_handler = PHY_SetTxPowerIndex_8188F;
5575 pHalFunc->get_tx_power_index_handler = hal_com_get_txpwr_idx;
5576
5577 pHalFunc->hal_dm_watchdog = &rtl8188f_HalDmWatchDog;
5578 pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8188f_SetBeaconRelatedRegisters;
5579
5580
5581 pHalFunc->run_thread = &rtl8188f_start_thread;
5582 pHalFunc->cancel_thread = &rtl8188f_stop_thread;
5583
5584 pHalFunc->read_bbreg = &PHY_QueryBBReg_8188F;
5585 pHalFunc->write_bbreg = &PHY_SetBBReg_8188F;
5586 pHalFunc->read_rfreg = &PHY_QueryRFReg_8188F;
5587 pHalFunc->write_rfreg = &PHY_SetRFReg_8188F;
5588
5589 pHalFunc->read_wmmedca_reg = &rtl8188f_read_wmmedca_reg;
5590
5591 /* Efuse related function */
5592 pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch;
5593 pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch;
5594 pHalFunc->ReadEFuse = &Hal_ReadEFuse;
5595 pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition;
5596 pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize;
5597 pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead;
5598 pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite;
5599 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
5600 pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT;
5601
5602 #ifdef DBG_CONFIG_ERROR_DETECT
5603 pHalFunc->sreset_init_value = &sreset_init_value;
5604 pHalFunc->sreset_reset_value = &sreset_reset_value;
5605 pHalFunc->silentreset = &sreset_reset;
5606 pHalFunc->sreset_xmit_status_check = &rtl8188f_sreset_xmit_status_check;
5607 pHalFunc->sreset_linked_status_check = &rtl8188f_sreset_linked_status_check;
5608 pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
5609 pHalFunc->sreset_inprogress = &sreset_inprogress;
5610 #endif
5611 pHalFunc->GetHalODMVarHandler = GetHalODMVar;
5612 pHalFunc->SetHalODMVarHandler = SetHalODMVar;
5613
5614 #ifdef CONFIG_XMIT_THREAD_MODE
5615 pHalFunc->xmit_thread_handler = &hal_xmit_handler;
5616 #endif
5617 pHalFunc->hal_notch_filter = &hal_notch_filter_8188f;
5618
5619 pHalFunc->c2h_handler = c2h_handler_8188f;
5620
5621 pHalFunc->fill_h2c_cmd = &FillH2CCmd8188F;
5622 pHalFunc->fill_fake_txdesc = &rtl8188f_fill_fake_txdesc;
5623 pHalFunc->fw_dl = &rtl8188f_FirmwareDownload;
5624 pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8188F;
5625 }
5626
5627