1 /******************************************************************************
2 *
3 * Copyright(c) 2016 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 /* ************************************************************
16 * Description:
17 *
18 * This file is for 8814A TXBF mechanism
19 *
20 * ************************************************************ */
21
22 #include "mp_precomp.h"
23 #include "../phydm_precomp.h"
24
25 #ifdef PHYDM_BEAMFORMING_SUPPORT
26 #if (RTL8814A_SUPPORT == 1)
27
28 boolean
phydm_beamforming_set_iqgen_8814A(void * dm_void)29 phydm_beamforming_set_iqgen_8814A(void *dm_void)
30 {
31 struct dm_struct *dm = (struct dm_struct *)dm_void;
32 u8 i = 0;
33 u16 counter = 0;
34 u32 rf_mode[4];
35
36 for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
37 odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
38
39 while (1) {
40 counter++;
41 for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
42 odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
43
44 ODM_delay_us(2);
45
46 for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
47 rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);
48
49 if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)
50 break;
51 else if (counter == 100) {
52 PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n");
53 return false;
54 }
55 }
56
57 for (i = RF_PATH_A; i < MAX_RF_PATH; i++) {
58 odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
59 odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/
60 }
61 odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/
62
63 for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
64 odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
65
66 return true;
67 }
68
hal_txbf_8814a_set_ndpa_rate(void * dm_void,u8 BW,u8 rate)69 void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)
70 {
71 struct dm_struct *dm = (struct dm_struct *)dm_void;
72
73 odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);
74 odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);
75 }
76 #if 0
77 #define PHYDM_MEMORY_MAP_BUF_READ 0x8000
78 #define PHYDM_CTRL_INFO_PAGE 0x660
79
80 void
81 phydm_data_rate_8814a(
82 struct dm_struct *dm,
83 u8 mac_id,
84 u32 *data,
85 u8 data_len
86 )
87 {
88 u8 i = 0;
89 u16 x_read_data_addr = 0;
90
91 odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
92 x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/
93
94 if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) {
95 PHYDM_DBG(dm, DBG_TXBF,
96 "x_read_data_addr(0x%x) is not correct!\n",
97 x_read_data_addr);
98 return;
99 }
100
101 /* Read data */
102 for (i = 0; i < data_len; i++)
103 *(data + i) = odm_read_2byte(dm, x_read_data_addr + i);
104 }
105 #endif
106
hal_txbf_8814a_get_tx_rate(void * dm_void)107 void hal_txbf_8814a_get_tx_rate(void *dm_void)
108 {
109 struct dm_struct *dm = (struct dm_struct *)dm_void;
110 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
111 struct _RT_BEAMFORMEE_ENTRY *entry;
112 struct ra_table *ra_tab = &dm->dm_ra_table;
113 struct cmn_sta_info *sta = NULL;
114 u8 data_rate = 0xFF;
115 u8 macid = 0;
116
117 entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
118 macid = (u8)entry->mac_id;
119
120 sta = dm->phydm_sta_info[macid];
121
122 if (is_sta_active(sta)) {
123 data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/
124 beam_info->tx_bf_data_rate = data_rate;
125 }
126
127 PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__,
128 beam_info->tx_bf_data_rate);
129 }
130
hal_txbf_8814a_reset_tx_path(void * dm_void,u8 idx)131 void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)
132 {
133 struct dm_struct *dm = (struct dm_struct *)dm_void;
134 #if DEV_BUS_TYPE == RT_USB_INTERFACE
135 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
136 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
137 u8 nr_index = 0, tx_ss = 0;
138
139 if (idx < BEAMFORMEE_ENTRY_NUM)
140 beamformee_entry = beamforming_info->beamformee_entry[idx];
141 else
142 return;
143
144 if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {
145 nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
146
147 if (*dm->hub_usb_mode == 2) {
148 if (dm->rf_type == RF_4T4R)
149 tx_ss = 0xf;
150 else if (dm->rf_type == RF_3T3R)
151 tx_ss = 0xe;
152 else
153 tx_ss = 0x6;
154 } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
155 tx_ss = 0x6;
156 else
157 tx_ss = 0x6;
158
159 if (tx_ss == 0xf) {
160 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
161 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
162 } else if (tx_ss == 0xe) {
163 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
164 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
165 } else if (tx_ss == 0x6) {
166 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
167 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
168 }
169
170 if (idx == 0) {
171 switch (nr_index) {
172 case 0:
173 break;
174
175 case 1: /*Nsts = 2 BC*/
176 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
177 break;
178
179 case 2: /*Nsts = 3 BCD*/
180 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
181 break;
182
183 default: /*nr>3, same as Case 3*/
184 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
185 break;
186 }
187 } else {
188 switch (nr_index) {
189 case 0:
190 break;
191
192 case 1: /*Nsts = 2 BC*/
193 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
194 break;
195
196 case 2: /*Nsts = 3 BCD*/
197 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
198 break;
199
200 default: /*nr>3, same as Case 3*/
201 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
202 break;
203 }
204 }
205
206 beamforming_info->last_usb_hub = *dm->hub_usb_mode;
207 } else
208 return;
209 #endif
210 }
211
hal_txbf_8814a_get_ntx(void * dm_void)212 u8 hal_txbf_8814a_get_ntx(void *dm_void)
213 {
214 struct dm_struct *dm = (struct dm_struct *)dm_void;
215 u8 ntx = 0, tx_ss = 3;
216
217 #if DEV_BUS_TYPE == RT_USB_INTERFACE
218 tx_ss = *dm->hub_usb_mode;
219 #endif
220 if (tx_ss == 3 || tx_ss == 2) {
221 if (dm->rf_type == RF_4T4R)
222 ntx = 3;
223 else if (dm->rf_type == RF_3T3R)
224 ntx = 2;
225 else
226 ntx = 1;
227 } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
228 ntx = 1;
229 else
230 ntx = 1;
231
232 PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx);
233 return ntx;
234 }
235
hal_txbf_8814a_get_nrx(void * dm_void)236 u8 hal_txbf_8814a_get_nrx(void *dm_void)
237 {
238 struct dm_struct *dm = (struct dm_struct *)dm_void;
239 u8 nrx = 0;
240
241 if (dm->rf_type == RF_4T4R)
242 nrx = 3;
243 else if (dm->rf_type == RF_3T3R)
244 nrx = 2;
245 else if (dm->rf_type == RF_2T2R)
246 nrx = 1;
247 else if (dm->rf_type == RF_2T3R)
248 nrx = 2;
249 else if (dm->rf_type == RF_2T4R)
250 nrx = 3;
251 else if (dm->rf_type == RF_1T1R)
252 nrx = 0;
253 else if (dm->rf_type == RF_1T2R)
254 nrx = 1;
255 else
256 nrx = 0;
257
258 PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx);
259 return nrx;
260 }
261
hal_txbf_8814a_rf_mode(void * dm_void,struct _RT_BEAMFORMING_INFO * beamforming_info,u8 idx)262 void hal_txbf_8814a_rf_mode(void *dm_void,
263 struct _RT_BEAMFORMING_INFO *beamforming_info,
264 u8 idx)
265 {
266 struct dm_struct *dm = (struct dm_struct *)dm_void;
267 u8 nr_index = 0;
268 u8 tx_ss = 3; /*@default use 3 Tx*/
269 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
270
271 if (idx < BEAMFORMEE_ENTRY_NUM)
272 beamformee_entry = beamforming_info->beamformee_entry[idx];
273 else
274 return;
275
276 nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
277
278 if (dm->rf_type == RF_1T1R)
279 return;
280
281 if (beamforming_info->beamformee_su_cnt > 0) {
282 #if DEV_BUS_TYPE == RT_USB_INTERFACE
283 beamforming_info->last_usb_hub = *dm->hub_usb_mode;
284 tx_ss = *dm->hub_usb_mode;
285 #endif
286 if (tx_ss == 3 || tx_ss == 2) {
287 if (dm->rf_type == RF_4T4R)
288 tx_ss = 0xf;
289 else if (dm->rf_type == RF_3T3R)
290 tx_ss = 0xe;
291 else
292 tx_ss = 0x6;
293 } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
294 tx_ss = 0x6;
295 else
296 tx_ss = 0x6;
297
298 if (tx_ss == 0xf) {
299 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
300 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
301 } else if (tx_ss == 0xe) {
302 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
303 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
304 } else if (tx_ss == 0x6) {
305 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
306 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
307 }
308
309 /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
310 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
311 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
312
313 if (idx == 0) {
314 switch (nr_index) {
315 case 0:
316 break;
317
318 case 1: /*Nsts = 2 BC*/
319 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
320 break;
321
322 case 2: /*Nsts = 3 BCD*/
323 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
324 break;
325
326 default: /*nr>3, same as Case 3*/
327 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
328
329 break;
330 }
331 } else {
332 switch (nr_index) {
333 case 0:
334 break;
335
336 case 1: /*Nsts = 2 BC*/
337 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
338 break;
339
340 case 2: /*Nsts = 3 BCD*/
341 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
342 break;
343
344 default: /*nr>3, same as Case 3*/
345 odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
346 break;
347 }
348 }
349 }
350
351 if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {
352 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
353 odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
354 }
355 }
356 #if 0
357 void
358 hal_txbf_8814a_download_ndpa(
359 void *dm_void,
360 u8 idx
361 )
362 {
363 struct dm_struct *dm = (struct dm_struct *)dm_void;
364 u8 u1b_tmp = 0, tmp_reg422 = 0;
365 u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
366 u16 head_page = 0x7FE;
367 boolean is_send_beacon = false;
368 u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
369 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
370 struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
371 void *adapter = dm->adapter;
372
373 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
374 *dm->is_fw_dw_rsvd_page_in_progress = true;
375 #endif
376 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
377
378 phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
379
380 /*Set REG_CR bit 8. DMA beacon by SW.*/
381 u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
382 odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
383
384
385 /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
386 tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2);
387 odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6)));
388
389 if (tmp_reg422 & BIT(6)) {
390 PHYDM_DBG(dm, DBG_TXBF,
391 "%s: There is an adapter is sending beacon.\n",
392 __func__);
393 is_send_beacon = true;
394 }
395
396 /*@0x204[11:0] Beacon Head for TXDMA*/
397 odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
398
399 do {
400 /*@Clear beacon valid check bit.*/
401 bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
402 odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
403
404 /*@download NDPA rsvd page.*/
405 if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
406 beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
407 else
408 beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
409
410 /*@check rsvd page download OK.*/
411 bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
412 count = 0;
413 while (!(bcn_valid_reg & BIT(7)) && count < 20) {
414 count++;
415 ODM_delay_ms(10);
416 bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2);
417 }
418 dl_bcn_count++;
419 } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
420
421 if (!(bcn_valid_reg & BIT(7)))
422 PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
423 __func__);
424
425 /*@0x204[11:0] Beacon Head for TXDMA*/
426 odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
427
428 /*To make sure that if there exists an adapter which would like to send beacon.*/
429 /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
430 /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
431 /*the beacon cannot be sent by HW.*/
432 /*@2010.06.23. Added by tynli.*/
433 if (is_send_beacon)
434 odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
435
436 /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
437 /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
438 u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
439 odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
440
441 p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
442
443 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
444 *dm->is_fw_dw_rsvd_page_in_progress = false;
445 #endif
446 }
447
448 void
449 hal_txbf_8814a_fw_txbf_cmd(
450 void *dm_void
451 )
452 {
453 struct dm_struct *dm = (struct dm_struct *)dm_void;
454 u8 idx, period = 0;
455 u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
456 u8 u1_tx_bf_parm[3] = {0};
457 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
458
459 for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
460 if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
461 if (beam_info->beamformee_entry[idx].is_sound) {
462 PageNum0 = 0xFE;
463 PageNum1 = 0x07;
464 period = (u8)(beam_info->beamformee_entry[idx].sound_period);
465 } else if (PageNum0 == 0xFF) {
466 PageNum0 = 0xFF; /*stop sounding*/
467 PageNum1 = 0x0F;
468 }
469 }
470 }
471
472 u1_tx_bf_parm[0] = PageNum0;
473 u1_tx_bf_parm[1] = PageNum1;
474 u1_tx_bf_parm[2] = period;
475 odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
476
477 PHYDM_DBG(dm, DBG_TXBF,
478 "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__,
479 PageNum0, PageNum1, period);
480 }
481 #endif
hal_txbf_8814a_enter(void * dm_void,u8 bfer_bfee_idx)482 void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
483 {
484 struct dm_struct *dm = (struct dm_struct *)dm_void;
485 u8 i = 0;
486 u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
487 u8 bfee_idx = (bfer_bfee_idx & 0xF);
488 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
489 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
490 struct _RT_BEAMFORMER_ENTRY beamformer_entry;
491 u16 sta_id = 0, csi_param = 0;
492 u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
493
494 PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__,
495 bfer_idx, bfee_idx);
496 odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
497
498 if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
499 beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
500 /*Sounding protocol control*/
501 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);
502
503 /*@MAC address/Partial AID of Beamformer*/
504 if (bfer_idx == 0) {
505 for (i = 0; i < 6; i++)
506 odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
507 } else {
508 for (i = 0; i < 6; i++)
509 odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
510 }
511
512 /*@CSI report parameters of Beamformer*/
513 nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
514 nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
515
516 grouping = 0;
517
518 /*@for ac = 1, for n = 3*/
519 if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
520 codebookinfo = 1;
521 else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
522 codebookinfo = 3;
523
524 coefficientsize = 3;
525
526 csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
527
528 if (bfer_idx == 0)
529 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
530 else
531 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
532 /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
533 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
534 }
535
536 if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
537 beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
538
539 hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);
540
541 if (phydm_acting_determine(dm, phydm_acting_as_ibss))
542 sta_id = beamformee_entry.mac_id;
543 else
544 sta_id = beamformee_entry.p_aid;
545
546 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
547 if (bfee_idx == 0) {
548 odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id);
549 odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
550 } else
551 odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
552
553 /*@CSI report parameters of Beamformee*/
554 if (bfee_idx == 0) {
555 /*@Get BIT24 & BIT25*/
556 u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
557
558 odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
559 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
560 } else
561 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
562
563 phydm_beamforming_notify(dm);
564 }
565 }
566
hal_txbf_8814a_leave(void * dm_void,u8 idx)567 void hal_txbf_8814a_leave(void *dm_void, u8 idx)
568 {
569 struct dm_struct *dm = (struct dm_struct *)dm_void;
570 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
571 struct _RT_BEAMFORMER_ENTRY beamformer_entry;
572 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
573
574 if (idx < BEAMFORMER_ENTRY_NUM) {
575 beamformer_entry = beamforming_info->beamformer_entry[idx];
576 beamformee_entry = beamforming_info->beamformee_entry[idx];
577 } else
578 return;
579
580 /*@Clear P_AID of Beamformee*/
581 /*@Clear MAC address of Beamformer*/
582 /*@Clear Associated Bfmee Sel*/
583
584 if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
585 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);
586 if (idx == 0) {
587 odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
588 odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
589 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
590 } else {
591 odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
592 odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
593 odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
594 }
595 }
596
597 if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
598 hal_txbf_8814a_rf_mode(dm, beamforming_info, idx);
599 if (idx == 0) {
600 odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0);
601 odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
602 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
603 } else {
604 odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
605
606 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
607 }
608 }
609 }
610
hal_txbf_8814a_status(void * dm_void,u8 idx)611 void hal_txbf_8814a_status(void *dm_void, u8 idx)
612 {
613 struct dm_struct *dm = (struct dm_struct *)dm_void;
614 u16 beam_ctrl_val, tmp_val;
615 u32 beam_ctrl_reg;
616 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
617 struct _RT_BEAMFORMEE_ENTRY beamform_entry;
618
619 if (idx < BEAMFORMEE_ENTRY_NUM)
620 beamform_entry = beamforming_info->beamformee_entry[idx];
621 else
622 return;
623
624 if (phydm_acting_determine(dm, phydm_acting_as_ibss))
625 beam_ctrl_val = beamform_entry.mac_id;
626 else
627 beam_ctrl_val = beamform_entry.p_aid;
628
629 PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d",
630 __func__, beamform_entry.beamform_entry_state);
631
632 if (idx == 0)
633 beam_ctrl_reg = REG_TXBF_CTRL_8814A;
634 else {
635 beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
636 beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
637 }
638
639 if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {
640 if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
641 beam_ctrl_val |= BIT(9);
642 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
643 beam_ctrl_val |= (BIT(9) | BIT(10));
644 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
645 beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
646 } else {
647 PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
648 beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
649 }
650
651 odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
652 /*@disable NDP packet use beamforming */
653 tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);
654 odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
655 }
656
hal_txbf_8814a_fw_txbf(void * dm_void,u8 idx)657 void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)
658 {
659 #if 0
660 struct dm_struct *dm = (struct dm_struct *)dm_void;
661 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
662 struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
663
664 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
665
666 if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
667 hal_txbf_8814a_download_ndpa(dm, idx);
668
669 hal_txbf_8814a_fw_txbf_cmd(dm);
670 #endif
671 }
672
673 #endif /* @(RTL8814A_SUPPORT == 1)*/
674
675 #endif
676