1 /******************************************************************************
2 *
3 * Copyright(c) 2016 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 /*************************************************************
16 * Description:
17 *
18 * This file is for 8192E TXBF mechanism
19 *
20 ************************************************************/
21 #include "mp_precomp.h"
22 #include "../phydm_precomp.h"
23
24 #ifdef PHYDM_BEAMFORMING_SUPPORT
25 #if (RTL8192E_SUPPORT == 1)
26
hal_txbf_8192e_set_ndpa_rate(void * dm_void,u8 BW,u8 rate)27 void hal_txbf_8192e_set_ndpa_rate(
28 void *dm_void,
29 u8 BW,
30 u8 rate)
31 {
32 struct dm_struct *dm = (struct dm_struct *)dm_void;
33
34 odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
35 }
36
hal_txbf_8192e_rf_mode(void * dm_void,struct _RT_BEAMFORMING_INFO * beam_info)37 void hal_txbf_8192e_rf_mode(
38 void *dm_void,
39 struct _RT_BEAMFORMING_INFO *beam_info)
40 {
41 struct dm_struct *dm = (struct dm_struct *)dm_void;
42
43 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
44
45 if (dm->rf_type == RF_1T1R)
46 return;
47
48 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
49 odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
50
51 if (beam_info->beamformee_su_cnt > 0) {
52 /*Path_A*/
53 odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
54 odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
55 odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
56 /*Path_B*/
57 odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
58 odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
59 odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
60 } else {
61 /*Path_A*/
62 odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
63 odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
64 odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
65 /*Path_B*/
66 odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
67 odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
68 odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
69 }
70
71 odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
72 odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
73
74 if (beam_info->beamformee_su_cnt > 0) {
75 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
76 odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);
77 } else
78 odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
79 }
80
hal_txbf_8192e_fw_txbf_cmd(void * dm_void)81 void hal_txbf_8192e_fw_txbf_cmd(
82 void *dm_void)
83 {
84 struct dm_struct *dm = (struct dm_struct *)dm_void;
85 u8 idx, period0 = 0, period1 = 0;
86 u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
87 u8 u1_tx_bf_parm[3] = {0};
88 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
89
90 for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
91 if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
92 if (idx == 0) {
93 if (beam_info->beamformee_entry[idx].is_sound)
94 PageNum0 = 0xFE;
95 else
96 PageNum0 = 0xFF; /* stop sounding */
97 period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
98 } else if (idx == 1) {
99 if (beam_info->beamformee_entry[idx].is_sound)
100 PageNum1 = 0xFE;
101 else
102 PageNum1 = 0xFF; /* stop sounding */
103 period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
104 }
105 }
106 }
107
108 u1_tx_bf_parm[0] = PageNum0;
109 u1_tx_bf_parm[1] = PageNum1;
110 u1_tx_bf_parm[2] = (period1 << 4) | period0;
111 odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
112
113 PHYDM_DBG(dm, DBG_TXBF,
114 "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
115 __func__, PageNum0, period0, PageNum1, period1);
116 }
117
hal_txbf_8192e_download_ndpa(void * dm_void,u8 idx)118 void hal_txbf_8192e_download_ndpa(
119 void *dm_void,
120 u8 idx)
121 {
122 struct dm_struct *dm = (struct dm_struct *)dm_void;
123 u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
124 u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
125 boolean is_send_beacon = false;
126 u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
127 /*@default reseved 1 page for the IC type which is undefined.*/
128 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
129 struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
130
131 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
132 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
133 *dm->is_fw_dw_rsvd_page_in_progress = true;
134 #endif
135 if (idx == 0)
136 head_page = 0xFE;
137 else
138 head_page = 0xFE;
139
140 phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
141
142 /*Set REG_CR bit 8. DMA beacon by SW.*/
143 u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
144 odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));
145
146 /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
147 tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);
148 odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));
149
150 if (tmp_reg422 & BIT(6)) {
151 PHYDM_DBG(dm, DBG_TXBF,
152 "%s There is an adapter is sending beacon.\n",
153 __func__);
154 is_send_beacon = true;
155 }
156
157 /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
158 odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);
159
160 do {
161 /*@Clear beacon valid check bit.*/
162 bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
163 odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));
164
165 /* @download NDPA rsvd page. */
166 beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
167
168 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
169 if (dm->support_interface == ODM_ITRF_PCIE) {
170 u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
171 count = 0;
172 while ((count < 20) && (u1b_tmp & BIT(4))) {
173 count++;
174 ODM_delay_us(10);
175 u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
176 }
177 odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));
178 }
179 #endif
180
181 /*@check rsvd page download OK.*/
182 bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
183 count = 0;
184 while (!(bcn_valid_reg & BIT(0)) && count < 20) {
185 count++;
186 ODM_delay_us(10);
187 bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
188 }
189 dl_bcn_count++;
190 } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
191
192 if (!(bcn_valid_reg & BIT(0)))
193 PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
194 __func__);
195
196 /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
197 odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);
198
199 /*To make sure that if there exists an adapter which would like to send beacon.*/
200 /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
201 /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
202 /*the beacon cannot be sent by HW.*/
203 /*@2010.06.23. Added by tynli.*/
204 if (is_send_beacon)
205 odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);
206
207 /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
208 /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
209 u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
210 odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));
211
212 p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
213 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
214 *dm->is_fw_dw_rsvd_page_in_progress = false;
215 #endif
216 }
217
hal_txbf_8192e_enter(void * dm_void,u8 bfer_bfee_idx)218 void hal_txbf_8192e_enter(
219 void *dm_void,
220 u8 bfer_bfee_idx)
221 {
222 struct dm_struct *dm = (struct dm_struct *)dm_void;
223 u8 i = 0;
224 u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
225 u8 bfee_idx = (bfer_bfee_idx & 0xF);
226 u32 csi_param;
227 struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
228 struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
229 struct _RT_BEAMFORMER_ENTRY beamformer_entry;
230 u16 sta_id = 0;
231
232 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
233
234 hal_txbf_8192e_rf_mode(dm, beamforming_info);
235
236 if (dm->rf_type == RF_2T2R)
237 odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
238
239 if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
240 beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
241
242 /*Sounding protocol control*/
243 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);
244
245 /*@MAC address/Partial AID of Beamformer*/
246 if (bfer_idx == 0) {
247 for (i = 0; i < 6; i++)
248 odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);
249 } else {
250 for (i = 0; i < 6; i++)
251 odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);
252 }
253
254 /*@CSI report parameters of Beamformer Default use nc = 2*/
255 csi_param = 0x03090309;
256
257 odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
258 odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
259 odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
260
261 /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
262 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);
263 }
264
265 if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
266 beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
267
268 if (phydm_acting_determine(dm, phydm_acting_as_ibss))
269 sta_id = beamformee_entry.mac_id;
270 else
271 sta_id = beamformee_entry.p_aid;
272
273 PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__,
274 sta_id);
275
276 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
277 if (bfee_idx == 0) {
278 odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);
279 odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));
280 } else
281 odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
282
283 /*@CSI report parameters of Beamformee*/
284 if (bfee_idx == 0) {
285 /*@Get BIT24 & BIT25*/
286 u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;
287
288 odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);
289 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
290 } else {
291 /*Set BIT25*/
292 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);
293 }
294 phydm_beamforming_notify(dm);
295 }
296 }
297
hal_txbf_8192e_leave(void * dm_void,u8 idx)298 void hal_txbf_8192e_leave(
299 void *dm_void,
300 u8 idx)
301 {
302 struct dm_struct *dm = (struct dm_struct *)dm_void;
303 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
304
305 hal_txbf_8192e_rf_mode(dm, beam_info);
306
307 /* @Clear P_AID of Beamformee
308 * Clear MAC addresss of Beamformer
309 * Clear Associated Bfmee Sel
310 */
311 if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
312 odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8);
313
314 if (idx == 0) {
315 odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);
316 odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
317 odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);
318 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
319 } else {
320 odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);
321 odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
322 odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);
323 odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);
324 }
325
326 PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx);
327 }
328
hal_txbf_8192e_status(void * dm_void,u8 idx)329 void hal_txbf_8192e_status(
330 void *dm_void,
331 u8 idx)
332 {
333 struct dm_struct *dm = (struct dm_struct *)dm_void;
334 u16 beam_ctrl_val;
335 u32 beam_ctrl_reg;
336 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
337 struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
338
339 if (phydm_acting_determine(dm, phydm_acting_as_ibss))
340 beam_ctrl_val = beamform_entry.mac_id;
341 else
342 beam_ctrl_val = beamform_entry.p_aid;
343
344 if (idx == 0)
345 beam_ctrl_reg = REG_TXBF_CTRL_8192E;
346 else {
347 beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;
348 beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
349 }
350
351 if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
352 if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
353 beam_ctrl_val |= BIT(9);
354 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
355 beam_ctrl_val |= BIT(10);
356 } else
357 beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
358
359 odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
360
361 PHYDM_DBG(dm, DBG_TXBF,
362 "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__,
363 idx, beam_ctrl_reg, beam_ctrl_val);
364 }
365
hal_txbf_8192e_fw_tx_bf(void * dm_void,u8 idx)366 void hal_txbf_8192e_fw_tx_bf(
367 void *dm_void,
368 u8 idx)
369 {
370 struct dm_struct *dm = (struct dm_struct *)dm_void;
371 struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
372 struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
373
374 PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
375
376 if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
377 hal_txbf_8192e_download_ndpa(dm, idx);
378
379 hal_txbf_8192e_fw_txbf_cmd(dm);
380 }
381
382 #endif /* @#if (RTL8192E_SUPPORT == 1)*/
383
384 #endif
385