1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
phydm_is_vht_rate(void * dm_void,u8 rate)32 boolean phydm_is_vht_rate(void *dm_void, u8 rate)
33 {
34 return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;
35 }
36
phydm_is_ht_rate(void * dm_void,u8 rate)37 boolean phydm_is_ht_rate(void *dm_void, u8 rate)
38 {
39 return (((rate & 0x7f) >= ODM_RATEMCS0) &&
40 ((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;
41 }
42
phydm_is_ofdm_rate(void * dm_void,u8 rate)43 boolean phydm_is_ofdm_rate(void *dm_void, u8 rate)
44 {
45 return (((rate & 0x7f) >= ODM_RATE6M) &&
46 ((rate & 0x7f) <= ODM_RATE54M)) ? true : false;
47 }
48
phydm_is_cck_rate(void * dm_void,u8 rate)49 boolean phydm_is_cck_rate(void *dm_void, u8 rate)
50 {
51 return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
52 }
53
phydm_legacy_rate_2_spec_rate(void * dm_void,u8 rate)54 u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate)
55 {
56 u8 rate_idx = 0x0;
57 u8 legacy_spec_rate_t[8] = {PHYDM_SPEC_RATE_6M, PHYDM_SPEC_RATE_9M,
58 PHYDM_SPEC_RATE_12M, PHYDM_SPEC_RATE_18M,
59 PHYDM_SPEC_RATE_24M, PHYDM_SPEC_RATE_36M,
60 PHYDM_SPEC_RATE_48M, PHYDM_SPEC_RATE_54M};
61
62 rate_idx = rate - ODM_RATE6M;
63 return legacy_spec_rate_t[rate_idx];
64 }
65
phydm_rate_2_rate_digit(void * dm_void,u8 rate)66 u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
67 {
68 u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
69 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
70 u8 rate_digit = 0;
71
72 if (rate_idx >= ODM_RATEVHTSS1MCS0)
73 rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;
74 else if (rate_idx >= ODM_RATEMCS0)
75 rate_digit = (rate_idx - ODM_RATEMCS0);
76 else if (rate_idx <= ODM_RATE54M)
77 rate_digit = legacy_table[rate_idx];
78
79 return rate_digit;
80 }
81
phydm_rate_type_2_num_ss(void * dm_void,enum PDM_RATE_TYPE type)82 u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)
83 {
84 u8 num_ss = 1;
85
86 switch (type) {
87 case PDM_CCK:
88 case PDM_OFDM:
89 case PDM_1SS:
90 num_ss = 1;
91 break;
92 case PDM_2SS:
93 num_ss = 2;
94 break;
95 case PDM_3SS:
96 num_ss = 3;
97 break;
98 case PDM_4SS:
99 num_ss = 4;
100 break;
101 default:
102 break;
103 }
104
105 return num_ss;
106 }
107
phydm_rate_to_num_ss(void * dm_void,u8 data_rate)108 u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)
109 {
110 u8 num_ss = 1;
111
112 if (data_rate <= ODM_RATE54M)
113 num_ss = 1;
114 else if (data_rate <= ODM_RATEMCS31)
115 num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
116 else if (data_rate <= ODM_RATEVHTSS1MCS9)
117 num_ss = 1;
118 else if (data_rate <= ODM_RATEVHTSS2MCS9)
119 num_ss = 2;
120 else if (data_rate <= ODM_RATEVHTSS3MCS9)
121 num_ss = 3;
122 else if (data_rate <= ODM_RATEVHTSS4MCS9)
123 num_ss = 4;
124
125 return num_ss;
126 }
127
phydm_h2C_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)128 void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
129 char *output, u32 *_out_len)
130 {
131 struct dm_struct *dm = (struct dm_struct *)dm_void;
132 u32 used = *_used;
133 u32 out_len = *_out_len;
134 u32 dm_value[10] = {0};
135 u8 i = 0, input_idx = 0;
136 u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
137 u8 phydm_h2c_id = 0;
138
139 for (i = 0; i < 8; i++) {
140 if (input[i + 1]) {
141 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
142 input_idx++;
143 }
144 }
145
146 if (input_idx == 0)
147 return;
148
149 phydm_h2c_id = (u8)dm_value[0];
150
151 PDM_SNPF(out_len, used, output + used, out_len - used,
152 "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
153
154 for (i = 0; i < H2C_MAX_LENGTH; i++) {
155 h2c_parameter[i] = (u8)dm_value[i + 1];
156 PDM_SNPF(out_len, used, output + used, out_len - used,
157 "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]);
158 }
159
160 odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
161
162 *_used = used;
163 *_out_len = out_len;
164 }
165
phydm_fw_fix_rate(void * dm_void,u8 en,u8 macid,u8 bw,u8 rate)166 void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
167 {
168 struct dm_struct *dm = (struct dm_struct *)dm_void;
169 u32 reg_u32_tmp;
170
171 if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
172 reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
173 odm_set_mac_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
174
175 } else {
176 if (en == 1)
177 reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);
178 else
179 reg_u32_tmp = 0x40000000;
180 if (dm->support_ic_type & ODM_RTL8814B)
181 odm_set_mac_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);
182 else
183 odm_set_mac_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
184 }
185 if (en == 1) {
186 PHYDM_DBG(dm, ODM_COMP_API,
187 "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid,
188 (20 << bw), rate);
189 phydm_print_rate(dm, rate, ODM_COMP_API);
190 } else {
191 PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n");
192 }
193 }
194
phydm_ra_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)195 void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
196 u32 *_out_len)
197 {
198 struct dm_struct *dm = (struct dm_struct *)dm_void;
199 struct ra_table *ra_tab = &dm->dm_ra_table;
200 u32 used = *_used;
201 u32 out_len = *_out_len;
202 char help[] = "-h";
203 u32 var[5] = {0};
204 u8 macid = 0, bw = 0, rate = 0;
205 u8 tx_cls_en = 0, tx_cls_th = 0, tmp = 0;
206 u8 i = 0;
207
208 for (i = 0; i < 5; i++) {
209 if (input[i + 1])
210 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
211 }
212
213 if ((strcmp(input[1], help) == 0)) {
214 PDM_SNPF(out_len, used, output + used, out_len - used,
215 "{1} {0:-,1:+} {ofst}: set offset\n");
216 PDM_SNPF(out_len, used, output + used, out_len - used,
217 "{1} {100}: show offset\n");
218 PDM_SNPF(out_len, used, output + used, out_len - used,
219 "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
220 PDM_SNPF(out_len, used, output + used, out_len - used,
221 "{3} {en}: Dynamic RRSR\n");
222 PDM_SNPF(out_len, used, output + used, out_len - used,
223 "{4} {0:pkt RA, 1:TBTT RA, 100:query RA mode}\n");
224 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
225 PDM_SNPF(out_len, used, output + used, out_len - used,
226 "{5} {0:dis, 1:en}{th; 255:auto, xx:dB}: Tx CLS\n");
227 #endif
228 #ifdef RA_MASK_BY_RX_UTILITY
229 PDM_SNPF(out_len, used, output + used, out_len - used,
230 "{6} {th} RA MASK disable by rx_utility\n");
231 #endif
232 } else if (var[0] == 1) { /*@Adjust PCR offset*/
233
234 if (var[1] == 100) {
235 PDM_SNPF(out_len, used, output + used, out_len - used,
236 "[Get] RA_ofst=((%s%d))\n",
237 ((ra_tab->ra_ofst_direc) ? "+" : "-"),
238 ra_tab->ra_th_ofst);
239
240 } else if (var[1] == 0) {
241 ra_tab->ra_ofst_direc = 0;
242 ra_tab->ra_th_ofst = (u8)var[2];
243 PDM_SNPF(out_len, used, output + used, out_len - used,
244 "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst);
245 } else if (var[1] == 1) {
246 ra_tab->ra_ofst_direc = 1;
247 ra_tab->ra_th_ofst = (u8)var[2];
248 PDM_SNPF(out_len, used, output + used, out_len - used,
249 "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst);
250 }
251
252 } else if (var[0] == 2) { /*@FW fix rate*/
253 macid = (u8)var[2];
254 bw = (u8)var[3];
255 rate = (u8)var[4];
256
257 PDM_SNPF(out_len, used, output + used, out_len - used,
258 "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}",
259 var[1], macid, bw, rate);
260
261 phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
262 } else if (var[0] == 3) { /*@Dynamic RRSR*/
263 ra_tab->dynamic_rrsr_en = (boolean)var[1];
264 PDM_SNPF(out_len, used, output + used, out_len - used,
265 "[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en);
266 } else if (var[0] == 4) { /*@RA trigger mode*/
267 if (var[1] == 0 || var[1] == 1)
268 ra_tab->ra_trigger_mode = (u8)var[1];
269 PDM_SNPF(out_len, used, output + used, out_len - used,
270 "[RA trigger] mode=%d\n", ra_tab->ra_trigger_mode);
271 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
272 } else if (var[0] == 5) { /*@Tx Collision Detection*/
273 tx_cls_en = (u8)var[1];
274 ra_tab->ra_tx_cls_th = (u8)var[2];
275 tmp = (u8)var[2];
276 tx_cls_th = (tmp < 50) ? 0 : (tmp > 81) ? 31 : tmp - 50;
277 if (tx_cls_en) {
278 odm_set_bb_reg(dm, R_0x8f8, BIT(16), 1);
279 if (ra_tab->ra_tx_cls_th != 255) {
280 phydm_tx_collsion_th_set(dm, tx_cls_th,
281 tx_cls_th);
282 }
283
284 } else {
285 odm_set_bb_reg(dm, R_0x8f8, BIT(16), 0);
286 }
287
288 if (tx_cls_en & ra_tab->ra_tx_cls_th != 255) {
289 PDM_SNPF(out_len, used, output + used, out_len - used,
290 "[Tx Collision Detec] {en, th}={%d, %d}\n",
291 tx_cls_en, tx_cls_th + 50);
292 } else if (tx_cls_en & ra_tab->ra_tx_cls_th == 255) {
293 PDM_SNPF(out_len, used, output + used, out_len - used,
294 "[Tx Collision Detec] {en, th}={%d, auto}\n",
295 tx_cls_en);
296 } else {
297 PDM_SNPF(out_len, used, output + used, out_len - used,
298 "[Tx Collision Detec] {en, th}={%d, xx}\n",
299 tx_cls_en);
300 }
301 #endif
302 #ifdef RA_MASK_BY_RX_UTILITY
303 } else if (var[0] == 6) { /*@RA trigger mode*/
304 ra_tab->dis_mask_rx_utility_th = (u16)var[1];
305 PDM_SNPF(out_len, used, output + used, out_len - used,
306 "[RA_MASK_BY_RX_UTILITY] th=%d\n", ra_tab->dis_mask_rx_utility_th);
307 #endif
308 } else {
309 PDM_SNPF(out_len, used, output + used, out_len - used,
310 "[Set] Error\n");
311 }
312 *_used = used;
313 *_out_len = out_len;
314 }
315
phydm_ra_mask_report_h2c_trigger(void * dm_void,struct ra_mask_rpt_trig * trig_rpt)316 void phydm_ra_mask_report_h2c_trigger(void *dm_void,
317 struct ra_mask_rpt_trig *trig_rpt)
318 {
319 struct dm_struct *dm = (struct dm_struct *)dm_void;
320 struct ra_table *ra_tab = &dm->dm_ra_table;
321
322 phydm_fw_trace_en_h2c(dm, true, 1, 2, trig_rpt->macid);
323
324 trig_rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
325 }
phydm_ra_mask_report_c2h_result(void * dm_void,struct ra_mask_rpt * rpt)326 void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt)
327 {
328 struct dm_struct *dm = (struct dm_struct *)dm_void;
329 struct ra_table *ra_tab = &dm->dm_ra_table;
330 u8 i = 0;
331
332 rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
333
334 odm_move_memory(dm, &rpt->ra_mask_buf[0], &ra_tab->ra_mask_buf[0], 8);
335 }
336
odm_c2h_ra_para_report_handler(void * dm_void,u8 * cmd_buf,u8 cmd_len)337 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
338 {
339 struct dm_struct *dm = (struct dm_struct *)dm_void;
340 struct ra_table *ra_tab = &dm->dm_ra_table;
341 u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
342 u8 i;
343
344 PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n",
345 __func__, mode);
346
347 if (mode == RADBG_DEBUG_MONITOR1) {
348 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
349 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =",
350 cmd_buf[1]);
351 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "rate =",
352 cmd_buf[2] & 0x7f);
353 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI =",
354 (cmd_buf[2] & 0x80) >> 7);
355 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW =",
356 cmd_buf[3]);
357 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW_max =",
358 cmd_buf[4]);
359 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
360 "multi_rate0 =", cmd_buf[5]);
361 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
362 "multi_rate1 =", cmd_buf[6]);
363 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =",
364 cmd_buf[7]);
365 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =",
366 cmd_buf[8]);
367 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n",
368 "SGI_support =", cmd_buf[9]);
369 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "try_ness =",
370 cmd_buf[10]);
371 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "pre_rate =",
372 cmd_buf[11]);
373 } else {
374 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =",
375 cmd_buf[1]);
376 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x\n", "BW =",
377 cmd_buf[2]);
378 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =",
379 cmd_buf[3]);
380 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =",
381 cmd_buf[4]);
382 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n",
383 "Hightest rate =", cmd_buf[5]);
384 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
385 "Lowest rate =", cmd_buf[6]);
386 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
387 "SGI_support =", cmd_buf[7]);
388 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Rate_ID =",
389 cmd_buf[8]);
390 }
391 } else if (mode == RADBG_DEBUG_MONITOR2) {
392 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
393 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate_id =",
394 cmd_buf[1]);
395 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
396 "highest_rate =", cmd_buf[2]);
397 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
398 "lowest_rate =", cmd_buf[3]);
399
400 for (i = 4; i <= 11; i++)
401 PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK = 0x%x\n",
402 cmd_buf[i]);
403
404 odm_move_memory(dm, &ra_tab->ra_mask_buf[0], &cmd_buf[4], 8);
405 ra_tab->ra_mask_rpt_stamp++;
406 } else {
407 PHYDM_DBG(dm, DBG_FW_TRACE,
408 "%5s %x%x %x%x %x%x %x%x\n", "RA Mask:",
409 cmd_buf[8], cmd_buf[7], cmd_buf[6],
410 cmd_buf[5], cmd_buf[4], cmd_buf[3],
411 cmd_buf[2], cmd_buf[1]);
412 }
413 } else if (mode == RADBG_DEBUG_MONITOR3) {
414 for (i = 0; i < (cmd_len - 1); i++)
415 PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i,
416 cmd_buf[1 + i]);
417 } else if (mode == RADBG_DEBUG_MONITOR4)
418 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {%d.%d}\n", "RA version =",
419 cmd_buf[1], cmd_buf[2]);
420 else if (mode == RADBG_DEBUG_MONITOR5) {
421 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Current rate =",
422 cmd_buf[1]);
423 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Retry ratio =",
424 cmd_buf[2]);
425 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate down ratio =",
426 cmd_buf[3]);
427 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest rate =",
428 cmd_buf[4]);
429 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {0x%x 0x%x}\n", "Muti-try =",
430 cmd_buf[5], cmd_buf[6]);
431 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x%x%x%x%x\n", "RA mask =",
432 cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],
433 cmd_buf[7]);
434 }
435 PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n");
436 }
437
phydm_ra_dynamic_retry_count(void * dm_void)438 void phydm_ra_dynamic_retry_count(void *dm_void)
439 {
440 struct dm_struct *dm = (struct dm_struct *)dm_void;
441
442 if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
443 return;
444
445 /*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
446
447 if (dm->pre_b_noisy != dm->noisy_decision) {
448 if (dm->noisy_decision) {
449 PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
450 odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);
451 odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);
452 } else {
453 PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n");
454 odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);
455 odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);
456 }
457 dm->pre_b_noisy = dm->noisy_decision;
458 }
459 }
460
phydm_print_rate(void * dm_void,u8 rate,u32 dbg_component)461 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
462 {
463 struct dm_struct *dm = (struct dm_struct *)dm_void;
464 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
465 boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
466 u8 b_sgi = (rate & 0x80) >> 7;
467 u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
468 u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
469
470 PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%s%d%s%s)\n",
471 (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
472 (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
473 (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
474 (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
475 (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
476 rate_digit,
477 (b_sgi) ? "-S" : " ",
478 (rate_idx >= ODM_RATEMCS0) ? "" : "M");
479 }
480
phydm_print_rate_2_buff(void * dm_void,u8 rate,char * buf,u16 buf_size)481 void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
482 {
483 struct dm_struct *dm = (struct dm_struct *)dm_void;
484 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
485 boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
486 u8 b_sgi = (rate & 0x80) >> 7;
487 u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
488 u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
489
490 PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%s%d%s%s)",
491 (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
492 (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
493 (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
494 (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
495 (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
496 rate_digit,
497 (b_sgi) ? "-S" : " ",
498 (rate_idx >= ODM_RATEMCS0) ? "" : "M");
499 }
500
phydm_c2h_ra_report_handler(void * dm_void,u8 * cmd_buf,u8 cmd_len)501 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
502 {
503 struct dm_struct *dm = (struct dm_struct *)dm_void;
504 struct ra_table *ra_tab = &dm->dm_ra_table;
505 struct cmn_sta_info *sta = NULL;
506 u8 macid = cmd_buf[1];
507 u8 rate = cmd_buf[0];
508 u8 ra_ratio = 0xff;
509 u8 curr_bw = 0xff;
510 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
511 u8 rate_order;
512 u8 gid_index = 0;
513 u8 txcls_rate = 0;
514 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
515
516 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
517 sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];
518 #else
519 sta = dm->phydm_sta_info[macid];
520 #endif
521
522 if (cmd_len == 7) {
523 ra_ratio = cmd_buf[5];
524 curr_bw = cmd_buf[6];
525 PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d\n", macid, ra_ratio);
526 } else if (cmd_len == 8) {
527 ra_ratio = cmd_buf[5];
528 curr_bw = cmd_buf[6];
529 txcls_rate = cmd_buf[7];
530 PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d TxCLS=%d\n", macid, ra_ratio,
531 txcls_rate);
532 }
533
534 if (cmd_buf[3] != 0) {
535 if (cmd_buf[3] == 0xff)
536 PHYDM_DBG(dm, DBG_RA, "FW Fix Rate\n");
537 else if (cmd_buf[3] == 1)
538 PHYDM_DBG(dm, DBG_RA, "Try Success\n");
539 else if (cmd_buf[3] == 2)
540 PHYDM_DBG(dm, DBG_RA, "Try Fail & Again\n");
541 else if (cmd_buf[3] == 3)
542 PHYDM_DBG(dm, DBG_RA, "Rate Back\n");
543 else if (cmd_buf[3] == 4)
544 PHYDM_DBG(dm, DBG_RA, "Start rate by RSSI\n");
545 else if (cmd_buf[3] == 5)
546 PHYDM_DBG(dm, DBG_RA, "Try rate\n");
547 }
548 phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
549 PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)\n", dbg_buf, rate);
550
551 #ifdef MU_EX_MACID
552 if (macid >= 128 && macid < (128 + MU_EX_MACID)) {
553 gid_index = macid - 128;
554 ra_tab->mu1_rate[gid_index] = rate;
555 }
556 if (macid >= ODM_ASSOCIATE_ENTRY_NUM)
557 return;
558 #endif
559 if (is_sta_active(sta)) {
560 sta->ra_info.curr_tx_rate = rate;
561 sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
562 sta->ra_info.curr_retry_ratio = ra_ratio;
563 }
564
565 /*trigger power training*/
566 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
567
568 rate_order = phydm_rate_order_compute(dm, rate_idx);
569
570 if (dm->is_one_entry_only ||
571 (rate_order > ra_tab->highest_client_tx_order &&
572 ra_tab->power_tracking_flag == 1)) {
573 halrf_update_pwr_track(dm, rate_idx);
574 ra_tab->power_tracking_flag = 0;
575 }
576
577 #endif
578
579 #if 0
580 /*trigger dynamic rate ID*/
581 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
582 phydm_update_rate_id(dm, rate, macid);
583 #endif
584 }
585
odm_ra_post_action_on_assoc(void * dm_void)586 void odm_ra_post_action_on_assoc(void *dm_void)
587 {
588 }
589
phydm_modify_RA_PCR_threshold(void * dm_void,u8 ra_ofst_direc,u8 ra_th_ofst)590 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
591 u8 ra_th_ofst)
592 {
593 struct dm_struct *dm = (struct dm_struct *)dm_void;
594 struct ra_table *ra_tab = &dm->dm_ra_table;
595
596 ra_tab->ra_ofst_direc = ra_ofst_direc;
597 ra_tab->ra_th_ofst = ra_th_ofst;
598 PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n",
599 ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst);
600 }
601
602 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
603
phydm_gen_ramask_h2c_AP(void * dm_void,struct rtl8192cd_priv * priv,struct sta_info * entry,u8 rssi_level)604 void phydm_gen_ramask_h2c_AP(
605 void *dm_void,
606 struct rtl8192cd_priv *priv,
607 struct sta_info *entry,
608 u8 rssi_level)
609 {
610 struct dm_struct *dm = (struct dm_struct *)dm_void;
611
612 if (dm->support_ic_type == ODM_RTL8812) {
613 #if (RTL8812A_SUPPORT == 1)
614 UpdateHalRAMask8812(priv, entry, rssi_level);
615 #endif
616 } else if (dm->support_ic_type == ODM_RTL8188E) {
617 #if (RTL8188E_SUPPORT == 1)
618 #ifdef TXREPORT
619 add_RATid(priv, entry);
620 #endif
621 #endif
622 } else {
623 #ifdef CONFIG_WLAN_HAL
624 GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);
625 #endif
626 }
627 }
628
phydm_update_hal_ra_mask(void * dm_void,u32 wireless_mode,u8 rf_type,u8 bw,u8 mimo_ps_enable,u8 disable_cck_rate,u32 * ratr_bitmap_msb_in,u32 * ratr_bitmap_lsb_in,u8 tx_rate_level)629 void phydm_update_hal_ra_mask(
630 void *dm_void,
631 u32 wireless_mode,
632 u8 rf_type,
633 u8 bw,
634 u8 mimo_ps_enable,
635 u8 disable_cck_rate,
636 u32 *ratr_bitmap_msb_in,
637 u32 *ratr_bitmap_lsb_in,
638 u8 tx_rate_level)
639 {
640 struct dm_struct *dm = (struct dm_struct *)dm_void;
641 u32 ratr_bitmap = *ratr_bitmap_lsb_in;
642 u32 ratr_bitmap_msb = *ratr_bitmap_msb_in;
643
644 #if 0
645 /*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/
646 #endif
647 PHYDM_DBG(dm, DBG_RA_MASK,
648 "Platfoem original RA Mask = (( 0x %x | %x ))\n",
649 ratr_bitmap_msb, ratr_bitmap);
650
651 switch (wireless_mode) {
652 case PHYDM_WIRELESS_MODE_B: {
653 ratr_bitmap &= 0x0000000f;
654 } break;
655
656 case PHYDM_WIRELESS_MODE_G: {
657 ratr_bitmap &= 0x00000ff5;
658 } break;
659
660 case PHYDM_WIRELESS_MODE_A: {
661 ratr_bitmap &= 0x00000ff0;
662 } break;
663
664 case PHYDM_WIRELESS_MODE_N_24G:
665 case PHYDM_WIRELESS_MODE_N_5G: {
666 if (mimo_ps_enable)
667 rf_type = RF_1T1R;
668
669 if (rf_type == RF_1T1R) {
670 if (bw == CHANNEL_WIDTH_40)
671 ratr_bitmap &= 0x000ff015;
672 else
673 ratr_bitmap &= 0x000ff005;
674 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
675 if (bw == CHANNEL_WIDTH_40)
676 ratr_bitmap &= 0x0ffff015;
677 else
678 ratr_bitmap &= 0x0ffff005;
679 } else { /*@3T*/
680
681 ratr_bitmap &= 0xfffff015;
682 ratr_bitmap_msb &= 0xf;
683 }
684 } break;
685
686 case PHYDM_WIRELESS_MODE_AC_24G: {
687 if (rf_type == RF_1T1R) {
688 ratr_bitmap &= 0x003ff015;
689 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
690 ratr_bitmap &= 0xfffff015;
691 } else { /*@3T*/
692
693 ratr_bitmap &= 0xfffff010;
694 ratr_bitmap_msb &= 0x3ff;
695 }
696
697 if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
698 ratr_bitmap &= 0x7fdfffff;
699 ratr_bitmap_msb &= 0x1ff;
700 }
701 } break;
702
703 case PHYDM_WIRELESS_MODE_AC_5G: {
704 if (rf_type == RF_1T1R) {
705 ratr_bitmap &= 0x003ff010;
706 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
707 ratr_bitmap &= 0xfffff010;
708 } else { /*@3T*/
709
710 ratr_bitmap &= 0xfffff010;
711 ratr_bitmap_msb &= 0x3ff;
712 }
713
714 if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
715 ratr_bitmap &= 0x7fdfffff;
716 ratr_bitmap_msb &= 0x1ff;
717 }
718 } break;
719
720 default:
721 break;
722 }
723
724 if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
725 if (tx_rate_level == 0)
726 ratr_bitmap &= 0xffffffff;
727 else if (tx_rate_level == 1)
728 ratr_bitmap &= 0xfffffff0;
729 else if (tx_rate_level == 2)
730 ratr_bitmap &= 0xffffefe0;
731 else if (tx_rate_level == 3)
732 ratr_bitmap &= 0xffffcfc0;
733 else if (tx_rate_level == 4)
734 ratr_bitmap &= 0xffff8f80;
735 else if (tx_rate_level >= 5)
736 ratr_bitmap &= 0xffff0f00;
737 }
738
739 if (disable_cck_rate)
740 ratr_bitmap &= 0xfffffff0;
741
742 PHYDM_DBG(dm, DBG_RA_MASK,
743 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
744 wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);
745
746 #if 0
747 /*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/
748 #endif
749
750 *ratr_bitmap_lsb_in = ratr_bitmap;
751 *ratr_bitmap_msb_in = ratr_bitmap_msb;
752 PHYDM_DBG(dm, DBG_RA_MASK,
753 "Phydm modified RA Mask = (( 0x %x | %x ))\n",
754 *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
755 }
756
757 #endif
758
phydm_rate_adaptive_mask_init(void * dm_void)759 void phydm_rate_adaptive_mask_init(void *dm_void)
760 {
761 struct dm_struct *dm = (struct dm_struct *)dm_void;
762 struct ra_table *ra_t = &dm->dm_ra_table;
763
764 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
765 PADAPTER adapter = dm->adapter;
766 PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
767 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));
768
769 if (mgnt_info->DM_Type == dm_type_by_driver)
770 hal_data->bUseRAMask = true;
771 else
772 hal_data->bUseRAMask = false;
773
774 #endif
775
776 ra_t->ldpc_thres = 35;
777 ra_t->up_ramask_cnt = 0;
778 ra_t->up_ramask_cnt_tmp = 0;
779 }
780
phydm_refresh_rate_adaptive_mask(void * dm_void)781 void phydm_refresh_rate_adaptive_mask(void *dm_void)
782 {
783 /*@Will be removed*/
784 struct dm_struct *dm = (struct dm_struct *)dm_void;
785
786 phydm_ra_mask_watchdog(dm);
787 }
788
phydm_show_sta_info(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)789 void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
790 char *output, u32 *_out_len)
791 {
792 struct dm_struct *dm = (struct dm_struct *)dm_void;
793 struct cmn_sta_info *sta = NULL;
794 struct ra_sta_info *ra = NULL;
795 #ifdef CONFIG_BEAMFORMING
796 struct bf_cmn_info *bf = NULL;
797 #endif
798 char help[] = "-h";
799 u32 var[10] = {0};
800 u32 used = *_used;
801 u32 out_len = *_out_len;
802 u32 i, sta_idx_start, sta_idx_end;
803 u8 tatal_sta_num = 0;
804
805 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
806
807 if ((strcmp(input[1], help) == 0)) {
808 PDM_SNPF(out_len, used, output + used, out_len - used,
809 "All STA: {1}\n");
810 PDM_SNPF(out_len, used, output + used, out_len - used,
811 "STA[macid]: {2} {macid}\n");
812 return;
813 } else if (var[0] == 1) {
814 sta_idx_start = 0;
815 sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;
816 } else if (var[0] == 2) {
817 sta_idx_start = var[1];
818 sta_idx_end = var[1];
819 } else {
820 PDM_SNPF(out_len, used, output + used, out_len - used,
821 "Warning input value!\n");
822 return;
823 }
824
825 for (i = sta_idx_start; i < sta_idx_end; i++) {
826 sta = dm->phydm_sta_info[i];
827
828 if (!is_sta_active(sta))
829 continue;
830
831 ra = &sta->ra_info;
832 #ifdef CONFIG_BEAMFORMING
833 bf = &sta->bf_info;
834 #endif
835
836 tatal_sta_num++;
837
838 PDM_SNPF(out_len, used, output + used, out_len - used,
839 "==[sta_idx: %d][MACID: %d]============>\n", i,
840 sta->mac_id);
841 PDM_SNPF(out_len, used, output + used, out_len - used,
842 "AID:%d\n", sta->aid);
843 PDM_SNPF(out_len, used, output + used, out_len - used,
844 "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5],
845 sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],
846 sta->mac_addr[1], sta->mac_addr[0]);
847 PDM_SNPF(out_len, used, output + used, out_len - used,
848 "DM_ctrl:0x%x\n", sta->dm_ctrl);
849 PDM_SNPF(out_len, used, output + used, out_len - used,
850 "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode,
851 sta->mimo_type);
852 PDM_SNPF(out_len, used, output + used, out_len - used,
853 "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en,
854 sta->ldpc_en);
855
856 /*@[RSSI Info]*/
857 PDM_SNPF(out_len, used, output + used, out_len - used,
858 "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
859 sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,
860 sta->rssi_stat.rssi_cck);
861
862 /*@[RA Info]*/
863 PDM_SNPF(out_len, used, output + used, out_len - used,
864 "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
865 ra->rate_id, ra->rssi_level, ra->ra_bw_mode,
866 ra->is_support_sgi);
867
868 PDM_SNPF(out_len, used, output + used, out_len - used,
869 "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
870 ra->is_vht_enable, sta->support_wireless_set,
871 sta->sm_ps);
872
873 PDM_SNPF(out_len, used, output + used, out_len - used,
874 "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
875 ra->disable_ra, ra->disable_pt, ra->txrx_state,
876 ra->is_noisy);
877
878 PDM_SNPF(out_len, used, output + used, out_len - used,
879 "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate,
880 ra->curr_tx_bw, ra->curr_retry_ratio);
881
882 PDM_SNPF(out_len, used, output + used, out_len - used,
883 "RA_Mask:0x%llx\n", ra->ramask);
884
885 /*@[TP]*/
886 PDM_SNPF(out_len, used, output + used, out_len - used,
887 "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp,
888 sta->rx_moving_average_tp);
889
890 #ifdef CONFIG_BEAMFORMING
891 /*@[Beamforming]*/
892 PDM_SNPF(out_len, used, output + used, out_len - used,
893 "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap,
894 bf->vht_beamform_cap);
895 PDM_SNPF(out_len, used, output + used, out_len - used,
896 "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid,
897 bf->g_id);
898 #endif
899 }
900
901 if (tatal_sta_num == 0) {
902 PDM_SNPF(out_len, used, output + used, out_len - used,
903 "No Linked STA\n");
904 }
905
906 *_used = used;
907 *_out_len = out_len;
908 }
909
phydm_get_rx_stream_num(void * dm_void,enum rf_type type)910 u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type)
911 {
912 struct dm_struct *dm = (struct dm_struct *)dm_void;
913 u8 rx_num = 1;
914
915 if (type == RF_1T1R)
916 rx_num = 1;
917 else if (type == RF_2T2R || type == RF_1T2R)
918 rx_num = 2;
919 else if (type == RF_3T3R || type == RF_2T3R)
920 rx_num = 3;
921 else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)
922 rx_num = 4;
923 else
924 pr_debug("[Warrning] %s\n", __func__);
925
926 return rx_num;
927 }
928
phydm_get_tx_stream_num(void * dm_void,enum rf_type type)929 u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
930 {
931 struct dm_struct *dm = (struct dm_struct *)dm_void;
932 u8 tx_num = 1;
933
934 if (type == RF_1T1R || type == RF_1T2R)
935 tx_num = 1;
936 else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)
937 tx_num = 2;
938 else if (type == RF_3T3R || type == RF_3T4R)
939 tx_num = 3;
940 else if (type == RF_4T4R)
941 tx_num = 4;
942 else
943 PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n");
944
945 return tx_num;
946 }
947
phydm_get_bb_mod_ra_mask(void * dm_void,u8 sta_idx)948 u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
949 {
950 struct dm_struct *dm = (struct dm_struct *)dm_void;
951 struct phydm_iot_center *iot_table = &dm->iot_table;
952 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
953 struct ra_sta_info *ra = NULL;
954 enum channel_width bw = 0;
955 enum wireless_set wrls_mode = 0;
956 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
957 struct rtl8192cd_priv *priv = dm->priv;
958 #endif
959 u8 tx_stream_num = 1;
960 u8 rssi_lv = 0;
961 u64 ra_mask_bitmap = 0;
962
963 if (is_sta_active(sta)) {
964 ra = &sta->ra_info;
965 bw = ra->ra_bw_mode;
966 wrls_mode = sta->support_wireless_set;
967 tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
968 rssi_lv = ra->rssi_level;
969 ra_mask_bitmap = ra->ramask;
970 } else {
971 PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
972 return 0;
973 }
974
975 PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id,
976 ra_mask_bitmap);
977 PHYDM_DBG(dm, DBG_RA,
978 "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
979 wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);
980
981 if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/
982 tx_stream_num = 1;
983
984 /*@[Modify RA Mask by Wireless Mode]*/
985
986 if (wrls_mode == WIRELESS_CCK) { /*@B mode*/
987 ra_mask_bitmap &= 0x0000000f;
988 } else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/
989 ra_mask_bitmap &= 0x00000ff0;
990 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/
991 ra_mask_bitmap &= 0x00000ff5;
992 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
993 /*N_2G*/
994 if (tx_stream_num == 1) {
995 if (bw == CHANNEL_WIDTH_40)
996 ra_mask_bitmap &= 0x000ff015;
997 else
998 ra_mask_bitmap &= 0x000ff005;
999 } else if (tx_stream_num == 2) {
1000 if (bw == CHANNEL_WIDTH_40)
1001 ra_mask_bitmap &= 0x0ffff015;
1002 else
1003 ra_mask_bitmap &= 0x0ffff005;
1004 } else if (tx_stream_num == 3) {
1005 ra_mask_bitmap &= 0xffffff015;
1006 } else {
1007 ra_mask_bitmap &= 0xffffffff015;
1008 }
1009 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
1010
1011 if (tx_stream_num == 1) {
1012 if (bw == CHANNEL_WIDTH_40)
1013 ra_mask_bitmap &= 0x000ff030;
1014 else
1015 ra_mask_bitmap &= 0x000ff010;
1016 } else if (tx_stream_num == 2) {
1017 if (bw == CHANNEL_WIDTH_40)
1018 ra_mask_bitmap &= 0x0ffff030;
1019 else
1020 ra_mask_bitmap &= 0x0ffff010;
1021 } else if (tx_stream_num == 3) {
1022 ra_mask_bitmap &= 0xffffff010;
1023 } else {
1024 ra_mask_bitmap &= 0xffffffff010;
1025 }
1026 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
1027 /*@AC_2G*/
1028 if (tx_stream_num == 1)
1029 ra_mask_bitmap &= 0x003ff015;
1030 else if (tx_stream_num == 2)
1031 ra_mask_bitmap &= 0xfffff015;
1032 else if (tx_stream_num == 3)
1033 ra_mask_bitmap &= 0x3fffffff015;
1034 else /*@AC_4SS 2G*/
1035 ra_mask_bitmap &= 0x000ffffffffff015;
1036 if (bw == CHANNEL_WIDTH_20) {
1037 /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
1038 ra_mask_bitmap &= 0x0007ffff7fdff015;
1039 } else if (bw == CHANNEL_WIDTH_80) {
1040 /* @AC 80MHz doesn't support 3SS MCS6*/
1041 ra_mask_bitmap &= 0x000fffbffffff015;
1042 }
1043 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/
1044
1045 if (tx_stream_num == 1)
1046 ra_mask_bitmap &= 0x003ff010;
1047 else if (tx_stream_num == 2)
1048 ra_mask_bitmap &= 0xfffff010;
1049 else if (tx_stream_num == 3)
1050 ra_mask_bitmap &= 0x3fffffff010;
1051 else /*@AC_4SS 5G*/
1052 ra_mask_bitmap &= 0x000ffffffffff010;
1053
1054 if (bw == CHANNEL_WIDTH_20) {
1055 /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
1056 ra_mask_bitmap &= 0x0007ffff7fdff010;
1057 } else if (bw == CHANNEL_WIDTH_80) {
1058 /* @AC 80MHz doesn't support 3SS MCS6*/
1059 ra_mask_bitmap &= 0x000fffbffffff010;
1060 } else if (bw == CHANNEL_WIDTH_160) {
1061 /* @AC 80M+80M doesn't support 3SS & 4SS*/
1062 ra_mask_bitmap &= 0xfffff010;
1063 }
1064 } else {
1065 PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
1066 }
1067
1068 PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);
1069
1070 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
1071 if (priv->pshare->veriwave_sta_num > 0) {
1072 PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
1073 return ra_mask_bitmap;
1074 }
1075 #endif
1076 /*@[Modify RA Mask by RSSI level]*/
1077 if (wrls_mode != WIRELESS_CCK) {
1078 if (iot_table->patch_id_40010700) {
1079 ra_mask_bitmap &= (rssi_lv == 0 ?
1080 0xffffffffffffffff :
1081 0xfffffffffffffff0);
1082 return ra_mask_bitmap;
1083 }
1084
1085 if (rssi_lv == 0)
1086 ra_mask_bitmap &= 0xffffffffffffffff;
1087 else if (rssi_lv == 1)
1088 ra_mask_bitmap &= 0xfffffffffffffff0;
1089 else if (rssi_lv == 2)
1090 ra_mask_bitmap &= 0xffffffffffffefe0;
1091 else if (rssi_lv == 3)
1092 ra_mask_bitmap &= 0xffffffffffffcfc0;
1093 else if (rssi_lv == 4)
1094 ra_mask_bitmap &= 0xffffffffffff8f80;
1095 else if (rssi_lv >= 5)
1096 ra_mask_bitmap &= 0xffffffffffff0f00;
1097 }
1098 PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
1099
1100 return ra_mask_bitmap;
1101 }
1102
phydm_get_rate_from_rssi_lv(void * dm_void,u8 sta_idx)1103 u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)
1104 {
1105 struct dm_struct *dm = (struct dm_struct *)dm_void;
1106 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1107 struct ra_sta_info *ra = NULL;
1108 enum wireless_set wrls_set = 0;
1109 u8 rssi_lv = 0;
1110 u8 rate_idx = 0;
1111 u8 rate_ofst = 0;
1112
1113 if (is_sta_active(sta)) {
1114 ra = &sta->ra_info;
1115 wrls_set = sta->support_wireless_set;
1116 rssi_lv = ra->rssi_level;
1117 } else {
1118 pr_debug("[Warning] %s: invalid STA\n", __func__);
1119 return 0;
1120 }
1121
1122 PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n",
1123 __func__, sta->mac_id, wrls_set, rssi_lv);
1124
1125 rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);
1126
1127 if (wrls_set & WIRELESS_VHT) {
1128 rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;
1129 } else if (wrls_set & WIRELESS_HT) {
1130 rate_idx = ODM_RATEMCS0 + rate_ofst;
1131 } else if (wrls_set & WIRELESS_OFDM) {
1132 rate_idx = ODM_RATE6M + rate_ofst;
1133 } else {
1134 rate_idx = ODM_RATE1M + rate_ofst;
1135
1136 if (rate_idx > ODM_RATE11M)
1137 rate_idx = ODM_RATE11M;
1138 }
1139 return rate_idx;
1140 }
1141
phydm_get_rate_id(void * dm_void,u8 sta_idx)1142 u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
1143 {
1144 struct dm_struct *dm = (struct dm_struct *)dm_void;
1145 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1146 struct ra_sta_info *ra = NULL;
1147 enum channel_width bw = 0;
1148 enum wireless_set wrls_mode = 0;
1149 u8 tx_stream_num = 1;
1150 u8 rate_id_idx = PHYDM_BGN_20M_1SS;
1151
1152 if (is_sta_active(sta)) {
1153 ra = &sta->ra_info;
1154 bw = ra->ra_bw_mode;
1155 wrls_mode = sta->support_wireless_set;
1156 tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
1157
1158 } else {
1159 PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__);
1160 return 0;
1161 }
1162
1163 PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n",
1164 sta->mac_id, wrls_mode, tx_stream_num, bw);
1165
1166 if (wrls_mode == WIRELESS_CCK) {
1167 /*@B mode*/
1168 rate_id_idx = PHYDM_B_20M;
1169 } else if (wrls_mode == WIRELESS_OFDM) {
1170 /*@G mode*/
1171 rate_id_idx = PHYDM_G;
1172 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {
1173 /*@BG mode*/
1174 rate_id_idx = PHYDM_BG;
1175 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {
1176 /*@GN mode*/
1177 if (tx_stream_num == 1)
1178 rate_id_idx = PHYDM_GN_N1SS;
1179 else if (tx_stream_num == 2)
1180 rate_id_idx = PHYDM_GN_N2SS;
1181 else if (tx_stream_num == 3)
1182 rate_id_idx = PHYDM_ARFR5_N_3SS;
1183 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
1184 /*@BGN mode*/
1185 if (bw == CHANNEL_WIDTH_40) {
1186 if (tx_stream_num == 1)
1187 rate_id_idx = PHYDM_BGN_40M_1SS;
1188 else if (tx_stream_num == 2)
1189 rate_id_idx = PHYDM_BGN_40M_2SS;
1190 else if (tx_stream_num == 3)
1191 rate_id_idx = PHYDM_ARFR5_N_3SS;
1192 else if (tx_stream_num == 4)
1193 rate_id_idx = PHYDM_ARFR7_N_4SS;
1194
1195 } else {
1196 if (tx_stream_num == 1)
1197 rate_id_idx = PHYDM_BGN_20M_1SS;
1198 else if (tx_stream_num == 2)
1199 rate_id_idx = PHYDM_BGN_20M_2SS;
1200 else if (tx_stream_num == 3)
1201 rate_id_idx = PHYDM_ARFR5_N_3SS;
1202 else if (tx_stream_num == 4)
1203 rate_id_idx = PHYDM_ARFR7_N_4SS;
1204 }
1205 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
1206 /*@AC mode*/
1207 if (bw == CHANNEL_WIDTH_160) {
1208 if (tx_stream_num == 1)
1209 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1210 else if (tx_stream_num == 2)
1211 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1212 else if (tx_stream_num == 3)
1213 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1214 else if (tx_stream_num == 4)
1215 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1216 } else {
1217 if (tx_stream_num == 1)
1218 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1219 else if (tx_stream_num == 2)
1220 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1221 else if (tx_stream_num == 3)
1222 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1223 else if (tx_stream_num == 4)
1224 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1225 }
1226 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
1227 /*@AC 2.4G mode*/
1228 if (bw >= CHANNEL_WIDTH_80) {
1229 if (tx_stream_num == 1)
1230 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1231 else if (tx_stream_num == 2)
1232 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1233 else if (tx_stream_num == 3)
1234 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1235 else if (tx_stream_num == 4)
1236 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1237 } else {
1238 if (tx_stream_num == 1) {
1239 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
1240 rate_id_idx = PHYDM_TYPE2_ARFR5_AC_2G_1SS;
1241 else
1242 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1243 } else if (tx_stream_num == 2) {
1244 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
1245 rate_id_idx = PHYDM_TYPE2_ARFR3_AC_2G_2SS;
1246 else
1247 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1248 } else if (tx_stream_num == 3) {
1249 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1250 } else if (tx_stream_num == 4) {
1251 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1252 }
1253 }
1254 } else {
1255 PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
1256 rate_id_idx = 0;
1257 }
1258
1259 PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx);
1260
1261 return rate_id_idx;
1262 }
1263
1264 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_ra_mode_selection(void * dm_void,u8 mode)1265 void phydm_ra_mode_selection(void *dm_void, u8 mode)
1266 {
1267 struct dm_struct *dm = (struct dm_struct *)dm_void;
1268 struct ra_table *ra_tab = &dm->dm_ra_table;
1269 u8 pre_mode = ra_tab->ra_trigger_mode; /* 0:pkt RA, 1:TBTT RA */
1270
1271 if (mode >= 2) {
1272 PHYDM_DBG(dm, DBG_RA, "RA mode selection Fail\n");
1273 } else {
1274 ra_tab->ra_trigger_mode = mode;
1275 PHYDM_DBG(dm, DBG_RA, "RA mode, 0:pkt RA, 1:TBTT RA\n");
1276 PHYDM_DBG(dm, DBG_RA, "PreMode=%d,CurMode=%d\n", pre_mode,
1277 mode);
1278 }
1279 }
1280 #endif
1281
phydm_ra_h2c(void * dm_void,u8 sta_idx,u8 dis_ra,u8 dis_pt,u8 no_update_bw,u8 init_ra_lv,u64 ra_mask)1282 void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
1283 u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
1284 {
1285 struct dm_struct *dm = (struct dm_struct *)dm_void;
1286 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1287 struct ra_sta_info *ra = NULL;
1288 u8 h2c_val[H2C_MAX_LENGTH] = {0};
1289 u8 rate_id_idx = 0;
1290
1291 if (is_sta_active(sta)) {
1292 ra = &sta->ra_info;
1293 } else {
1294 PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n",
1295 __func__);
1296 return;
1297 }
1298
1299 PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
1300 PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
1301
1302 #ifdef PHYDM_POWER_TRAINING_SUPPORT
1303 if ((dm->support_ability & ODM_BB_PWR_TRAIN) && !dm->is_disable_power_training)
1304 dis_pt = false;
1305 else
1306 dis_pt = true;
1307
1308 #else
1309 dis_pt= true;
1310 #endif
1311
1312 rate_id_idx = ra->rate_id;
1313
1314 /*for compatibility issues with FW RA [PHYDM-405]*/
1315 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
1316 if (rate_id_idx == PHYDM_TYPE2_ARFR5_AC_2G_1SS)
1317 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1318 else if (rate_id_idx == PHYDM_TYPE2_ARFR3_AC_2G_2SS)
1319 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1320 }
1321
1322 h2c_val[0] = sta->mac_id;
1323 h2c_val[1] = (rate_id_idx & 0x1f) | ((init_ra_lv & 0x3) << 5) |
1324 (ra->is_support_sgi << 7);
1325 h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
1326 ((no_update_bw & 0x1) << 3) |
1327 (ra->is_vht_enable << 4) |
1328 ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
1329
1330 h2c_val[3] = (u8)(ra_mask & 0xff);
1331 h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
1332 h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
1333 h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
1334
1335 PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
1336 h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
1337 h2c_val[1], h2c_val[0]);
1338
1339 odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
1340
1341 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1342 if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
1343 h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
1344 h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
1345 h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
1346 h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
1347
1348 PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n",
1349 h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],
1350 h2c_val[2], h2c_val[1], h2c_val[0]);
1351
1352 odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS,
1353 H2C_MAX_LENGTH, h2c_val);
1354 }
1355 #endif
1356 }
1357
phydm_ra_registed(void * dm_void,u8 sta_idx,u8 rssi_from_assoc)1358 void phydm_ra_registed(void *dm_void, u8 sta_idx,
1359 /*@index of sta_info array, not MACID*/
1360 u8 rssi_from_assoc)
1361 {
1362 struct dm_struct *dm = (struct dm_struct *)dm_void;
1363 struct ra_table *ra_t = &dm->dm_ra_table;
1364 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1365 struct ra_sta_info *ra = NULL;
1366 u8 init_ra_lv = 0;
1367 u64 ra_mask = 0;
1368 /*@SD7 STA_idx != macid*/
1369 /*@SD4,8 STA_idx == macid, */
1370
1371 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
1372
1373 if (is_sta_active(sta)) {
1374 ra = &sta->ra_info;
1375 PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
1376 sta->mac_id);
1377 } else {
1378 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n",
1379 __func__);
1380 PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx);
1381 return;
1382 }
1383
1384 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1385 if (dm->support_ic_type == ODM_RTL8188E)
1386 ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);
1387 else
1388 #endif
1389 {
1390 ra->rate_id = phydm_get_rate_id(dm, sta_idx);
1391 }
1392
1393 ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
1394
1395 PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc);
1396
1397 if (rssi_from_assoc > 40)
1398 init_ra_lv = 1;
1399 else if (rssi_from_assoc > 20)
1400 init_ra_lv = 2;
1401 else if (rssi_from_assoc > 1)
1402 init_ra_lv = 3;
1403 else
1404 init_ra_lv = 0;
1405
1406 if (ra_t->record_ra_info)
1407 ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
1408
1409 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1410 if (dm->support_ic_type == ODM_RTL8188E)
1411 /*@Driver RA*/
1412 phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
1413 (u32)ra_mask, ra->is_support_sgi);
1414 else
1415 #endif
1416 {
1417 /*@FW RA*/
1418 phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,
1419 init_ra_lv, ra_mask);
1420 }
1421 }
1422
phydm_ra_offline(void * dm_void,u8 sta_idx)1423 void phydm_ra_offline(void *dm_void, u8 sta_idx)
1424 {
1425 struct dm_struct *dm = (struct dm_struct *)dm_void;
1426 struct ra_table *ra_t = &dm->dm_ra_table;
1427 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1428 struct ra_sta_info *ra = NULL;
1429
1430 if (is_sta_active(sta)) {
1431 ra = &sta->ra_info;
1432 } else {
1433 PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
1434 return;
1435 }
1436
1437 PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
1438 PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
1439
1440 odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));
1441 ra->disable_ra = 1;
1442 ra->disable_pt = 1;
1443
1444 if (ra_t->record_ra_info)
1445 ra_t->record_ra_info(dm, sta->mac_id, sta, 0);
1446
1447 if (dm->support_ic_type != ODM_RTL8188E)
1448 phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);
1449 }
1450
phydm_ra_mask_watchdog(void * dm_void)1451 void phydm_ra_mask_watchdog(void *dm_void)
1452 {
1453 struct dm_struct *dm = (struct dm_struct *)dm_void;
1454 struct ra_table *ra_t = &dm->dm_ra_table;
1455 struct cmn_sta_info *sta = NULL;
1456 struct ra_sta_info *ra = NULL;
1457 boolean force_ra_mask_en = false;
1458 u8 sta_idx;
1459 u64 ra_mask;
1460 u8 rssi_lv_new;
1461 u8 rssi = 0;
1462 #ifdef RA_MASK_BY_RX_UTILITY
1463 boolean mask_by_utility_en = false;
1464 #endif
1465
1466 if (!(dm->support_ability & ODM_BB_RA_MASK))
1467 return;
1468
1469 if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)
1470 return;
1471
1472 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
1473
1474 ra_t->up_ramask_cnt++;
1475
1476 if (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
1477 ra_t->up_ramask_cnt = 0;
1478 force_ra_mask_en = true;
1479 }
1480
1481 #ifdef RA_MASK_BY_RX_UTILITY
1482 if (dm->is_one_entry_only) {
1483 PHYDM_DBG(dm, DBG_RA_MASK, "rx_utility=%d, dis_mask_rx_utility_th=%d\n",
1484 dm->one_entry_rx_utility, ra_t->dis_mask_rx_utility_th);
1485
1486 if (dm->one_entry_rx_utility < ra_t->dis_mask_rx_utility_th &&
1487 dm->one_entry_rx_utility != 0) {
1488 mask_by_utility_en = true;
1489 }
1490 }
1491 #endif
1492
1493 for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
1494 sta = dm->phydm_sta_info[sta_idx];
1495
1496 if (!is_sta_active(sta))
1497 continue;
1498
1499 ra = &sta->ra_info;
1500
1501 if (ra->disable_ra)
1502 continue;
1503
1504 PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
1505 sta->mac_id);
1506
1507 rssi = (u8)(sta->rssi_stat.rssi);
1508
1509 /*@to be modified*/
1510 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
1511 if (dm->support_ic_type == ODM_RTL8812 ||
1512 (dm->support_ic_type == ODM_RTL8821 &&
1513 dm->cut_version == ODM_CUT_A)
1514 ) {
1515 if (rssi < ra_t->ldpc_thres) {
1516 /*@LDPC TX enable*/
1517 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1518 set_ra_ldpc_8812(sta, true);
1519 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1520 MgntSet_TX_LDPC(dm->adapter, sta->mac_id, true);
1521 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1522 /*to be added*/
1523 #endif
1524 PHYDM_DBG(dm, DBG_RA_MASK,
1525 "RSSI=%d, ldpc_en =TRUE\n", rssi);
1526
1527 } else if (rssi > (ra_t->ldpc_thres + 3)) {
1528 /*@LDPC TX disable*/
1529 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1530 set_ra_ldpc_8812(sta, false);
1531 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1532 MgntSet_TX_LDPC(dm->adapter, sta->mac_id, false);
1533 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1534 /*to be added*/
1535 #endif
1536 PHYDM_DBG(dm, DBG_RA_MASK,
1537 "RSSI=%d, ldpc_en =FALSE\n", rssi);
1538 }
1539 }
1540 #endif
1541
1542 rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
1543
1544 #ifdef RA_MASK_BY_RX_UTILITY
1545
1546 if (mask_by_utility_en) {
1547 if (rssi_lv_new > 1)
1548 rssi_lv_new = 1;
1549 }
1550 #endif
1551
1552 if (ra->rssi_level != rssi_lv_new ||
1553 (force_ra_mask_en && dm->number_linked_client < 10)) {
1554 PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
1555 ra->rssi_level, rssi_lv_new);
1556
1557 ra->rssi_level = rssi_lv_new;
1558
1559 ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
1560 PHYDM_DBG(dm, DBG_RA_MASK, "ra_mask=0x%llx\n", ra_mask);
1561
1562 if (ra_t->record_ra_info)
1563 ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
1564
1565 #if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)
1566 if (dm->support_ic_type == ODM_RTL8188E)
1567 /*@Driver RA*/
1568 phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
1569 (u32)ra_mask,
1570 ra->is_support_sgi);
1571 else
1572 #endif
1573 {
1574 /*@FW RA*/
1575 phydm_ra_h2c(dm, sta_idx, ra->disable_ra,
1576 ra->disable_pt, 1, 0, ra_mask);
1577 }
1578 }
1579 }
1580 }
1581
phydm_vht_en_mapping(void * dm_void,u32 wireless_mode)1582 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
1583 {
1584 struct dm_struct *dm = (struct dm_struct *)dm_void;
1585 u8 vht_en_out = 0;
1586
1587 if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||
1588 wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||
1589 wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
1590 vht_en_out = 1;
1591
1592 PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
1593 wireless_mode, vht_en_out);
1594 return vht_en_out;
1595 }
1596
phydm_rftype2rateid_2g_n20(void * dm_void,u8 rf_type)1597 u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)
1598 {
1599 u8 rate_id_idx = 0;
1600
1601 if (rf_type == RF_1T1R)
1602 rate_id_idx = PHYDM_BGN_20M_1SS;
1603 else if (rf_type == RF_2T2R)
1604 rate_id_idx = PHYDM_BGN_20M_2SS;
1605 else if (rf_type == RF_3T3R)
1606 rate_id_idx = PHYDM_ARFR5_N_3SS;
1607 else
1608 rate_id_idx = PHYDM_ARFR7_N_4SS;
1609 return rate_id_idx;
1610 }
1611
phydm_rftype2rateid_2g_n40(void * dm_void,u8 rf_type)1612 u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)
1613 {
1614 u8 rate_id_idx = 0;
1615
1616 if (rf_type == RF_1T1R)
1617 rate_id_idx = PHYDM_BGN_40M_1SS;
1618 else if (rf_type == RF_2T2R)
1619 rate_id_idx = PHYDM_BGN_40M_2SS;
1620 else if (rf_type == RF_3T3R)
1621 rate_id_idx = PHYDM_ARFR5_N_3SS;
1622 else
1623 rate_id_idx = PHYDM_ARFR7_N_4SS;
1624 return rate_id_idx;
1625 }
1626
phydm_rftype2rateid_5g_n(void * dm_void,u8 rf_type)1627 u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)
1628 {
1629 u8 rate_id_idx = 0;
1630
1631 if (rf_type == RF_1T1R)
1632 rate_id_idx = PHYDM_GN_N1SS;
1633 else if (rf_type == RF_2T2R)
1634 rate_id_idx = PHYDM_GN_N2SS;
1635 else if (rf_type == RF_3T3R)
1636 rate_id_idx = PHYDM_ARFR5_N_3SS;
1637 else
1638 rate_id_idx = PHYDM_ARFR7_N_4SS;
1639 return rate_id_idx;
1640 }
1641
phydm_rftype2rateid_ac80(void * dm_void,u8 rf_type)1642 u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)
1643 {
1644 u8 rate_id_idx = 0;
1645
1646 if (rf_type == RF_1T1R)
1647 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1648 else if (rf_type == RF_2T2R)
1649 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1650 else if (rf_type == RF_3T3R)
1651 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1652 else
1653 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1654 return rate_id_idx;
1655 }
1656
phydm_rftype2rateid_ac40(void * dm_void,u8 rf_type)1657 u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)
1658 {
1659 u8 rate_id_idx = 0;
1660
1661 if (rf_type == RF_1T1R)
1662 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1663 else if (rf_type == RF_2T2R)
1664 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1665 else if (rf_type == RF_3T3R)
1666 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1667 else
1668 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1669 return rate_id_idx;
1670 }
1671
phydm_rate_id_mapping(void * dm_void,u32 wireless_mode,u8 rf_type,u8 bw)1672 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
1673 {
1674 struct dm_struct *dm = (struct dm_struct *)dm_void;
1675 u8 rate_id_idx = 0;
1676
1677 PHYDM_DBG(dm, DBG_RA,
1678 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
1679 wireless_mode, rf_type, bw);
1680
1681 switch (wireless_mode) {
1682 case PHYDM_WIRELESS_MODE_N_24G:
1683 if (bw == CHANNEL_WIDTH_40)
1684 rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);
1685 else
1686 rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);
1687 break;
1688
1689 case PHYDM_WIRELESS_MODE_N_5G:
1690 rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);
1691 break;
1692
1693 case PHYDM_WIRELESS_MODE_G:
1694 rate_id_idx = PHYDM_BG;
1695 break;
1696
1697 case PHYDM_WIRELESS_MODE_A:
1698 rate_id_idx = PHYDM_G;
1699 break;
1700
1701 case PHYDM_WIRELESS_MODE_B:
1702 rate_id_idx = PHYDM_B_20M;
1703 break;
1704
1705 case PHYDM_WIRELESS_MODE_AC_5G:
1706 case PHYDM_WIRELESS_MODE_AC_ONLY:
1707 rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
1708 break;
1709
1710 case PHYDM_WIRELESS_MODE_AC_24G:
1711 /*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
1712 if (bw >= CHANNEL_WIDTH_80)
1713 rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
1714 else
1715 rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);
1716 break;
1717
1718 default:
1719 rate_id_idx = 0;
1720 break;
1721 }
1722
1723 PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx);
1724
1725 return rate_id_idx;
1726 }
1727
phydm_rssi_lv_dec(void * dm_void,u32 rssi,u8 ratr_state)1728 u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
1729 {
1730 struct dm_struct *dm = (struct dm_struct *)dm_void;
1731 /*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
1732 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
1733 u8 new_rssi_lv = 0;
1734 u8 i;
1735
1736 PHYDM_DBG(dm, DBG_RA_MASK,
1737 "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
1738 ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
1739 rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
1740
1741 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
1742 if (i >= (ratr_state))
1743 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
1744 }
1745
1746 PHYDM_DBG(dm, DBG_RA_MASK,
1747 "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
1748 rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
1749 rssi_lv_t[4], rssi_lv_t[5]);
1750
1751 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
1752 if (rssi < rssi_lv_t[i]) {
1753 new_rssi_lv = i;
1754 break;
1755 }
1756 }
1757 return new_rssi_lv;
1758 }
1759
phydm_get_ofdm_qam_order(void * dm_void,u8 rate_idx)1760 enum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx)
1761 {
1762 u8 tmp_idx = rate_idx;
1763 enum phydm_qam_order qam_order = PHYDM_QAM_BPSK;
1764 enum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK,
1765 PHYDM_QAM_QPSK, PHYDM_QAM_16QAM,
1766 PHYDM_QAM_16QAM, PHYDM_QAM_64QAM,
1767 PHYDM_QAM_64QAM, PHYDM_QAM_64QAM,
1768 PHYDM_QAM_256QAM, PHYDM_QAM_256QAM};
1769
1770 if (rate_idx <= ODM_RATE11M)
1771 return PHYDM_QAM_CCK;
1772
1773 if (rate_idx >= ODM_RATEVHTSS1MCS0) {
1774 if (rate_idx >= ODM_RATEVHTSS4MCS0)
1775 tmp_idx -= ODM_RATEVHTSS4MCS0;
1776 else if (rate_idx >= ODM_RATEVHTSS3MCS0)
1777 tmp_idx -= ODM_RATEVHTSS3MCS0;
1778 else if (rate_idx >= ODM_RATEVHTSS2MCS0)
1779 tmp_idx -= ODM_RATEVHTSS2MCS0;
1780 else
1781 tmp_idx -= ODM_RATEVHTSS1MCS0;
1782
1783 qam_order = qam[tmp_idx];
1784 } else if (rate_idx >= ODM_RATEMCS0) {
1785 if (rate_idx >= ODM_RATEMCS24)
1786 tmp_idx -= ODM_RATEMCS24;
1787 else if (rate_idx >= ODM_RATEMCS16)
1788 tmp_idx -= ODM_RATEMCS16;
1789 else if (rate_idx >= ODM_RATEMCS8)
1790 tmp_idx -= ODM_RATEMCS8;
1791 else
1792 tmp_idx -= ODM_RATEMCS0;
1793
1794 qam_order = qam[tmp_idx];
1795 } else {
1796 if (rate_idx > ODM_RATE6M) {
1797 tmp_idx -= ODM_RATE6M;
1798 qam_order = qam[tmp_idx - 1];
1799 } else {
1800 qam_order = PHYDM_QAM_BPSK;
1801 }
1802 }
1803
1804 return qam_order;
1805 }
1806
phydm_rate_order_compute(void * dm_void,u8 rate_idx)1807 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
1808 {
1809 u8 rate_order = rate_idx & 0x7f;
1810
1811 rate_idx &= 0x7f;
1812
1813 if (rate_idx >= ODM_RATEVHTSS4MCS0)
1814 rate_order -= ODM_RATEVHTSS4MCS0;
1815 else if (rate_idx >= ODM_RATEVHTSS3MCS0)
1816 rate_order -= ODM_RATEVHTSS3MCS0;
1817 else if (rate_idx >= ODM_RATEVHTSS2MCS0)
1818 rate_order -= ODM_RATEVHTSS2MCS0;
1819 else if (rate_idx >= ODM_RATEVHTSS1MCS0)
1820 rate_order -= ODM_RATEVHTSS1MCS0;
1821 else if (rate_idx >= ODM_RATEMCS24)
1822 rate_order -= ODM_RATEMCS24;
1823 else if (rate_idx >= ODM_RATEMCS16)
1824 rate_order -= ODM_RATEMCS16;
1825 else if (rate_idx >= ODM_RATEMCS8)
1826 rate_order -= ODM_RATEMCS8;
1827 else if (rate_idx >= ODM_RATEMCS0)
1828 rate_order -= ODM_RATEMCS0;
1829 else if (rate_idx >= ODM_RATE6M)
1830 rate_order -= ODM_RATE6M;
1831 else
1832 rate_order -= ODM_RATE1M;
1833
1834 if (rate_idx >= ODM_RATEMCS0)
1835 rate_order++;
1836
1837 return rate_order;
1838 }
1839
1840 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_rate2ss(void * dm_void,u8 rate_idx)1841 u8 phydm_rate2ss(void *dm_void, u8 rate_idx)
1842 {
1843 u8 ret = 0xff;
1844 u8 i, j;
1845 u8 search_idx;
1846 u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},
1847 {0x00000000, 0xffc00000, 0x0ff00000},
1848 {0x000003ff, 0x0000000f, 0xf0000000},
1849 {0x000ffc00, 0x00000ff0, 0x00000000} };
1850 if (rate_idx < 32) {
1851 search_idx = rate_idx;
1852 j = 0;
1853 } else if (rate_idx < 64) {
1854 search_idx = rate_idx - 32;
1855 j = 1;
1856 } else {
1857 search_idx = rate_idx - 64;
1858 j = 2;
1859 }
1860 for (i = 0; i < 4; i++)
1861 if (ss_mapping_tab[i][j] & BIT(search_idx))
1862 ret = i;
1863 return ret;
1864 }
1865
phydm_rate2plcp(void * dm_void,u8 rate_idx)1866 u8 phydm_rate2plcp(void *dm_void, u8 rate_idx)
1867 {
1868 u8 rate2ss = 0;
1869 u8 ltftime = 0;
1870 u8 plcptime = 0xff;
1871
1872 if (rate_idx < ODM_RATE6M) {
1873 plcptime = 192;
1874 /* @CCK PLCP = 192us (long preamble) */
1875 } else if (rate_idx < ODM_RATEMCS0) {
1876 plcptime = 20;
1877 /* @LegOFDM PLCP = 20us */
1878 } else {
1879 if (rate_idx < ODM_RATEVHTSS1MCS0)
1880 plcptime = 32;
1881 /* @HT mode PLCP = 20us + 12us + 4us x Nss */
1882 else
1883 plcptime = 36;
1884 /* VHT mode PLCP = 20us + 16us + 4us x Nss */
1885 rate2ss = phydm_rate2ss(dm_void, rate_idx);
1886 if (rate2ss != 0xff)
1887 ltftime = (rate2ss + 1) * 4;
1888 else
1889 return 0xff;
1890
1891 plcptime += ltftime;
1892 }
1893 return plcptime;
1894 }
1895
phydm_get_plcp(void * dm_void,u16 macid)1896 u8 phydm_get_plcp(void *dm_void, u16 macid)
1897 {
1898 u8 plcp_time = 0;
1899 struct dm_struct *dm = (struct dm_struct *)dm_void;
1900 struct cmn_sta_info *sta = NULL;
1901 struct ra_sta_info *ra = NULL;
1902
1903 sta = dm->phydm_sta_info[macid];
1904 ra = &sta->ra_info;
1905 plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);
1906 return plcp_time;
1907 }
1908 #endif
1909
phydm_ra_common_info_update(void * dm_void)1910 void phydm_ra_common_info_update(void *dm_void)
1911 {
1912 struct dm_struct *dm = (struct dm_struct *)dm_void;
1913 struct ra_table *ra_tab = &dm->dm_ra_table;
1914 struct cmn_sta_info *sta = NULL;
1915 u16 macid;
1916 u8 rate_order_tmp;
1917 u8 rate_idx = 0;
1918 u8 cnt = 0;
1919
1920 ra_tab->highest_client_tx_order = 0;
1921 ra_tab->power_tracking_flag = 1;
1922
1923 if (!dm->number_linked_client)
1924 return;
1925
1926 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
1927 sta = dm->phydm_sta_info[macid];
1928
1929 if (!is_sta_active(sta))
1930 continue;
1931
1932 rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
1933 rate_order_tmp = phydm_rate_order_compute(dm, rate_idx);
1934
1935 if (rate_order_tmp >= ra_tab->highest_client_tx_order) {
1936 ra_tab->highest_client_tx_order = rate_order_tmp;
1937 ra_tab->highest_client_tx_rate_order = macid;
1938 }
1939
1940 cnt++;
1941
1942 if (cnt == dm->number_linked_client)
1943 break;
1944 }
1945 PHYDM_DBG(dm, DBG_RA,
1946 "MACID[%d], Highest Tx order Update for power traking: %d\n",
1947 ra_tab->highest_client_tx_rate_order,
1948 ra_tab->highest_client_tx_order);
1949 }
1950
phydm_rrsr_set_register(void * dm_void,u32 rrsr_val)1951 void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val)
1952 {
1953 struct dm_struct *dm = (struct dm_struct *)dm_void;
1954
1955 odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
1956 }
1957
phydm_masked_rrsr_set_register(void * dm_void,u32 rrsr_val)1958 void phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val)
1959 {
1960 struct dm_struct *dm = (struct dm_struct *)dm_void;
1961 struct ra_table *ra_tab = &dm->dm_ra_table;
1962
1963 if (ra_tab->rrsr_val_curr == rrsr_val)
1964 return;
1965
1966 ra_tab->rrsr_val_curr = rrsr_val;
1967 odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
1968 }
1969
phydm_rrsr_mask(void * dm_void)1970 void phydm_rrsr_mask(void *dm_void)
1971 {
1972 struct dm_struct *dm = (struct dm_struct *)dm_void;
1973 struct ra_table *ra = &dm->dm_ra_table;
1974 struct cmn_sta_info *sta = NULL;
1975 u8 rate_order = 0;
1976 u8 rate_order_min = 0xff;
1977 u32 rrsr_mask = 0, rrsr_mask_ofdm = 0;
1978 u8 tx_rate_idx = 0;
1979 u8 i = 0, sta_cnt = 0;
1980
1981 if (!ra->dynamic_rrsr_en)
1982 return;
1983
1984 if (!dm->is_linked) {
1985 phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init);
1986 return;
1987 }
1988
1989 #if 1
1990 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1991 sta = dm->phydm_sta_info[i];
1992 if (!is_sta_active(sta))
1993 continue;
1994
1995 sta_cnt++;
1996 tx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
1997 rate_order = phydm_rate_order_compute(dm, tx_rate_idx);
1998 if (rate_order < rate_order_min)
1999 rate_order_min = rate_order;
2000
2001 if (sta_cnt == dm->number_linked_client)
2002 break;
2003 }
2004 #else
2005 sta = dm->phydm_sta_info[dm->rssi_min_macid];
2006
2007 if (!is_sta_active(sta)) {
2008 PHYDM_DBG(dm, DBG_DYN_ARFR, "[Warning] %s invalid STA\n",
2009 __func__);
2010 return;
2011 }
2012
2013 rate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate);
2014 #endif
2015 if (rate_order_min == 0) {
2016 rrsr_mask = 0x1f;
2017 } else {
2018 rrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min);
2019 rrsr_mask = (rrsr_mask_ofdm << 4) | 0xf;
2020 }
2021
2022 /*ra->rrsr_val_init = 0x15d;*/
2023
2024 phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask);
2025
2026 PHYDM_DBG(dm, DBG_DYN_ARFR,
2027 "tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\n",
2028 tx_rate_idx, rate_order_min, ra->rrsr_val_init,
2029 rrsr_mask, ra->rrsr_val_curr);
2030 }
2031
phydm_ra_info_watchdog(void * dm_void)2032 void phydm_ra_info_watchdog(void *dm_void)
2033 {
2034 struct dm_struct *dm = (struct dm_struct *)dm_void;
2035
2036 phydm_ra_common_info_update(dm);
2037 phydm_ra_dynamic_retry_count(dm);
2038 phydm_rrsr_mask(dm);
2039 phydm_ra_mask_watchdog(dm);
2040
2041 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2042 odm_refresh_basic_rate_mask(dm);
2043 #endif
2044 }
2045
phydm_rrsr_en(void * dm_void,boolean en_rrsr)2046 void phydm_rrsr_en(void *dm_void, boolean en_rrsr)
2047 {
2048 struct dm_struct *dm = (struct dm_struct *)dm_void;
2049 struct ra_table *ra_tab = &dm->dm_ra_table;
2050
2051 ra_tab->dynamic_rrsr_en = en_rrsr;
2052 }
2053
phydm_arfr_table_init(void * dm_void)2054 void phydm_arfr_table_init(void *dm_void)
2055 {
2056 struct dm_struct *dm = (struct dm_struct *)dm_void;
2057
2058 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
2059 /*ARFR table3(2.4g ac 2ss) for rate_id = 16*/
2060 odm_set_mac_reg(dm, R_0x494, MASKDWORD, 0xfe01f015);
2061 odm_set_mac_reg(dm, R_0x498, MASKDWORD, 0x40000000);
2062
2063 /*ARFR table5(2.4g ac 1ss) for rate_id = 18*/
2064 odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0x3ff015);
2065 odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x40000000);
2066 }
2067 }
2068
phydm_ra_info_init(void * dm_void)2069 void phydm_ra_info_init(void *dm_void)
2070 {
2071 struct dm_struct *dm = (struct dm_struct *)dm_void;
2072 struct ra_table *ra_tab = &dm->dm_ra_table;
2073
2074 ra_tab->highest_client_tx_rate_order = 0;
2075 ra_tab->highest_client_tx_order = 0;
2076 ra_tab->ra_th_ofst = 0;
2077 ra_tab->ra_ofst_direc = 0;
2078 ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);
2079 ra_tab->ra_trigger_mode = 1; // default TBTT RA
2080 ra_tab->ra_tx_cls_th = 255;
2081 #ifdef RA_MASK_BY_RX_UTILITY
2082 ra_tab->dis_mask_rx_utility_th = 80;
2083 #endif
2084 #if (RTL8822B_SUPPORT == 1)
2085 if (dm->support_ic_type == ODM_RTL8822B) {
2086 u32 ret_value;
2087
2088 ret_value = odm_get_mac_reg(dm, R_0x4c8, MASKBYTE2);
2089 odm_set_mac_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
2090 }
2091 #endif
2092
2093 #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
2094 phydm_ra_dynamic_retry_limit_init(dm);
2095 #endif
2096
2097 #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
2098 phydm_ra_dynamic_rate_id_init(dm);
2099 #endif
2100
2101 phydm_arfr_table_init(dm);
2102
2103 phydm_rate_adaptive_mask_init(dm);
2104 }
2105
odm_find_rts_rate(void * dm_void,u8 tx_rate,boolean is_erp_protect)2106 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)
2107 {
2108 struct dm_struct *dm = (struct dm_struct *)dm_void;
2109 u8 rts_ini_rate = ODM_RATE6M;
2110
2111 if (is_erp_protect) { /* use CCK rate as RTS*/
2112 rts_ini_rate = ODM_RATE1M;
2113 } else {
2114 switch (tx_rate) {
2115 case ODM_RATEVHTSS4MCS9:
2116 case ODM_RATEVHTSS4MCS8:
2117 case ODM_RATEVHTSS4MCS7:
2118 case ODM_RATEVHTSS4MCS6:
2119 case ODM_RATEVHTSS4MCS5:
2120 case ODM_RATEVHTSS4MCS4:
2121 case ODM_RATEVHTSS4MCS3:
2122 case ODM_RATEVHTSS3MCS9:
2123 case ODM_RATEVHTSS3MCS8:
2124 case ODM_RATEVHTSS3MCS7:
2125 case ODM_RATEVHTSS3MCS6:
2126 case ODM_RATEVHTSS3MCS5:
2127 case ODM_RATEVHTSS3MCS4:
2128 case ODM_RATEVHTSS3MCS3:
2129 case ODM_RATEVHTSS2MCS9:
2130 case ODM_RATEVHTSS2MCS8:
2131 case ODM_RATEVHTSS2MCS7:
2132 case ODM_RATEVHTSS2MCS6:
2133 case ODM_RATEVHTSS2MCS5:
2134 case ODM_RATEVHTSS2MCS4:
2135 case ODM_RATEVHTSS2MCS3:
2136 case ODM_RATEVHTSS1MCS9:
2137 case ODM_RATEVHTSS1MCS8:
2138 case ODM_RATEVHTSS1MCS7:
2139 case ODM_RATEVHTSS1MCS6:
2140 case ODM_RATEVHTSS1MCS5:
2141 case ODM_RATEVHTSS1MCS4:
2142 case ODM_RATEVHTSS1MCS3:
2143 case ODM_RATEMCS31:
2144 case ODM_RATEMCS30:
2145 case ODM_RATEMCS29:
2146 case ODM_RATEMCS28:
2147 case ODM_RATEMCS27:
2148 case ODM_RATEMCS23:
2149 case ODM_RATEMCS22:
2150 case ODM_RATEMCS21:
2151 case ODM_RATEMCS20:
2152 case ODM_RATEMCS19:
2153 case ODM_RATEMCS15:
2154 case ODM_RATEMCS14:
2155 case ODM_RATEMCS13:
2156 case ODM_RATEMCS12:
2157 case ODM_RATEMCS11:
2158 case ODM_RATEMCS7:
2159 case ODM_RATEMCS6:
2160 case ODM_RATEMCS5:
2161 case ODM_RATEMCS4:
2162 case ODM_RATEMCS3:
2163 case ODM_RATE54M:
2164 case ODM_RATE48M:
2165 case ODM_RATE36M:
2166 case ODM_RATE24M:
2167 rts_ini_rate = ODM_RATE24M;
2168 break;
2169 case ODM_RATEVHTSS4MCS2:
2170 case ODM_RATEVHTSS4MCS1:
2171 case ODM_RATEVHTSS3MCS2:
2172 case ODM_RATEVHTSS3MCS1:
2173 case ODM_RATEVHTSS2MCS2:
2174 case ODM_RATEVHTSS2MCS1:
2175 case ODM_RATEVHTSS1MCS2:
2176 case ODM_RATEVHTSS1MCS1:
2177 case ODM_RATEMCS26:
2178 case ODM_RATEMCS25:
2179 case ODM_RATEMCS18:
2180 case ODM_RATEMCS17:
2181 case ODM_RATEMCS10:
2182 case ODM_RATEMCS9:
2183 case ODM_RATEMCS2:
2184 case ODM_RATEMCS1:
2185 case ODM_RATE18M:
2186 case ODM_RATE12M:
2187 rts_ini_rate = ODM_RATE12M;
2188 break;
2189 case ODM_RATEVHTSS4MCS0:
2190 case ODM_RATEVHTSS3MCS0:
2191 case ODM_RATEVHTSS2MCS0:
2192 case ODM_RATEVHTSS1MCS0:
2193 case ODM_RATEMCS24:
2194 case ODM_RATEMCS16:
2195 case ODM_RATEMCS8:
2196 case ODM_RATEMCS0:
2197 case ODM_RATE9M:
2198 case ODM_RATE6M:
2199 rts_ini_rate = ODM_RATE6M;
2200 break;
2201 case ODM_RATE11M:
2202 case ODM_RATE5_5M:
2203 case ODM_RATE2M:
2204 case ODM_RATE1M:
2205 rts_ini_rate = ODM_RATE1M;
2206 break;
2207 default:
2208 rts_ini_rate = ODM_RATE6M;
2209 break;
2210 }
2211 }
2212
2213 if (*dm->band_type == ODM_BAND_5G) {
2214 if (rts_ini_rate < ODM_RATE6M)
2215 rts_ini_rate = ODM_RATE6M;
2216 }
2217 return rts_ini_rate;
2218 }
2219
2220 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2221
odm_refresh_basic_rate_mask(void * dm_void)2222 void odm_refresh_basic_rate_mask(
2223 void *dm_void)
2224 {
2225 struct dm_struct *dm = (struct dm_struct *)dm_void;
2226 void *adapter = dm->adapter;
2227 static u8 stage = 0;
2228 u8 cur_stage = 0;
2229 OCTET_STRING os_rate_set;
2230 PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));
2231 u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
2232
2233 if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)
2234 return;
2235
2236 if (dm->is_linked == false) /* unlink Default port information */
2237 cur_stage = 0;
2238 else if (dm->rssi_min < 40) /* @link RSSI < 40% */
2239 cur_stage = 1;
2240 else if (dm->rssi_min > 45) /* @link RSSI > 45% */
2241 cur_stage = 3;
2242 else
2243 cur_stage = 2; /* @link 25% <= RSSI <= 30% */
2244
2245 if (cur_stage != stage) {
2246 if (cur_stage == 1) {
2247 FillOctetString(os_rate_set, rate_set, 5);
2248 FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);
2249 phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
2250 } else if (cur_stage == 3 && (stage == 1 || stage == 2))
2251 phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));
2252 }
2253
2254 stage = cur_stage;
2255 }
2256
2257 #endif
2258
2259 #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
2260
2261 void phydm_retry_limit_table_bound(
2262 void *dm_void,
2263 u8 *retry_limit,
2264 u8 offset)
2265 {
2266 struct dm_struct *dm = (struct dm_struct *)dm_void;
2267 struct ra_table *ra_tab = &dm->dm_ra_table;
2268
2269 if (*retry_limit > offset) {
2270 *retry_limit -= offset;
2271
2272 if (*retry_limit < ra_tab->retrylimit_low)
2273 *retry_limit = ra_tab->retrylimit_low;
2274 else if (*retry_limit > ra_tab->retrylimit_high)
2275 *retry_limit = ra_tab->retrylimit_high;
2276 } else
2277 *retry_limit = ra_tab->retrylimit_low;
2278 }
2279
2280 void phydm_reset_retry_limit_table(
2281 void *dm_void)
2282 {
2283 struct dm_struct *dm = (struct dm_struct *)dm_void;
2284 struct ra_table *ra_t = &dm->dm_ra_table;
2285 u8 i;
2286
2287 u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
2288 1, 1, 2, 4, /*@CCK*/
2289 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
2290 2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/
2291 2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/
2292 };
2293 u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
2294 1, 1, 2, 4, /*@CCK*/
2295 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
2296 4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/
2297 4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/
2298 };
2299
2300 memcpy(&ra_t->per_rate_retrylimit_20M[0],
2301 &per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX);
2302 memcpy(&ra_t->per_rate_retrylimit_40M[0],
2303 &per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX);
2304
2305 for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
2306 phydm_retry_limit_table_bound(dm,
2307 &ra_t->per_rate_retrylimit_20M[i],
2308 0);
2309 phydm_retry_limit_table_bound(dm,
2310 &ra_t->per_rate_retrylimit_40M[i],
2311 0);
2312 }
2313 }
2314
2315 void phydm_ra_dynamic_retry_limit_init(
2316 void *dm_void)
2317 {
2318 struct dm_struct *dm = (struct dm_struct *)dm_void;
2319 struct ra_table *ra_tab = &dm->dm_ra_table;
2320
2321 ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;
2322 ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;
2323 ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;
2324
2325 phydm_reset_retry_limit_table(dm);
2326 }
2327
2328 void phydm_ra_dynamic_retry_limit(
2329 void *dm_void)
2330 {
2331 struct dm_struct *dm = (struct dm_struct *)dm_void;
2332 struct ra_table *ra_tab = &dm->dm_ra_table;
2333 u8 i, retry_offset;
2334 u32 ma_rx_tp;
2335
2336 if (dm->pre_number_active_client == dm->number_active_client) {
2337 PHYDM_DBG(dm, DBG_RA,
2338 "pre_number_active_client == number_active_client\n");
2339 return;
2340
2341 } else {
2342 if (dm->number_active_client == 1) {
2343 phydm_reset_retry_limit_table(dm);
2344 PHYDM_DBG(dm, DBG_RA,
2345 "one client only->reset to default value\n");
2346 } else {
2347 retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
2348
2349 for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
2350 phydm_retry_limit_table_bound(dm,
2351 &ra_tab->per_rate_retrylimit_20M[i],
2352 retry_offset);
2353 phydm_retry_limit_table_bound(dm,
2354 &ra_tab->per_rate_retrylimit_40M[i],
2355 retry_offset);
2356 }
2357 }
2358 }
2359 }
2360 #endif
2361
2362 #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
2363 void phydm_ra_dynamic_rate_id_on_assoc(
2364 void *dm_void,
2365 u8 wireless_mode,
2366 u8 init_rate_id)
2367 {
2368 struct dm_struct *dm = (struct dm_struct *)dm_void;
2369
2370 PHYDM_DBG(dm, DBG_RA,
2371 "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n",
2372 dm->rf_type, wireless_mode, init_rate_id);
2373
2374 if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
2375 if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
2376 (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {
2377 PHYDM_DBG(dm, DBG_RA,
2378 "[ON ASSOC] set N-2SS ARFR5 table\n");
2379 odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
2380 odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
2381 } else if ((dm->support_ic_type & (ODM_RTL8812)) &&
2382 (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {
2383 PHYDM_DBG(dm, DBG_RA,
2384 "[ON ASSOC] set AC-2SS ARFR0 table\n");
2385 odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2386 odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2387 }
2388 }
2389 }
2390
2391 void phydm_ra_dynamic_rate_id_init(
2392 void *dm_void)
2393 {
2394 struct dm_struct *dm = (struct dm_struct *)dm_void;
2395
2396 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
2397 odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
2398 odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
2399
2400 odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2401 odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2402 }
2403 }
2404
2405 void phydm_update_rate_id(
2406 void *dm_void,
2407 u8 rate,
2408 u8 platform_macid)
2409 {
2410 #if 0
2411
2412 struct dm_struct *dm = (struct dm_struct *)dm_void;
2413 struct ra_table *ra_tab = &dm->dm_ra_table;
2414 u8 current_tx_ss;
2415 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
2416 enum wireless_set wireless_set;
2417 u8 phydm_macid;
2418 struct cmn_sta_info *sta;
2419
2420 #if 0
2421 if (rate_idx >= ODM_RATEVHTSS2MCS0) {
2422 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n",
2423 platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));
2424 /*@dummy for SD4 check patch*/
2425 } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
2426 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n",
2427 platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));
2428 /*@dummy for SD4 check patch*/
2429 } else if (rate_idx >= ODM_RATEMCS0) {
2430 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
2431 platform_macid, (rate_idx - ODM_RATEMCS0));
2432 /*@dummy for SD4 check patch*/
2433 } else {
2434 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
2435 platform_macid, rate_idx);
2436 /*@dummy for SD4 check patch*/
2437 }
2438 #endif
2439
2440 phydm_macid = dm->phydm_macid_table[platform_macid];
2441 sta = dm->phydm_sta_info[phydm_macid];
2442
2443 if (is_sta_active(sta)) {
2444 wireless_set = sta->support_wireless_set;
2445
2446 if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
2447 if (wireless_set & WIRELESS_HT) { /*N mode*/
2448 if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/
2449
2450 sta->ra_info.rate_id = ARFR_5_RATE_ID;
2451 PHYDM_DBG(dm, DBG_RA, "ARFR_5\n");
2452 }
2453 } else if (wireless_set & WIRELESS_VHT) {/*@AC mode*/
2454 if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/
2455
2456 sta->ra_info.rate_id = ARFR_0_RATE_ID;
2457 PHYDM_DBG(dm, DBG_RA, "ARFR_0\n");
2458 }
2459 } else
2460 sta->ra_info.rate_id = ARFR_0_RATE_ID;
2461
2462 PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n",
2463 platform_macid, sta->ra_info.rate_id);
2464 }
2465 }
2466 #endif
2467 }
2468
2469 #endif
2470