1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /******************************************************************************
27 * include files
28 *****************************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 #ifdef CONFIG_PSD_TOOL
phydm_get_psd_data(void * dm_void,u32 psd_tone_idx,u32 igi)33 u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
34 {
35 struct dm_struct *dm = (struct dm_struct *)dm_void;
36 struct psd_info *dm_psd_table = &dm->dm_psd_table;
37 u32 psd_report = 0;
38
39 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
40 #if 0
41 odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
42 odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
43 psd_tone_idx >> 10);
44 /*PSD trigger start*/
45 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
46 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
47 /*PSD trigger stop*/
48 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
49 #endif
50 } else if (dm->support_ic_type & (ODM_RTL8721D |
51 ODM_RTL8710C)) {
52 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
53 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
54 /*PSD trigger start*/
55 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
56 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
57 /*PSD trigger stop*/
58 } else {
59 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
60 /*PSD trigger start*/
61 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
62 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
63 /*PSD trigger stop*/
64 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
65 }
66
67 /*Get PSD Report*/
68 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
69 ODM_RTL8710C)) {
70 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
71 0xffffff);
72 psd_report = psd_report >> 5;
73 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
74 #if 0
75 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
76 0xffffff);
77 #endif
78 } else {
79 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
80 0xffff);
81 }
82 psd_report = odm_convert_to_db((u64)psd_report) + igi;
83
84 return psd_report;
85 }
86
87 u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
88 u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
89
phydm_psd(void * dm_void,u32 igi,u16 start_point,u16 stop_point)90 u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
91 {
92 struct dm_struct *dm = (struct dm_struct *)dm_void;
93 struct psd_info *dm_psd_table = &dm->dm_psd_table;
94 u32 i = 0, mod_tone_idx = 0;
95 u32 t = 0;
96 u16 fft_max_half_bw = 0;
97 u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
98 u8 ag_rf_mode_reg = 0;
99 u8 is_5G = 0;
100 u32 psd_result_tmp = 0;
101 u8 psd_result = 0;
102 u8 psd_result_cali_tone[7] = {0};
103 u8 psd_result_cali_val[7] = {0};
104 u8 noise_idx = 0;
105 u8 set_result = 0;
106 u32 igi_tmp = 0x6e;
107
108 if (dm->support_ic_type == ODM_RTL8821) {
109 odm_move_memory(dm, psd_result_cali_tone,
110 psd_result_cali_tone_8821, 7);
111 odm_move_memory(dm, psd_result_cali_val,
112 psd_result_cali_val_8821, 7);
113 }
114
115 dm_psd_table->psd_in_progress = 1;
116
117 PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
118
119 /* @[Stop DIG]*/
120 /* @IGI target at 0dBm & make it can't CCA*/
121 if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,
122 &igi_tmp) == PAUSE_FAIL) {
123 return PHYDM_SET_FAIL;
124 }
125
126 ODM_delay_us(10);
127
128 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
129 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,
130 1, &igi_tmp);
131 return PHYDM_SET_FAIL;
132 }
133
134 /* @[Set IGI]*/
135 phydm_write_dig_reg(dm, (u8)igi);
136
137 /* @[Backup RF Reg]*/
138 dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
139 RFREG_MASK);
140 dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
141 RFREG_MASK);
142
143 if (psd_fc_channel > 14) {
144 is_5G = 1;
145 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
146 ODM_RTL8197G)) {
147 #if 0
148 if (psd_fc_channel < 80)
149 ag_rf_mode_reg = 0x1;
150 else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
151 ag_rf_mode_reg = 0x3;
152 else if (psd_fc_channel > 140)
153 ag_rf_mode_reg = 0x5;
154 #endif
155 } else if (dm->support_ic_type == ODM_RTL8721D) {
156 if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
157 ag_rf_mode_reg = 0x1;
158 else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
159 ag_rf_mode_reg = 0x5;
160 else if (psd_fc_channel > 140)
161 ag_rf_mode_reg = 0x9;
162 } else {
163 if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
164 ag_rf_mode_reg = 0x1;
165 else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
166 ag_rf_mode_reg = 0x3;
167 else if (psd_fc_channel > 140)
168 ag_rf_mode_reg = 0x5;
169 }
170 }
171
172 /* Set RF fc*/
173 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);
174 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
175 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
176 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
177 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
178 ODM_RTL8197G)) {
179 #if 0
180 /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
181 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
182 dm_psd_table->psd_bw_rf_reg);
183 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,
184 dm_psd_table->psd_bw_rf_reg);
185 /* Set RF ag fc mode*/
186 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,
187 ag_rf_mode_reg);
188 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
189 ag_rf_mode_reg);
190 #endif
191 } else {
192 /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
193 if (dm->support_ic_type == ODM_RTL8721D) {
194 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
195 dm_psd_table->psd_bw_rf_reg);
196 #if (RTL8710C_SUPPORT == 1)
197 } else if (dm->support_ic_type == ODM_RTL8710C) {
198 odm_set_rf_reg(dm, RF_PATH_A,
199 RF_0x18, 0x1c00,
200 dm_psd_table->psd_bw_rf_reg);
201 #endif
202 } else {
203 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
204 dm_psd_table->psd_bw_rf_reg);
205 }
206 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
207 dm_psd_table->psd_bw_rf_reg);
208 /* Set RF ag fc mode*/
209 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,
210 ag_rf_mode_reg);
211 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
212 ag_rf_mode_reg);
213 }
214
215 #if 0
216 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
217 PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
218 odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
219 else
220 #endif
221 PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
222 odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
223
224 PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
225 odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));
226
227 /* @[Stop 3-wires]*/
228 phydm_stop_3_wire(dm, PHYDM_SET);
229
230 ODM_delay_us(10);
231
232 if (stop_point > (dm_psd_table->fft_smp_point - 1))
233 stop_point = (dm_psd_table->fft_smp_point - 1);
234
235 if (start_point > (dm_psd_table->fft_smp_point - 1))
236 start_point = (dm_psd_table->fft_smp_point - 1);
237
238 if (start_point > stop_point)
239 stop_point = start_point;
240
241 for (i = start_point; i <= stop_point; i++) {
242 fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
243
244 if (i < fft_max_half_bw)
245 mod_tone_idx = i + fft_max_half_bw;
246 else
247 mod_tone_idx = i - fft_max_half_bw;
248
249 psd_result_tmp = 0;
250 for (t = 0; t < dm_psd_table->sw_avg_time; t++)
251 psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
252 igi);
253 psd_result =
254 (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
255 dm_psd_table->psd_pwr_common_offset;
256
257 if (dm_psd_table->fft_smp_point == 128 &&
258 dm_psd_table->noise_k_en) {
259 if (i > psd_result_cali_tone[noise_idx])
260 noise_idx++;
261
262 if (noise_idx > 6)
263 noise_idx = 6;
264
265 if (psd_result >= psd_result_cali_val[noise_idx])
266 psd_result = psd_result -
267 psd_result_cali_val[noise_idx];
268 else
269 psd_result = 0;
270
271 dm_psd_table->psd_result[i] = psd_result;
272 }
273
274 PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
275 mod_tone_idx, psd_result_cali_val[noise_idx],
276 psd_result);
277 }
278
279 /*@[Start 3-wires]*/
280 phydm_stop_3_wire(dm, PHYDM_REVERT);
281
282 ODM_delay_us(10);
283
284 /*@[Revert Reg]*/
285 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
286
287 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,
288 dm_psd_table->rf_0x18_bkp);
289 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,
290 dm_psd_table->rf_0x18_bkp_b);
291
292 PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
293
294 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,
295 &igi_tmp);
296 dm_psd_table->psd_in_progress = 0;
297
298 return PHYDM_SET_SUCCESS;
299 }
300
phydm_psd_para_setting(void * dm_void,u8 sw_avg_time,u8 hw_avg_time,u8 i_q_setting,u16 fft_smp_point,u8 ant_sel,u8 psd_input,u8 channel,u8 noise_k_en)301 void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
302 u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
303 u8 psd_input, u8 channel, u8 noise_k_en)
304 {
305 struct dm_struct *dm = (struct dm_struct *)dm_void;
306 struct psd_info *dm_psd_table = &dm->dm_psd_table;
307 u8 fft_smp_point_idx = 0;
308
309 dm_psd_table->fft_smp_point = fft_smp_point;
310
311 if (sw_avg_time == 0)
312 sw_avg_time = 1;
313
314 dm_psd_table->sw_avg_time = sw_avg_time;
315 dm_psd_table->psd_fc_channel = channel;
316 dm_psd_table->noise_k_en = noise_k_en;
317
318 if (fft_smp_point == 128)
319 fft_smp_point_idx = 0;
320 else if (fft_smp_point == 256)
321 fft_smp_point_idx = 1;
322 else if (fft_smp_point == 512)
323 fft_smp_point_idx = 2;
324 else if (fft_smp_point == 1024)
325 fft_smp_point_idx = 3;
326
327 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
328 #if 0
329 odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
330 odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);
331
332 if (fft_smp_point == 4096) {
333 odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);
334 } else if (fft_smp_point == 2048) {
335 odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);
336 } else {
337 odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);
338 odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),
339 fft_smp_point_idx);
340 }
341 odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
342 odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
343 #endif
344 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
345 odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
346 odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
347 odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
348 fft_smp_point_idx);
349 odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
350 odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
351 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
352 odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting);
353 odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time);
354 odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22),
355 fft_smp_point_idx);
356 odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel);
357 odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input);
358
359 #if 0
360 } else { /*ODM_IC_11N_SERIES*/
361 #endif
362 }
363 /*@bw = (*dm->band_width); //ODM_BW20M */
364 /*@channel = *(dm->channel);*/
365 }
366
phydm_psd_init(void * dm_void)367 void phydm_psd_init(void *dm_void)
368 {
369 struct dm_struct *dm = (struct dm_struct *)dm_void;
370 struct psd_info *dm_psd_table = &dm->dm_psd_table;
371
372 PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
373
374 dm_psd_table->psd_in_progress = false;
375
376 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
377 #if 0
378 dm_psd_table->psd_reg = R_0x1e8c;
379 dm_psd_table->psd_report_reg = R_0x2d90;
380
381 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
382 dm_psd_table->psd_bw_rf_reg = 1;
383 #endif
384
385 return;
386 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
387 dm_psd_table->psd_reg = R_0x910;
388 dm_psd_table->psd_report_reg = R_0xf44;
389
390 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
391 if (ODM_IC_11AC_2_SERIES)
392 dm_psd_table->psd_bw_rf_reg = 1;
393 else
394 dm_psd_table->psd_bw_rf_reg = 2;
395 } else {
396 dm_psd_table->psd_reg = R_0x808;
397 dm_psd_table->psd_report_reg = R_0x8b4;
398 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
399 dm_psd_table->psd_bw_rf_reg = 2;
400 }
401
402 dm_psd_table->psd_pwr_common_offset = 0;
403
404 phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
405 #if 0
406 /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
407 #endif
408 }
409
phydm_psd_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)410 void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
411 char *output, u32 *_out_len)
412 {
413 struct dm_struct *dm = (struct dm_struct *)dm_void;
414 char help[] = "-h";
415 u32 var1[10] = {0};
416 u32 used = *_used;
417 u32 out_len = *_out_len;
418 u8 i = 0;
419
420 if ((strcmp(input[1], help) == 0)) {
421 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
422 #if 0
423 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
424 PDM_SNPF(out_len, used, output + used, out_len - used,
425 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
426 else
427 #endif
428 #endif
429 PDM_SNPF(out_len, used, output + used, out_len - used,
430 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
431
432 PDM_SNPF(out_len, used, output + used, out_len - used,
433 "{1} {IGI(hex)} {start_point} {stop_point}\n");
434 goto out;
435 }
436
437 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
438
439 if (var1[0] == 0) {
440 for (i = 1; i < 10; i++) {
441 if (input[i + 1])
442 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
443 &var1[i]);
444 }
445 PDM_SNPF(out_len, used, output + used, out_len - used,
446 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
447 var1[1], var1[2], var1[3], var1[4], var1[5],
448 var1[6], (u8)var1[7], (u8)var1[8]);
449 phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
450 (u8)var1[3], (u16)var1[4],
451 (u8)var1[5], (u8)var1[6],
452 (u8)var1[7], (u8)var1[8]);
453
454 } else if (var1[0] == 1) {
455 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
456 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
457 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
458 PDM_SNPF(out_len, used, output + used, out_len - used,
459 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
460 var1[1], var1[2], var1[3]);
461 dm->debug_components |= ODM_COMP_API;
462 if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==
463 PHYDM_SET_FAIL)
464 PDM_SNPF(out_len, used, output + used, out_len - used,
465 "PSD_SET_FAIL\n");
466 dm->debug_components &= ~(ODM_COMP_API);
467 }
468
469 out:
470 *_used = used;
471 *_out_len = out_len;
472 }
473
phydm_get_psd_result_table(void * dm_void,int index)474 u8 phydm_get_psd_result_table(void *dm_void, int index)
475 {
476 struct dm_struct *dm = (struct dm_struct *)dm_void;
477 struct psd_info *dm_psd_table = &dm->dm_psd_table;
478 u8 result = 0;
479
480 if (index < 128)
481 result = dm_psd_table->psd_result[index];
482
483 return result;
484 }
485
486 #endif
487