1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMPREDEFINE_H__ 27 #define __PHYDMPREDEFINE_H__ 28 29 /**************************************************************** 30 * 1 ============================================================ 31 * 1 Definition 32 * 1 ============================================================ 33 ***************************************************************/ 34 35 #define PHYDM_CODE_BASE "PHYDM_V048_GIT" 36 #define PHYDM_RELEASE_DATE "20210331.0" 37 38 /*PHYDM API status*/ 39 #define PHYDM_SET_FAIL 0 40 #define PHYDM_SET_SUCCESS 1 41 #define PHYDM_SET_NO_NEED 3 42 43 /*PHYDM Set/Revert*/ 44 #define PHYDM_SET 1 45 #define PHYDM_REVERT 2 46 47 /* @Max path of IC */ 48 /*N-IC*/ 49 #define MAX_PATH_NUM_8188E 1 50 #define MAX_PATH_NUM_8188F 1 51 #define MAX_PATH_NUM_8710B 1 52 #define MAX_PATH_NUM_8723B 1 53 #define MAX_PATH_NUM_8723D 1 54 #define MAX_PATH_NUM_8703B 1 55 #define MAX_PATH_NUM_8192E 2 56 #define MAX_PATH_NUM_8192F 2 57 #define MAX_PATH_NUM_8197F 2 58 #define MAX_PATH_NUM_8198F 4 59 #define MAX_PATH_NUM_8197G 2 60 #define MAX_PATH_NUM_8721D 1 61 #define MAX_PATH_NUM_8710C 1 62 63 /*@AC-IC*/ 64 #define MAX_PATH_NUM_8821A 1 65 #define MAX_PATH_NUM_8881A 1 66 #define MAX_PATH_NUM_8821C 1 67 #define MAX_PATH_NUM_8195B 1 68 #define MAX_PATH_NUM_8812A 2 69 #define MAX_PATH_NUM_8822B 2 70 #define MAX_PATH_NUM_8822C 2 71 #define MAX_PATH_NUM_8814A 4 72 #define MAX_PATH_NUM_8814B 4 73 #define MAX_PATH_NUM_8814C 4 74 #define MAX_PATH_NUM_8195B 1 75 #define MAX_PATH_NUM_8812F 2 76 77 /* @Max RF path */ 78 #define PHYDM_MAX_RF_PATH_N 2 /*@For old N-series IC*/ 79 #define PHYDM_MAX_RF_PATH 4 80 81 /* number of entry */ 82 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 83 #ifdef DM_ODM_CE_MAC80211 84 /* @defined in wifi.h (32+1) */ 85 #else 86 #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* @Max size of asoc_entry[].*/ 87 #endif 88 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 89 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) 90 #define ASSOCIATE_ENTRY_NUM NUM_STAT 91 #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM + 1) 92 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 93 #ifdef CONFIG_CONCURRENT_MODE 94 #define ASSOCIATE_ENTRY_NUM NUM_STA + 2 /*@2 is for station mod*/ 95 #else 96 #define ASSOCIATE_ENTRY_NUM NUM_STA /*@8 is for max size of asoc_entry[].*/ 97 #endif 98 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 99 #else 100 #define ODM_ASSOCIATE_ENTRY_NUM (((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1) 101 #endif 102 103 /* @-----MGN rate--------------------------------- */ 104 105 enum PDM_RATE_TYPE { 106 PDM_1SS = 1, /*VHT/HT 1SS*/ 107 PDM_2SS = 2, /*VHT/HT 2SS*/ 108 PDM_3SS = 3, /*VHT/HT 3SS*/ 109 PDM_4SS = 4, /*VHT/HT 4SS*/ 110 PDM_CCK = 11, /*@B*/ 111 PDM_OFDM = 12 /*@G*/ 112 }; 113 114 enum ODM_MGN_RATE { 115 ODM_MGN_1M = 0x02, 116 ODM_MGN_2M = 0x04, 117 ODM_MGN_5_5M = 0x0B, 118 ODM_MGN_6M = 0x0C, 119 ODM_MGN_9M = 0x12, 120 ODM_MGN_11M = 0x16, 121 ODM_MGN_12M = 0x18, 122 ODM_MGN_18M = 0x24, 123 ODM_MGN_24M = 0x30, 124 ODM_MGN_36M = 0x48, 125 ODM_MGN_48M = 0x60, 126 ODM_MGN_54M = 0x6C, 127 ODM_MGN_MCS32 = 0x7F, 128 ODM_MGN_MCS0 = 0x80, 129 ODM_MGN_MCS1, 130 ODM_MGN_MCS2, 131 ODM_MGN_MCS3, 132 ODM_MGN_MCS4, 133 ODM_MGN_MCS5, 134 ODM_MGN_MCS6, 135 ODM_MGN_MCS7 = 0x87, 136 ODM_MGN_MCS8, 137 ODM_MGN_MCS9, 138 ODM_MGN_MCS10, 139 ODM_MGN_MCS11, 140 ODM_MGN_MCS12, 141 ODM_MGN_MCS13, 142 ODM_MGN_MCS14, 143 ODM_MGN_MCS15, 144 ODM_MGN_MCS16 = 0x90, 145 ODM_MGN_MCS17, 146 ODM_MGN_MCS18, 147 ODM_MGN_MCS19, 148 ODM_MGN_MCS20, 149 ODM_MGN_MCS21, 150 ODM_MGN_MCS22, 151 ODM_MGN_MCS23, 152 ODM_MGN_MCS24 = 0x98, 153 ODM_MGN_MCS25, 154 ODM_MGN_MCS26, 155 ODM_MGN_MCS27, 156 ODM_MGN_MCS28, 157 ODM_MGN_MCS29, 158 ODM_MGN_MCS30, 159 ODM_MGN_MCS31, 160 ODM_MGN_VHT1SS_MCS0 = 0xa0, 161 ODM_MGN_VHT1SS_MCS1, 162 ODM_MGN_VHT1SS_MCS2, 163 ODM_MGN_VHT1SS_MCS3, 164 ODM_MGN_VHT1SS_MCS4, 165 ODM_MGN_VHT1SS_MCS5, 166 ODM_MGN_VHT1SS_MCS6, 167 ODM_MGN_VHT1SS_MCS7, 168 ODM_MGN_VHT1SS_MCS8, 169 ODM_MGN_VHT1SS_MCS9, 170 ODM_MGN_VHT2SS_MCS0 = 0xaa, 171 ODM_MGN_VHT2SS_MCS1 = 0xab, 172 ODM_MGN_VHT2SS_MCS2, 173 ODM_MGN_VHT2SS_MCS3, 174 ODM_MGN_VHT2SS_MCS4, 175 ODM_MGN_VHT2SS_MCS5 = 0xaf, 176 ODM_MGN_VHT2SS_MCS6 = 0xb0, 177 ODM_MGN_VHT2SS_MCS7, 178 ODM_MGN_VHT2SS_MCS8, 179 ODM_MGN_VHT2SS_MCS9 = 0xb3, 180 ODM_MGN_VHT3SS_MCS0 = 0xb4, 181 ODM_MGN_VHT3SS_MCS1, 182 ODM_MGN_VHT3SS_MCS2, 183 ODM_MGN_VHT3SS_MCS3, 184 ODM_MGN_VHT3SS_MCS4, 185 ODM_MGN_VHT3SS_MCS5, 186 ODM_MGN_VHT3SS_MCS6, 187 ODM_MGN_VHT3SS_MCS7 = 0xbb, 188 ODM_MGN_VHT3SS_MCS8 = 0xbc, 189 ODM_MGN_VHT3SS_MCS9 = 0xbd, 190 ODM_MGN_VHT4SS_MCS0 = 0xbe, 191 ODM_MGN_VHT4SS_MCS1, 192 ODM_MGN_VHT4SS_MCS2, 193 ODM_MGN_VHT4SS_MCS3, 194 ODM_MGN_VHT4SS_MCS4, 195 ODM_MGN_VHT4SS_MCS5, 196 ODM_MGN_VHT4SS_MCS6, 197 ODM_MGN_VHT4SS_MCS7, 198 ODM_MGN_VHT4SS_MCS8, 199 ODM_MGN_VHT4SS_MCS9 = 0xc7, 200 ODM_MGN_UNKNOWN 201 }; 202 203 #define ODM_MGN_MCS0_SG 0xc0 204 #define ODM_MGN_MCS1_SG 0xc1 205 #define ODM_MGN_MCS2_SG 0xc2 206 #define ODM_MGN_MCS3_SG 0xc3 207 #define ODM_MGN_MCS4_SG 0xc4 208 #define ODM_MGN_MCS5_SG 0xc5 209 #define ODM_MGN_MCS6_SG 0xc6 210 #define ODM_MGN_MCS7_SG 0xc7 211 #define ODM_MGN_MCS8_SG 0xc8 212 #define ODM_MGN_MCS9_SG 0xc9 213 #define ODM_MGN_MCS10_SG 0xca 214 #define ODM_MGN_MCS11_SG 0xcb 215 #define ODM_MGN_MCS12_SG 0xcc 216 #define ODM_MGN_MCS13_SG 0xcd 217 #define ODM_MGN_MCS14_SG 0xce 218 #define ODM_MGN_MCS15_SG 0xcf 219 220 /* @-----DESC rate--------------------------------- */ 221 222 #define ODM_RATEMCS15_SG 0x1c 223 #define ODM_RATEMCS32 0x20 224 225 enum phydm_ctrl_info_rate { 226 ODM_RATE1M = 0x00, 227 ODM_RATE2M = 0x01, 228 ODM_RATE5_5M = 0x02, 229 ODM_RATE11M = 0x03, 230 /* OFDM Rates, TxHT = 0 */ 231 ODM_RATE6M = 0x04, 232 ODM_RATE9M = 0x05, 233 ODM_RATE12M = 0x06, 234 ODM_RATE18M = 0x07, 235 ODM_RATE24M = 0x08, 236 ODM_RATE36M = 0x09, 237 ODM_RATE48M = 0x0A, 238 ODM_RATE54M = 0x0B, 239 /* @MCS Rates, TxHT = 1 */ 240 ODM_RATEMCS0 = 0x0C, 241 ODM_RATEMCS1 = 0x0D, 242 ODM_RATEMCS2 = 0x0E, 243 ODM_RATEMCS3 = 0x0F, 244 ODM_RATEMCS4 = 0x10, 245 ODM_RATEMCS5 = 0x11, 246 ODM_RATEMCS6 = 0x12, 247 ODM_RATEMCS7 = 0x13, 248 ODM_RATEMCS8 = 0x14, 249 ODM_RATEMCS9 = 0x15, 250 ODM_RATEMCS10 = 0x16, 251 ODM_RATEMCS11 = 0x17, 252 ODM_RATEMCS12 = 0x18, 253 ODM_RATEMCS13 = 0x19, 254 ODM_RATEMCS14 = 0x1A, 255 ODM_RATEMCS15 = 0x1B, 256 ODM_RATEMCS16 = 0x1C, 257 ODM_RATEMCS17 = 0x1D, 258 ODM_RATEMCS18 = 0x1E, 259 ODM_RATEMCS19 = 0x1F, 260 ODM_RATEMCS20 = 0x20, 261 ODM_RATEMCS21 = 0x21, 262 ODM_RATEMCS22 = 0x22, 263 ODM_RATEMCS23 = 0x23, 264 ODM_RATEMCS24 = 0x24, 265 ODM_RATEMCS25 = 0x25, 266 ODM_RATEMCS26 = 0x26, 267 ODM_RATEMCS27 = 0x27, 268 ODM_RATEMCS28 = 0x28, 269 ODM_RATEMCS29 = 0x29, 270 ODM_RATEMCS30 = 0x2A, 271 ODM_RATEMCS31 = 0x2B, 272 ODM_RATEVHTSS1MCS0 = 0x2C, 273 ODM_RATEVHTSS1MCS1 = 0x2D, 274 ODM_RATEVHTSS1MCS2 = 0x2E, 275 ODM_RATEVHTSS1MCS3 = 0x2F, 276 ODM_RATEVHTSS1MCS4 = 0x30, 277 ODM_RATEVHTSS1MCS5 = 0x31, 278 ODM_RATEVHTSS1MCS6 = 0x32, 279 ODM_RATEVHTSS1MCS7 = 0x33, 280 ODM_RATEVHTSS1MCS8 = 0x34, 281 ODM_RATEVHTSS1MCS9 = 0x35, 282 ODM_RATEVHTSS2MCS0 = 0x36, 283 ODM_RATEVHTSS2MCS1 = 0x37, 284 ODM_RATEVHTSS2MCS2 = 0x38, 285 ODM_RATEVHTSS2MCS3 = 0x39, 286 ODM_RATEVHTSS2MCS4 = 0x3A, 287 ODM_RATEVHTSS2MCS5 = 0x3B, 288 ODM_RATEVHTSS2MCS6 = 0x3C, 289 ODM_RATEVHTSS2MCS7 = 0x3D, 290 ODM_RATEVHTSS2MCS8 = 0x3E, 291 ODM_RATEVHTSS2MCS9 = 0x3F, 292 ODM_RATEVHTSS3MCS0 = 0x40, 293 ODM_RATEVHTSS3MCS1 = 0x41, 294 ODM_RATEVHTSS3MCS2 = 0x42, 295 ODM_RATEVHTSS3MCS3 = 0x43, 296 ODM_RATEVHTSS3MCS4 = 0x44, 297 ODM_RATEVHTSS3MCS5 = 0x45, 298 ODM_RATEVHTSS3MCS6 = 0x46, 299 ODM_RATEVHTSS3MCS7 = 0x47, 300 ODM_RATEVHTSS3MCS8 = 0x48, 301 ODM_RATEVHTSS3MCS9 = 0x49, 302 ODM_RATEVHTSS4MCS0 = 0x4A, 303 ODM_RATEVHTSS4MCS1 = 0x4B, 304 ODM_RATEVHTSS4MCS2 = 0x4C, 305 ODM_RATEVHTSS4MCS3 = 0x4D, 306 ODM_RATEVHTSS4MCS4 = 0x4E, 307 ODM_RATEVHTSS4MCS5 = 0x4F, 308 ODM_RATEVHTSS4MCS6 = 0x50, 309 ODM_RATEVHTSS4MCS7 = 0x51, 310 ODM_RATEVHTSS4MCS8 = 0x52, 311 ODM_RATEVHTSS4MCS9 = 0x53, 312 }; 313 314 enum phydm_legacy_spec_rate { 315 PHYDM_SPEC_RATE_6M = 0xb, 316 PHYDM_SPEC_RATE_9M = 0xf, 317 PHYDM_SPEC_RATE_12M = 0xa, 318 PHYDM_SPEC_RATE_18M = 0xe, 319 PHYDM_SPEC_RATE_24M = 0x9, 320 PHYDM_SPEC_RATE_36M = 0xd, 321 PHYDM_SPEC_RATE_48M = 0x8, 322 PHYDM_SPEC_RATE_54M = 0xc 323 }; 324 325 #define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1) 326 #define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1) 327 #define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1) 328 #define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1) 329 #define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1) 330 #define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1) 331 #define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1) 332 #define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1) 333 334 /*Define from larger rate size to small rate size, DO NOT change the position*/ 335 /*[AC-4SS]*/ 336 #if (RTL8814B_SUPPORT) 337 #define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS 338 /*[AC-3SS]*/ 339 #elif (RTL8814A_SUPPORT) 340 #define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS 341 /*[AC-2SS]*/ 342 #elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ 343 RTL8812F_SUPPORT) 344 #define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS 345 /*[AC-1SS]*/ 346 #elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\ 347 RTL8195B_SUPPORT) 348 #define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS 349 /*[N-4SS]*/ 350 #elif (RTL8198F_SUPPORT) 351 #define PHY_NUM_RATE_IDX NUM_RATE_N_4SS 352 /*[N-2SS]*/ 353 #elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\ 354 RTL8197G_SUPPORT) 355 #define PHY_NUM_RATE_IDX NUM_RATE_N_2SS 356 /*[N-1SS]*/ 357 #elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \ 358 RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\ 359 RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 360 #define PHY_NUM_RATE_IDX NUM_RATE_N_1SS 361 #else 362 #define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS 363 #endif 364 365 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 366 #define CONFIG_SFW_SUPPORTED 367 #endif 368 369 /**************************************************************** 370 * 1 ============================================================ 371 * 1 enumeration 372 * 1 ============================================================ 373 ***************************************************************/ 374 375 /* ODM_CMNINFO_INTERFACE */ 376 enum odm_interface { 377 ODM_ITRF_PCIE = 0x1, 378 ODM_ITRF_USB = 0x2, 379 ODM_ITRF_SDIO = 0x4, 380 ODM_ITRF_ALL = 0x7, 381 }; 382 383 enum phydm_api_host { 384 RUN_IN_FW = 0, 385 RUN_IN_DRIVER = 1, 386 }; 387 388 /*@========[Run time IC flag] ===================================*/ 389 390 enum phydm_ic { 391 ODM_RTL8188E = BIT(0), 392 ODM_RTL8812 = BIT(1), 393 ODM_RTL8821 = BIT(2), 394 ODM_RTL8192E = BIT(3), 395 ODM_RTL8723B = BIT(4), 396 ODM_RTL8814A = BIT(5), 397 ODM_RTL8881A = BIT(6), 398 ODM_RTL8822B = BIT(7), 399 ODM_RTL8703B = BIT(8), 400 ODM_RTL8195A = BIT(9), 401 ODM_RTL8188F = BIT(10), 402 ODM_RTL8723D = BIT(11), 403 ODM_RTL8197F = BIT(12), 404 ODM_RTL8821C = BIT(13), 405 ODM_RTL8814B = BIT(14), 406 ODM_RTL8198F = BIT(15), 407 ODM_RTL8710B = BIT(16), 408 ODM_RTL8192F = BIT(17), 409 ODM_RTL8822C = BIT(18), 410 ODM_RTL8195B = BIT(19), 411 ODM_RTL8812F = BIT(20), 412 ODM_RTL8197G = BIT(21), 413 ODM_RTL8721D = BIT(22), 414 ODM_RTL8710C = BIT(23) 415 }; 416 417 #define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\ 418 ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\ 419 ODM_RTL8710B | ODM_RTL8721D | ODM_RTL8710C) 420 #define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) 421 #define ODM_IC_N_3SS 0 422 #define ODM_IC_N_4SS 0 423 424 #define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\ 425 ODM_RTL8195B) 426 #define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B) 427 #define ODM_IC_AC_3SS 0 428 #define ODM_IC_AC_4SS (ODM_RTL8814A) 429 430 #define ODM_IC_JGR3_1SS 0 431 #define ODM_IC_JGR3_2SS (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G) 432 #define ODM_IC_JGR3_3SS 0 433 #define ODM_IC_JGR3_4SS (ODM_RTL8198F | ODM_RTL8814B) 434 435 /*@====the following macro DO NOT need to update when adding a new IC======= */ 436 #define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS) 437 #define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS) 438 #define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS) 439 #define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS) 440 441 #define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\ 442 ODM_IC_4SS) 443 #define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) 444 #define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS) 445 #define PHYDM_IC_ABOVE_4SS ODM_IC_4SS 446 447 #define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\ 448 ODM_IC_N_4SS) 449 #define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS |\ 450 ODM_IC_AC_3SS | ODM_IC_AC_4SS) 451 #define ODM_IC_JGR3_SERIES (ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\ 452 ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS) 453 /*@====================================================*/ 454 455 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) 456 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\ 457 ODM_RTL8195B) 458 459 /*@[Phy status type]*/ 460 #define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\ 461 ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\ 462 ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C) 463 #define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\ 464 ODM_RTL8812F | ODM_RTL8197G) 465 /*@[FW Type]*/ 466 #define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\ 467 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\ 468 ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D |\ 469 ODM_RTL8710C) 470 #define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ 471 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ 472 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\ 473 ODM_RTL8197G) 474 /*@[LA mode]*/ 475 #define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ 476 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ 477 ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\ 478 ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G) 479 /*@[BF]*/ 480 #define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\ 481 ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\ 482 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\ 483 ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\ 484 ODM_RTL8814B | ODM_RTL8197G) 485 #define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\ 486 ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\ 487 ODM_RTL8812F) 488 #define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\ 489 ODM_RTL8822C | ODM_RTL8812F) 490 491 #define PHYDM_IC_SUPPORT_MU (PHYDM_IC_SUPPORT_MU_BFEE |\ 492 PHYDM_IC_SUPPORT_MU_BFER) 493 /*@[PHYDM API]*/ 494 #define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\ 495 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\ 496 ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\ 497 ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C) 498 499 /* fw offload ability*/ 500 #define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\ 501 ODM_RTL8821C | ODM_RTL8822C) 502 503 /*[ARFR]*/ 504 /*for MAC HW control rate_id=0~12 and 2.4g vht mode(1ss/2ss) support*/ 505 #define PHYDM_IC_RATEID_IDX_TYPE2 (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8195B |\ 506 ODM_RTL8821C) 507 508 /*@========[Compile time IC flag] ========================*/ 509 /*@========[AC-3/AC/N Support] ===========================*/ 510 511 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\ 512 RTL8812F_SUPPORT || RTL8197G_SUPPORT) 513 #define PHYDM_IC_JGR3_SERIES_SUPPORT 514 #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) 515 #define PHYDM_IC_JGR3_80M_SUPPORT 516 #endif 517 #endif 518 519 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 520 521 #ifdef RTK_AC_SUPPORT 522 #define ODM_IC_11AC_SERIES_SUPPORT 1 523 #else 524 #define ODM_IC_11AC_SERIES_SUPPORT 0 525 #endif 526 527 #define ODM_IC_11N_SERIES_SUPPORT 1 528 529 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 530 531 #define ODM_IC_11AC_SERIES_SUPPORT 1 532 #define ODM_IC_11N_SERIES_SUPPORT 1 533 534 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) 535 536 #define ODM_IC_11AC_SERIES_SUPPORT 1 537 #define ODM_IC_11N_SERIES_SUPPORT 1 538 539 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) 540 541 #define ODM_IC_11AC_SERIES_SUPPORT 1 542 #define ODM_IC_11N_SERIES_SUPPORT 1 543 544 #else /*ODM_CE*/ 545 546 #if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\ 547 RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\ 548 RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\ 549 RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 550 #define ODM_IC_11N_SERIES_SUPPORT 1 551 #define ODM_IC_11AC_SERIES_SUPPORT 0 552 #else 553 #define ODM_IC_11N_SERIES_SUPPORT 0 554 #define ODM_IC_11AC_SERIES_SUPPORT 1 555 #endif 556 #endif 557 558 /*@===IC SS Compile Flag, prepare for code size reduction==============*/ 559 #if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\ 560 RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\ 561 RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\ 562 RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\ 563 RTL8710C_SUPPORT) 564 565 #define PHYDM_COMPILE_IC_1SS 566 #endif 567 568 #if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\ 569 RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\ 570 RTL8812F_SUPPORT || RTL8197G_SUPPORT) 571 #define PHYDM_COMPILE_IC_2SS 572 #endif 573 574 /*@#define PHYDM_COMPILE_IC_3SS*/ 575 576 #if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT)) 577 #define PHYDM_COMPILE_IC_4SS 578 #endif 579 580 /*@==[ABOVE N-SS COMPILE FLAG]=================================================*/ 581 #if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\ 582 defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 583 #define PHYDM_COMPILE_ABOVE_1SS 584 #endif 585 586 #if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\ 587 defined(PHYDM_COMPILE_IC_4SS)) 588 #define PHYDM_COMPILE_ABOVE_2SS 589 #endif 590 591 #if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 592 #define PHYDM_COMPILE_ABOVE_3SS 593 #endif 594 595 #if (defined(PHYDM_COMPILE_IC_4SS)) 596 #define PHYDM_COMPILE_ABOVE_4SS 597 #endif 598 599 /*@==[Max RF path number among all compiled ICs]==============================*/ 600 /*@ ex: support 8814B & 8821C => size=4 */ 601 /*@ ex: support 8822C & 8821C => size=2 */ 602 #if (defined(PHYDM_COMPILE_IC_4SS)) 603 #define RF_PATH_MEM_SIZE 4 604 #elif (defined(PHYDM_COMPILE_IC_3SS)) 605 #define RF_PATH_MEM_SIZE 3 606 #elif (defined(PHYDM_COMPILE_IC_2SS)) 607 #define RF_PATH_MEM_SIZE 2 608 #else 609 #define RF_PATH_MEM_SIZE 1 610 #endif 611 612 /*@========[New Phy-Status Support] ========================*/ 613 #if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\ 614 RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\ 615 RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 616 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 617 #else 618 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 619 #endif 620 621 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\ 622 RTL8812F_SUPPORT || RTL8197G_SUPPORT) 623 #define PHYSTS_3RD_TYPE_SUPPORT 624 #endif 625 626 #ifdef PHYSTS_3RD_TYPE_SUPPORT 627 #define PHYSTS_AUTO_SWITCH_IC (ODM_RTL8822C) 628 #endif 629 630 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\ 631 RTL8812F_SUPPORT || RTL8197G_SUPPORT) 632 #define BB_RAM_SUPPORT 633 #endif 634 635 #if (RTL8821C_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ 636 RTL8812F_SUPPORT || RTL8814B_SUPPORT || RTL8195B_SUPPORT ||\ 637 RTL8198F_SUPPORT) 638 #define PHYDM_COMPILE_MU 639 #endif 640 641 #if (RTL8822B_SUPPORT) 642 #define CONFIG_MU_JAGUAR_2 643 #endif 644 645 #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) 646 #define CONFIG_MU_JAGUAR_3 647 #endif 648 649 #if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3)) 650 #if (RTL8814B_SUPPORT) 651 #define MU_EX_MACID 76 652 #elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) 653 #define MU_EX_MACID 30 654 #endif 655 #endif 656 /*@============================================================================*/ 657 658 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ 659 RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\ 660 RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\ 661 RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 662 #define PHYDM_COMMON_API_SUPPORT 663 #endif 664 665 #define PHYDM_COMMON_API_IC (ODM_IC_JGR3_SERIES | ODM_RTL8822B |\ 666 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8195B |\ 667 ODM_RTL8721D | ODM_RTL8710C) 668 669 #if (RTL8188E_SUPPORT || RTL8192E_SUPPORT || RTL8821A_SUPPORT ||\ 670 RTL8812A_SUPPORT || RTL8723B_SUPPORT || RTL8703B_SUPPORT ||\ 671 RTL8195A_SUPPORT || RTL8814A_SUPPORT) 672 #define PHYDM_COMMON_API_NOT_SUPPORT 673 #endif 674 675 #if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8197G_SUPPORT) 676 #define CONFIG_RFE_BY_HW_INFO 677 #endif 678 679 #define CCK_RATE_NUM 4 680 #define OFDM_RATE_NUM 8 681 682 #define LEGACY_RATE_NUM 12 683 684 #define HT_RATE_NUM_4SS 32 685 #define VHT_RATE_NUM_4SS 40 686 687 #define HT_RATE_NUM_3SS 24 688 #define VHT_RATE_NUM_3SS 30 689 690 #define HT_RATE_NUM_2SS 16 691 #define VHT_RATE_NUM_2SS 20 692 693 #define HT_RATE_NUM_1SS 8 694 #define VHT_RATE_NUM_1SS 10 695 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 696 #define HT_RATE_NUM HT_RATE_NUM_4SS 697 #define VHT_RATE_NUM VHT_RATE_NUM_4SS 698 #elif (defined(PHYDM_COMPILE_ABOVE_3SS)) 699 #define HT_RATE_NUM HT_RATE_NUM_3SS 700 #define VHT_RATE_NUM VHT_RATE_NUM_3SS 701 #elif (defined(PHYDM_COMPILE_ABOVE_2SS)) 702 #define HT_RATE_NUM HT_RATE_NUM_2SS 703 #define VHT_RATE_NUM VHT_RATE_NUM_2SS 704 #else 705 #define HT_RATE_NUM HT_RATE_NUM_1SS 706 #define VHT_RATE_NUM VHT_RATE_NUM_1SS 707 #endif 708 709 #define LOW_BW_RATE_NUM VHT_RATE_NUM 710 711 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 712 #define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/ 713 #define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/ 714 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 715 #define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/ 716 #define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/ 717 #else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ 718 #define SECOND_CH_AT_LSB 1 /*@primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/ 719 #define SECOND_CH_AT_USB 2 /*@primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/ 720 #endif 721 722 enum phydm_ic_ip { 723 PHYDM_IC_N = 0, 724 PHYDM_IC_AC = 1, 725 PHYDM_IC_JGR3 = 2 726 }; 727 728 enum phydm_phy_sts_type { 729 PHYDM_PHYSTS_TYPE_1 = 1, 730 PHYDM_PHYSTS_TYPE_2 = 2, 731 PHYDM_PHYSTS_TYPE_3 = 3 732 }; 733 734 /* ODM_CMNINFO_CUT_VER */ 735 enum odm_cut_version { 736 ODM_CUT_A = 0, 737 ODM_CUT_B = 1, 738 ODM_CUT_C = 2, 739 ODM_CUT_D = 3, 740 ODM_CUT_E = 4, 741 ODM_CUT_F = 5, 742 ODM_CUT_G = 6, 743 ODM_CUT_H = 7, 744 ODM_CUT_I = 8, 745 ODM_CUT_J = 9, 746 ODM_CUT_K = 10, 747 ODM_CUT_L = 11, 748 ODM_CUT_M = 12, 749 ODM_CUT_N = 13, 750 ODM_CUT_O = 14, 751 ODM_CUT_TEST = 15, 752 }; 753 754 /* ODM_CMNINFO_FAB_VER */ 755 enum odm_fab { 756 ODM_TSMC = 0, 757 ODM_UMC = 1, 758 }; 759 760 /* ODM_CMNINFO_OP_MODE */ 761 enum odm_operation_mode { 762 ODM_NO_LINK = BIT(0), 763 ODM_LINK = BIT(1), 764 ODM_SCAN = BIT(2), 765 ODM_POWERSAVE = BIT(3), 766 ODM_AP_MODE = BIT(4), 767 ODM_CLIENT_MODE = BIT(5), 768 ODM_AD_HOC = BIT(6), 769 ODM_WIFI_DIRECT = BIT(7), 770 ODM_WIFI_DISPLAY = BIT(8), 771 }; 772 773 /* ODM_CMNINFO_WM_MODE */ 774 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 775 enum odm_wireless_mode { 776 ODM_WM_UNKNOW = 0x0, 777 ODM_WM_B = BIT(0), 778 ODM_WM_G = BIT(1), 779 ODM_WM_A = BIT(2), 780 ODM_WM_N24G = BIT(3), 781 ODM_WM_N5G = BIT(4), 782 ODM_WM_AUTO = BIT(5), 783 ODM_WM_AC = BIT(6), 784 }; 785 #else 786 enum odm_wireless_mode { 787 ODM_WM_UNKNOWN = 0x00,/*@0x0*/ 788 ODM_WM_A = BIT(0), /* @0x1*/ 789 ODM_WM_B = BIT(1), /* @0x2*/ 790 ODM_WM_G = BIT(2),/* @0x4*/ 791 ODM_WM_AUTO = BIT(3),/* @0x8*/ 792 ODM_WM_N24G = BIT(4),/* @0x10*/ 793 ODM_WM_N5G = BIT(5),/* @0x20*/ 794 ODM_WM_AC_5G = BIT(6),/* @0x40*/ 795 ODM_WM_AC_24G = BIT(7),/* @0x80*/ 796 ODM_WM_AC_ONLY = BIT(8),/* @0x100*/ 797 ODM_WM_MAX = BIT(11)/* @0x800*/ 798 799 }; 800 #endif 801 802 /* ODM_CMNINFO_BAND */ 803 enum odm_band_type { 804 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 805 ODM_BAND_2_4G = BIT(0), 806 ODM_BAND_5G = BIT(1), 807 #else 808 ODM_BAND_2_4G = 0, 809 ODM_BAND_5G, 810 ODM_BAND_ON_BOTH, 811 ODM_BANDMAX 812 #endif 813 }; 814 815 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 816 enum phydm_sec_chnl_offset { 817 PHYDM_DONT_CARE = 0, 818 PHYDM_BELOW = 1, 819 PHYDM_ABOVE = 2 820 }; 821 822 /* ODM_CMNINFO_SEC_MODE */ 823 enum odm_security { 824 ODM_SEC_OPEN = 0, 825 ODM_SEC_WEP40 = 1, 826 ODM_SEC_TKIP = 2, 827 ODM_SEC_RESERVE = 3, 828 ODM_SEC_AESCCMP = 4, 829 ODM_SEC_WEP104 = 5, 830 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 831 ODM_SEC_SMS4 = 7, 832 }; 833 834 /* ODM_CMNINFO_CHNL */ 835 836 /* ODM_CMNINFO_BOARD_TYPE */ 837 enum odm_board_type { 838 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 839 ODM_BOARD_MINICARD = BIT(0), /* @0 = non-mini card, 1= mini card. */ 840 ODM_BOARD_SLIM = BIT(1), /* @0 = non-slim card, 1 = slim card */ 841 ODM_BOARD_BT = BIT(2), /* @0 = without BT card, 1 = with BT */ 842 ODM_BOARD_EXT_PA = BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 843 ODM_BOARD_EXT_LNA = BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 844 ODM_BOARD_EXT_TRSW = BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */ 845 ODM_BOARD_EXT_PA_5G = BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 846 ODM_BOARD_EXT_LNA_5G = BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 847 }; 848 849 enum odm_package_type { 850 ODM_PACKAGE_DEFAULT = 0, 851 ODM_PACKAGE_QFN68 = BIT(0), 852 ODM_PACKAGE_TFBGA90 = BIT(1), 853 ODM_PACKAGE_TFBGA79 = BIT(2), 854 }; 855 856 enum odm_type_gpa { 857 TYPE_GPA0 = 0x0000, 858 TYPE_GPA1 = 0x0055, 859 TYPE_GPA2 = 0x00AA, 860 TYPE_GPA3 = 0x00FF, 861 TYPE_GPA4 = 0x5500, 862 TYPE_GPA5 = 0x5555, 863 TYPE_GPA6 = 0x55AA, 864 TYPE_GPA7 = 0x55FF, 865 TYPE_GPA8 = 0xAA00, 866 TYPE_GPA9 = 0xAA55, 867 TYPE_GPA10 = 0xAAAA, 868 TYPE_GPA11 = 0xAAFF, 869 TYPE_GPA12 = 0xFF00, 870 TYPE_GPA13 = 0xFF55, 871 TYPE_GPA14 = 0xFFAA, 872 TYPE_GPA15 = 0xFFFF, 873 }; 874 875 enum odm_type_apa { 876 TYPE_APA0 = 0x0000, 877 TYPE_APA1 = 0x0055, 878 TYPE_APA2 = 0x00AA, 879 TYPE_APA3 = 0x00FF, 880 TYPE_APA4 = 0x5500, 881 TYPE_APA5 = 0x5555, 882 TYPE_APA6 = 0x55AA, 883 TYPE_APA7 = 0x55FF, 884 TYPE_APA8 = 0xAA00, 885 TYPE_APA9 = 0xAA55, 886 TYPE_APA10 = 0xAAAA, 887 TYPE_APA11 = 0xAAFF, 888 TYPE_APA12 = 0xFF00, 889 TYPE_APA13 = 0xFF55, 890 TYPE_APA14 = 0xFFAA, 891 TYPE_APA15 = 0xFFFF, 892 }; 893 894 enum odm_type_glna { 895 TYPE_GLNA0 = 0x0000, 896 TYPE_GLNA1 = 0x0055, 897 TYPE_GLNA2 = 0x00AA, 898 TYPE_GLNA3 = 0x00FF, 899 TYPE_GLNA4 = 0x5500, 900 TYPE_GLNA5 = 0x5555, 901 TYPE_GLNA6 = 0x55AA, 902 TYPE_GLNA7 = 0x55FF, 903 TYPE_GLNA8 = 0xAA00, 904 TYPE_GLNA9 = 0xAA55, 905 TYPE_GLNA10 = 0xAAAA, 906 TYPE_GLNA11 = 0xAAFF, 907 TYPE_GLNA12 = 0xFF00, 908 TYPE_GLNA13 = 0xFF55, 909 TYPE_GLNA14 = 0xFFAA, 910 TYPE_GLNA15 = 0xFFFF, 911 }; 912 913 enum odm_type_alna { 914 TYPE_ALNA0 = 0x0000, 915 TYPE_ALNA1 = 0x0055, 916 TYPE_ALNA2 = 0x00AA, 917 TYPE_ALNA3 = 0x00FF, 918 TYPE_ALNA4 = 0x5500, 919 TYPE_ALNA5 = 0x5555, 920 TYPE_ALNA6 = 0x55AA, 921 TYPE_ALNA7 = 0x55FF, 922 TYPE_ALNA8 = 0xAA00, 923 TYPE_ALNA9 = 0xAA55, 924 TYPE_ALNA10 = 0xAAAA, 925 TYPE_ALNA11 = 0xAAFF, 926 TYPE_ALNA12 = 0xFF00, 927 TYPE_ALNA13 = 0xFF55, 928 TYPE_ALNA14 = 0xFFAA, 929 TYPE_ALNA15 = 0xFFFF, 930 }; 931 932 #if (RTL8721D_SUPPORT) 933 /* ODM_CMNINFO_POWER_VOLTAGE */ 934 enum odm_power_voltage { 935 ODM_POWER_18V = 0, 936 ODM_POWER_33V = 1, 937 }; 938 939 /* ODM_CMNINFO_ANTDIV_GPIO */ 940 enum odm_antdiv_gpio { 941 ANTDIV_GPIO_PA2PA4 = 0, 942 ANTDIV_GPIO_PA5PA6 = 1, 943 ANTDIV_GPIO_PA12PA13 = 2, 944 ANTDIV_GPIO_PA14PA15 = 3, 945 ANTDIV_GPIO_PA16PA17 = 4, 946 ANTDIV_GPIO_PB1PB2 = 5, 947 ANTDIV_GPIO_PB26PB29 = 6, 948 }; 949 950 /* ODM_CMNINFO_PEAK_DETECT_MODE */ 951 enum odm_peak_detect_mode { 952 ODM_PD_DIS = 0, 953 ODM_PD_ENG = 1, 954 ODM_PD_ENA = 2, 955 ODM_PD_ENALL = 3, 956 }; 957 #endif 958 959 #define PAUSE_FAIL 0 960 #define PAUSE_SUCCESS 1 961 962 enum odm_parameter_init { 963 ODM_PRE_SETTING = 0, 964 ODM_POST_SETTING = 1, 965 ODM_INIT_FW_SETTING = 2, 966 ODM_PRE_RF_SET = 3, 967 ODM_POST_RF_SET = 4 968 }; 969 970 enum phydm_pause_type { 971 PHYDM_PAUSE = 1, /*Pause & Set new value*/ 972 PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ 973 PHYDM_RESUME = 3 974 }; 975 976 enum phydm_backup_type { 977 PHYDM_BACKUP = 1, 978 PHYDM_RESTORE = 2 979 }; 980 981 enum phydm_pause_level { 982 PHYDM_PAUSE_RELEASE = -1, 983 PHYDM_PAUSE_LEVEL_0 = 0, /* @Low Priority function */ 984 PHYDM_PAUSE_LEVEL_1 = 1, /* @Middle Priority function */ 985 PHYDM_PAUSE_LEVEL_2 = 2, /* @High priority function (ex: Check hang function) */ 986 PHYDM_PAUSE_LEVEL_3 = 3, /* @Debug function (the highest priority) */ 987 PHYDM_PAUSE_MAX_NUM = 4 988 }; 989 990 enum phydm_dis_hw_fun { 991 HW_FUN_DIS = 0, /*@Disable a cetain HW function & backup the original value*/ 992 HW_FUN_RESUME = 1 /*Revert */ 993 }; 994 995 #endif 996