1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDM_PHYSTATUS_H__ 27 #define __PHYDM_PHYSTATUS_H__ 28 29 /* 2019.09.26 force jgr3 cck channel = 0 due to hw bug*/ 30 #define PHYSTS_VERSION "1.1" 31 32 /*@--------------------------Define ------------------------------------------*/ 33 #define CCK_RSSI_INIT_COUNT 5 34 35 #define RA_RSSI_STATE_INIT 0 36 #define RA_RSSI_STATE_SEND 1 37 #define RA_RSSI_STATE_HOLD 2 38 39 #if defined(DM_ODM_CE_MAC80211) 40 #define CFO_HW_RPT_2_KHZ(val) ({ \ 41 s32 cfo_hw_rpt_2_khz_tmp = (val); \ 42 (cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1); \ 43 }) 44 #else 45 #define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1)) 46 #endif 47 48 /* @(X* 312.5 Khz)>>7 ~= X*2.5 Khz= (X<<1 + X>>1)Khz */ 49 50 #define IGI_2_RSSI(igi) (igi - 10) 51 52 #define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */ 53 #define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */ 54 #define SHOW_PHY_STATUS_UNLIMITED 0 55 #define RSSI_MA 4 /*moving average factor for RSSI: 2^4=16 */ 56 57 #define PHYSTS_PATH_NUM 4 58 59 /*@************************************************************ 60 * structure and define 61 ************************************************************/ 62 63 __PACK struct phy_rx_agc_info { 64 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 65 u8 gain : 7, trsw : 1; 66 #else 67 u8 trsw : 1, gain : 7; 68 #endif 69 }; 70 71 __PACK struct phy_status_rpt_8192cd { 72 struct phy_rx_agc_info path_agc[2]; 73 u8 ch_corr[2]; 74 u8 cck_sig_qual_ofdm_pwdb_all; 75 u8 cck_agc_rpt_ofdm_cfosho_a; 76 u8 cck_rpt_b_ofdm_cfosho_b; 77 u8 rsvd_1;/*@ch_corr_msb;*/ 78 u8 noise_power_db_msb; 79 s8 path_cfotail[2]; 80 u8 pcts_mask[2]; 81 s8 stream_rxevm[2]; 82 u8 path_rxsnr[2]; 83 u8 noise_power_db_lsb; 84 u8 rsvd_2[3]; 85 u8 stream_csi[2]; 86 u8 stream_target_csi[2]; 87 s8 sig_evm; 88 u8 rsvd_3; 89 90 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 91 u8 antsel_rx_keep_2: 1; /*@ex_intf_flg:1;*/ 92 u8 sgi_en: 1; 93 u8 rxsc: 2; 94 u8 idle_long: 1; 95 u8 r_ant_train_en: 1; 96 u8 ant_sel_b: 1; 97 u8 ant_sel: 1; 98 #else /*@_BIG_ENDIAN_ */ 99 u8 ant_sel: 1; 100 u8 ant_sel_b: 1; 101 u8 r_ant_train_en: 1; 102 u8 idle_long: 1; 103 u8 rxsc: 2; 104 u8 sgi_en: 1; 105 u8 antsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/ 106 #endif 107 }; 108 109 struct phy_status_rpt_8812 { 110 /* @DWORD 0*/ 111 u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ 112 u8 chl_num_LSB; /*@channel number[7:0]*/ 113 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 114 u8 chl_num_MSB : 2; /*@channel number[9:8]*/ 115 u8 sub_chnl : 4; /*sub-channel location[3:0]*/ 116 u8 r_RFMOD : 2; /*RF mode[1:0]*/ 117 #else /*@_BIG_ENDIAN_ */ 118 u8 r_RFMOD : 2; 119 u8 sub_chnl : 4; 120 u8 chl_num_MSB : 2; 121 #endif 122 123 /* @DWORD 1*/ 124 u8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/ 125 s8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/ 126 /*OFDM path-A and path-B short CFO*/ 127 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 128 u8 resvd_0 : 6; 129 u8 bt_RF_ch_MSB : 2; /*@8812A:2'b0 8814A: bt rf channel keep[7:6]*/ 130 #else /*@_BIG_ENDIAN_*/ 131 u8 bt_RF_ch_MSB : 2; 132 u8 resvd_0 : 6; 133 #endif 134 135 /* @DWORD 2*/ 136 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 137 u8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a 8814A: 1'b0*/ 138 u8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b 8814A: 1'b0*/ 139 u8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ 140 #else /*@_BIG_ENDIAN_ */ 141 u8 bt_RF_ch_LSB : 6; 142 u8 ant_div_sw_b : 1; 143 u8 ant_div_sw_a : 1; 144 #endif 145 s8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ 146 u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ 147 u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ 148 149 /* @DWORD 3*/ 150 s8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ 151 s8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ 152 153 /* @DWORD 4*/ 154 u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ 155 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 156 u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/ 157 u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/ 158 u8 resvd_1 : 1; /*@1'b0*/ 159 #else /*@_BIG_ENDIAN_*/ 160 u8 resvd_1 : 1; 161 u8 pcts_rpt_valid : 1; 162 u8 PCTS_MSK_RPT_3 : 6; 163 #endif 164 s8 rxevm_cd[2]; /*@8812A: 16'b0*/ 165 /*@8814A: stream 3 and stream 4 RX EVM*/ 166 /* @DWORD 5*/ 167 u8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/ 168 /*@8814A: path-C and path-D RX SNR*/ 169 u8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/ 170 171 /* @DWORD 6*/ 172 s8 sigevm; /*signal field EVM*/ 173 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 174 u8 antidx_antc : 3; /*@8812A: 3'b0 8814A: antidx_antc[2:0]*/ 175 u8 antidx_antd : 3; /*@8812A: 3'b0 8814A: antidx_antd[2:0]*/ 176 u8 dpdt_ctrl_keep : 1; /*@8812A: 1'b0 8814A: dpdt_ctrl_keep*/ 177 u8 GNT_BT_keep : 1; /*@8812A: 1'b0 8814A: GNT_BT_keep*/ 178 #else /*@_BIG_ENDIAN_*/ 179 u8 GNT_BT_keep : 1; 180 u8 dpdt_ctrl_keep : 1; 181 u8 antidx_antd : 3; 182 u8 antidx_antc : 3; 183 #endif 184 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 185 u8 antidx_anta : 3; /*@antidx_anta[2:0]*/ 186 u8 antidx_antb : 3; /*@antidx_antb[2:0]*/ 187 u8 hw_antsw_occur : 2; /*@1'b0*/ 188 #else /*@_BIG_ENDIAN_*/ 189 u8 hw_antsw_occur : 2; 190 u8 antidx_antb : 3; 191 u8 antidx_anta : 3; 192 #endif 193 }; 194 195 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 196 197 __PACK struct phy_sts_rpt_jgr2_type0 { 198 /* @DW0 */ 199 u8 page_num; 200 u8 pwdb; 201 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 202 u8 gain : 6; 203 u8 rsvd_0 : 1; 204 u8 trsw : 1; 205 #else 206 u8 trsw : 1; 207 u8 rsvd_0 : 1; 208 u8 gain : 6; 209 #endif 210 u8 rsvd_1; 211 212 /* @DW1 */ 213 u8 rsvd_2; 214 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 215 u8 rxsc : 4; 216 u8 agc_table : 4; 217 #else 218 u8 agc_table : 4; 219 u8 rxsc : 4; 220 #endif 221 u8 channel; 222 u8 band; 223 224 /* @DW2 */ 225 u16 length; 226 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 227 u8 antidx_a : 3; 228 u8 antidx_b : 3; 229 u8 rsvd_3 : 2; 230 u8 antidx_c : 3; 231 u8 antidx_d : 3; 232 u8 rsvd_4 : 2; 233 #else 234 u8 rsvd_3 : 2; 235 u8 antidx_b : 3; 236 u8 antidx_a : 3; 237 u8 rsvd_4 : 2; 238 u8 antidx_d : 3; 239 u8 antidx_c : 3; 240 #endif 241 242 /* @DW3 */ 243 u8 signal_quality; 244 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 245 u8 vga : 5; 246 u8 lna_l : 3; 247 u8 bb_power : 6; 248 u8 rsvd_9 : 1; 249 u8 lna_h : 1; 250 #else 251 u8 lna_l : 3; 252 u8 vga : 5; 253 u8 lna_h : 1; 254 u8 rsvd_9 : 1; 255 u8 bb_power : 6; 256 #endif 257 u8 rsvd_5; 258 259 /* @DW4 */ 260 u32 rsvd_6; 261 262 /* @DW5 */ 263 u32 rsvd_7; 264 265 /* @DW6 */ 266 u32 rsvd_8; 267 }; 268 269 __PACK struct phy_sts_rpt_jgr2_type1 { 270 /* @DW0 and DW1 */ 271 u8 page_num; 272 u8 pwdb[4]; 273 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 274 u8 l_rxsc : 4; 275 u8 ht_rxsc : 4; 276 #else 277 u8 ht_rxsc : 4; 278 u8 l_rxsc : 4; 279 #endif 280 u8 channel; 281 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 282 u8 band : 2; 283 u8 rsvd_0 : 1; 284 u8 hw_antsw_occu : 1; 285 u8 gnt_bt : 1; 286 u8 ldpc : 1; 287 u8 stbc : 1; 288 u8 beamformed : 1; 289 #else 290 u8 beamformed : 1; 291 u8 stbc : 1; 292 u8 ldpc : 1; 293 u8 gnt_bt : 1; 294 u8 hw_antsw_occu : 1; 295 u8 rsvd_0 : 1; 296 u8 band : 2; 297 #endif 298 299 /* @DW2 */ 300 u16 lsig_length; 301 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 302 u8 antidx_a : 3; 303 u8 antidx_b : 3; 304 u8 rsvd_1 : 2; 305 u8 antidx_c : 3; 306 u8 antidx_d : 3; 307 u8 rsvd_2 : 2; 308 #else 309 u8 rsvd_1 : 2; 310 u8 antidx_b : 3; 311 u8 antidx_a : 3; 312 u8 rsvd_2 : 2; 313 u8 antidx_d : 3; 314 u8 antidx_c : 3; 315 #endif 316 317 /* @DW3 */ 318 u8 paid; 319 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 320 u8 paid_msb : 1; 321 u8 gid : 6; 322 u8 rsvd_3 : 1; 323 #else 324 u8 rsvd_3 : 1; 325 u8 gid : 6; 326 u8 paid_msb : 1; 327 #endif 328 u8 intf_pos; 329 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 330 u8 intf_pos_msb : 1; 331 u8 rsvd_4 : 2; 332 u8 nb_intf_flag : 1; 333 u8 rf_mode : 2; 334 u8 rsvd_5 : 2; 335 #else 336 u8 rsvd_5 : 2; 337 u8 rf_mode : 2; 338 u8 nb_intf_flag : 1; 339 u8 rsvd_4 : 2; 340 u8 intf_pos_msb : 1; 341 #endif 342 343 /* @DW4 */ 344 s8 rxevm[4]; /* s(8,1) */ 345 346 /* @DW5 */ 347 s8 cfo_tail[4]; /* s(8,7) */ 348 349 /* @DW6 */ 350 s8 rxsnr[4]; /* s(8,1) */ 351 }; 352 353 __PACK struct phy_sts_rpt_jgr2_type2 { 354 /* @DW0 ane DW1 */ 355 u8 page_num; 356 u8 pwdb[4]; 357 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 358 u8 l_rxsc : 4; 359 u8 ht_rxsc : 4; 360 #else 361 u8 ht_rxsc : 4; 362 u8 l_rxsc : 4; 363 #endif 364 u8 channel; 365 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 366 u8 band : 2; 367 u8 rsvd_0 : 1; 368 u8 hw_antsw_occu : 1; 369 u8 gnt_bt : 1; 370 u8 ldpc : 1; 371 u8 stbc : 1; 372 u8 beamformed : 1; 373 #else 374 u8 beamformed : 1; 375 u8 stbc : 1; 376 u8 ldpc : 1; 377 u8 gnt_bt : 1; 378 u8 hw_antsw_occu : 1; 379 u8 rsvd_0 : 1; 380 u8 band : 2; 381 #endif 382 383 /* @DW2 */ 384 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 385 u8 shift_l_map : 6; 386 u8 rsvd_1 : 2; 387 #else 388 u8 rsvd_1 : 2; 389 u8 shift_l_map : 6; 390 #endif 391 u8 cnt_pw2cca; 392 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 393 u8 agc_table_a : 4; 394 u8 agc_table_b : 4; 395 u8 agc_table_c : 4; 396 u8 agc_table_d : 4; 397 #else 398 u8 agc_table_b : 4; 399 u8 agc_table_a : 4; 400 u8 agc_table_d : 4; 401 u8 agc_table_c : 4; 402 #endif 403 404 /* @DW3 ~ DW6*/ 405 u8 cnt_cca2agc_rdy; 406 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 407 u8 gain_a : 6; 408 u8 rsvd_2 : 1; 409 u8 trsw_a : 1; 410 u8 gain_b : 6; 411 u8 rsvd_3 : 1; 412 u8 trsw_b : 1; 413 u8 gain_c : 6; 414 u8 rsvd_4 : 1; 415 u8 trsw_c : 1; 416 u8 gain_d : 6; 417 u8 rsvd_5 : 1; 418 u8 trsw_d : 1; 419 u8 aagc_step_a : 2; 420 u8 aagc_step_b : 2; 421 u8 aagc_step_c : 2; 422 u8 aagc_step_d : 2; 423 #else 424 u8 trsw_a : 1; 425 u8 rsvd_2 : 1; 426 u8 gain_a : 6; 427 u8 trsw_b : 1; 428 u8 rsvd_3 : 1; 429 u8 gain_b : 6; 430 u8 trsw_c : 1; 431 u8 rsvd_4 : 1; 432 u8 gain_c : 6; 433 u8 trsw_d : 1; 434 u8 rsvd_5 : 1; 435 u8 gain_d : 6; 436 u8 aagc_step_d : 2; 437 u8 aagc_step_c : 2; 438 u8 aagc_step_b : 2; 439 u8 aagc_step_a : 2; 440 #endif 441 u8 ht_aagc_gain[4]; 442 u8 dagc_gain[4]; 443 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 444 u8 counter : 6; 445 u8 rsvd_6 : 2; 446 u8 syn_count : 5; 447 u8 rsvd_7 : 3; 448 #else 449 u8 rsvd_6 : 2; 450 u8 counter : 6; 451 u8 rsvd_7 : 3; 452 u8 syn_count : 5; 453 #endif 454 }; 455 #endif 456 457 /*@==============================================*/ 458 #ifdef PHYSTS_3RD_TYPE_SUPPORT 459 __PACK struct phy_sts_rpt_jgr3_type0 { 460 /* @DW0 : Offset 0 */ 461 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 462 u8 page_num : 4; 463 u8 pkt_cnt : 2; 464 u8 channel_msb : 2; 465 #else 466 u8 channel_msb : 2; 467 u8 pkt_cnt : 2; 468 u8 page_num : 4; 469 #endif 470 u8 pwdb_a; 471 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 472 u8 gain_a : 6; 473 u8 rsvd_0 : 1; 474 u8 trsw : 1; 475 #else 476 u8 trsw : 1; 477 u8 rsvd_0 : 1; 478 u8 gain_a : 6; 479 #endif 480 481 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 482 u8 agc_table_b : 4; 483 u8 agc_table_c : 4; 484 #else 485 u8 agc_table_c : 4; 486 u8 agc_table_b : 4; 487 #endif 488 489 /* @DW1 : Offset 4 */ 490 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 491 u8 rsvd_1 : 4; 492 u8 agc_table_d : 4; 493 #else 494 u8 agc_table_d : 4; 495 u8 rsvd_1 : 4; 496 #endif 497 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 498 u8 l_rxsc : 4; 499 u8 agc_table_a : 4; 500 #else 501 u8 agc_table_a : 4; 502 u8 l_rxsc : 4; 503 #endif 504 u8 channel; 505 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 506 u8 band : 2; 507 u8 rsvd_2_1 : 1; 508 u8 hw_antsw_occur_keep_cck : 1; 509 u8 gnt_bt_keep_cck : 1; 510 u8 rsvd_2_2 : 1; 511 u8 path_sel_o : 2; 512 #else 513 u8 path_sel_o : 2; 514 u8 rsvd_2_2 : 1; 515 u8 gnt_bt_keep_cck : 1; 516 u8 hw_antsw_occur_keep_cck : 1; 517 u8 rsvd_2_1 : 1; 518 u8 band : 2; 519 #endif 520 521 /* @DW2 : Offset 8 */ 522 u16 length; 523 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 524 u8 antidx_a : 4; 525 u8 antidx_b : 4; 526 #else 527 u8 antidx_b : 4; 528 u8 antidx_a : 4; 529 #endif 530 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 531 u8 antidx_c : 4; 532 u8 antidx_d : 4; 533 #else 534 u8 antidx_d : 4; 535 u8 antidx_c : 4; 536 #endif 537 538 /* @DW3 : Offset 12 */ 539 u8 signal_quality; 540 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 541 u8 vga_a : 5; 542 u8 lna_l_a : 3; 543 #else 544 u8 lna_l_a : 3; 545 u8 vga_a : 5; 546 #endif 547 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 548 u8 bb_power_a : 6; 549 u8 rsvd_3_1 : 1; 550 u8 lna_h_a : 1; 551 #else 552 553 u8 lna_h_a : 1; 554 u8 rsvd_3_1 : 1; 555 u8 bb_power_a : 6; 556 #endif 557 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 558 u8 rxrate : 2; 559 u8 raterr : 1; 560 u8 lockbit : 1; 561 u8 sqloss : 1; 562 u8 mf_off : 1; 563 u8 rsvd_3_2 : 2; 564 #else 565 u8 rsvd_3_2 : 2; 566 u8 mf_off : 1; 567 u8 sqloss : 1; 568 u8 lockbit : 1; 569 u8 raterr : 1; 570 u8 rxrate : 2; 571 #endif 572 573 /* @DW4 : Offset 16 */ 574 u8 pwdb_b; 575 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 576 u8 vga_b : 5; 577 u8 lna_l_b : 3; 578 #else 579 u8 lna_l_b : 3; 580 u8 vga_b : 5; 581 #endif 582 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 583 u8 bb_power_b : 6; 584 u8 rsvd_4_1 : 1; 585 u8 lna_h_b : 1; 586 #else 587 u8 lna_h_b : 1; 588 u8 rsvd_4_1 : 1; 589 u8 bb_power_b : 6; 590 #endif 591 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 592 u8 gain_b : 6; 593 u8 rsvd_4_2 : 2; 594 #else 595 u8 rsvd_4_2 : 2; 596 u8 gain_b : 6; 597 #endif 598 599 /* @DW5 : Offset 20 */ 600 u8 pwdb_c; 601 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 602 u8 vga_c : 5; 603 u8 lna_l_c : 3; 604 #else 605 u8 lna_l_c : 3; 606 u8 vga_c : 5; 607 #endif 608 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 609 u8 bb_power_c : 6; 610 u8 rsvd_5_1 : 1; 611 u8 lna_h_c : 1; 612 #else 613 u8 lna_h_c : 1; 614 u8 rsvd_5_1 : 1; 615 u8 bb_power_c : 6; 616 #endif 617 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 618 u8 gain_c : 6; 619 u8 rsvd_5_2 : 2; 620 #else 621 u8 rsvd_5_2 : 2; 622 u8 gain_c : 6; 623 #endif 624 625 /* @DW6 : Offset 24 */ 626 u8 pwdb_d; 627 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 628 u8 vga_d : 5; 629 u8 lna_l_d : 3; 630 #else 631 u8 lna_l_d : 3; 632 u8 vga_d : 5; 633 #endif 634 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 635 u8 bb_power_d : 6; 636 u8 rsvd_6_1 : 1; 637 u8 lna_h_d : 1; 638 #else 639 u8 lna_h_d : 1; 640 u8 rsvd_6_1 : 1; 641 u8 bb_power_d : 6; 642 #endif 643 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 644 u8 gain_d : 6; 645 u8 rsvd_6_2 : 2; 646 #else 647 u8 rsvd_6_2 : 2; 648 u8 gain_d : 6; 649 #endif 650 }; 651 652 __PACK struct phy_sts_rpt_jgr3_type1 { 653 /* @DW0 : Offset 0 */ 654 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 655 u8 page_num : 4; 656 u8 pkt_cnt : 2; 657 u8 channel_pri_msb : 2; 658 #else 659 u8 channel_pri_msb : 2; 660 u8 pkt_cnt : 2; 661 u8 page_num : 4; 662 #endif 663 u8 pwdb_a; 664 u8 pwdb_b; 665 u8 pwdb_c; 666 667 /* @DW1 : Offset 4 */ 668 u8 pwdb_d; 669 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 670 u8 l_rxsc : 4; 671 u8 ht_rxsc : 4; 672 #else 673 u8 ht_rxsc : 4; 674 u8 l_rxsc : 4; 675 #endif 676 u8 channel_pri_lsb; 677 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 678 u8 band : 2; 679 u8 rsvd_0 : 2; 680 u8 gnt_bt : 1; 681 u8 ldpc : 1; 682 u8 stbc : 1; 683 u8 beamformed : 1; 684 #else 685 u8 beamformed : 1; 686 u8 stbc : 1; 687 u8 ldpc : 1; 688 u8 gnt_bt : 1; 689 u8 rsvd_0 : 2; 690 u8 band : 2; 691 #endif 692 693 /* @DW2 : Offset 8 */ 694 u8 channel_sec_lsb; 695 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 696 u8 channel_sec_msb : 2; 697 u8 rsvd_1 : 2; 698 u8 hw_antsw_occur_a : 1; 699 u8 hw_antsw_occur_b : 1; 700 u8 hw_antsw_occur_c : 1; 701 u8 hw_antsw_occur_d : 1; 702 #else 703 u8 hw_antsw_occur_d : 1; 704 u8 hw_antsw_occur_c : 1; 705 u8 hw_antsw_occur_b : 1; 706 u8 hw_antsw_occur_a : 1; 707 u8 rsvd_1 : 2; 708 u8 channel_sec_msb : 2; 709 710 #endif 711 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 712 u8 antidx_a : 4; 713 u8 antidx_b : 4; 714 #else 715 u8 antidx_b : 4; 716 u8 antidx_a : 4; 717 #endif 718 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 719 u8 antidx_c : 4; 720 u8 antidx_d : 4; 721 #else 722 u8 antidx_d : 4; 723 u8 antidx_c : 4; 724 #endif 725 726 /* @DW3 : Offset 12 */ 727 u8 paid; 728 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 729 u8 paid_msb : 1; 730 u8 gid : 6; 731 u8 rsvd_3 : 1; 732 #else 733 u8 rsvd_3 : 1; 734 u8 gid : 6; 735 u8 paid_msb : 1; 736 #endif 737 u16 rsvd_4; 738 #if 0 739 /*@ 740 u8 rsvd_4; 741 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 742 u8 rsvd_5: 6; 743 u8 rf_mode: 2; 744 #else 745 u8 rf_mode: 2; 746 u8 rsvd_5: 6; 747 #endif 748 */ 749 #endif 750 /* @DW4 : Offset 16 */ 751 s8 rxevm[4]; /* s(8,1) */ 752 753 /* @DW5 : Offset 20 */ 754 s8 cfo_tail[4]; /* s(8,7) */ 755 756 /* @DW6 : Offset 24 */ 757 s8 rxsnr[4]; /* s(8,1) */ 758 }; 759 760 __PACK struct phy_sts_rpt_jgr3_type2_3 { 761 /* Type2 is primary channel & type3 is secondary channel */ 762 /* @DW0 and DW1: Offest 0 and Offset 4 */ 763 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 764 u8 page_num : 4; 765 u8 pkt_cnt : 2; 766 u8 channel_msb : 2; 767 #else 768 u8 channel_msb : 2; 769 u8 pkt_cnt : 2; 770 u8 page_num : 4; 771 #endif 772 u8 pwdb[4]; 773 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 774 u8 l_rxsc : 4; 775 u8 ht_rxsc : 4; 776 #else 777 u8 ht_rxsc : 4; 778 u8 l_rxsc : 4; 779 #endif 780 u8 channel_lsb; 781 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 782 u8 band : 2; 783 u8 rsvd_0 : 2; 784 u8 gnt_bt : 1; 785 u8 ldpc : 1; 786 u8 stbc : 1; 787 u8 beamformed : 1; 788 #else 789 u8 beamformed : 1; 790 u8 stbc : 1; 791 u8 ldpc : 1; 792 u8 gnt_bt : 1; 793 u8 rsvd_0 : 2; 794 u8 band : 2; 795 #endif 796 797 /* @DW2 : Offset 8 */ 798 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 799 u8 shift_l_map : 6; 800 u8 rsvd_1 : 2; 801 #else 802 u8 rsvd_1 : 2; 803 u8 shift_l_map : 6; 804 #endif 805 s8 pwed_th; /* @dynamic energy threshold S(8,2) */ 806 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 807 u8 agc_table_a : 4; 808 u8 agc_table_b : 4; 809 #else 810 u8 agc_table_b : 4; 811 u8 agc_table_a : 4; 812 #endif 813 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 814 u8 agc_table_c : 4; 815 u8 agc_table_d : 4; 816 #else 817 u8 agc_table_d : 4; 818 u8 agc_table_c : 4; 819 #endif 820 821 /* @DW3 : Offset 12 */ 822 u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */ 823 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 824 u8 mp_gain_a : 6; 825 u8 mp_gain_b_lsb : 2; 826 #else 827 u8 mp_gain_b_lsb : 2; 828 u8 mp_gain_a : 6; 829 #endif 830 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 831 u8 mp_gain_b_msb : 4; 832 u8 mp_gain_c_lsb : 4; 833 #else 834 u8 mp_gain_c_lsb : 4; 835 u8 mp_gain_b_msb : 4; 836 #endif 837 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 838 u8 mp_gain_c_msb : 2; 839 u8 avg_noise_pwr_lsb : 4; 840 u8 rsvd_3 : 2; 841 /* u8 r_rfmod:2; */ 842 #else 843 /* u8 r_rfmod:2; */ 844 u8 rsvd_3 : 2; 845 u8 avg_noise_pwr_lsb : 4; 846 u8 mp_gain_c_msb : 2; 847 #endif 848 /* @DW4 ~ 5: offset 16 ~20 */ 849 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 850 u8 mp_gain_d : 6; 851 u8 is_freq_select_fading : 1; 852 u8 rsvd_2 : 1; 853 #else 854 u8 rsvd_2 : 1; 855 u8 is_freq_select_fading : 1; 856 u8 mp_gain_d : 6; 857 #endif 858 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 859 u8 aagc_step_a : 2; 860 u8 aagc_step_b : 2; 861 u8 aagc_step_c : 2; 862 u8 aagc_step_d : 2; 863 #else 864 u8 aagc_step_d : 2; 865 u8 aagc_step_c : 2; 866 u8 aagc_step_b : 2; 867 u8 aagc_step_a : 2; 868 #endif 869 u8 ht_aagc_gain[4]; 870 u8 dagc_gain[4]; 871 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 872 u8 counter : 6; 873 u8 syn_count_lsb : 2; 874 #else 875 u8 syn_count_lsb : 2; 876 u8 counter : 6; 877 #endif 878 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 879 u8 syn_count_msb : 3; 880 u8 avg_noise_pwr_msb : 5; 881 #else 882 u8 avg_noise_pwr_msb : 5; 883 u8 syn_count_msb : 3; 884 #endif 885 }; 886 887 __PACK struct phy_sts_rpt_jgr3_type4 { 888 /* smart antenna */ 889 /* @DW0 and DW1 : offset 0 and 4 */ 890 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 891 u8 page_num : 4; 892 u8 pkt_cnt : 2; 893 u8 channel_msb : 2; 894 #else 895 u8 channel_msb : 2; 896 u8 pkt_cnt : 2; 897 u8 page_num : 4; 898 #endif 899 u8 pwdb[4]; 900 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 901 u8 l_rxsc : 4; 902 u8 ht_rxsc : 4; 903 #else 904 u8 ht_rxsc : 4; 905 u8 l_rxsc : 4; 906 #endif 907 u8 channel_lsb; 908 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 909 u8 band : 2; 910 u8 rsvd_0 : 2; 911 u8 gnt_bt : 1; 912 u8 ldpc : 1; 913 u8 stbc : 1; 914 u8 beamformed : 1; 915 #else 916 u8 beamformed : 1; 917 u8 stbc : 1; 918 u8 ldpc : 1; 919 u8 gnt_bt : 1; 920 u8 rsvd_0 : 1; 921 u8 band : 2; 922 #endif 923 924 /* @DW2 : offset 8 */ 925 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 926 u8 bad_tone_cnt_min_eign_0 : 4; 927 u8 bad_tone_cnt_cn_excess_0 : 4; 928 #else 929 u8 bad_tone_cnt_cn_excess_0 : 4; 930 u8 bad_tone_cnt_min_eign_0 : 4; 931 #endif 932 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 933 u8 training_done_a : 1; 934 u8 training_done_b : 1; 935 u8 training_done_c : 1; 936 u8 training_done_d : 1; 937 u8 hw_antsw_occur_a : 1; 938 u8 hw_antsw_occur_b : 1; 939 u8 hw_antsw_occur_c : 1; 940 u8 hw_antsw_occur_d : 1; 941 #else 942 u8 hw_antsw_occur_d : 1; 943 u8 hw_antsw_occur_c : 1; 944 u8 hw_antsw_occur_b : 1; 945 u8 hw_antsw_occur_a : 1; 946 u8 training_done_d : 1; 947 u8 training_done_c : 1; 948 u8 training_done_b : 1; 949 u8 training_done_a : 1; 950 #endif 951 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 952 u8 antidx_a : 4; 953 u8 antidx_b : 4; 954 #else 955 u8 antidx_b : 4; 956 u8 antidx_a : 4; 957 #endif 958 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 959 u8 antidx_c : 4; 960 u8 antidx_d : 4; 961 #else 962 u8 antidx_d : 4; 963 u8 antidx_c : 4; 964 #endif 965 /* @DW3 : offset 12 */ 966 u8 tx_pkt_cnt; 967 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 968 u8 bad_tone_cnt_min_eign_1 : 4; 969 u8 bad_tone_cnt_cn_excess_1 : 4; 970 #else 971 u8 bad_tone_cnt_cn_excess_1 : 4; 972 u8 bad_tone_cnt_min_eign_1 : 4; 973 #endif 974 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 975 u8 avg_cond_num_0 : 7; 976 u8 avg_cond_num_1_lsb : 1; 977 #else 978 u8 avg_cond_num_1_lsb : 1; 979 u8 avg_cond_num_0 : 7; 980 #endif 981 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 982 u8 avg_cond_num_1_msb : 6; 983 u8 rsvd_1 : 2; 984 #else 985 u8 rsvd_1 : 2; 986 u8 avg_cond_num_1_msb : 6; 987 #endif 988 989 /* @DW4 : offset 16 */ 990 s8 rxevm[4]; /* s(8,1) */ 991 992 /* @DW5 : offset 20 */ 993 u8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */ 994 995 /* @DW6 : ofset 24 */ 996 s8 rxsnr[4]; /* s(8,1) */ 997 }; 998 999 __PACK struct phy_sts_rpt_jgr3_type5 { 1000 /* @Debug */ 1001 /* @DW0 ane DW1 : offset 0 and 4 */ 1002 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1003 u8 page_num : 4; 1004 u8 pkt_cnt : 2; 1005 u8 channel_msb : 2; 1006 #else 1007 u8 channel_msb : 2; 1008 u8 pkt_cnt : 2; 1009 u8 page_num : 4; 1010 #endif 1011 u8 pwdb[4]; 1012 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1013 u8 l_rxsc : 4; 1014 u8 ht_rxsc : 4; 1015 #else 1016 u8 ht_rxsc : 4; 1017 u8 l_rxsc : 4; 1018 #endif 1019 u8 channel_lsb; 1020 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1021 u8 band : 2; 1022 u8 rsvd_0 : 2; 1023 u8 gnt_bt : 1; 1024 u8 ldpc : 1; 1025 u8 stbc : 1; 1026 u8 beamformed : 1; 1027 #else 1028 u8 beamformed : 1; 1029 u8 stbc : 1; 1030 u8 ldpc : 1; 1031 u8 gnt_bt : 1; 1032 u8 rsvd_0 : 2; 1033 u8 band : 2; 1034 #endif 1035 /* @DW2 : offset 8 */ 1036 u8 rsvd_1; 1037 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1038 u8 rsvd_2 : 4; 1039 u8 hw_antsw_occur_a : 1; 1040 u8 hw_antsw_occur_b : 1; 1041 u8 hw_antsw_occur_c : 1; 1042 u8 hw_antsw_occur_d : 1; 1043 #else 1044 u8 hw_antsw_occur_d : 1; 1045 u8 hw_antsw_occur_c : 1; 1046 u8 hw_antsw_occur_b : 1; 1047 u8 hw_antsw_occur_a : 1; 1048 u8 rsvd_2 : 4; 1049 #endif 1050 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1051 u8 antidx_a : 4; 1052 u8 antidx_b : 4; 1053 #else 1054 u8 antidx_b : 4; 1055 u8 antidx_a : 4; 1056 #endif 1057 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1058 u8 antidx_c : 4; 1059 u8 antidx_d : 4; 1060 #else 1061 u8 antidx_d : 4; 1062 u8 antidx_c : 4; 1063 #endif 1064 /* @DW3 : offset 12 */ 1065 u8 tx_pkt_cnt; 1066 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1067 u8 inf_pos_0_A_flg : 1; 1068 u8 inf_pos_1_A_flg : 1; 1069 u8 inf_pos_0_B_flg : 1; 1070 u8 inf_pos_1_B_flg : 1; 1071 u8 inf_pos_0_C_flg : 1; 1072 u8 inf_pos_1_C_flg : 1; 1073 u8 inf_pos_0_D_flg : 1; 1074 u8 inf_pos_1_D_flg : 1; 1075 #else 1076 u8 inf_pos_1_D_flg : 1; 1077 u8 inf_pos_0_D_flg : 1; 1078 u8 inf_pos_1_C_flg : 1; 1079 u8 inf_pos_0_C_flg : 1; 1080 u8 inf_pos_1_B_flg : 1; 1081 u8 inf_pos_0_B_flg : 1; 1082 u8 inf_pos_1_A_flg : 1; 1083 u8 inf_pos_0_A_flg : 1; 1084 #endif 1085 u8 rsvd_3; 1086 u8 rsvd_4; 1087 /* @DW4 : offset 16 */ 1088 u8 inf_pos_0_a; 1089 u8 inf_pos_1_a; 1090 u8 inf_pos_0_b; 1091 u8 inf_pos_1_b; 1092 /* @DW5 : offset 20 */ 1093 u8 inf_pos_0_c; 1094 u8 inf_pos_1_c; 1095 u8 inf_pos_0_d; 1096 u8 inf_pos_1_d; 1097 }; 1098 1099 __PACK struct phy_sts_rpt_jgr3_ofdm_cmn { 1100 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1101 u8 page_num : 4; 1102 u8 pkt_cnt : 2; 1103 u8 channel_msb : 2; 1104 #else 1105 u8 channel_msb : 2; 1106 u8 pkt_cnt : 2; 1107 u8 page_num : 4; 1108 #endif 1109 u8 pwdb[4]; 1110 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1111 u8 l_rxsc : 4; 1112 u8 ht_rxsc : 4; 1113 #else 1114 u8 ht_rxsc : 4; 1115 u8 l_rxsc : 4; 1116 #endif 1117 u8 channel_lsb; 1118 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 1119 u8 band : 2; 1120 u8 rsvd_0 : 2; 1121 u8 gnt_bt : 1; 1122 u8 ldpc : 1; 1123 u8 stbc : 1; 1124 u8 beamformed : 1; 1125 #else 1126 u8 beamformed : 1; 1127 u8 stbc : 1; 1128 u8 ldpc : 1; 1129 u8 gnt_bt : 1; 1130 u8 rsvd_0 : 1; 1131 u8 band : 2; 1132 #endif 1133 }; 1134 #endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/ 1135 1136 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 1137 void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable, 1138 u8 bitmap_en); 1139 #endif 1140 1141 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 1142 boolean 1143 phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate, 1144 u8 *p_gid); 1145 #endif 1146 1147 void phydm_reset_phystatus_avg(struct dm_struct *dm); 1148 1149 void phydm_reset_phystatus_statistic(struct dm_struct *dm); 1150 1151 void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id); 1152 1153 void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm); 1154 1155 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1156 void phydm_normal_driver_rx_sniffer( 1157 struct dm_struct *dm, 1158 u8 *desc, 1159 PRT_RFD_STATUS rt_rfd_status, 1160 u8 *drv_info, 1161 u8 phy_status); 1162 #endif 1163 1164 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1165 s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig); 1166 #endif 1167 1168 boolean odm_phy_status_query(struct dm_struct *dm, 1169 struct phydm_phyinfo_struct *phy_info, 1170 u8 *phy_sts, 1171 struct phydm_perpkt_info_struct *pktinfo); 1172 1173 void phydm_rx_phy_status_init(void *dm_void); 1174 1175 void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used, 1176 char *output, u32 *_out_len); 1177 1178 #endif /*@#ifndef __HALHWOUTSRC_H__*/ 1179