1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_MP_SUPPORT
34 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
35
phydm_mp_set_single_tone_jgr3(void * dm_void,boolean is_single_tone,u8 path)36 void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
37 u8 path)
38 {
39 struct dm_struct *dm = (struct dm_struct *)dm_void;
40 struct phydm_mp *mp = &dm->dm_mp_table;
41 u8 start = RF_PATH_A, end = RF_PATH_A;
42 u8 i = 0;
43
44 switch (path) {
45 case RF_PATH_A:
46 case RF_PATH_B:
47 case RF_PATH_C:
48 case RF_PATH_D:
49 start = path;
50 end = path;
51 break;
52 case RF_PATH_AB:
53 start = RF_PATH_A;
54 end = RF_PATH_B;
55 break;
56 #if (defined(PHYDM_COMPILE_IC_4SS))
57 case RF_PATH_AC:
58 start = RF_PATH_A;
59 end = RF_PATH_C;
60 break;
61 case RF_PATH_AD:
62 start = RF_PATH_A;
63 end = RF_PATH_D;
64 break;
65 case RF_PATH_BC:
66 start = RF_PATH_B;
67 end = RF_PATH_C;
68 break;
69 case RF_PATH_BD:
70 start = RF_PATH_B;
71 end = RF_PATH_D;
72 break;
73 case RF_PATH_CD:
74 start = RF_PATH_C;
75 end = RF_PATH_D;
76 break;
77 case RF_PATH_ABC:
78 start = RF_PATH_A;
79 end = RF_PATH_C;
80 break;
81 case RF_PATH_ABD:
82 start = RF_PATH_A;
83 end = RF_PATH_D;
84 break;
85 case RF_PATH_ACD:
86 start = RF_PATH_A;
87 end = RF_PATH_D;
88 break;
89 case RF_PATH_BCD:
90 start = RF_PATH_B;
91 end = RF_PATH_D;
92 break;
93 case RF_PATH_ABCD:
94 start = RF_PATH_A;
95 end = RF_PATH_D;
96 break;
97 #endif
98 }
99 if (is_single_tone) {
100 /* Disable CCK and OFDM */
101 odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);
102 for (i = start; i <= end; i++) {
103 /* @Tx mode: RF0x00[19:16]=4'b0010 */
104 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
105 /*Lowest RF gain index: RF_0x0[4:0] = 0*/
106 odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
107 /*RF LO enabled */
108 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
109 }
110 #if (RTL8814B_SUPPORT)
111 if (dm->support_ic_type & ODM_RTL8814B) {
112 /*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
113 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
114 0x1f, 0x0);
115 /*RF LO enabled */
116 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
117 BIT(1), 0x1);
118 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
119 /*SYN1*/
120 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
121 RF_0x0, 0x1f,
122 0x0);
123 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
124 RF_0x58, BIT(1),
125 0x1);
126 }
127 }
128 #endif
129 } else {
130 /*Enable CCK and OFDM */
131 odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);
132 /*RF LO disabled */
133 for (i = start; i <= end; i++)
134 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
135 #if (RTL8814B_SUPPORT)
136 if (dm->support_ic_type & ODM_RTL8814B) {
137 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
138 BIT(1), 0x1);
139 if (*dm->band_width == CHANNEL_WIDTH_80_80)
140 /*SYN1*/
141 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
142 RF_0x58, BIT(1),
143 0x1);
144 }
145 #endif
146 }
147 }
148
phydm_mp_set_carrier_supp_jgr3(void * dm_void,boolean is_carrier_supp,u32 rate_index)149 void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
150 u32 rate_index)
151 {
152 struct dm_struct *dm = (struct dm_struct *)dm_void;
153 struct phydm_mp *mp = &dm->dm_mp_table;
154
155 if (is_carrier_supp) {
156 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
157 /*if CCK block on? */
158 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
159 odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
160
161 /*Turn Off All Test mode */
162 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
163
164 /*transmit mode */
165 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
166 /*turn off scramble setting */
167 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
168 /*Set CCK Tx Test Rate, set FTxRate to 1Mbps */
169 odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
170 }
171 } else { /*Stop Carrier Suppression. */
172 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
173 /*normal mode */
174 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
175 /*turn on scramble setting */
176 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
177 /*BB Reset */
178 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
179 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
180 }
181 }
182 }
183
phydm_mp_set_single_carrier_jgr3(void * dm_void,boolean is_single_carrier)184 void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
185 {
186 struct dm_struct *dm = (struct dm_struct *)dm_void;
187 struct phydm_mp *mp = &dm->dm_mp_table;
188
189 if (is_single_carrier) {
190 /*1. if OFDM block on? */
191 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
192 odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
193
194 /*2. set CCK test mode off, set to CCK normal mode */
195 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
196
197 /*3. turn on scramble setting */
198 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
199
200 /*4. Turn On single carrier. */
201 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
202 } else {
203 /*Turn off all test modes. */
204 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
205
206 /*Delay 10 ms */
207 ODM_delay_ms(10);
208
209 /*BB Reset*/
210 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
211 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
212 }
213 }
214
phydm_mp_get_tx_ok_jgr3(void * dm_void,u32 rate_index)215 void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
216 {
217 struct dm_struct *dm = (struct dm_struct *)dm_void;
218 struct phydm_mp *mp = &dm->dm_mp_table;
219
220 if (phydm_is_cck_rate(dm, (u8)rate_index))
221 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
222 else
223 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
224 }
225
phydm_mp_get_rx_ok_jgr3(void * dm_void)226 void phydm_mp_get_rx_ok_jgr3(void *dm_void)
227 {
228 struct dm_struct *dm = (struct dm_struct *)dm_void;
229 struct phydm_mp *mp = &dm->dm_mp_table;
230
231 u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
232 u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
233
234 cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
235 ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
236 ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
237 vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
238
239 cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
240 ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
241 ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
242 vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
243
244 mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
245 mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
246 mp->io_value = (u32)mp->rx_phy_ok_cnt;
247 }
248 #endif
phydm_mp_set_crystal_cap(void * dm_void,u8 crystal_cap)249 void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
250 {
251 struct dm_struct *dm = (struct dm_struct *)dm_void;
252
253 phydm_set_crystal_cap(dm, crystal_cap);
254 }
255
phydm_mp_set_single_tone(void * dm_void,boolean is_single_tone,u8 path)256 void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
257 {
258 struct dm_struct *dm = (struct dm_struct *)dm_void;
259
260 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
261 phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
262 }
263
phydm_mp_set_carrier_supp(void * dm_void,boolean is_carrier_supp,u32 rate_index)264 void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
265 u32 rate_index)
266 {
267 struct dm_struct *dm = (struct dm_struct *)dm_void;
268
269 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
270 phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
271 }
272
phydm_mp_set_single_carrier(void * dm_void,boolean is_single_carrier)273 void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
274 {
275 struct dm_struct *dm = (struct dm_struct *)dm_void;
276
277 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
278 phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
279 }
phydm_mp_reset_rx_counters_phy(void * dm_void)280 void phydm_mp_reset_rx_counters_phy(void *dm_void)
281 {
282 struct dm_struct *dm = (struct dm_struct *)dm_void;
283
284 phydm_reset_bb_hw_cnt(dm);
285 }
286
phydm_mp_get_tx_ok(void * dm_void,u32 rate_index)287 void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
288 {
289 struct dm_struct *dm = (struct dm_struct *)dm_void;
290
291 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
292 phydm_mp_get_tx_ok_jgr3(dm, rate_index);
293 }
294
phydm_mp_get_rx_ok(void * dm_void)295 void phydm_mp_get_rx_ok(void *dm_void)
296 {
297 struct dm_struct *dm = (struct dm_struct *)dm_void;
298
299 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
300 phydm_mp_get_rx_ok_jgr3(dm);
301 }
302 #endif
303