1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 /*@
34 * ODM IO Relative API.
35 */
36
odm_read_1byte(struct dm_struct * dm,u32 reg_addr)37 u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)
38 {
39 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
40 struct rtl8192cd_priv *priv = dm->priv;
41 return RTL_R8(reg_addr);
42 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
43 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
44
45 return rtl_read_byte(rtlpriv, reg_addr);
46 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
47 struct rtw_dev *rtwdev = dm->adapter;
48
49 return rtw_read8(rtwdev, reg_addr);
50 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
51 void *adapter = dm->adapter;
52 return rtw_read8(adapter, reg_addr);
53 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
54 void *adapter = dm->adapter;
55 return PlatformEFIORead1Byte(adapter, reg_addr);
56 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
57 void *adapter = dm->adapter;
58
59 return rtw_read8(adapter, reg_addr);
60 #endif
61 }
62
odm_read_2byte(struct dm_struct * dm,u32 reg_addr)63 u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)
64 {
65 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
66 struct rtl8192cd_priv *priv = dm->priv;
67 return RTL_R16(reg_addr);
68 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
69 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
70
71 return rtl_read_word(rtlpriv, reg_addr);
72 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
73 struct rtw_dev *rtwdev = dm->adapter;
74
75 return rtw_read16(rtwdev, reg_addr);
76 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
77 void *adapter = dm->adapter;
78 return rtw_read16(adapter, reg_addr);
79 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
80 void *adapter = dm->adapter;
81 return PlatformEFIORead2Byte(adapter, reg_addr);
82 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
83 void *adapter = dm->adapter;
84
85 return rtw_read16(adapter, reg_addr);
86 #endif
87 }
88
odm_read_4byte(struct dm_struct * dm,u32 reg_addr)89 u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)
90 {
91 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
92 struct rtl8192cd_priv *priv = dm->priv;
93 return RTL_R32(reg_addr);
94 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
95 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
96
97 return rtl_read_dword(rtlpriv, reg_addr);
98 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
99 struct rtw_dev *rtwdev = dm->adapter;
100
101 return rtw_read32(rtwdev, reg_addr);
102 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
103 void *adapter = dm->adapter;
104 return rtw_read32(adapter, reg_addr);
105 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
106 void *adapter = dm->adapter;
107 return PlatformEFIORead4Byte(adapter, reg_addr);
108 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
109 void *adapter = dm->adapter;
110
111 return rtw_read32(adapter, reg_addr);
112 #endif
113 }
114
odm_write_1byte(struct dm_struct * dm,u32 reg_addr,u8 data)115 void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
116 {
117 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
118 struct rtl8192cd_priv *priv = dm->priv;
119 RTL_W8(reg_addr, data);
120 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
121 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
122
123 rtl_write_byte(rtlpriv, reg_addr, data);
124 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
125 struct rtw_dev *rtwdev = dm->adapter;
126
127 rtw_write8(rtwdev, reg_addr, data);
128 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
129 void *adapter = dm->adapter;
130 rtw_write8(adapter, reg_addr, data);
131 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
132 void *adapter = dm->adapter;
133 PlatformEFIOWrite1Byte(adapter, reg_addr, data);
134 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
135 void *adapter = dm->adapter;
136
137 rtw_write8(adapter, reg_addr, data);
138 #endif
139
140 if (dm->en_reg_mntr_byte)
141 pr_debug("1byte:addr=0x%x, data=0x%x\n", reg_addr, data);
142 }
143
odm_write_2byte(struct dm_struct * dm,u32 reg_addr,u16 data)144 void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
145 {
146 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
147 struct rtl8192cd_priv *priv = dm->priv;
148 RTL_W16(reg_addr, data);
149 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
150 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
151
152 rtl_write_word(rtlpriv, reg_addr, data);
153 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
154 struct rtw_dev *rtwdev = dm->adapter;
155
156 rtw_write16(rtwdev, reg_addr, data);
157 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
158 void *adapter = dm->adapter;
159 rtw_write16(adapter, reg_addr, data);
160 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
161 void *adapter = dm->adapter;
162 PlatformEFIOWrite2Byte(adapter, reg_addr, data);
163 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
164 void *adapter = dm->adapter;
165
166 rtw_write16(adapter, reg_addr, data);
167 #endif
168
169 if (dm->en_reg_mntr_byte)
170 pr_debug("2byte:addr=0x%x, data=0x%x\n", reg_addr, data);
171 }
172
odm_write_4byte(struct dm_struct * dm,u32 reg_addr,u32 data)173 void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
174 {
175 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
176 struct rtl8192cd_priv *priv = dm->priv;
177 RTL_W32(reg_addr, data);
178 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
179 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
180
181 rtl_write_dword(rtlpriv, reg_addr, data);
182 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
183 struct rtw_dev *rtwdev = dm->adapter;
184
185 rtw_write32(rtwdev, reg_addr, data);
186 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
187 void *adapter = dm->adapter;
188 rtw_write32(adapter, reg_addr, data);
189 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
190 void *adapter = dm->adapter;
191 PlatformEFIOWrite4Byte(adapter, reg_addr, data);
192 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
193 void *adapter = dm->adapter;
194
195 rtw_write32(adapter, reg_addr, data);
196 #endif
197
198 if (dm->en_reg_mntr_byte)
199 pr_debug("4byte:addr=0x%x, data=0x%x\n", reg_addr, data);
200 }
201
odm_set_mac_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask,u32 data)202 void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
203 {
204 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
205 phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
206 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
207 void *adapter = dm->adapter;
208 PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
209 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
210 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
211
212 rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
213 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
214 struct rtw_dev *rtwdev = dm->adapter;
215
216 rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
217 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
218 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
219 #else
220 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
221 #endif
222
223 if (dm->en_reg_mntr_mac)
224 pr_debug("MAC:addr=0x%x, mask=0x%x, data=0x%x\n",
225 reg_addr, bit_mask, data);
226 }
227
odm_get_mac_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask)228 u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
229 {
230 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
231 return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
232 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
233 return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask);
234 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
235 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
236
237 return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
238 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
239 struct rtw_dev *rtwdev = dm->adapter;
240
241 return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
242 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
243 return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
244 #else
245 return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask);
246 #endif
247 }
248
odm_set_bb_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask,u32 data)249 void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
250 {
251 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
252 phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
253 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
254 void *adapter = dm->adapter;
255 PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
256 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
257 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
258
259 rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
260 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
261 struct rtw_dev *rtwdev = dm->adapter;
262
263 rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
264 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
265 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
266 #else
267 phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
268 #endif
269
270 if (dm->en_reg_mntr_bb)
271 pr_debug("BB:addr=0x%x, mask=0x%x, data=0x%x\n",
272 reg_addr, bit_mask, data);
273 }
274
odm_get_bb_reg(struct dm_struct * dm,u32 reg_addr,u32 bit_mask)275 u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
276 {
277 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
278 return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
279 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
280 void *adapter = dm->adapter;
281 return PHY_QueryBBReg(adapter, reg_addr, bit_mask);
282 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
283 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
284
285 return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
286 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
287 struct rtw_dev *rtwdev = dm->adapter;
288
289 return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
290 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
291 return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
292 #else
293 return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
294 #endif
295 }
296
odm_set_rf_reg(struct dm_struct * dm,u8 e_rf_path,u32 reg_addr,u32 bit_mask,u32 data)297 void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
298 u32 bit_mask, u32 data)
299 {
300 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
301 phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data);
302 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
303 void *adapter = dm->adapter;
304 PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);
305 ODM_delay_us(2);
306
307 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
308 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
309
310 rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data);
311 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
312 struct rtw_dev *rtwdev = dm->adapter;
313
314 rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data);
315 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
316 phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
317 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
318 phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
319 ODM_delay_us(2);
320 #endif
321
322 if (dm->en_reg_mntr_rf)
323 pr_debug("RF:path=0x%x, addr=0x%x, mask=0x%x, data=0x%x\n",
324 e_rf_path, reg_addr, bit_mask, data);
325 }
326
odm_get_rf_reg(struct dm_struct * dm,u8 e_rf_path,u32 reg_addr,u32 bit_mask)327 u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
328 u32 bit_mask)
329 {
330 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
331 return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1);
332 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
333 void *adapter = dm->adapter;
334 return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);
335 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
336 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
337
338 return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask);
339 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
340 struct rtw_dev *rtwdev = dm->adapter;
341
342 return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask);
343 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
344 return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
345 #else
346 return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
347 #endif
348 }
349
350 enum hal_status
phydm_set_reg_by_fw(struct dm_struct * dm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)351 phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
352 u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
353 u32 delay_time)
354 {
355 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
356 return HAL_MAC_Config_PHY_WriteNByte(dm,
357 config_type,
358 offset,
359 data,
360 mask,
361 e_rf_path,
362 delay_time);
363 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
364 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
365 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
366 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
367 return -ENOTSUPP;
368 #else
369 return rtw_phydm_cfg_phy_para(dm,
370 config_type,
371 offset,
372 data,
373 mask,
374 e_rf_path,
375 delay_time);
376 #endif
377 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
378 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
379 #endif
380 }
381
382 /*@
383 * ODM Memory relative API.
384 */
odm_allocate_memory(struct dm_struct * dm,void ** ptr,u32 length)385 void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length)
386 {
387 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
388 *ptr = kmalloc(length, GFP_ATOMIC);
389 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
390 *ptr = kmalloc(length, GFP_ATOMIC);
391 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
392 *ptr = kmalloc(length, GFP_ATOMIC);
393 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
394 *ptr = rtw_zvmalloc(length);
395 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
396 void *adapter = dm->adapter;
397 PlatformAllocateMemory(adapter, ptr, length);
398 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
399 *ptr = rtw_zvmalloc(length);
400 #endif
401 }
402
403 /* @length could be ignored, used to detect memory leakage. */
odm_free_memory(struct dm_struct * dm,void * ptr,u32 length)404 void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length)
405 {
406 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
407 kfree(ptr);
408 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
409 kfree(ptr);
410 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
411 kfree(ptr);
412 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
413 rtw_vmfree(ptr, length);
414 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
415 /* struct void* adapter = dm->adapter; */
416 PlatformFreeMemory(ptr, length);
417 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
418 rtw_vmfree(ptr, length);
419 #endif
420 }
421
odm_move_memory(struct dm_struct * dm,void * dest,void * src,u32 length)422 void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length)
423 {
424 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
425 memcpy(dest, src, length);
426 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
427 memcpy(dest, src, length);
428 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
429 memcpy(dest, src, length);
430 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
431 _rtw_memcpy(dest, src, length);
432 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
433 PlatformMoveMemory(dest, src, length);
434 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
435 rtw_memcpy(dest, src, length);
436 #endif
437 }
438
odm_memory_set(struct dm_struct * dm,void * pbuf,s8 value,u32 length)439 void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length)
440 {
441 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
442 memset(pbuf, value, length);
443 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
444 memset(pbuf, value, length);
445 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
446 memset(pbuf, value, length);
447 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
448 _rtw_memset(pbuf, value, length);
449 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
450 PlatformFillMemory(pbuf, length, value);
451 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
452 rtw_memset(pbuf, value, length);
453 #endif
454 }
455
odm_compare_memory(struct dm_struct * dm,void * buf1,void * buf2,u32 length)456 s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length)
457 {
458 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
459 return memcmp(buf1, buf2, length);
460 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
461 return memcmp(buf1, buf2, length);
462 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
463 return memcmp(buf1, buf2, length);
464 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
465 return _rtw_memcmp(buf1, buf2, length);
466 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
467 return PlatformCompareMemory(buf1, buf2, length);
468 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
469 return rtw_memcmp(buf1, buf2, length);
470 #endif
471 }
472
473 /*@
474 * ODM MISC relative API.
475 */
odm_acquire_spin_lock(struct dm_struct * dm,enum rt_spinlock_type type)476 void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
477 {
478 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
479
480 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
481 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
482
483 rtl_odm_acquirespinlock(rtlpriv, type);
484 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
485 struct rtw_dev *rtwdev = dm->adapter;
486
487 spin_lock(&rtwdev->hal.dm_lock);
488 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
489 void *adapter = dm->adapter;
490 rtw_odm_acquirespinlock(adapter, type);
491 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
492 void *adapter = dm->adapter;
493 PlatformAcquireSpinLock(adapter, type);
494 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
495 void *adapter = dm->adapter;
496
497 rtw_odm_acquirespinlock(adapter, type);
498 #endif
499 }
500
odm_release_spin_lock(struct dm_struct * dm,enum rt_spinlock_type type)501 void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
502 {
503 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
504
505 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
506 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
507
508 rtl_odm_releasespinlock(rtlpriv, type);
509 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
510 struct rtw_dev *rtwdev = dm->adapter;
511
512 spin_unlock(&rtwdev->hal.dm_lock);
513 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
514 void *adapter = dm->adapter;
515 rtw_odm_releasespinlock(adapter, type);
516 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
517 void *adapter = dm->adapter;
518 PlatformReleaseSpinLock(adapter, type);
519 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
520 void *adapter = dm->adapter;
521
522 rtw_odm_releasespinlock(adapter, type);
523 #endif
524 }
525
526 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
527 /*@
528 * Work item relative API. FOr MP driver only~!
529 * */
odm_initialize_work_item(struct dm_struct * dm,PRT_WORK_ITEM work_item,RT_WORKITEM_CALL_BACK callback,void * context,const char * id)530 void odm_initialize_work_item(
531 struct dm_struct *dm,
532 PRT_WORK_ITEM work_item,
533 RT_WORKITEM_CALL_BACK callback,
534 void *context,
535 const char *id)
536 {
537 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
538
539 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
540
541 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
542 void *adapter = dm->adapter;
543 PlatformInitializeWorkItem(adapter, work_item, callback, context, id);
544 #endif
545 }
546
odm_start_work_item(PRT_WORK_ITEM p_rt_work_item)547 void odm_start_work_item(
548 PRT_WORK_ITEM p_rt_work_item)
549 {
550 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
551
552 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
553
554 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
555 PlatformStartWorkItem(p_rt_work_item);
556 #endif
557 }
558
odm_stop_work_item(PRT_WORK_ITEM p_rt_work_item)559 void odm_stop_work_item(
560 PRT_WORK_ITEM p_rt_work_item)
561 {
562 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
563
564 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
565
566 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
567 PlatformStopWorkItem(p_rt_work_item);
568 #endif
569 }
570
odm_free_work_item(PRT_WORK_ITEM p_rt_work_item)571 void odm_free_work_item(
572 PRT_WORK_ITEM p_rt_work_item)
573 {
574 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
575
576 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
577
578 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
579 PlatformFreeWorkItem(p_rt_work_item);
580 #endif
581 }
582
odm_schedule_work_item(PRT_WORK_ITEM p_rt_work_item)583 void odm_schedule_work_item(
584 PRT_WORK_ITEM p_rt_work_item)
585 {
586 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
587
588 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
589
590 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
591 PlatformScheduleWorkItem(p_rt_work_item);
592 #endif
593 }
594
595 boolean
odm_is_work_item_scheduled(PRT_WORK_ITEM p_rt_work_item)596 odm_is_work_item_scheduled(
597 PRT_WORK_ITEM p_rt_work_item)
598 {
599 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
600
601 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
602
603 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
604 return PlatformIsWorkItemScheduled(p_rt_work_item);
605 #endif
606 }
607 #endif
608
609 /*@
610 * ODM Timer relative API.
611 */
612
ODM_delay_ms(u32 ms)613 void ODM_delay_ms(u32 ms)
614 {
615 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
616 delay_ms(ms);
617 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
618 mdelay(ms);
619 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
620 mdelay(ms);
621 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
622 rtw_mdelay_os(ms);
623 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
624 delay_ms(ms);
625 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
626 rtw_mdelay_os(ms);
627 #endif
628 }
629
ODM_delay_us(u32 us)630 void ODM_delay_us(u32 us)
631 {
632 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
633 delay_us(us);
634 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
635 udelay(us);
636 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
637 udelay(us);
638 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
639 rtw_udelay_os(us);
640 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
641 PlatformStallExecution(us);
642 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
643 rtw_udelay_os(us);
644 #endif
645 }
646
ODM_sleep_ms(u32 ms)647 void ODM_sleep_ms(u32 ms)
648 {
649 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
650 delay_ms(ms);
651 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
652 msleep(ms);
653 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
654 msleep(ms);
655 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
656 rtw_msleep_os(ms);
657 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
658 delay_ms(ms);
659 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
660 rtw_msleep_os(ms);
661 #endif
662 }
663
ODM_sleep_us(u32 us)664 void ODM_sleep_us(u32 us)
665 {
666 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
667 delay_us(us);
668 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
669 usleep_range(us, us + 1);
670 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
671 usleep_range(us, us + 1);
672 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
673 rtw_usleep_os(us);
674 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
675 PlatformStallExecution(us);
676 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
677 rtw_usleep_os(us);
678 #endif
679 }
680
odm_set_timer(struct dm_struct * dm,struct phydm_timer_list * timer,u32 ms_delay)681 void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
682 u32 ms_delay)
683 {
684 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
685 mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));
686 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
687 mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));
688 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
689 mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay));
690 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
691 _set_timer(timer, ms_delay); /* @ms */
692 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
693 void *adapter = dm->adapter;
694 PlatformSetTimer(adapter, timer, ms_delay);
695 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
696 rtw_set_timer(timer, ms_delay); /* @ms */
697 #endif
698 }
699
odm_initialize_timer(struct dm_struct * dm,struct phydm_timer_list * timer,void * call_back_func,void * context,const char * sz_id)700 void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
701 void *call_back_func, void *context,
702 const char *sz_id)
703 {
704 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
705 init_timer(timer);
706 timer->function = call_back_func;
707 timer->data = (unsigned long)dm;
708 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
709 timer_setup(timer, call_back_func, 0);
710 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
711 struct _ADAPTER *adapter = dm->adapter;
712
713 _init_timer(timer, adapter->pnetdev, call_back_func, dm);
714 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
715 void *adapter = dm->adapter;
716
717 PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id);
718 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
719 struct _ADAPTER *adapter = dm->adapter;
720
721 rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL);
722 #endif
723 }
724
odm_cancel_timer(struct dm_struct * dm,struct phydm_timer_list * timer)725 void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
726 {
727 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
728 del_timer(timer);
729 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
730 del_timer(timer);
731 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
732 del_timer(&timer->timer);
733 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
734 _cancel_timer_ex(timer);
735 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
736 void *adapter = dm->adapter;
737 PlatformCancelTimer(adapter, timer);
738 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
739 rtw_cancel_timer(timer);
740 #endif
741 }
742
odm_release_timer(struct dm_struct * dm,struct phydm_timer_list * timer)743 void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
744 {
745 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
746
747 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
748
749 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
750
751 void *adapter = dm->adapter;
752
753 /* @<20120301, Kordan> If the initilization fails,
754 * InitializeAdapterXxx will return regardless of InitHalDm.
755 * Hence, uninitialized timers cause BSOD when the driver
756 * releases resources since the init fail.
757 */
758 if (timer == 0) {
759 PHYDM_DBG(dm, ODM_COMP_INIT,
760 "[%s] Timer is NULL! Please check!\n", __func__);
761 return;
762 }
763
764 PlatformReleaseTimer(adapter, timer);
765 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
766 rtw_del_timer(timer);
767 #endif
768 }
769
phydm_trans_h2c_id(struct dm_struct * dm,u8 phydm_h2c_id)770 u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)
771 {
772 u8 platform_h2c_id = phydm_h2c_id;
773
774 switch (phydm_h2c_id) {
775 /* @1 [0] */
776 case ODM_H2C_RSSI_REPORT:
777
778 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
779 #if (RTL8188E_SUPPORT == 1)
780 if (dm->support_ic_type == ODM_RTL8188E)
781 platform_h2c_id = H2C_88E_RSSI_REPORT;
782 else
783 #endif
784 platform_h2c_id = H2C_RSSI_REPORT;
785
786 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
787 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
788 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
789 platform_h2c_id = H2C_RSSI_SETTING;
790
791 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
792 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
793 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
794 platform_h2c_id = H2C_88XX_RSSI_REPORT;
795 else
796 #endif
797 #if (RTL8812A_SUPPORT == 1)
798 if (dm->support_ic_type == ODM_RTL8812)
799 platform_h2c_id = H2C_8812_RSSI_REPORT;
800 else
801 #endif
802 {
803 }
804 #endif
805
806 break;
807
808 /* @1 [3] */
809 case ODM_H2C_WIFI_CALIBRATION:
810 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
811 platform_h2c_id = H2C_WIFI_CALIBRATION;
812
813 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
814 #if (RTL8723B_SUPPORT == 1)
815 platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
816 #endif
817
818 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
819 #endif
820 break;
821
822 /* @1 [4] */
823 case ODM_H2C_IQ_CALIBRATION:
824 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
825 platform_h2c_id = H2C_IQ_CALIBRATION;
826
827 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
828 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
829 platform_h2c_id = H2C_8812_IQ_CALIBRATION;
830 #endif
831 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
832 #endif
833
834 break;
835 /* @1 [5] */
836 case ODM_H2C_RA_PARA_ADJUST:
837
838 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
839 platform_h2c_id = H2C_RA_PARA_ADJUST;
840 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
841 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
842 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
843 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
844 platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
845 #elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
846 platform_h2c_id = H2C_RA_PARA_ADJUST;
847 #elif (RTL8192E_SUPPORT == 1)
848 platform_h2c_id = H2C_8192E_RA_PARA_ADJUST;
849 #elif (RTL8723B_SUPPORT == 1)
850 platform_h2c_id = H2C_8723B_RA_PARA_ADJUST;
851 #endif
852
853 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
854 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
855 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
856 platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
857 else
858 #endif
859 #if (RTL8812A_SUPPORT == 1)
860 if (dm->support_ic_type == ODM_RTL8812)
861 platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
862 else
863 #endif
864 {
865 }
866 #endif
867
868 break;
869
870 /* @1 [6] */
871 case PHYDM_H2C_DYNAMIC_TX_PATH:
872
873 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
874 #if (RTL8814A_SUPPORT == 1)
875 if (dm->support_ic_type == ODM_RTL8814A)
876 platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;
877 #endif
878 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
879 #if (RTL8814A_SUPPORT == 1)
880 if (dm->support_ic_type == ODM_RTL8814A)
881 platform_h2c_id = H2C_DYNAMIC_TX_PATH;
882 #endif
883 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
884 #if (RTL8814A_SUPPORT == 1)
885 if (dm->support_ic_type == ODM_RTL8814A)
886 platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
887 #endif
888
889 #endif
890
891 break;
892
893 /* @[7]*/
894 case PHYDM_H2C_FW_TRACE_EN:
895
896 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
897
898 platform_h2c_id = H2C_FW_TRACE_EN;
899
900 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
901
902 platform_h2c_id = 0x49;
903
904 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
905 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
906 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
907 platform_h2c_id = H2C_88XX_FW_TRACE_EN;
908 else
909 #endif
910 #if (RTL8812A_SUPPORT == 1)
911 if (dm->support_ic_type == ODM_RTL8812)
912 platform_h2c_id = H2C_8812_FW_TRACE_EN;
913 else
914 #endif
915 {
916 }
917
918 #endif
919
920 break;
921
922 case PHYDM_H2C_TXBF:
923 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
924 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812))
925 platform_h2c_id = 0x41; /*@H2C_TxBF*/
926 #endif
927 break;
928
929 case PHYDM_H2C_MU:
930 #if (RTL8822B_SUPPORT == 1)
931 platform_h2c_id = 0x4a; /*@H2C_MU*/
932 #endif
933 break;
934
935 default:
936 platform_h2c_id = phydm_h2c_id;
937 break;
938 }
939
940 return platform_h2c_id;
941 }
942
943 /*@ODM FW relative API.*/
944
odm_fill_h2c_cmd(struct dm_struct * dm,u8 phydm_h2c_id,u32 cmd_len,u8 * cmd_buf)945 void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
946 u8 *cmd_buf)
947 {
948 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
949 struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
950 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
951 struct rtw_dev *rtwdev = dm->adapter;
952 u8 cmd_id, cmd_class;
953 u8 h2c_pkt[8];
954 #else
955 void *adapter = dm->adapter;
956 #endif
957 u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
958
959 PHYDM_DBG(dm, DBG_RA, "[H2C] h2c_id=((0x%x))\n", h2c_id);
960
961 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
962 if (dm->support_ic_type == ODM_RTL8188E) {
963 if (!dm->ra_support88e)
964 FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf);
965 } else if (dm->support_ic_type == ODM_RTL8814A)
966 FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf);
967 else if (dm->support_ic_type == ODM_RTL8822B)
968 FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf);
969 else
970 FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf);
971
972 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
973
974 #ifdef DM_ODM_CE_MAC80211
975 rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf);
976 #elif defined(DM_ODM_CE_MAC80211_V2)
977 cmd_id = phydm_h2c_id & 0x1f;
978 cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7;
979 memcpy(h2c_pkt + 1, cmd_buf, 7);
980 h2c_pkt[0] = phydm_h2c_id;
981 rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class);
982 /* TODO: implement fill h2c command for rtwlan */
983 #else
984 rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
985 #endif
986
987 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
988
989 #if (RTL8812A_SUPPORT == 1)
990 if (dm->support_ic_type == ODM_RTL8812) {
991 fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf);
992 } else
993 #endif
994 {
995 GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf);
996 }
997
998 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
999 rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
1000
1001 #endif
1002 }
1003
phydm_c2H_content_parsing(void * dm_void,u8 c2h_cmd_id,u8 c2h_cmd_len,u8 * tmp_buf)1004 u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
1005 u8 *tmp_buf)
1006 {
1007 struct dm_struct *dm = (struct dm_struct *)dm_void;
1008 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1009 void *adapter = dm->adapter;
1010 #endif
1011 u8 extend_c2h_sub_id = 0;
1012 u8 find_c2h_cmd = true;
1013
1014 if (c2h_cmd_len > 12 || c2h_cmd_len == 0) {
1015 pr_debug("[Warning] Error C2H ID=%d, len=%d\n",
1016 c2h_cmd_id, c2h_cmd_len);
1017
1018 find_c2h_cmd = false;
1019 return find_c2h_cmd;
1020 }
1021
1022 switch (c2h_cmd_id) {
1023 case PHYDM_C2H_DBG:
1024 phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
1025 break;
1026
1027 case PHYDM_C2H_RA_RPT:
1028 phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
1029 break;
1030
1031 case PHYDM_C2H_RA_PARA_RPT:
1032 odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
1033 break;
1034 #ifdef CONFIG_PATH_DIVERSITY
1035 case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
1036 if (dm->support_ic_type & (ODM_RTL8814A))
1037 phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len);
1038 break;
1039 #endif
1040
1041 case PHYDM_C2H_IQK_FINISH:
1042 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1043
1044 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
1045 RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
1046 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1047 dm->rf_calibrate_info.is_iqk_in_progress = false;
1048 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1049 dm->rf_calibrate_info.iqk_progressing_time = 0;
1050 dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
1051 }
1052
1053 #endif
1054 break;
1055
1056 case PHYDM_C2H_CLM_MONITOR:
1057 phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len);
1058 break;
1059
1060 case PHYDM_C2H_DBG_CODE:
1061 phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
1062 break;
1063
1064 case PHYDM_C2H_EXTEND:
1065 extend_c2h_sub_id = tmp_buf[0];
1066 if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
1067 phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
1068
1069 break;
1070
1071 default:
1072 find_c2h_cmd = false;
1073 break;
1074 }
1075
1076 return find_c2h_cmd;
1077 }
1078
odm_get_current_time(struct dm_struct * dm)1079 u64 odm_get_current_time(struct dm_struct *dm)
1080 {
1081 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1082 return (u64)rtw_get_current_time();
1083 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1084 return jiffies;
1085 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1086 return jiffies;
1087 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1088 return rtw_get_current_time();
1089 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1090 return PlatformGetCurrentTime();
1091 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1092 return rtw_get_current_time();
1093 #endif
1094 }
1095
odm_get_progressing_time(struct dm_struct * dm,u64 start_time)1096 u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time)
1097 {
1098 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1099 return rtw_get_passing_time_ms((u32)start_time);
1100 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1101 return jiffies_to_msecs(jiffies - start_time);
1102 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1103 return jiffies_to_msecs(jiffies - start_time);
1104 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1105 return rtw_get_passing_time_ms((systime)start_time);
1106 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1107 return ((PlatformGetCurrentTime() - start_time) >> 10);
1108 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1109 return rtw_get_passing_time_ms(start_time);
1110 #endif
1111 }
1112
1113 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
1114 (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
1115
phydm_set_hw_reg_handler_interface(struct dm_struct * dm,u8 RegName,u8 * val)1116 void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName,
1117 u8 *val)
1118 {
1119 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1120 struct _ADAPTER *adapter = dm->adapter;
1121
1122 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1123 ((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val);
1124 #else
1125 adapter->hal_func.set_hw_reg_handler(adapter, RegName, val);
1126 #endif
1127
1128 #endif
1129 }
1130
phydm_get_hal_def_var_handler_interface(struct dm_struct * dm,enum _HAL_DEF_VARIABLE e_variable,void * value)1131 void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
1132 enum _HAL_DEF_VARIABLE e_variable,
1133 void *value)
1134 {
1135 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1136 struct _ADAPTER *adapter = dm->adapter;
1137
1138 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1139 ((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value);
1140 #else
1141 adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value);
1142 #endif
1143
1144 #endif
1145 }
1146
1147 #endif
1148
odm_set_tx_power_index_by_rate_section(struct dm_struct * dm,enum rf_path path,u8 ch,u8 section)1149 void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
1150 enum rf_path path, u8 ch,
1151 u8 section)
1152 {
1153 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1154 void *adapter = dm->adapter;
1155 PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
1156 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
1157 void *adapter = dm->adapter;
1158
1159 phy_set_tx_power_index_by_rs(adapter, ch, path, section);
1160 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1161 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1162 phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section);
1163 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1164 void *adapter = dm->adapter;
1165
1166 PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
1167 #endif
1168 }
1169
odm_get_tx_power_index(struct dm_struct * dm,enum rf_path path,u8 rate,u8 bw,u8 ch)1170 u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate,
1171 u8 bw, u8 ch)
1172 {
1173 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1174 void *adapter = dm->adapter;
1175
1176 return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch);
1177 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1178 void *adapter = dm->adapter;
1179
1180 return phy_get_tx_power_index(adapter, path, rate, bw, ch);
1181 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1182 void *adapter = dm->adapter;
1183
1184 return phy_get_tx_power_index(adapter, path, rate, bw, ch);
1185 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1186 return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch);
1187 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1188 void *adapter = dm->adapter;
1189
1190 return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch);
1191 #endif
1192 }
1193
odm_efuse_one_byte_read(struct dm_struct * dm,u16 addr,u8 * data,boolean b_pseu_do_test)1194 u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
1195 boolean b_pseu_do_test)
1196 {
1197 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1198 void *adapter = dm->adapter;
1199
1200 return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test);
1201 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1202 void *adapter = dm->adapter;
1203
1204 return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test);
1205 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1206 return -1;
1207 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1208 return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test);
1209 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
1210 return Efuse_OneByteRead(dm, addr, data);
1211 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1212 void *adapter = dm->adapter;
1213
1214 return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test);
1215 #endif
1216 }
1217
odm_efuse_logical_map_read(struct dm_struct * dm,u8 type,u16 offset,u32 * data)1218 void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
1219 u32 *data)
1220 {
1221 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1222 void *adapter = dm->adapter;
1223
1224 EFUSE_ShadowRead(adapter, type, offset, data);
1225 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1226 void *adapter = dm->adapter;
1227
1228 rtl_efuse_logical_map_read(adapter, type, offset, data);
1229 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1230 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1231 efuse_logical_map_read(dm->adapter, type, offset, data);
1232 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1233 void *adapter = dm->adapter;
1234
1235 EFUSE_ShadowRead(adapter, type, offset, data);
1236 #endif
1237 }
1238
1239 enum hal_status
odm_iq_calibrate_by_fw(struct dm_struct * dm,u8 clear,u8 segment)1240 odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)
1241 {
1242 enum hal_status iqk_result = HAL_STATUS_FAILURE;
1243
1244 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1245 struct _ADAPTER *adapter = dm->adapter;
1246
1247 if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0)
1248 iqk_result = HAL_STATUS_SUCCESS;
1249 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1250 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1251 void *adapter = dm->adapter;
1252
1253 iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment);
1254 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1255 #else
1256 iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
1257 #endif
1258 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1259 iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
1260 #endif
1261 return iqk_result;
1262 }
1263
1264 enum hal_status
odm_dpk_by_fw(struct dm_struct * dm)1265 odm_dpk_by_fw(struct dm_struct *dm)
1266 {
1267 enum hal_status dpk_result = HAL_STATUS_FAILURE;
1268 #if 0
1269
1270 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1271 struct _ADAPTER *adapter = dm->adapter;
1272
1273 if (hal_mac_fwdpk_trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
1274 dpk_result = HAL_STATUS_SUCCESS;
1275 #else
1276 dpk_result = rtw_phydm_fw_dpk(dm);
1277 #endif
1278
1279 #endif
1280 return dpk_result;
1281 }
1282
phydm_cmn_sta_info_hook(struct dm_struct * dm,u8 mac_id,struct cmn_sta_info * pcmn_sta_info)1283 void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,
1284 struct cmn_sta_info *pcmn_sta_info)
1285 {
1286 dm->phydm_sta_info[mac_id] = pcmn_sta_info;
1287
1288 if (is_sta_active(pcmn_sta_info))
1289 dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id;
1290 }
1291
phydm_macid2sta_idx_table(struct dm_struct * dm,u8 entry_idx,struct cmn_sta_info * pcmn_sta_info)1292 void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
1293 struct cmn_sta_info *pcmn_sta_info)
1294 {
1295 if (is_sta_active(pcmn_sta_info))
1296 dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx;
1297 }
1298
phydm_add_interrupt_mask_handler(struct dm_struct * dm,u8 interrupt_type)1299 void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type)
1300 {
1301 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1302 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1303
1304 struct rtl8192cd_priv *priv = dm->priv;
1305
1306 #if IS_EXIST_PCI || IS_EXIST_EMBEDDED
1307 if (dm->support_interface == ODM_ITRF_PCIE)
1308 GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv,
1309 interrupt_type)
1310 ;
1311 #endif
1312
1313 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1314 #endif
1315 }
1316
phydm_enable_rx_related_interrupt_handler(struct dm_struct * dm)1317 void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)
1318 {
1319 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1320 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1321
1322 struct rtl8192cd_priv *priv = dm->priv;
1323
1324 #if IS_EXIST_PCI || IS_EXIST_EMBEDDED
1325 if (dm->support_interface == ODM_ITRF_PCIE)
1326 GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv);
1327 #endif
1328
1329 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1330 #endif
1331 }
1332
phydm_iqk_wait(struct dm_struct * dm,u32 timeout)1333 void phydm_iqk_wait(struct dm_struct *dm, u32 timeout)
1334 {
1335 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1336 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1337 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
1338 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
1339 #else
1340 void *adapter = dm->adapter;
1341
1342 rtl8812_iqk_wait(adapter, timeout);
1343 #endif
1344 #endif
1345 }
1346
phydm_get_hwrate_to_mrate(struct dm_struct * dm,u8 rate)1347 u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate)
1348 {
1349 #if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
1350 return HwRateToMRate(rate);
1351 #endif
1352 return 0;
1353 }
1354
phydm_set_crystalcap(struct dm_struct * dm,u8 crystal_cap)1355 void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap)
1356 {
1357 #if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
1358 ROM_odm_SetCrystalCap(dm, crystal_cap);
1359 #endif
1360 }
1361
phydm_run_in_thread_cmd(struct dm_struct * dm,void (* func)(void *),void * context)1362 void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
1363 void *context)
1364 {
1365 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1366 PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
1367 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1368 void *adapter = dm->adapter;
1369
1370 rtw_run_in_thread_cmd(adapter, func, context);
1371 #endif
1372 }
1373
phydm_get_tx_rate(struct dm_struct * dm)1374 u8 phydm_get_tx_rate(struct dm_struct *dm)
1375 {
1376 struct _hal_rf_ *rf = &dm->rf_table;
1377 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1378 struct _ADAPTER *adapter = dm->adapter;
1379 #endif
1380 u8 tx_rate = 0xff;
1381 u8 mpt_rate_index = 0;
1382
1383 if (*dm->mp_mode == 1) {
1384 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1385 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1386 #if (MP_DRIVER == 1)
1387 PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
1388
1389 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
1390 #endif
1391 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1392 #ifdef CONFIG_MP_INCLUDED
1393 if (rf->mp_rate_index)
1394 mpt_rate_index = *rf->mp_rate_index;
1395
1396 tx_rate = mpt_to_mgnt_rate(mpt_rate_index);
1397 #endif
1398 #endif
1399 #endif
1400 } else {
1401 u16 rate = *dm->forced_data_rate;
1402
1403 if (!rate) { /*auto rate*/
1404 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1405 struct _ADAPTER *adapter = dm->adapter;
1406
1407 tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
1408 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
1409 tx_rate = dm->tx_rate;
1410 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1411 if (dm->number_linked_client != 0)
1412 tx_rate = hw_rate_to_m_rate(dm->tx_rate);
1413 else
1414 tx_rate = rf->p_rate_index;
1415 #endif
1416 } else { /*force rate*/
1417 tx_rate = (u8)rate;
1418 }
1419 }
1420
1421 return tx_rate;
1422 }
1423
phydm_get_tx_power_dbm(struct dm_struct * dm,u8 rf_path,u8 rate,u8 bandwidth,u8 channel)1424 u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
1425 u8 rate, u8 bandwidth, u8 channel)
1426 {
1427 u8 tx_power_dbm = 0;
1428 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1429 struct _ADAPTER *adapter = dm->adapter;
1430 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel);
1431 #endif
1432
1433 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1434 tx_power_dbm = phy_get_tx_power_final_absolute_value(dm->adapter, rf_path, rate, bandwidth, channel);
1435 #endif
1436
1437 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1438 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(dm, rf_path, rate, bandwidth, channel);
1439 #endif
1440 return tx_power_dbm;
1441 }
1442
phydm_get_tx_power_mdbm(struct dm_struct * dm,u8 rf_path,u8 rate,u8 bandwidth,u8 channel)1443 s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
1444 u8 rate, u8 bandwidth, u8 channel)
1445 {
1446 s16 tx_power_dbm = 0;
1447 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1448 struct _ADAPTER *adapter = dm->adapter;
1449 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuemdBm(adapter, rf_path, rate, bandwidth, channel);
1450 #endif
1451
1452 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1453 tx_power_dbm = rtw_odm_get_tx_power_mbm(dm, rf_path, rate, bandwidth, channel);
1454 #endif
1455
1456 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1457 tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuembm(dm, rf_path, rate, bandwidth, channel);
1458 #endif
1459 return tx_power_dbm;
1460 }
1461
phydm_rfe_ctrl_gpio(struct dm_struct * dm,u8 gpio_num)1462 u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num)
1463 {
1464 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1465 return rtw_phydm_rfe_ctrl_gpio(dm->adapter, gpio_num);
1466 #endif
1467 return 0;
1468 }
1469
phydm_division64(u64 x,u64 y)1470 u64 phydm_division64(u64 x, u64 y)
1471 {
1472 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1473 do_div(x, y);
1474 return x;
1475 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1476 return x / y;
1477 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1478 return rtw_division64(x, y);
1479 #endif
1480 }
1481