1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMDIG_H__ 27 #define __PHYDMDIG_H__ 28 29 /* 2019.10.25 remove redundant code*/ 30 #define DIG_VERSION "3.7" 31 32 #define DIG_HW 0 33 #define DIG_LIMIT_PERIOD 60 /*60 sec*/ 34 35 /*@--------------------Define ---------------------------------------*/ 36 37 /*@=== [DIG Boundary] ========================================*/ 38 /*@DIG coverage mode*/ 39 #define DIG_MAX_COVERAGR 0x26 40 #define DIG_MIN_COVERAGE 0x1c 41 #define DIG_MAX_OF_MIN_COVERAGE 0x22 42 43 /*@[DIG Balance mode]*/ 44 #if (DIG_HW == 1) 45 #define DIG_MAX_BALANCE_MODE 0x32 46 #else 47 #define DIG_MAX_BALANCE_MODE 0x3e 48 #endif 49 #define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a 50 51 /*@[DIG Performance mode]*/ 52 #define DIG_MAX_PERFORMANCE_MODE 0x5a 53 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/ 54 #define DIG_MIN_PERFORMANCE 0x20 55 #if (RTL8822B_SUPPORT == 1) 56 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE_22B 0x38 57 #endif 58 59 /*@DIG DFS function*/ 60 #define DIG_MAX_DFS 0x28 61 #define DIG_MIN_DFS 0x20 62 63 /*@DIG LPS function*/ 64 #define DIG_MAX_LPS 0x3e 65 #define DIG_MIN_LPS 0x20 66 67 #ifdef PHYDM_TDMA_DIG_SUPPORT 68 #define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/ 69 #define DIG_TIMER_MS 250 70 #define ONE_SEC_MS 1000 71 #endif 72 73 /*@=== [DIG FA Threshold] ======================================*/ 74 75 /*Normal*/ 76 #define DM_DIG_FA_TH0 500 77 #define DM_DIG_FA_TH1 750 78 79 /*@LPS*/ 80 #define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */ 81 #define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */ 82 #define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */ 83 84 #define RSSI_OFFSET_DIG_LPS 5 85 #define DIG_RECORD_NUM 4 86 87 /*@--------------------Enum-----------------------------------*/ 88 enum phydm_dig_mode { 89 PHYDM_DIG_PERFORAMNCE_MODE = 0, 90 PHYDM_DIG_COVERAGE_MODE = 1, 91 }; 92 93 enum phydm_dig_trend { 94 DIG_STABLE = 0, 95 DIG_INCREASING = 1, 96 DIG_DECREASING = 2 97 }; 98 99 enum phydm_fw_dig_mode_e { 100 DIG_PERFORMANCE_MODE = 0, 101 DIG_COVERAGE_MODE = 1, 102 DIG_LPS_MODE = 2 103 }; 104 105 #ifdef PHYDM_TDMA_DIG_SUPPORT 106 enum upd_type { 107 ENABLE_TDMA, 108 MODE_DECISION 109 }; 110 111 enum tdma_opmode { 112 MODE_PERFORMANCE = 1, 113 MODE_COVERAGE = 2 114 }; 115 116 #ifdef IS_USE_NEW_TDMA 117 enum tdma_dig_timer { 118 INIT_TDMA_DIG_TIMMER, 119 CANCEL_TDMA_DIG_TIMMER, 120 RELEASE_TDMA_DIG_TIMMER 121 }; 122 123 enum tdma_dig_state { 124 TDMA_DIG_LOW_STATE = 0, 125 TDMA_DIG_HIGH_STATE = 1, 126 NORMAL_DIG = 2 127 }; 128 #endif 129 #endif 130 131 /*@--------------------Define Struct-----------------------------------*/ 132 #ifdef CFG_DIG_DAMPING_CHK 133 struct phydm_dig_recorder_strcut { 134 u8 igi_bitmap; /*@Don't add any new parameter before this*/ 135 u8 igi_history[DIG_RECORD_NUM]; 136 u32 fa_history[DIG_RECORD_NUM]; 137 u8 damping_limit_en; 138 u8 damping_limit_val; /*@Limit IGI_dyn_min*/ 139 u32 limit_time; 140 u8 limit_rssi; 141 }; 142 #endif 143 144 struct phydm_mcc_dig { 145 u8 mcc_rssi_A; 146 u8 mcc_rssi_B; 147 }; 148 149 struct phydm_dig_struct { 150 #ifdef CFG_DIG_DAMPING_CHK 151 struct phydm_dig_recorder_strcut dig_recorder_t; 152 u8 dig_dl_en; /*@damping limit function enable*/ 153 #endif 154 boolean fw_dig_enable; 155 boolean is_dbg_fa_th; 156 u8 cur_ig_value; 157 boolean igi_dyn_up_hit; 158 u8 igi_trend; 159 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 160 u8 igi_backup; 161 u8 rx_gain_range_max; /*@dig_dynamic_max*/ 162 u8 rx_gain_range_min; /*@dig_dynamic_min*/ 163 u8 dm_dig_max; /*@Absolutly upper bound*/ 164 u8 dm_dig_min; /*@Absolutly lower bound*/ 165 u8 dig_max_of_min; /*@Absolutly max of min*/ 166 u32 ant_div_rssi_max; 167 u8 *is_p2p_in_process; 168 u16 fa_th[3]; 169 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ 170 RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\ 171 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\ 172 RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 173 u8 rf_gain_idx; 174 u8 agc_table_idx; 175 u8 big_jump_lmt[16]; 176 u8 enable_adjust_big_jump:1; 177 u8 big_jump_step1:3; 178 u8 big_jump_step2:2; 179 u8 big_jump_step3:2; 180 #endif 181 u8 upcheck_init_val; 182 u8 lv0_ratio_reciprocal; 183 u8 lv1_ratio_reciprocal; 184 #ifdef PHYDM_TDMA_DIG_SUPPORT 185 u8 cur_ig_value_tdma; 186 u8 low_ig_value; 187 u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/ 188 u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/ 189 u8 pre_tdma_dig_cnt; 190 u8 sec_factor; 191 u32 cur_timestamp; 192 u32 pre_timestamp; 193 u32 fa_start_timestamp; 194 u32 fa_end_timestamp; 195 u32 fa_acc_1sec_timestamp; 196 #ifdef IS_USE_NEW_TDMA 197 u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/ 198 /*@dynamic upper bound for L/H state*/ 199 u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES]; 200 /*@dynamic lower bound for L/H state*/ 201 u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES]; 202 /*To distinguish current state(L-sate or H-state)*/ 203 #endif 204 u8 tdma_force_l_igi; 205 u8 tdma_force_h_igi; 206 #endif 207 }; 208 209 struct phydm_fa_struct { 210 u32 cnt_parity_fail; 211 u32 cnt_rate_illegal; 212 u32 cnt_crc8_fail; 213 u32 cnt_crc8_fail_vhta; 214 u32 cnt_crc8_fail_vhtb; 215 u32 cnt_mcs_fail; 216 u32 cnt_mcs_fail_vht; 217 u32 cnt_ofdm_fail; 218 u32 cnt_ofdm_fail_pre; /* @For RTL8881A */ 219 u32 cnt_cck_fail; 220 u32 cnt_all; 221 u32 cnt_all_accumulated; 222 u32 cnt_all_pre; 223 u32 cnt_fast_fsync; 224 u32 cnt_sb_search_fail; 225 u32 cnt_ofdm_cca; 226 u32 cnt_cck_cca; 227 u32 cnt_cca_all; 228 u32 cnt_bw_usc; 229 u32 cnt_bw_lsc; 230 u32 cnt_cck_crc32_error; 231 u32 cnt_cck_crc32_ok; 232 u32 cnt_ofdm_crc32_error; 233 u32 cnt_ofdm_crc32_ok; 234 u32 cnt_ht_crc32_error; 235 u32 cnt_ht_crc32_ok; 236 u32 cnt_ht_crc32_error_agg; 237 u32 cnt_ht_crc32_ok_agg; 238 u32 cnt_vht_crc32_error; 239 u32 cnt_vht_crc32_ok; 240 u32 cnt_crc32_error_all; 241 u32 cnt_crc32_ok_all; 242 u32 time_fa_all; 243 boolean cck_block_enable; 244 boolean ofdm_block_enable; 245 u32 dbg_port0; 246 boolean edcca_flag; 247 u8 ofdm2_rate_idx; 248 u32 cnt_ofdm2_crc32_error; 249 u32 cnt_ofdm2_crc32_ok; 250 u8 ofdm2_pcr; 251 u8 ht2_rate_idx; 252 u32 cnt_ht2_crc32_error; 253 u32 cnt_ht2_crc32_ok; 254 u8 ht2_pcr; 255 u8 vht2_rate_idx; 256 u32 cnt_vht2_crc32_error; 257 u32 cnt_vht2_crc32_ok; 258 u8 vht2_pcr; 259 260 }; 261 262 #ifdef PHYDM_TDMA_DIG_SUPPORT 263 struct phydm_fa_acc_struct { 264 u32 cnt_parity_fail; 265 u32 cnt_rate_illegal; 266 u32 cnt_crc8_fail; 267 u32 cnt_mcs_fail; 268 u32 cnt_ofdm_fail; 269 u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/ 270 u32 cnt_cck_fail; 271 u32 cnt_all; 272 u32 cnt_all_pre; 273 u32 cnt_fast_fsync; 274 u32 cnt_sb_search_fail; 275 u32 cnt_ofdm_cca; 276 u32 cnt_cck_cca; 277 u32 cnt_cca_all; 278 u32 cnt_cck_crc32_error; 279 u32 cnt_cck_crc32_ok; 280 u32 cnt_ofdm_crc32_error; 281 u32 cnt_ofdm_crc32_ok; 282 u32 cnt_ht_crc32_error; 283 u32 cnt_ht_crc32_ok; 284 u32 cnt_vht_crc32_error; 285 u32 cnt_vht_crc32_ok; 286 u32 cnt_crc32_error_all; 287 u32 cnt_crc32_ok_all; 288 u32 cnt_all_1sec; 289 u32 cnt_cca_all_1sec; 290 u32 cnt_cck_fail_1sec; 291 }; 292 293 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 294 295 /*@--------------------Function declaration-----------------------------*/ 296 void phydm_write_dig_reg(void *dm_void, u8 igi); 297 298 void odm_write_dig(void *dm_void, u8 current_igi); 299 300 u8 phydm_get_igi(void *dm_void, enum bb_path path); 301 302 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len); 303 304 void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type, 305 enum phydm_pause_level pause_level, u8 igi_value); 306 307 #ifdef PHYDM_HW_IGI 308 void phydm_hwigi(void *dm_void); 309 310 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used, 311 char *output, u32 *_out_len); 312 #endif 313 314 void phydm_dig_init(void *dm_void); 315 316 void phydm_dig(void *dm_void); 317 318 void phydm_dig_lps_32k(void *dm_void); 319 320 void phydm_dig_by_rssi_lps(void *dm_void); 321 322 void phydm_false_alarm_counter_statistics(void *dm_void); 323 324 u32 phydm_get_edcca_report(void * dm_void); 325 326 #ifdef PHYDM_TDMA_DIG_SUPPORT 327 void phydm_set_tdma_dig_timer(void *dm_void); 328 329 void phydm_tdma_dig_timer_check(void *dm_void); 330 331 void phydm_tdma_dig(void *dm_void); 332 333 void phydm_tdma_false_alarm_counter_check(void *dm_void); 334 335 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void); 336 337 void phydm_false_alarm_counter_reset(void *dm_void); 338 339 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en); 340 341 void phydm_false_alarm_counter_acc_reset(void *dm_void); 342 343 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input); 344 345 #ifdef IS_USE_NEW_TDMA 346 void phydm_tdma_dig_timers(void *dm_void, u8 state); 347 348 void phydm_tdma_dig_cbk(void *dm_void); 349 350 void phydm_tdma_dig_workitem_callback(void *dm_void); 351 352 void phydm_tdma_fa_cnt_chk(void *dm_void); 353 354 void phydm_tdma_low_dig(void *dm_void); 355 356 void phydm_tdma_high_dig(void *dm_void); 357 358 void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, 359 u8 cur_tdma_dig_state); 360 #endif /*@#ifdef IS_USE_NEW_TDMA*/ 361 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 362 363 void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel); 364 365 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, 366 u32 *_out_len); 367 368 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable, 369 u8 *para4, u8 *para8); 370 371 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used, 372 char *output, u32 *_out_len); 373 374 #ifdef CONFIG_MCC_DM 375 void phydm_mcc_igi_cal(void *dm_void); 376 #endif 377 378 #endif 379