1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef CFG_DIG_DAMPING_CHK
phydm_dig_recorder_reset(void * dm_void)34 void phydm_dig_recorder_reset(void *dm_void)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
38 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
39
40 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
41
42 odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
43 sizeof(struct phydm_dig_recorder_strcut));
44 }
45
phydm_dig_recorder(void * dm_void,u8 igi_curr,u32 fa_cnt)46 void phydm_dig_recorder(void *dm_void, u8 igi_curr,
47 u32 fa_cnt)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
51 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
52 u8 igi_pre = dig_rc->igi_history[0];
53 u8 igi_up = 0;
54
55 if (!dm->is_linked)
56 return;
57
58 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
59
60 if (dm->first_connect) {
61 phydm_dig_recorder_reset(dm);
62 dig_rc->igi_history[0] = igi_curr;
63 dig_rc->fa_history[0] = fa_cnt;
64 return;
65 }
66
67 if (igi_curr % 2)
68 igi_curr--;
69
70 igi_pre = dig_rc->igi_history[0];
71 igi_up = (igi_curr > igi_pre) ? 1 : 0;
72 dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
73
74 dig_rc->igi_history[3] = dig_rc->igi_history[2];
75 dig_rc->igi_history[2] = dig_rc->igi_history[1];
76 dig_rc->igi_history[1] = dig_rc->igi_history[0];
77 dig_rc->igi_history[0] = igi_curr;
78
79 dig_rc->fa_history[3] = dig_rc->fa_history[2];
80 dig_rc->fa_history[2] = dig_rc->fa_history[1];
81 dig_rc->fa_history[1] = dig_rc->fa_history[0];
82 dig_rc->fa_history[0] = fa_cnt;
83
84 PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
85 dig_rc->igi_history[3], dig_rc->igi_history[2],
86 dig_rc->igi_history[1], dig_rc->igi_history[0]);
87 PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
88 dig_rc->fa_history[3], dig_rc->fa_history[2],
89 dig_rc->fa_history[1], dig_rc->fa_history[0]);
90 PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
91 (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
92 (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
93 (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
94 (u8)(dig_rc->igi_bitmap & BIT(0)),
95 dig_rc->igi_bitmap);
96 }
97
phydm_dig_damping_chk(void * dm_void)98 void phydm_dig_damping_chk(void *dm_void)
99 {
100 struct dm_struct *dm = (struct dm_struct *)dm_void;
101 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
102 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
103 u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
104 u8 diff1 = 0, diff2 = 0;
105 u32 fa_low_th = dig_t->fa_th[0];
106 u32 fa_high_th = dig_t->fa_th[1];
107 u32 fa_high_th2 = dig_t->fa_th[2];
108 u8 fa_pattern_match = 0;
109 u32 time_tmp = 0;
110
111 if (!dm->is_linked)
112 return;
113
114 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
115
116 /*@== Release Damping ================================================*/
117 if (dig_rc->damping_limit_en) {
118 PHYDM_DBG(dm, DBG_DIG,
119 "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
120 dig_rc->limit_time, dm->phydm_sys_up_time);
121
122 time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
123
124 if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
125 time_tmp < dm->phydm_sys_up_time) {
126 dig_rc->damping_limit_en = 0;
127 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
128 dm->rssi_min, dig_rc->limit_rssi);
129 }
130 return;
131 }
132
133 /*@== Damping Pattern Check===========================================*/
134 PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
135
136 switch (igi_bitmap_4bit) {
137 case 0x5:
138 /*@ 4b'0101
139 * IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
140 * FA: [3] >high1 ->[2] <low ->[1] >high1 ->[0] <low ->[new] <low
141 *
142 * IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
143 * FA: [3] >high2 ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
144 */
145 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
146 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
147
148 if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
149 diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
150
151 if (dig_rc->fa_history[0] < fa_low_th &&
152 dig_rc->fa_history[1] > fa_high_th &&
153 dig_rc->fa_history[2] < fa_low_th &&
154 dig_rc->fa_history[3] > fa_high_th) {
155 /*@Check each fa element*/
156 fa_pattern_match = 1;
157 }
158 break;
159 case 0x9:
160 /*@ 4b'1001
161 * IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
162 * FA: [3] <low ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
163 */
164 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
165 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
166
167 if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
168 diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
169
170 if (dig_rc->fa_history[0] < fa_low_th &&
171 dig_rc->fa_history[1] > fa_high_th2 &&
172 dig_rc->fa_history[2] < fa_low_th &&
173 dig_rc->fa_history[3] < fa_low_th) {
174 /*@Check each fa element*/
175 fa_pattern_match = 1;
176 }
177 break;
178 default:
179 break;
180 }
181
182 if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
183 dig_rc->damping_limit_en = 1;
184 dig_rc->damping_limit_val = dig_rc->igi_history[0];
185 dig_rc->limit_time = dm->phydm_sys_up_time;
186 dig_rc->limit_rssi = dm->rssi_min;
187
188 PHYDM_DBG(dm, DBG_DIG,
189 "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
190 dig_rc->damping_limit_val,
191 dig_rc->limit_time, dig_rc->limit_rssi);
192 }
193
194 PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
195 }
196 #endif
197
phydm_fa_threshold_check(void * dm_void,boolean is_dfs_band)198 void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
199 {
200 struct dm_struct *dm = (struct dm_struct *)dm_void;
201 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
202
203 if (dig_t->is_dbg_fa_th) {
204 PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
205 } else if (dm->is_linked) {
206 if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
207 dig_t->fa_th[0] = 500;
208 dig_t->fa_th[1] = 750;
209 dig_t->fa_th[2] = 1000;
210 } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
211 (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
212 dig_t->fa_th[0] = 125;
213 dig_t->fa_th[1] = 250;
214 dig_t->fa_th[2] = 500;
215 } else {
216 dig_t->fa_th[0] = 250;
217 dig_t->fa_th[1] = 500;
218 dig_t->fa_th[2] = 750;
219 }
220 } else {
221 if (is_dfs_band) { /* @For DFS band and no link */
222
223 dig_t->fa_th[0] = 250;
224 dig_t->fa_th[1] = 1000;
225 dig_t->fa_th[2] = 2000;
226 } else {
227 dig_t->fa_th[0] = 2000;
228 dig_t->fa_th[1] = 4000;
229 dig_t->fa_th[2] = 5000;
230 }
231 }
232
233 PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
234 dig_t->fa_th[1], dig_t->fa_th[2]);
235 }
236
phydm_set_big_jump_step(void * dm_void,u8 curr_igi)237 void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
238 {
239 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
240 struct dm_struct *dm = (struct dm_struct *)dm_void;
241 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
242 u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
243 u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
244 u8 i;
245
246 if (dig_t->enable_adjust_big_jump == 0)
247 return;
248
249 for (i = 0; i <= dig_t->big_jump_step1; i++) {
250 if ((curr_igi + step1[i]) > big_jump_lmt) {
251 if (i != 0)
252 i = i - 1;
253 break;
254 } else if (i == dig_t->big_jump_step1) {
255 break;
256 }
257 }
258 if (dm->support_ic_type & ODM_RTL8822B)
259 odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
260 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
261 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
262
263 PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
264 dig_t->big_jump_step1, big_jump_lmt);
265 #endif
266 }
267
268 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_write_dig_reg_jgr3(void * dm_void,u8 igi)269 void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
270 {
271 struct dm_struct *dm = (struct dm_struct *)dm_void;
272 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
273
274 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
275
276 /* Set IGI value */
277 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
278 return;
279
280 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
281
282 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
283 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
284 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
285 #endif
286
287 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
288 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
289 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
290 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
291 }
292 #endif
293 }
294
phydm_get_igi_reg_val_jgr3(void * dm_void,enum bb_path path)295 u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
296 {
297 struct dm_struct *dm = (struct dm_struct *)dm_void;
298 u32 val = 0;
299
300 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
301
302 /* Set IGI value */
303 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
304 return (u8)val;
305
306 if (path == BB_PATH_A)
307 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
308 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
309 else if (path == BB_PATH_B)
310 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
311 #endif
312
313 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
314 else if (path == BB_PATH_C)
315 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
316 #endif
317
318 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
319 else if (path == BB_PATH_D)
320 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
321 #endif
322 return (u8)val;
323 }
324
phydm_fa_cnt_statistics_jgr3(void * dm_void)325 void phydm_fa_cnt_statistics_jgr3(void *dm_void)
326 {
327 struct dm_struct *dm = (struct dm_struct *)dm_void;
328 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
329 u32 ret_value = 0;
330 u32 cck_enable = 0;
331
332 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
333 return;
334
335 ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
336 fa_t->cnt_fast_fsync = ret_value & 0xffff;
337 fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
338
339 ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
340 fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
341
342 ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
343 fa_t->cnt_rate_illegal = ret_value & 0xffff;
344 fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
345
346 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
347 fa_t->cnt_mcs_fail = ret_value & 0xffff;
348
349 /* read CCK CRC32 counter */
350 ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
351 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
352 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
353
354 /* read OFDM CRC32 counter */
355 ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
356 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
357 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
358
359 /* read OFDM2 CRC32 counter */
360 ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD);
361 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
362 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
363
364 /* read HT CRC32 counter */
365 ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
366 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
367 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
368
369 /* read HT2 CRC32 counter */
370 ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD);
371 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
372 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
373
374 /*for VHT part */
375 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
376 ODM_RTL8814B)) {
377 /*read VHT CRC32 counter */
378 ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
379 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
380 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
381
382 /*read VHT2 CRC32 counter */
383 ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD);
384 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
385 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
386
387 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
388 fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
389
390 ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
391 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
392 fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
393 } else {
394 fa_t->cnt_vht_crc32_error = 0;
395 fa_t->cnt_vht_crc32_ok = 0;
396 fa_t->cnt_vht2_crc32_error = 0;
397 fa_t->cnt_vht2_crc32_ok = 0;
398 fa_t->cnt_mcs_fail_vht = 0;
399 fa_t->cnt_crc8_fail_vhta = 0;
400 fa_t->cnt_crc8_fail_vhtb = 0;
401 }
402
403 /* @calculate OFDM FA counter instead of reading brk_cnt*/
404 fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
405 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
406 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
407 fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
408
409 /* Read CCK FA counter */
410 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
411
412 /* read CCK/OFDM CCA counter */
413 ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
414 fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
415 fa_t->cnt_cck_cca = ret_value & 0xffff;
416
417 /* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
418 cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
419 if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
420 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
421 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
422 } else {
423 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
424 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
425 }
426 }
427
428 #endif
429
phydm_write_dig_reg_c50(void * dm_void,u8 igi)430 void phydm_write_dig_reg_c50(void *dm_void, u8 igi)
431 {
432 struct dm_struct *dm = (struct dm_struct *)dm_void;
433
434 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
435
436 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
437
438 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
439 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
440 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
441 #endif
442
443 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
444 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
445 odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
446 odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
447 }
448 #endif
449 }
450
phydm_write_dig_reg(void * dm_void,u8 igi)451 void phydm_write_dig_reg(void *dm_void, u8 igi)
452 {
453 struct dm_struct *dm = (struct dm_struct *)dm_void;
454 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
455 u8 rf_gain = 0;
456
457 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
458
459 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
460 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
461 phydm_write_dig_reg_jgr3(dm, igi);
462 else
463 #endif
464 phydm_write_dig_reg_c50(dm, igi);
465
466 #if (RTL8721D_SUPPORT)
467 if (dm->invalid_mode) {
468 if (igi <= 0x10)
469 rf_gain = 0xfa;
470 else if (igi <= 0x40)
471 rf_gain = 0xe3 + 0x20 - (igi >> 1);
472 else if (igi <= 0x50)
473 rf_gain = 0xcb - (igi >> 1);
474 else if (igi <= 0x5e)
475 rf_gain = 0x92 - (igi >> 1);
476 else if (igi <= 0x64)
477 rf_gain = 0x74 - (igi >> 1);
478 else
479 rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
480 odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
481 }
482 #endif
483
484 if (igi == dig_t->cur_ig_value)
485 dig_t->igi_trend = DIG_STABLE;
486 else if (igi > dig_t->cur_ig_value)
487 dig_t->igi_trend = DIG_INCREASING;
488 else
489 dig_t->igi_trend = DIG_DECREASING;
490
491 PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n",
492 dig_t->cur_ig_value, igi);
493
494 dig_t->cur_ig_value = igi;
495 }
496
odm_write_dig(void * dm_void,u8 new_igi)497 void odm_write_dig(void *dm_void, u8 new_igi)
498 {
499 struct dm_struct *dm = (struct dm_struct *)dm_void;
500 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
501 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
502
503 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
504
505 /* @1 Check IGI by upper bound */
506 if (adaptivity->igi_lmt_en &&
507 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
508 new_igi = adaptivity->adapt_igi_up;
509
510 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
511 new_igi);
512 }
513
514 #if (RTL8192F_SUPPORT)
515 if ((dm->support_ic_type & ODM_RTL8192F) &&
516 dm->cut_version == ODM_CUT_A &&
517 new_igi > 0x38) {
518 new_igi = 0x38;
519 PHYDM_DBG(dm, DBG_DIG,
520 "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
521 }
522 #endif
523
524 if (dig_t->cur_ig_value != new_igi) {
525 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
526 /* @Modify big jump step for 8822B and 8197F */
527 if (dm->support_ic_type &
528 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
529 phydm_set_big_jump_step(dm, new_igi);
530 #endif
531
532 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
533 /* Set IGI value of CCK for new CCK AGC */
534 if (dm->cck_new_agc &&
535 (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
536 odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
537 #endif
538
539 /*@Add by YuChen for USB IO too slow issue*/
540 if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
541 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
542 new_igi < dig_t->cur_ig_value) {
543 dig_t->cur_ig_value = new_igi;
544 phydm_adaptivity(dm);
545 }
546 } else {
547 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
548 new_igi > dig_t->cur_ig_value) {
549 dig_t->cur_ig_value = new_igi;
550 phydm_adaptivity(dm);
551 }
552 }
553 phydm_write_dig_reg(dm, new_igi);
554 } else {
555 dig_t->igi_trend = DIG_STABLE;
556 }
557
558 PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n",
559 ((dig_t->igi_trend == DIG_STABLE) ? "=" :
560 ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")),
561 new_igi);
562 }
563
phydm_get_igi_reg_val(void * dm_void,enum bb_path path)564 u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
565 {
566 struct dm_struct *dm = (struct dm_struct *)dm_void;
567 u32 val = 0;
568 u32 bit_map = ODM_BIT(IGI, dm);
569
570 switch (path) {
571 case BB_PATH_A:
572 val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
573 break;
574 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
575 case BB_PATH_B:
576 val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
577 break;
578 #endif
579
580 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
581 case BB_PATH_C:
582 val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
583 break;
584 #endif
585
586 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
587 case BB_PATH_D:
588 val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
589 break;
590 #endif
591
592 default:
593 break;
594 }
595
596 return (u8)val;
597 }
598
phydm_get_igi(void * dm_void,enum bb_path path)599 u8 phydm_get_igi(void *dm_void, enum bb_path path)
600 {
601 struct dm_struct *dm = (struct dm_struct *)dm_void;
602 u8 val = 0;
603
604 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
605 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
606 val = phydm_get_igi_reg_val_jgr3(dm, path);
607 else
608 #endif
609 val = phydm_get_igi_reg_val(dm, path);
610
611 return val;
612 }
613
phydm_set_dig_val(void * dm_void,u32 * val_buf,u8 val_len)614 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
615 {
616 struct dm_struct *dm = (struct dm_struct *)dm_void;
617
618 if (val_len != 1) {
619 PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
620 return;
621 }
622
623 odm_write_dig(dm, (u8)(*val_buf));
624 }
625
odm_pause_dig(void * dm_void,enum phydm_pause_type type,enum phydm_pause_level lv,u8 igi_input)626 void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
627 enum phydm_pause_level lv, u8 igi_input)
628 {
629 struct dm_struct *dm = (struct dm_struct *)dm_void;
630 u8 rpt = false;
631 u32 igi = (u32)igi_input;
632
633 PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
634 lv, igi);
635
636 switch (type) {
637 case PHYDM_PAUSE:
638 case PHYDM_PAUSE_NO_SET: {
639 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
640 break;
641 }
642
643 case PHYDM_RESUME: {
644 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
645 break;
646 }
647 default:
648 PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
649 break;
650 }
651
652 PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
653 }
654
655 boolean
phydm_dig_abort(void * dm_void)656 phydm_dig_abort(void *dm_void)
657 {
658 struct dm_struct *dm = (struct dm_struct *)dm_void;
659 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
660 void *adapter = dm->adapter;
661 #endif
662
663 /* support_ability */
664 if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
665 (!(dm->support_ability & ODM_BB_DIG))) {
666 PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
667 return true;
668 }
669
670 if (dm->pause_ability & ODM_BB_DIG) {
671 PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
672 dm->pause_lv_table.lv_dig);
673 return true;
674 }
675
676 if (*dm->is_scan_in_process) {
677 PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
678 return true;
679 }
680
681 if (dm->dm_dig_table.fw_dig_enable) {
682 PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n");
683 return true;
684 }
685
686 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
687 #if OS_WIN_FROM_WIN7(OS_VERSION)
688 if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
689 PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
690 return true;
691 }
692 #endif
693 #endif
694
695 return false;
696 }
697
698 #ifdef PHYDM_HW_IGI
699 #ifdef BB_RAM_SUPPORT
phydm_rd_hwigi_pre_setting(void * dm_void,u32 * _used,char * output,u32 * _out_len)700 void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output,
701 u32 *_out_len)
702 {
703 struct dm_struct *dm = (struct dm_struct *)dm_void;
704 u32 used = *_used;
705 u32 out_len = *_out_len;
706 u8 igi_ofst = 0x0;
707 u32 t1, t2, t3 = 0x0;
708
709 igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0);
710 t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400;
711 t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400;
712 t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400;
713
714 PDM_SNPF(out_len, used, output + used, out_len - used,
715 "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n",
716 igi_ofst, t1, t2, t3);
717 }
718
phydm_set_hwigi_pre_setting(void * dm_void,u8 igi_ofst,u8 t1,u8 t2,u8 t3)719 void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2,
720 u8 t3)
721 {
722 struct dm_struct *dm = (struct dm_struct *)dm_void;
723 u32 reg_0x1e80 = 0;
724
725 reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24);
726 odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80);
727 }
728
phydm_rd_hwigi_table(void * dm_void,u8 macid,u32 * _used,char * output,u32 * _out_len)729 void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output,
730 u32 *_out_len)
731 {
732 struct dm_struct *dm = (struct dm_struct *)dm_void;
733 u32 used = *_used;
734 u32 out_len = *_out_len;
735 boolean hwigi_en = false;
736 u8 hwigi = 0x0;
737 u8 hwigi_rx_offset = 0x0;
738 u32 reg_0x1e84 = 0x0;
739
740 reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/
741 reg_0x1e84 |= BIT(31); /*read_en*/
742 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
743
744 hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15));
745 hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00);
746 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
747
748 PDM_SNPF(out_len, used, output + used, out_len - used,
749 "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en,
750 hwigi);
751
752 *_used = used;
753 *_out_len = out_len;
754 }
755
phydm_wt_hwigi_table(void * dm_void,u8 macid,boolean hwigi_en,u8 hwigi)756 void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi)
757 {
758 struct dm_struct *dm = (struct dm_struct *)dm_void;
759 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
760 u32 reg_0x1e84 = 0;
761
762 if (macid > 63)
763 macid = 63;
764
765 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
766 dm_ram_per_sta->hw_igi_en = hwigi_en;
767 dm_ram_per_sta->hw_igi = hwigi;
768
769 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
770 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
771 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
772 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
773
774 reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f);
775 reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/
776 reg_0x1e84 |= BIT(30); /*write_en*/
777 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
778 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/
779 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/
780 }
781
phydm_rst_hwigi(void * dm_void)782 void phydm_rst_hwigi(void *dm_void)
783 {
784 struct dm_struct *dm = (struct dm_struct *)dm_void;
785 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
786 u32 reg_0x1e84 = 0;
787 u8 i = 0;
788
789 PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n");
790
791 for (i = 0; i < 64; i++) {
792 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
793 dm_ram_per_sta->hw_igi_en = false;
794 dm_ram_per_sta->hw_igi = 0x0;
795
796 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
797 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
798 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
799 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
800
801 reg_0x1e84 |= (i & 0x3f) << 24;
802 reg_0x1e84 |= BIT(30);
803 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
804 }
805
806 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
807 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
808 }
809
phydm_hwigi_init(void * dm_void)810 void phydm_hwigi_init(void *dm_void)
811 {
812 struct dm_struct *dm = (struct dm_struct *)dm_void;
813 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
814 u8 igi_ofst = 0x0;
815 u8 t1 = 0x0;
816 u8 t2 = 0x0;
817 u8 t3 = 0x0;
818
819 t1 = 0x55; /*34 us*/
820 t3 = 0x55; /*34 us*/
821
822 bb_ctrl->hwigi_watchdog_en = false;
823 phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3);
824 }
825
phydm_hwigi(void * dm_void)826 void phydm_hwigi(void *dm_void)
827 {
828 struct dm_struct *dm = (struct dm_struct *)dm_void;
829 struct cmn_sta_info *sta = NULL;
830 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
831 struct rssi_info *rssi = NULL;
832 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
833 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
834 u8 sta_cnt = 0;
835 u8 i = 0;
836 u8 hwigi = 0x0;
837 u8 macid = 0;
838
839 if (!(bb_ctrl->hwigi_watchdog_en)) {
840 return;
841 } else if (dm->first_disconnect) {
842 phydm_rst_hwigi(dm);
843 return;
844 }
845
846 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
847 sta = dm->phydm_sta_info[i];
848 if (is_sta_active(sta)) {
849 sta_cnt++;
850
851 if (sta->mac_id > 63)
852 macid = 63;
853 else
854 macid = sta->mac_id;
855
856 dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid];
857 rssi = &sta->rssi_stat;
858 PHYDM_DBG(dm, DBG_DIG,
859 "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n",
860 i, sta->mac_id, rssi->rssi,
861 dm_ram_per_sta->hw_igi_en,
862 dm_ram_per_sta->hw_igi);
863
864 hwigi = MAX_2((u8)(rssi->rssi + 10),
865 dig_t->cur_ig_value);
866
867 if (rssi->rssi + 10 > DIG_MAX_PERFORMANCE_MODE)
868 hwigi = DIG_MAX_PERFORMANCE_MODE;
869 else if (rssi->rssi + 10 < DIG_MIN_PERFORMANCE)
870 hwigi = DIG_MIN_PERFORMANCE;
871
872 if (dm_ram_per_sta->hw_igi == hwigi) {
873 PHYDM_DBG(dm, DBG_DIG,
874 "hwigi not change!\n");
875 return;
876 }
877
878 PHYDM_DBG(dm, DBG_DIG,
879 "hwigi update: ((0x%x)) -> ((0x%x))\n",
880 dm_ram_per_sta->hw_igi, hwigi);
881
882 phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi);
883
884 if (sta_cnt == dm->number_linked_client)
885 break;
886 }
887 }
888 }
889
phydm_hwigi_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)890 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
891 char *output, u32 *_out_len)
892 {
893 struct dm_struct *dm = (struct dm_struct *)dm_void;
894 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
895 char help[] = "-h";
896 u32 used = *_used;
897 u32 out_len = *_out_len;
898 u32 var1[7] = {0};
899 u8 i = 0;
900
901 if ((strcmp(input[1], help) == 0)) {
902 PDM_SNPF(out_len, used, output + used, out_len - used,
903 "Disable/Enable watchdog : {0/1}\n");
904 PDM_SNPF(out_len, used, output + used, out_len - used,
905 "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n");
906 PDM_SNPF(out_len, used, output + used, out_len - used,
907 "Set hwigi table: {3} {en} {value} {macid}\n");
908 PDM_SNPF(out_len, used, output + used, out_len - used,
909 "Read hwigi : {4} {macid(0~63), 255:all}\n");
910 PDM_SNPF(out_len, used, output + used, out_len - used,
911 "Reset all hwigi : {5}\n");
912 } else {
913 for (i = 0; i < 7; i++) {
914 if (input[i + 1])
915 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
916 &var1[i]);
917 }
918 switch (var1[0]) {
919 case 0:
920 case 1:
921 bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false;
922 break;
923 case 2:
924 phydm_set_hwigi_pre_setting(dm, (u8)var1[1],
925 (u8)var1[2], (u8)var1[3],
926 (u8)var1[4]);
927 break;
928 case 3:
929 phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1],
930 (boolean)var1[2]);
931 break;
932 case 4:
933 phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len);
934 if ((u8)var1[1] == 0xff)
935 for (i = 0; i < 64; i++)
936 phydm_rd_hwigi_table(dm, i, &used,
937 output, &out_len);
938 else
939 phydm_rd_hwigi_table(dm, (u8)var1[1], &used,
940 output, &out_len);
941 break;
942 case 5:
943 phydm_rst_hwigi(dm);
944 break;
945 }
946 }
947 *_used = used;
948 *_out_len = out_len;
949 }
950 #endif
951 #endif
952
phydm_dig_init(void * dm_void)953 void phydm_dig_init(void *dm_void)
954 {
955 struct dm_struct *dm = (struct dm_struct *)dm_void;
956 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
957 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
958 struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
959 #endif
960 u32 ret_value = 0;
961 u8 i;
962
963 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
964 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
965 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
966
967 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
968
969 dig_t->fa_th[0] = 250;
970 dig_t->fa_th[1] = 500;
971 dig_t->fa_th[2] = 750;
972 dig_t->is_dbg_fa_th = false;
973 dig_t->igi_dyn_up_hit = false;
974 dig_t->fw_dig_enable = false;
975
976 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
977 /* @For RTL8881A */
978 false_alm_cnt->cnt_ofdm_fail_pre = 0;
979 #endif
980
981 dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
982 dig_t->rx_gain_range_min = dig_t->cur_ig_value;
983
984 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
985 if (dm->support_ic_type &
986 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
987 dig_t->enable_adjust_big_jump = 1;
988
989 if (dm->support_ic_type & ODM_RTL8822B)
990 ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
991 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
992 ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
993
994 dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
995 dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
996 dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
997
998 for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
999 if (dig_t->big_jump_lmt[i] == 0)
1000 dig_t->big_jump_lmt[i] = 0x64;
1001 /* Set -10dBm as default value */
1002 }
1003 }
1004 #endif
1005
1006 #ifdef PHYDM_TDMA_DIG_SUPPORT
1007 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1008 dm->original_dig_restore = true;
1009 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
1010 dm->tdma_dig_timer_ms = DIG_TIMER_MS;
1011 #endif
1012 dig_t->tdma_force_l_igi = 0xff;
1013 dig_t->tdma_force_h_igi = 0xff;
1014 #endif
1015 #ifdef CFG_DIG_DAMPING_CHK
1016 phydm_dig_recorder_reset(dm);
1017 dig_t->dig_dl_en = 1;
1018 #endif
1019
1020 #ifdef PHYDM_HW_IGI
1021 phydm_hwigi_init(dm);
1022 #endif
1023 }
phydm_dig_abs_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1024 void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1025 {
1026 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1027 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
1028
1029 if (is_dfs_band) {
1030 if (*dm->band_width == CHANNEL_WIDTH_20){
1031 if (dm->support_ic_type &
1032 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
1033 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
1034 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
1035 else
1036 dig_t->dm_dig_min = DIG_MIN_DFS;
1037 }
1038 else
1039 dig_t->dm_dig_min = DIG_MIN_DFS;
1040 }
1041 else
1042 dig_t->dm_dig_min = DIG_MIN_DFS;
1043
1044 dig_t->dig_max_of_min = DIG_MIN_DFS;
1045 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1046 } else if (!dm->is_linked) {
1047 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
1048 dig_t->dm_dig_min = DIG_MIN_COVERAGE;
1049 } else {
1050 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
1051 /*service > 2 devices*/
1052 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1053 #if (DIG_HW == 1)
1054 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
1055 #else
1056 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
1057 #endif
1058 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
1059 /*service 1 devices*/
1060 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
1061 dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1062 /*dig_max shouldn't be too high because of adaptivity*/
1063 dig_t->dm_dig_max =
1064 MIN_2((adapt->th_l2h + 40),
1065 DIG_MAX_PERFORMANCE_MODE);
1066 else
1067 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
1068
1069 #if (RTL8822B_SUPPORT == 1)
1070 if (dm->is_dig_low_bond)
1071 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE_22B;
1072 else
1073 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
1074 #else
1075 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
1076 #endif
1077 }
1078
1079 if (dm->support_ic_type &
1080 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
1081 dig_t->dm_dig_min = 0x1c;
1082 else if (dm->support_ic_type & ODM_RTL8197F)
1083 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
1084 else
1085 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
1086 }
1087
1088 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
1089 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
1090 }
1091
phydm_dig_dym_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1092 void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1093 {
1094 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1095 #ifdef CFG_DIG_DAMPING_CHK
1096 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
1097 #endif
1098 u8 offset = 15, tmp_max = 0;
1099 u8 max_of_rssi_min = 0;
1100
1101 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
1102
1103 #if (RTL8822B_SUPPORT == 1)
1104 if (dm->is_dig_low_bond)
1105 offset = 5;
1106 else
1107 offset = 15;
1108 #else
1109 offset = 15;
1110 #endif
1111
1112 if (!dm->is_linked) {
1113 /*@if no link, always stay at lower bound*/
1114 dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
1115 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1116
1117 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
1118 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1119 return;
1120 }
1121
1122 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
1123
1124 /* @DIG lower bound */
1125 if (is_dfs_band)
1126 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1127 else if (dm->rssi_min > dig_t->dig_max_of_min)
1128 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1129 else if (dm->rssi_min < dig_t->dm_dig_min)
1130 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1131 else
1132 dig_t->rx_gain_range_min = dm->rssi_min;
1133
1134 #ifdef CFG_DIG_DAMPING_CHK
1135 /*@Limit Dyn min by damping*/
1136 if (dig_t->dig_dl_en &&
1137 dig_rc->damping_limit_en &&
1138 dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
1139 PHYDM_DBG(dm, DBG_DIG,
1140 "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
1141 dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
1142
1143 dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
1144 }
1145 #endif
1146
1147 /* @DIG upper bound */
1148 tmp_max = dig_t->rx_gain_range_min + offset;
1149 if (dig_t->rx_gain_range_min != dm->rssi_min) {
1150 max_of_rssi_min = dm->rssi_min + offset;
1151 if (tmp_max > max_of_rssi_min)
1152 tmp_max = max_of_rssi_min;
1153 }
1154
1155 if (tmp_max > dig_t->dm_dig_max)
1156 dig_t->rx_gain_range_max = dig_t->dm_dig_max;
1157 else if (tmp_max < dig_t->dm_dig_min)
1158 dig_t->rx_gain_range_max = dig_t->dm_dig_min;
1159 else
1160 dig_t->rx_gain_range_max = tmp_max;
1161
1162 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1163 /* @1 Force Lower Bound for AntDiv */
1164 if (!dm->is_one_entry_only &&
1165 (dm->support_ability & ODM_BB_ANT_DIV) &&
1166 (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
1167 dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
1168 if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
1169 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1170 else
1171 dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
1172
1173 PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
1174 dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
1175 }
1176 #endif
1177
1178 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
1179 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1180 }
1181
phydm_dig_abnormal_case(struct dm_struct * dm)1182 void phydm_dig_abnormal_case(struct dm_struct *dm)
1183 {
1184 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1185
1186 /* @Abnormal lower bound case */
1187 if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
1188 dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
1189
1190 PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
1191 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1192 }
1193
phydm_new_igi_by_fa(struct dm_struct * dm,u8 igi,u32 fa_cnt,u8 * step_size)1194 u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)
1195 {
1196 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1197
1198 if (fa_cnt > dig_t->fa_th[2])
1199 igi = igi + step_size[0];
1200 else if (fa_cnt > dig_t->fa_th[1])
1201 igi = igi + step_size[1];
1202 else if (fa_cnt < dig_t->fa_th[0])
1203 igi = igi - step_size[2];
1204
1205 return igi;
1206 }
1207
phydm_get_new_igi(struct dm_struct * dm,u8 igi,u32 fa_cnt,boolean is_dfs_band)1208 u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
1209 boolean is_dfs_band)
1210 {
1211 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1212 u8 step[3] = {0};
1213
1214 if (dm->is_linked) {
1215 if (dm->pre_rssi_min <= dm->rssi_min) {
1216 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
1217 step[0] = 2;
1218 step[1] = 1;
1219 step[2] = 2;
1220 } else {
1221 step[0] = 4;
1222 step[1] = 2;
1223 step[2] = 2;
1224 }
1225 } else {
1226 step[0] = 2;
1227 step[1] = 1;
1228 step[2] = 2;
1229 }
1230
1231 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
1232 step[0]);
1233
1234 if (dm->first_connect) {
1235 if (is_dfs_band) {
1236 if (dm->rssi_min > DIG_MAX_DFS)
1237 igi = DIG_MAX_DFS;
1238 else
1239 igi = dm->rssi_min;
1240 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
1241 dig_t->rx_gain_range_max);
1242 } else {
1243 igi = dig_t->rx_gain_range_min;
1244 }
1245
1246 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1247 #if (RTL8812A_SUPPORT)
1248 if (dm->support_ic_type == ODM_RTL8812)
1249 odm_config_bb_with_header_file(dm,
1250 CONFIG_BB_AGC_TAB_DIFF);
1251 #endif
1252 #endif
1253 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
1254 } else if (dm->is_linked) {
1255 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
1256 /* @4 Abnormal # beacon case */
1257 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1258 if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
1259 fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
1260 dm->support_ic_type != ODM_RTL8723D &&
1261 dm->support_ic_type != ODM_RTL8822B &&
1262 dm->support_ic_type != ODM_RTL8822C) {
1263 dig_t->rx_gain_range_min = 0x1c;
1264 igi = dig_t->rx_gain_range_min;
1265 PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
1266 dm->phy_dbg_info.num_qry_beacon_pkt, igi);
1267 } else {
1268 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
1269 }
1270 #else
1271 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
1272 #endif
1273 } else {
1274 /* @2 Before link */
1275 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
1276
1277 if (dm->first_disconnect) {
1278 igi = dig_t->dm_dig_min;
1279 PHYDM_DBG(dm, DBG_DIG,
1280 "First disconnect:foce IGI to lower bound\n");
1281 } else {
1282 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
1283 igi, fa_cnt);
1284
1285 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
1286 }
1287 }
1288
1289 /*@Check IGI by dyn-upper/lower bound */
1290 if (igi < dig_t->rx_gain_range_min)
1291 igi = dig_t->rx_gain_range_min;
1292
1293 if (igi >= dig_t->rx_gain_range_max) {
1294 igi = dig_t->rx_gain_range_max;
1295 dig_t->igi_dyn_up_hit = true;
1296 } else {
1297 dig_t->igi_dyn_up_hit = false;
1298 }
1299 PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n",
1300 dig_t->igi_dyn_up_hit);
1301
1302 PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
1303 fa_cnt, dig_t->cur_ig_value, igi);
1304
1305 return igi;
1306 }
1307
phydm_dig_dfs_mode_en(void * dm_void)1308 boolean phydm_dig_dfs_mode_en(void *dm_void)
1309 {
1310 struct dm_struct *dm = (struct dm_struct *)dm_void;
1311 boolean dfs_mode_en = false;
1312
1313 /* @Modify lower bound for DFS band */
1314 if (dm->is_dfs_band) {
1315 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1316 dfs_mode_en = true;
1317 #else
1318 if (phydm_dfs_master_enabled(dm))
1319 dfs_mode_en = true;
1320 #endif
1321 PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
1322 }
1323 return dfs_mode_en;
1324 }
1325
phydm_dig(void * dm_void)1326 void phydm_dig(void *dm_void)
1327 {
1328 struct dm_struct *dm = (struct dm_struct *)dm_void;
1329 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1330 struct phydm_fa_struct *fa = &dm->false_alm_cnt;
1331 #ifdef PHYDM_TDMA_DIG_SUPPORT
1332 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1333 #endif
1334 u8 igi = dig_t->cur_ig_value;
1335 u8 new_igi = 0x20;
1336 u32 fa_cnt = fa->cnt_all;
1337 boolean dfs_mode_en = false;
1338
1339 #ifdef PHYDM_DCC_ENHANCE
1340 if (dm->dm_dcc_info.dcc_en)
1341 fa_cnt = fa->cnt_ofdm_fail; /*OFDM FA only*/
1342 #endif
1343
1344 #ifdef PHYDM_TDMA_DIG_SUPPORT
1345 if (!(dm->original_dig_restore)) {
1346 if (dig_t->cur_ig_value_tdma == 0)
1347 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1348
1349 igi = dig_t->cur_ig_value_tdma;
1350 fa_cnt = falm_cnt_acc->cnt_all_1sec;
1351 }
1352 #endif
1353
1354 if (phydm_dig_abort(dm)) {
1355 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1356 return;
1357 }
1358
1359 PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
1360 PHYDM_DBG(dm, DBG_DIG,
1361 "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
1362 dm->is_linked, dm->rssi_min,
1363 dm->first_connect, dm->first_disconnect);
1364
1365 PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
1366 (*dm->bb_op_mode ? "Balance" : "Performance"));
1367
1368 /*@DFS mode enable check*/
1369 dfs_mode_en = phydm_dig_dfs_mode_en(dm);
1370
1371 #ifdef CFG_DIG_DAMPING_CHK
1372 /*Record IGI History*/
1373 phydm_dig_recorder(dm, igi, fa_cnt);
1374
1375 /*@DIG Damping Check*/
1376 phydm_dig_damping_chk(dm);
1377 #endif
1378
1379 /*@Absolute Boundary Decision */
1380 phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
1381
1382 /*@Dynamic Boundary Decision*/
1383 phydm_dig_dym_boundary_decision(dm, dfs_mode_en);
1384
1385 /*@Abnormal case check*/
1386 phydm_dig_abnormal_case(dm);
1387
1388 /*@FA threshold decision */
1389 phydm_fa_threshold_check(dm, dfs_mode_en);
1390
1391 /*Select new IGI by FA */
1392 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
1393
1394 /* @1 Update status */
1395 #ifdef PHYDM_TDMA_DIG_SUPPORT
1396 if (!(dm->original_dig_restore)) {
1397 dig_t->cur_ig_value_tdma = new_igi;
1398 /*@It is possible fa_acc_1sec_tsf >= */
1399 /*@1sec while tdma_dig_state == 0*/
1400 if (dig_t->tdma_dig_state != 0)
1401 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
1402 } else
1403 #endif
1404 odm_write_dig(dm, new_igi);
1405 }
1406
phydm_dig_lps_32k(void * dm_void)1407 void phydm_dig_lps_32k(void *dm_void)
1408 {
1409 struct dm_struct *dm = (struct dm_struct *)dm_void;
1410 u8 current_igi = dm->rssi_min;
1411
1412 odm_write_dig(dm, current_igi);
1413 }
1414
phydm_dig_by_rssi_lps(void * dm_void)1415 void phydm_dig_by_rssi_lps(void *dm_void)
1416 {
1417 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1418 struct dm_struct *dm = (struct dm_struct *)dm_void;
1419 struct phydm_fa_struct *falm_cnt;
1420
1421 u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
1422 u8 current_igi = dm->rssi_min;
1423
1424 falm_cnt = &dm->false_alm_cnt;
1425 if (phydm_dig_abort(dm))
1426 return;
1427
1428 current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
1429 PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
1430
1431 /* Using FW PS mode to make IGI */
1432 /* @Adjust by FA in LPS MODE */
1433 if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
1434 current_igi = current_igi + 4;
1435 else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
1436 current_igi = current_igi + 2;
1437 else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
1438 current_igi = current_igi - 2;
1439
1440 /* @Lower bound checking */
1441
1442 /* RSSI Lower bound check */
1443 if ((dm->rssi_min - 10) > DIG_MIN_LPS)
1444 rssi_lower = (dm->rssi_min - 10);
1445 else
1446 rssi_lower = DIG_MIN_LPS;
1447
1448 /* Upper and Lower Bound checking */
1449 if (current_igi > DIG_MAX_LPS)
1450 current_igi = DIG_MAX_LPS;
1451 else if (current_igi < rssi_lower)
1452 current_igi = rssi_lower;
1453
1454 PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
1455 falm_cnt->cnt_all, dm->rssi_min, current_igi);
1456 odm_write_dig(dm, current_igi);
1457 #endif
1458 }
1459
1460 /* @3============================================================
1461 * 3 FASLE ALARM CHECK
1462 * 3============================================================
1463 */
phydm_false_alarm_counter_reg_reset(void * dm_void)1464 void phydm_false_alarm_counter_reg_reset(void *dm_void)
1465 {
1466 struct dm_struct *dm = (struct dm_struct *)dm_void;
1467 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
1468 #ifdef PHYDM_TDMA_DIG_SUPPORT
1469 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1470 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1471 #endif
1472 u32 false_alm_cnt = 0;
1473
1474 #ifdef PHYDM_TDMA_DIG_SUPPORT
1475 if (!(dm->original_dig_restore)) {
1476 if (dig_t->cur_ig_value_tdma == 0)
1477 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1478
1479 false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
1480 } else
1481 #endif
1482 {
1483 false_alm_cnt = falm_cnt->cnt_all;
1484 }
1485
1486 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1487 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1488 /* @reset CCK FA counter */
1489 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
1490 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
1491
1492 /* @reset CCK CCA counter */
1493 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
1494 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
1495
1496 /* @Disable common rx clk gating => WLANBB-1106*/
1497 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);
1498 /* @reset OFDM CCA counter, OFDM FA counter*/
1499 phydm_reset_bb_hw_cnt(dm);
1500 /* @Enable common rx clk gating => WLANBB-1106*/
1501 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);
1502 }
1503 #endif
1504 #if (ODM_IC_11N_SERIES_SUPPORT)
1505 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1506 /* @reset false alarm counter registers*/
1507 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
1508 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
1509 odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
1510 odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
1511
1512 /* @update ofdm counter*/
1513 /* @update page C counter*/
1514 odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
1515 /* @update page D counter*/
1516 odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
1517
1518 /* @reset CCK CCA counter*/
1519 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
1520 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
1521
1522 /* @reset CCK FA counter*/
1523 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
1524 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
1525
1526 /* @reset CRC32 counter*/
1527 odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
1528 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
1529 }
1530 #endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
1531
1532 #if (ODM_IC_11AC_SERIES_SUPPORT)
1533 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1534 #if (RTL8881A_SUPPORT)
1535 /* @Reset FA counter by enable/disable OFDM */
1536 if ((dm->support_ic_type == ODM_RTL8881A) &&
1537 false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
1538 /* reset OFDM */
1539 odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
1540 odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
1541 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1542 PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
1543 }
1544 #endif /* @#if (RTL8881A_SUPPORT) */
1545
1546 /* @reset OFDM FA countner */
1547 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
1548 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
1549
1550 /* @reset CCK FA counter */
1551 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
1552 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
1553
1554 /* @reset CCA counter */
1555 phydm_reset_bb_hw_cnt(dm);
1556 }
1557 #endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
1558 }
1559
phydm_false_alarm_counter_reg_hold(void * dm_void)1560 void phydm_false_alarm_counter_reg_hold(void *dm_void)
1561 {
1562 struct dm_struct *dm = (struct dm_struct *)dm_void;
1563
1564 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1565 /* @hold cck counter */
1566 odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
1567 odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
1568 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1569 /*@hold ofdm counter*/
1570 /*@hold page C counter*/
1571 odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
1572 /*@hold page D counter*/
1573 odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
1574
1575 /*@hold cck counter*/
1576 odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
1577 odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
1578 }
1579 }
1580
1581 #if (ODM_IC_11N_SERIES_SUPPORT)
phydm_fa_cnt_statistics_n(void * dm_void)1582 void phydm_fa_cnt_statistics_n(void *dm_void)
1583 {
1584 struct dm_struct *dm = (struct dm_struct *)dm_void;
1585 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1586 u32 reg = 0;
1587
1588 if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
1589 return;
1590
1591 /* @hold ofdm & cck counter */
1592 phydm_false_alarm_counter_reg_hold(dm);
1593
1594 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
1595 fa_t->cnt_fast_fsync = (reg & 0xffff);
1596 fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
1597
1598 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
1599 fa_t->cnt_ofdm_cca = (reg & 0xffff);
1600 fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
1601
1602 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
1603 fa_t->cnt_rate_illegal = (reg & 0xffff);
1604 fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
1605
1606 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
1607 fa_t->cnt_mcs_fail = (reg & 0xffff);
1608
1609 fa_t->cnt_ofdm_fail =
1610 fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
1611 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
1612 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
1613
1614 /* read CCK CRC32 counter */
1615 fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
1616 fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
1617
1618 /* read OFDM CRC32 counter */
1619 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
1620 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1621 fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
1622
1623 /* read OFDM2 CRC32 counter */
1624 reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD);
1625 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1626 fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff;
1627
1628 /* read HT CRC32 counter */
1629 reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1630 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1631 fa_t->cnt_ht_crc32_ok = reg & 0xffff;
1632
1633 /* read HT2 CRC32 counter */
1634 reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
1635 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1636 fa_t->cnt_ht2_crc32_ok = reg & 0xffff;
1637
1638 /* read VHT CRC32 counter */
1639 fa_t->cnt_vht_crc32_error = 0;
1640 fa_t->cnt_vht_crc32_ok = 0;
1641
1642 #if (RTL8723D_SUPPORT)
1643 if (dm->support_ic_type == ODM_RTL8723D) {
1644 /* read HT CRC32 agg counter */
1645 reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
1646 fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
1647 fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
1648 }
1649 #endif
1650
1651 #if (RTL8188E_SUPPORT)
1652 if (dm->support_ic_type == ODM_RTL8188E) {
1653 reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
1654 fa_t->cnt_bw_lsc = (reg & 0xffff);
1655 fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
1656 }
1657 #endif
1658
1659 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
1660 fa_t->cnt_cck_fail = reg;
1661
1662 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
1663 fa_t->cnt_cck_fail += (reg & 0xff) << 8;
1664
1665 reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
1666 fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
1667
1668 fa_t->cnt_all_pre = fa_t->cnt_all;
1669
1670 fa_t->cnt_all = fa_t->cnt_fast_fsync +
1671 fa_t->cnt_sb_search_fail +
1672 fa_t->cnt_parity_fail +
1673 fa_t->cnt_rate_illegal +
1674 fa_t->cnt_crc8_fail +
1675 fa_t->cnt_mcs_fail +
1676 fa_t->cnt_cck_fail;
1677
1678 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
1679 }
1680 #endif
1681
1682 #if (ODM_IC_11AC_SERIES_SUPPORT)
phydm_fa_cnt_statistics_ac(void * dm_void)1683 void phydm_fa_cnt_statistics_ac(void *dm_void)
1684 {
1685 struct dm_struct *dm = (struct dm_struct *)dm_void;
1686 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1687 u32 ret_value = 0;
1688 u32 cck_enable = 0;
1689
1690 if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
1691 return;
1692
1693 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
1694 fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
1695
1696 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
1697 fa_t->cnt_sb_search_fail = ret_value & 0xffff;
1698
1699 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
1700 fa_t->cnt_parity_fail = ret_value & 0xffff;
1701 fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
1702
1703 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
1704 fa_t->cnt_crc8_fail = ret_value & 0xffff;
1705 fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
1706
1707 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
1708 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
1709 fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
1710
1711 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
1712 fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
1713
1714 /* read OFDM FA counter */
1715 fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
1716
1717 /* Read CCK FA counter */
1718 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1719
1720 /* read CCK/OFDM CCA counter */
1721 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1722 fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1723 fa_t->cnt_cck_cca = ret_value & 0xffff;
1724
1725 /* read CCK CRC32 counter */
1726 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
1727 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
1728 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
1729
1730 /* read OFDM CRC32 counter */
1731 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
1732 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1733 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1734
1735 /* read OFDM2 CRC32 counter */
1736 ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD);
1737 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
1738 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
1739
1740 /* read HT CRC32 counter */
1741 ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
1742 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1743 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
1744
1745 /* read HT2 CRC32 counter */
1746 ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD);
1747 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
1748 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1749
1750 /* read VHT CRC32 counter */
1751 ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
1752 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
1753 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
1754
1755 /*read VHT2 CRC32 counter */
1756 ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
1757 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
1758 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1759
1760 #if (RTL8881A_SUPPORT)
1761 if (dm->support_ic_type == ODM_RTL8881A) {
1762 u32 tmp = 0;
1763
1764 if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
1765 tmp = fa_t->cnt_ofdm_fail_pre;
1766 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1767 fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
1768 } else {
1769 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1770 }
1771
1772 PHYDM_DBG(dm, DBG_FA_CNT,
1773 "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
1774 fa_t->cnt_ofdm_fail_pre, tmp);
1775 }
1776 #endif
1777
1778 cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1779
1780 if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
1781 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
1782 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
1783 } else {
1784 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
1785 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
1786 }
1787 }
1788 #endif
1789
phydm_get_edcca_report(void * dm_void)1790 u32 phydm_get_edcca_report(void *dm_void)
1791 {
1792 struct dm_struct *dm = (struct dm_struct *)dm_void;
1793 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1794 u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
1795 u32 val = 0;
1796
1797 if (dm->support_ic_type & ODM_RTL8723D) {
1798 val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
1799 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1800 val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
1801 } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
1802 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
1803 val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
1804 else
1805 val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
1806 phydm_release_bb_dbg_port(dm);
1807 }
1808
1809 return val;
1810 }
1811
phydm_get_dbg_port_info(void * dm_void)1812 void phydm_get_dbg_port_info(void *dm_void)
1813 {
1814 struct dm_struct *dm = (struct dm_struct *)dm_void;
1815 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1816
1817 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1818 fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);
1819 } else {
1820 /*set debug port to 0x0*/
1821 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
1822 fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
1823 phydm_release_bb_dbg_port(dm);
1824 }
1825 }
1826
1827 fa_t->edcca_flag = (boolean)phydm_get_edcca_report(dm);
1828
1829 PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n",
1830 fa_t->dbg_port0, fa_t->edcca_flag);
1831 }
1832
phydm_set_crc32_cnt2_rate(void * dm_void,u8 rate_idx)1833 void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx)
1834 {
1835 struct dm_struct *dm = (struct dm_struct *)dm_void;
1836 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1837 boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx);
1838 boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx);
1839 boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx);
1840 u32 reg_addr = 0x0;
1841 u32 ofdm_rate_bitmask = 0x0;
1842 u32 ht_mcs_bitmask = 0x0;
1843 u32 vht_mcs_bitmask = 0x0;
1844 u32 vht_ss_bitmask = 0x0;
1845 u8 rate = 0x0;
1846 u8 ss = 0x0;
1847
1848 if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate)
1849 PHYDM_DBG(dm, DBG_FA_CNT,
1850 "[FA CNT] rate_idx = (0x%x) is not supported !\n",
1851 rate_idx);
1852
1853 switch (dm->ic_ip_series) {
1854 case PHYDM_IC_N:
1855 reg_addr = R_0xf04;
1856 ofdm_rate_bitmask = 0x0000f000;
1857 ht_mcs_bitmask = 0x007f0000;
1858 break;
1859 case PHYDM_IC_AC:
1860 reg_addr = R_0xb04;
1861 ofdm_rate_bitmask = 0x0000f000;
1862 ht_mcs_bitmask = 0x007f0000;
1863 vht_mcs_bitmask = 0x0f000000;
1864 vht_ss_bitmask = 0x30000000;
1865 break;
1866 case PHYDM_IC_JGR3:
1867 reg_addr = R_0x1eb8;
1868 ofdm_rate_bitmask = 0x00000f00;
1869 ht_mcs_bitmask = 0x007f0000;
1870 vht_mcs_bitmask = 0x0000f000;
1871 vht_ss_bitmask = 0x000000c0;
1872 break;
1873 default:
1874 break;
1875 }
1876
1877 if (is_ofdm_rate) {
1878 rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx);
1879
1880 odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate);
1881 fa_t->ofdm2_rate_idx = rate_idx;
1882 } else if (is_ht_rate) {
1883 rate = phydm_rate_2_rate_digit(dm, rate_idx);
1884
1885 odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate);
1886 fa_t->ht2_rate_idx = rate_idx;
1887 } else if (is_vht_rate) {
1888 rate = phydm_rate_2_rate_digit(dm, rate_idx);
1889 ss = phydm_rate_to_num_ss(dm, rate_idx);
1890
1891 odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate);
1892 odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1);
1893 fa_t->vht2_rate_idx = rate_idx;
1894 }
1895 }
1896
phydm_false_alarm_counter_statistics(void * dm_void)1897 void phydm_false_alarm_counter_statistics(void *dm_void)
1898 {
1899 struct dm_struct *dm = (struct dm_struct *)dm_void;
1900 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1901 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
1902 u32 tmp = 0;
1903
1904 if (!(dm->support_ability & ODM_BB_FA_CNT))
1905 return;
1906
1907 PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
1908
1909 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1910 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1911 phydm_fa_cnt_statistics_jgr3(dm);
1912 #endif
1913 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1914 #if (ODM_IC_11N_SERIES_SUPPORT)
1915 phydm_fa_cnt_statistics_n(dm);
1916 #endif
1917 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1918 #if (ODM_IC_11AC_SERIES_SUPPORT)
1919 phydm_fa_cnt_statistics_ac(dm);
1920 #endif
1921 }
1922
1923 phydm_get_dbg_port_info(dm);
1924 phydm_false_alarm_counter_reg_reset(dm_void);
1925
1926 fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
1927 fa_t->cnt_sb_search_fail * 12 +
1928 fa_t->cnt_parity_fail * 28 +
1929 fa_t->cnt_rate_illegal * 28 +
1930 fa_t->cnt_crc8_fail * 20 +
1931 fa_t->cnt_crc8_fail_vhta * 28 +
1932 fa_t->cnt_mcs_fail_vht * 36 +
1933 fa_t->cnt_mcs_fail * 32 +
1934 fa_t->cnt_cck_fail * 80;
1935
1936 fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
1937 fa_t->cnt_ht_crc32_error +
1938 fa_t->cnt_ofdm_crc32_error +
1939 fa_t->cnt_cck_crc32_error;
1940
1941 fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
1942 fa_t->cnt_ht_crc32_ok +
1943 fa_t->cnt_ofdm_crc32_ok +
1944 fa_t->cnt_cck_crc32_ok;
1945
1946 PHYDM_DBG(dm, DBG_FA_CNT,
1947 "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1948 fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
1949 PHYDM_DBG(dm, DBG_FA_CNT,
1950 "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1951 fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
1952 PHYDM_DBG(dm, DBG_FA_CNT,
1953 "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
1954 fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
1955 fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
1956 PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
1957 fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
1958 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
1959 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
1960 PHYDM_DBG(dm, DBG_FA_CNT,
1961 "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
1962 fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
1963 fa_t->cnt_mcs_fail_vht);
1964 }
1965 #endif
1966
1967 PHYDM_DBG(dm, DBG_FA_CNT,
1968 "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
1969 fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
1970 fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
1971 fa_t->cnt_crc32_ok_all);
1972 PHYDM_DBG(dm, DBG_FA_CNT,
1973 "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
1974 fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
1975 fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
1976 fa_t->cnt_crc32_error_all);
1977
1978 if (fa_t->ofdm2_rate_idx) {
1979 tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok;
1980 fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100,
1981 tmp);
1982 phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf,
1983 PHYDM_SNPRINT_SIZE);
1984 PHYDM_DBG(dm, DBG_FA_CNT,
1985 "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
1986 dbg_buf, fa_t->cnt_ofdm2_crc32_error,
1987 fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
1988 } else {
1989 phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M);
1990 }
1991
1992 if (fa_t->ht2_rate_idx) {
1993 tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok;
1994 fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100,
1995 tmp);
1996 phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
1997 PHYDM_SNPRINT_SIZE);
1998 PHYDM_DBG(dm, DBG_FA_CNT,
1999 "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2000 dbg_buf, fa_t->cnt_ht2_crc32_error,
2001 fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
2002 } else {
2003 phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0);
2004 }
2005
2006 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
2007 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
2008 if (fa_t->vht2_rate_idx) {
2009 tmp = fa_t->cnt_vht2_crc32_error +
2010 fa_t->cnt_vht2_crc32_ok;
2011 fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok *
2012 100, tmp);
2013 phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
2014 dbg_buf, PHYDM_SNPRINT_SIZE);
2015 PHYDM_DBG(dm, DBG_FA_CNT,
2016 "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2017 dbg_buf, fa_t->cnt_vht2_crc32_error,
2018 fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
2019 } else {
2020 phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0);
2021 }
2022 }
2023 #endif
2024 }
2025
phydm_fill_fw_dig_info(void * dm_void,boolean * enable,u8 * para4,u8 * para8)2026 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
2027 u8 *para4, u8 *para8) {
2028 struct dm_struct *dm = (struct dm_struct *)dm_void;
2029 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2030
2031 dig_t->fw_dig_enable = *enable;
2032 para8[0] = dig_t->rx_gain_range_max;
2033 para8[1] = dig_t->rx_gain_range_min;
2034 para8[2] = dm->number_linked_client;
2035 para4[0] = (u8)DIG_LPS_MODE;
2036 }
2037
phydm_crc32_cnt_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2038 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
2039 char *output, u32 *_out_len)
2040 {
2041 struct dm_struct *dm = (struct dm_struct *)dm_void;
2042 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2043 char help[] = "-h";
2044 u32 var1[10] = {0};
2045 u32 used = *_used;
2046 u32 out_len = *_out_len;
2047 u8 i = 0;
2048 u8 rate = 0x0;
2049
2050 if ((strcmp(input[1], help) == 0)) {
2051 PDM_SNPF(out_len, used, output + used, out_len - used,
2052 "[CRC32 Cnt] {rate_idx}\n");
2053 } else {
2054 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2055 rate = (u8)var1[0];
2056
2057 PDM_SNPF(out_len, used, output + used, out_len - used,
2058 "{rate}={0x%x}", rate);
2059
2060 phydm_set_crc32_cnt2_rate(dm, rate);
2061 }
2062 *_used = used;
2063 *_out_len = out_len;
2064 }
2065
2066 #ifdef PHYDM_TDMA_DIG_SUPPORT
phydm_set_tdma_dig_timer(void * dm_void)2067 void phydm_set_tdma_dig_timer(void *dm_void)
2068 {
2069 struct dm_struct *dm = (struct dm_struct *)dm_void;
2070 u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
2071 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2072 u32 timeout = 0;
2073 u32 current_time_stamp, diff_time_stamp, regb0 = 0;
2074
2075 /*some IC has no FREERUN_CUNT register, like 92E*/
2076 if (dm->support_ic_type & ODM_RTL8197F)
2077 current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
2078 else
2079 return;
2080
2081 timeout = current_time_stamp + delta_time_us;
2082
2083 diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
2084 dig_t->pre_timestamp = dig_t->cur_timestamp;
2085 dig_t->cur_timestamp = current_time_stamp;
2086
2087 /*@HIMR0, it shows HW interrupt mask*/
2088 regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
2089
2090 PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
2091 PHYDM_DBG(dm, DBG_DIG,
2092 "curr_time_stamp=%d, delta_time_us=%d\n",
2093 current_time_stamp, delta_time_us);
2094 PHYDM_DBG(dm, DBG_DIG,
2095 "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
2096 timeout, diff_time_stamp, regb0);
2097
2098 if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
2099 odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
2100 else {
2101 PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
2102 return;
2103 }
2104 }
2105
phydm_tdma_dig_timer_check(void * dm_void)2106 void phydm_tdma_dig_timer_check(void *dm_void)
2107 {
2108 struct dm_struct *dm = (struct dm_struct *)dm_void;
2109 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2110
2111 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
2112 dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
2113
2114 if (dig_t->tdma_dig_cnt == 0 ||
2115 dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
2116 if (dm->support_ability & ODM_BB_DIG) {
2117 #ifdef IS_USE_NEW_TDMA
2118 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
2119 ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
2120 ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
2121 ODM_RTL8723D)) {
2122 PHYDM_DBG(dm, DBG_DIG,
2123 "Check fail, Restart timer\n\n");
2124 phydm_false_alarm_counter_reset(dm);
2125 odm_set_timer(dm, &dm->tdma_dig_timer,
2126 dm->tdma_dig_timer_ms);
2127 } else {
2128 PHYDM_DBG(dm, DBG_DIG,
2129 "Not support TDMADIG, no SW timer\n");
2130 }
2131 #else
2132 /*@if interrupt mask info is got.*/
2133 /*Reg0xb0 is no longer needed*/
2134 #if 0
2135 /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
2136 #endif
2137 PHYDM_DBG(dm, DBG_DIG,
2138 "Check fail, Mask[0]=0x%x, restart timer\n",
2139 *dm->interrupt_mask);
2140
2141 phydm_tdma_dig_add_interrupt_mask_handler(dm);
2142 phydm_enable_rx_related_interrupt_handler(dm);
2143 phydm_set_tdma_dig_timer(dm);
2144 #endif
2145 }
2146 } else {
2147 PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
2148 }
2149
2150 dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
2151 }
2152
2153 /*@different IC/team may use different timer for tdma-dig*/
phydm_tdma_dig_add_interrupt_mask_handler(void * dm_void)2154 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
2155 {
2156 struct dm_struct *dm = (struct dm_struct *)dm_void;
2157
2158 #if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
2159 if (dm->support_ic_type & ODM_RTL8197F) {
2160 /*@HAL_INT_TYPE_PSTIMEOUT2*/
2161 phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
2162 }
2163 #elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
2164 #elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
2165 #endif
2166 }
2167
2168 /* will be triggered by HW timer*/
phydm_tdma_dig(void * dm_void)2169 void phydm_tdma_dig(void *dm_void)
2170 {
2171 struct dm_struct *dm = (struct dm_struct *)dm_void;
2172 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2173 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2174 u32 reg_c50 = 0;
2175
2176 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
2177 RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
2178 #ifdef IS_USE_NEW_TDMA
2179 if (dm->support_ic_type &
2180 (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |
2181 ODM_RTL8192F | ODM_RTL8821C)) {
2182 PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n");
2183 return;
2184 }
2185 #endif
2186 #endif
2187 reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
2188
2189 dig_t->tdma_dig_state =
2190 dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2191
2192 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
2193 dig_t->tdma_dig_state, reg_c50);
2194
2195 dig_t->tdma_dig_cnt++;
2196
2197 if (dig_t->tdma_dig_state == 1) {
2198 /* update IGI from tdma_dig_state == 0*/
2199 if (dig_t->cur_ig_value_tdma == 0)
2200 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
2201
2202 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2203 phydm_tdma_false_alarm_counter_check(dm);
2204 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
2205 dig_t->tdma_dig_state);
2206
2207 } else if (dig_t->tdma_dig_state == 0) {
2208 /* update dig_t->CurIGValue,*/
2209 /* @it may different from dig_t->cur_ig_value_tdma */
2210 /* TDMA IGI upperbond @ L-state = */
2211 /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
2212
2213 if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
2214 dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
2215 else
2216 dig_t->low_ig_value = dig_t->cur_ig_value;
2217
2218 odm_write_dig(dm, dig_t->low_ig_value);
2219 phydm_tdma_false_alarm_counter_check(dm);
2220 } else {
2221 phydm_tdma_false_alarm_counter_check(dm);
2222 }
2223 }
2224
2225 /*@============================================================*/
2226 /*@FASLE ALARM CHECK*/
2227 /*@============================================================*/
phydm_tdma_false_alarm_counter_check(void * dm_void)2228 void phydm_tdma_false_alarm_counter_check(void *dm_void)
2229 {
2230 struct dm_struct *dm = (struct dm_struct *)dm_void;
2231 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2232 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2233 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2234 boolean rssi_dump_en = 0;
2235 u32 timestamp = 0;
2236 u8 tdma_dig_state_number = 0;
2237 u32 start_th = 0;
2238
2239 if (dig_t->tdma_dig_state == 1)
2240 phydm_false_alarm_counter_reset(dm);
2241 /* Reset FalseAlarmCounterStatistics */
2242 /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
2243 /* @fa_end_tsf = fa_start_tsf = TSF */
2244 else {
2245 phydm_false_alarm_counter_statistics(dm);
2246 if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
2247 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2248 else {
2249 PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
2250 return;
2251 }
2252 dig_t->fa_end_timestamp = timestamp;
2253 dig_t->fa_acc_1sec_timestamp +=
2254 (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
2255
2256 /*prevent dumb*/
2257 if (dm->tdma_dig_state_number == 1)
2258 dm->tdma_dig_state_number = 2;
2259
2260 tdma_dig_state_number = dm->tdma_dig_state_number;
2261 dig_t->sec_factor =
2262 tdma_dig_state_number / (tdma_dig_state_number - 1);
2263
2264 /*@1sec = 1000000us*/
2265 if (dig_t->sec_factor)
2266 start_th = (u32)(1000000 / dig_t->sec_factor);
2267
2268 if (dig_t->fa_acc_1sec_timestamp >= start_th) {
2269 rssi_dump_en = 1;
2270 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2271 PHYDM_DBG(dm, DBG_DIG,
2272 "sec_factor=%d, total FA=%d, is_linked=%d\n",
2273 dig_t->sec_factor, falm_cnt_acc->cnt_all,
2274 dm->is_linked);
2275
2276 phydm_noisy_detection(dm);
2277 #ifdef PHYDM_SUPPORT_CCKPD
2278 phydm_cck_pd_th(dm);
2279 #endif
2280 phydm_dig(dm);
2281 phydm_false_alarm_counter_acc_reset(dm);
2282
2283 /* Reset FalseAlarmCounterStatistics */
2284 /* @fa_end_tsf = fa_start_tsf = TSF, keep */
2285 /* @fa_acc_1sec_tsf = 0 */
2286 phydm_false_alarm_counter_reset(dm);
2287 } else {
2288 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2289 }
2290 }
2291 }
2292
phydm_false_alarm_counter_acc(void * dm_void,boolean rssi_dump_en)2293 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
2294 {
2295 struct dm_struct *dm = (struct dm_struct *)dm_void;
2296 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2297 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2298 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2299
2300 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
2301 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
2302 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
2303 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
2304 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
2305 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
2306 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
2307 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
2308 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
2309 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
2310 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
2311 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
2312 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
2313 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
2314 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
2315 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
2316 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
2317 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
2318 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
2319 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
2320 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
2321 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
2322
2323 if (rssi_dump_en == 1) {
2324 falm_cnt_acc->cnt_all_1sec =
2325 falm_cnt_acc->cnt_all * dig_t->sec_factor;
2326 falm_cnt_acc->cnt_cca_all_1sec =
2327 falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
2328 falm_cnt_acc->cnt_cck_fail_1sec =
2329 falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
2330 }
2331 }
2332
phydm_false_alarm_counter_acc_reset(void * dm_void)2333 void phydm_false_alarm_counter_acc_reset(void *dm_void)
2334 {
2335 struct dm_struct *dm = (struct dm_struct *)dm_void;
2336 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
2337
2338 #ifdef IS_USE_NEW_TDMA
2339 struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
2340 u32 tmp_cca_1sec = 0;
2341 u32 tmp_fa_1sec = 0;
2342
2343 /*@clear L-fa_acc struct*/
2344 falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
2345 tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
2346 tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
2347 odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
2348 falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
2349 falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
2350
2351 /*@clear H-fa_acc struct*/
2352 falm_cnt_acc = &dm->false_alm_cnt_acc;
2353 tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
2354 tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
2355 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
2356 falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
2357 falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
2358 #else
2359 falm_cnt_acc = &dm->false_alm_cnt_acc;
2360 /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
2361 /* @do NOT need to be reset */
2362 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
2363 #endif
2364 }
2365
phydm_false_alarm_counter_reset(void * dm_void)2366 void phydm_false_alarm_counter_reset(void *dm_void)
2367 {
2368 struct dm_struct *dm = (struct dm_struct *)dm_void;
2369 struct phydm_fa_struct *falm_cnt;
2370 struct phydm_dig_struct *dig_t;
2371 u32 timestamp;
2372
2373 falm_cnt = &dm->false_alm_cnt;
2374 dig_t = &dm->dm_dig_table;
2375
2376 memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
2377 phydm_false_alarm_counter_reg_reset(dm);
2378
2379 #ifdef IS_USE_NEW_TDMA
2380 return;
2381 #endif
2382 if (dig_t->tdma_dig_state != 1)
2383 dig_t->fa_acc_1sec_timestamp = 0;
2384 else
2385 dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
2386
2387 /*REG_FREERUN_CNT*/
2388 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2389 dig_t->fa_start_timestamp = timestamp;
2390 dig_t->fa_end_timestamp = timestamp;
2391 }
2392
phydm_tdma_dig_para_upd(void * dm_void,enum upd_type type,u8 input)2393 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
2394 {
2395 struct dm_struct *dm = (struct dm_struct *)dm_void;
2396
2397 switch (type) {
2398 case ENABLE_TDMA:
2399 dm->original_dig_restore = !((boolean)input);
2400 break;
2401 case MODE_DECISION:
2402 if (input == (u8)MODE_PERFORMANCE)
2403 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
2404 else if (input == (u8)MODE_COVERAGE)
2405 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2406 else
2407 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2408 break;
2409 }
2410 }
2411
2412 #ifdef IS_USE_NEW_TDMA
2413 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
pre_phydm_tdma_dig_cbk(unsigned long task_dm)2414 static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
2415 {
2416 struct dm_struct *dm = (struct dm_struct *)task_dm;
2417 struct rtl8192cd_priv *priv = dm->priv;
2418 struct priv_shared_info *pshare = priv->pshare;
2419
2420 if (!(priv->drv_state & DRV_STATE_OPEN))
2421 return;
2422
2423 if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
2424 printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
2425 __FUNCTION__, pshare->bDriverStopped,
2426 pshare->bSurpriseRemoved);
2427 return;
2428 }
2429
2430 rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
2431 ENQUEUE_TO_TAIL);
2432 }
2433
phydm_tdma_dig_timers_usb(void * dm_void,u8 state)2434 void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
2435 {
2436 struct dm_struct *dm = (struct dm_struct *)dm_void;
2437 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2438
2439 if (state == INIT_TDMA_DIG_TIMMER) {
2440 struct rtl8192cd_priv *priv = dm->priv;
2441
2442 init_timer(&dm->tdma_dig_timer);
2443 dm->tdma_dig_timer.data = (unsigned long)dm;
2444 dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
2445 INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
2446 phydm_tdma_dig_cbk,
2447 (unsigned long)dm);
2448 } else if (state == CANCEL_TDMA_DIG_TIMMER) {
2449 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2450 } else if (state == RELEASE_TDMA_DIG_TIMMER) {
2451 odm_release_timer(dm, &dm->tdma_dig_timer);
2452 }
2453 }
2454 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2455
phydm_tdma_dig_timers(void * dm_void,u8 state)2456 void phydm_tdma_dig_timers(void *dm_void, u8 state)
2457 {
2458 struct dm_struct *dm = (struct dm_struct *)dm_void;
2459 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2460 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
2461 struct rtl8192cd_priv *priv = dm->priv;
2462
2463 if (priv->hci_type == RTL_HCI_USB) {
2464 phydm_tdma_dig_timers_usb(dm_void, state);
2465 return;
2466 }
2467 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2468
2469 if (state == INIT_TDMA_DIG_TIMMER)
2470 odm_initialize_timer(dm, &dm->tdma_dig_timer,
2471 (void *)phydm_tdma_dig_cbk,
2472 NULL, "phydm_tdma_dig_timer");
2473 else if (state == CANCEL_TDMA_DIG_TIMMER)
2474 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2475 else if (state == RELEASE_TDMA_DIG_TIMMER)
2476 odm_release_timer(dm, &dm->tdma_dig_timer);
2477 }
2478
get_new_igi_bound(struct dm_struct * dm,u8 igi,u32 fa_cnt,u8 * rx_gain_max,u8 * rx_gain_min,boolean is_dfs_band)2479 u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
2480 u8 *rx_gain_min, boolean is_dfs_band)
2481 {
2482 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2483 u8 step[3] = {0};
2484 u8 cur_igi = igi;
2485
2486 if (dm->is_linked) {
2487 if (dm->pre_rssi_min <= dm->rssi_min) {
2488 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
2489 step[0] = 2;
2490 step[1] = 1;
2491 step[2] = 2;
2492 } else {
2493 step[0] = 4;
2494 step[1] = 2;
2495 step[2] = 2;
2496 }
2497 } else {
2498 step[0] = 2;
2499 step[1] = 1;
2500 step[2] = 2;
2501 }
2502
2503 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
2504 step[0]);
2505
2506 if (dm->first_connect) {
2507 if (is_dfs_band) {
2508 if (dm->rssi_min > DIG_MAX_DFS)
2509 igi = DIG_MAX_DFS;
2510 else
2511 igi = dm->rssi_min;
2512 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
2513 *rx_gain_max);
2514 } else {
2515 igi = *rx_gain_min;
2516 }
2517
2518 #if 0
2519 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2520 #if (RTL8812A_SUPPORT)
2521 if (dm->support_ic_type == ODM_RTL8812)
2522 odm_config_bb_with_header_file(dm,
2523 CONFIG_BB_AGC_TAB_DIFF);
2524 #endif
2525 #endif
2526 #endif
2527 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
2528 } else {
2529 /* @2 Before link */
2530 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
2531
2532 if (dm->first_disconnect) {
2533 igi = dig_t->dm_dig_min;
2534 PHYDM_DBG(dm, DBG_DIG,
2535 "First disconnect:foce IGI to lower bound\n");
2536 } else {
2537 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
2538 igi, fa_cnt);
2539
2540 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2541 }
2542 }
2543 /*@Check IGI by dyn-upper/lower bound */
2544 if (igi < *rx_gain_min)
2545 igi = *rx_gain_min;
2546
2547 if (igi > *rx_gain_max)
2548 igi = *rx_gain_max;
2549
2550 PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
2551 fa_cnt, cur_igi, igi);
2552
2553 return igi;
2554 }
2555
phydm_write_tdma_dig(void * dm_void,u8 new_igi)2556 void phydm_write_tdma_dig(void *dm_void, u8 new_igi)
2557 {
2558 struct dm_struct *dm = (struct dm_struct *)dm_void;
2559 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2560 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
2561
2562 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
2563 #if 0
2564 /* @1 Check IGI by upper bound */
2565 if (adaptivity->igi_lmt_en &&
2566 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
2567 new_igi = adaptivity->adapt_igi_up;
2568
2569 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
2570 new_igi);
2571 }
2572 #endif
2573 phydm_write_dig_reg(dm, new_igi);
2574
2575 PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n",
2576 (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H",
2577 new_igi);
2578 }
2579
phydm_tdma_dig_new(void * dm_void)2580 void phydm_tdma_dig_new(void *dm_void)
2581 {
2582 struct dm_struct *dm = (struct dm_struct *)dm_void;
2583 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2584
2585 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2586 return;
2587 /*@
2588 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2589 * dig_t->tdma_dig_state);
2590 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2591 * dig_t->cur_ig_value_tdma,
2592 * dig_t->low_ig_value);
2593 */
2594 phydm_tdma_fa_cnt_chk(dm);
2595
2596 /*@prevent dumb*/
2597 if (dm->tdma_dig_state_number < 2)
2598 dm->tdma_dig_state_number = 2;
2599
2600 /*@update state*/
2601 dig_t->tdma_dig_cnt++;
2602 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2603
2604 /*@
2605 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2606 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2607 */
2608
2609 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2610 odm_write_dig(dm, dig_t->low_ig_value);
2611 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2612 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2613
2614 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2615 }
2616
2617 /*@callback function triggered by SW timer*/
2618 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_tdma_dig_cbk(struct phydm_timer_list * timer)2619 void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
2620 {
2621 void *adapter = (void *)timer->Adapter;
2622 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2623 struct dm_struct *dm = &hal_data->DM_OutSrcs;
2624
2625 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2626 #if USE_WORKITEM
2627 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2628 #else
2629 phydm_tdma_dig_new(dm);
2630 #endif
2631 #else
2632 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2633 #endif
2634 }
2635
phydm_tdma_dig_workitem_callback(void * context)2636 void phydm_tdma_dig_workitem_callback(void *context)
2637 {
2638 void *adapter = (void *)context;
2639 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2640 struct dm_struct *dm = &hal_data->DM_OutSrc;
2641
2642 phydm_tdma_dig_new(dm);
2643 }
2644
2645 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_tdma_dig_cbk(void * dm_void)2646 void phydm_tdma_dig_cbk(void *dm_void)
2647 {
2648 struct dm_struct *dm = (struct dm_struct *)dm_void;
2649 void *padapter = dm->adapter;
2650
2651 if (dm->support_interface == ODM_ITRF_PCIE)
2652 phydm_tdma_dig_workitem_callback(dm);
2653 /* @Can't do I/O in timer callback*/
2654 else
2655 phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,
2656 dm);
2657 }
2658
phydm_tdma_dig_workitem_callback(void * dm_void)2659 void phydm_tdma_dig_workitem_callback(void *dm_void)
2660 {
2661 struct dm_struct *dm = (struct dm_struct *)dm_void;
2662 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2663
2664 if (phydm_dig_abort(dm) || (dm->original_dig_restore))
2665 return;
2666 /*@
2667 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2668 * dig_t->tdma_dig_state);
2669 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2670 * dig_t->cur_ig_value_tdma,
2671 * dig_t->low_ig_value);
2672 */
2673 phydm_tdma_fa_cnt_chk(dm);
2674
2675 /*@prevent dumb*/
2676 if (dm->tdma_dig_state_number < 2)
2677 dm->tdma_dig_state_number = 2;
2678
2679 /*@update state*/
2680 dig_t->tdma_dig_cnt++;
2681 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2682
2683 /*@
2684 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2685 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2686 */
2687
2688 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2689 odm_write_dig(dm, dig_t->low_ig_value);
2690 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2691 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2692
2693 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2694 }
2695 #else
phydm_tdma_dig_cbk(void * dm_void)2696 void phydm_tdma_dig_cbk(void *dm_void)
2697 {
2698 struct dm_struct *dm = (struct dm_struct *)dm_void;
2699 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2700
2701 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2702 return;
2703 /*@
2704 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2705 * dig_t->tdma_dig_state);
2706 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2707 * dig_t->cur_ig_value_tdma,
2708 * dig_t->low_ig_value);
2709 */
2710 phydm_tdma_fa_cnt_chk(dm);
2711
2712 /*@prevent dumb*/
2713 if (dm->tdma_dig_state_number < 2)
2714 dm->tdma_dig_state_number = 2;
2715
2716 /*@update state*/
2717 dig_t->tdma_dig_cnt++;
2718 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2719
2720 /*@
2721 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2722 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2723 */
2724
2725 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2726 phydm_write_tdma_dig(dm, dig_t->low_ig_value);
2727 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2728 phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma);
2729
2730 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2731 }
2732 #endif
2733 /*@============================================================*/
2734 /*@FASLE ALARM CHECK*/
2735 /*@============================================================*/
phydm_tdma_fa_cnt_chk(void * dm_void)2736 void phydm_tdma_fa_cnt_chk(void *dm_void)
2737 {
2738 struct dm_struct *dm = (struct dm_struct *)dm_void;
2739 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2740 struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
2741 struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
2742 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2743 boolean tdma_dig_block_1sec_flag = false;
2744 u32 timestamp = 0;
2745 u8 states_per_block = dm->tdma_dig_state_number;
2746 u8 cur_tdma_dig_state = 0;
2747 u32 start_th = 0;
2748 u8 state_diff = 0;
2749 u32 tdma_dig_block_period_ms = 0;
2750 u32 tdma_dig_block_cnt_thd = 0;
2751 u32 timestamp_diff = 0;
2752
2753 /*@calculate duration of a tdma block*/
2754 tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
2755
2756 /*@
2757 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
2758 *or FA will be fewer.
2759 */
2760 tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
2761
2762 /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
2763 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2764 cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
2765 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2766 cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
2767 /*@
2768 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
2769 * cur_tdma_dig_state, dig_t->tdma_dig_cnt);
2770 */
2771 if (cur_tdma_dig_state == 0) {
2772 /*@L-state indicates next block*/
2773 dig_t->tdma_dig_block_cnt++;
2774
2775 /*@1sec dump check*/
2776 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2777 tdma_dig_block_1sec_flag = true;
2778
2779 /*@
2780 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
2781 * dig_t->tdma_dig_block_cnt);
2782 */
2783
2784 /*@collect FA till this block end*/
2785 phydm_false_alarm_counter_statistics(dm);
2786 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2787 cur_tdma_dig_state);
2788 /*@1s L-FA collect end*/
2789
2790 /*@1sec dump reached*/
2791 if (tdma_dig_block_1sec_flag) {
2792 /*@L-DIG*/
2793 phydm_noisy_detection(dm);
2794 #ifdef PHYDM_SUPPORT_CCKPD
2795 phydm_cck_pd_th(dm);
2796 #endif
2797 PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
2798 phydm_tdma_low_dig(dm);
2799 PHYDM_DBG(dm, DBG_DIG, "\n\n");
2800 }
2801 } else if (cur_tdma_dig_state == 1) {
2802 /*@1sec dump check*/
2803 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2804 tdma_dig_block_1sec_flag = true;
2805
2806 /*@
2807 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
2808 * dig_t->tdma_dig_block_cnt);
2809 */
2810
2811 /*@collect FA till this block end*/
2812 phydm_false_alarm_counter_statistics(dm);
2813 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2814 cur_tdma_dig_state);
2815 /*@1s H-FA collect end*/
2816
2817 /*@1sec dump reached*/
2818 state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
2819 if (tdma_dig_block_1sec_flag && state_diff == 1) {
2820 /*@H-DIG*/
2821 phydm_noisy_detection(dm);
2822 #ifdef PHYDM_SUPPORT_CCKPD
2823 phydm_cck_pd_th(dm);
2824 #endif
2825 PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
2826 phydm_tdma_high_dig(dm);
2827 PHYDM_DBG(dm, DBG_DIG, "\n\n");
2828 PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
2829 dm->is_linked);
2830 PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
2831 fa_t_acc_low->cnt_cca_all_1sec,
2832 fa_t_acc_low->cnt_all_1sec);
2833 PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
2834 fa_t_acc->cnt_cca_all_1sec,
2835 fa_t_acc->cnt_all_1sec);
2836 PHYDM_DBG(dm, DBG_DIG,
2837 "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
2838 fa_t_acc->cnt_cca_all +
2839 fa_t_acc_low->cnt_cca_all,
2840 fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
2841
2842 /*@Reset AccFalseAlarmCounterStatistics */
2843 phydm_false_alarm_counter_acc_reset(dm);
2844 dig_t->tdma_dig_block_cnt = 0;
2845 }
2846 }
2847 /*@Reset FalseAlarmCounterStatistics */
2848 phydm_false_alarm_counter_reset(dm);
2849 }
2850
phydm_tdma_low_dig(void * dm_void)2851 void phydm_tdma_low_dig(void *dm_void)
2852 {
2853 struct dm_struct *dm = (struct dm_struct *)dm_void;
2854 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2855 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2856 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
2857 #ifdef CFG_DIG_DAMPING_CHK
2858 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
2859 #endif
2860 u8 igi = dig_t->cur_ig_value;
2861 u8 new_igi = 0x20;
2862 u8 tdma_l_igi = dig_t->low_ig_value;
2863 u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
2864 u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
2865 u32 fa_cnt = falm_cnt->cnt_all;
2866 boolean dfs_mode_en = false, is_performance = true;
2867 u8 rssi_min = dm->rssi_min;
2868 u8 igi_upper_rssi_min = 0;
2869 u8 offset = 15;
2870
2871 if (!(dm->original_dig_restore)) {
2872 if (tdma_l_igi == 0)
2873 tdma_l_igi = igi;
2874
2875 fa_cnt = falm_cnt_acc->cnt_all_1sec;
2876 }
2877
2878 if (phydm_dig_abort(dm)) {
2879 dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
2880 return;
2881 }
2882
2883 /*@Mode Decision*/
2884 dfs_mode_en = false;
2885 is_performance = true;
2886
2887 /* @Abs Boundary Decision*/
2888 dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
2889 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
2890 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
2891
2892 if (dm->is_dfs_band) {
2893 if (*dm->band_width == CHANNEL_WIDTH_20){
2894 if (dm->support_ic_type &
2895 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
2896 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
2897 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
2898 else
2899 dig_t->dm_dig_min = DIG_MIN_DFS;
2900 }
2901 else
2902 dig_t->dm_dig_min = DIG_MIN_DFS;
2903 }
2904 else
2905 dig_t->dm_dig_min = DIG_MIN_DFS;
2906
2907 } else {
2908 #if 0
2909 if (dm->support_ic_type &
2910 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
2911 dig_t->dm_dig_min = 0x1c;
2912 else if (dm->support_ic_type & ODM_RTL8197F)
2913 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
2914 #endif
2915 }
2916
2917 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
2918 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
2919
2920 /* @Dyn Boundary by RSSI*/
2921 if (!dm->is_linked) {
2922 /*@if no link, always stay at lower bound*/
2923 tdma_l_dym_max = 0x26;
2924 tdma_l_dym_min = dig_t->dm_dig_min;
2925
2926 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
2927 tdma_l_dym_max, tdma_l_dym_min);
2928 } else {
2929 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
2930 dm->rssi_min, offset);
2931
2932 /* @DIG lower bound in L-state*/
2933 tdma_l_dym_min = dig_t->dm_dig_min;
2934 if (dm->is_dfs_band)
2935 tdma_l_dym_min = DIG_MIN_DFS;
2936 /*@
2937 *#ifdef CFG_DIG_DAMPING_CHK
2938 *@Limit Dyn min by damping
2939 *if (dig_t->dig_dl_en &&
2940 * dig_rc->damping_limit_en &&
2941 * tdma_l_dym_min < dig_rc->damping_limit_val) {
2942 * PHYDM_DBG(dm, DBG_DIG,
2943 * "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
2944 * tdma_l_dym_min, dig_rc->damping_limit_val);
2945 *
2946 * tdma_l_dym_min = dig_rc->damping_limit_val;
2947 *}
2948 *#endif
2949 */
2950
2951 /*@DIG upper bound in L-state*/
2952 igi_upper_rssi_min = rssi_min + offset;
2953 if (igi_upper_rssi_min > dig_t->dm_dig_max)
2954 tdma_l_dym_max = dig_t->dm_dig_max;
2955 else if (igi_upper_rssi_min < dig_t->dm_dig_min)
2956 tdma_l_dym_max = dig_t->dm_dig_min;
2957 else
2958 tdma_l_dym_max = igi_upper_rssi_min;
2959
2960 /* @1 Force Lower Bound for AntDiv */
2961 /*@
2962 *if (!dm->is_one_entry_only &&
2963 *(dm->support_ability & ODM_BB_ANT_DIV) &&
2964 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
2965 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
2966 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
2967 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
2968 *else
2969 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
2970 *
2971 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
2972 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
2973 *}
2974 */
2975
2976 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
2977 tdma_l_dym_max, tdma_l_dym_min);
2978 }
2979
2980 /*@Abnormal Case Check*/
2981 /*@Abnormal lower bound case*/
2982 if (tdma_l_dym_min > tdma_l_dym_max)
2983 tdma_l_dym_min = tdma_l_dym_max;
2984
2985 PHYDM_DBG(dm, DBG_DIG,
2986 "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
2987 tdma_l_dym_max, tdma_l_dym_min);
2988
2989 /*@False Alarm Threshold Decision*/
2990 phydm_fa_threshold_check(dm, dfs_mode_en);
2991
2992 /*@Adjust Initial Gain by False Alarm*/
2993 /*Select new IGI by FA */
2994 if (!(dm->original_dig_restore)) {
2995 tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
2996 &tdma_l_dym_max,
2997 &tdma_l_dym_min,
2998 dfs_mode_en);
2999 } else {
3000 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3001 }
3002
3003 /*Update status*/
3004 if (!(dm->original_dig_restore)) {
3005 if (dig_t->tdma_force_l_igi == 0xff)
3006 dig_t->low_ig_value = tdma_l_igi;
3007 else
3008 dig_t->low_ig_value = dig_t->tdma_force_l_igi;
3009 dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
3010 dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
3011 #if 0
3012 /*odm_write_dig(dm, tdma_l_igi);*/
3013 #endif
3014 } else {
3015 odm_write_dig(dm, new_igi);
3016 }
3017 }
3018
phydm_tdma_high_dig(void * dm_void)3019 void phydm_tdma_high_dig(void *dm_void)
3020 {
3021 struct dm_struct *dm = (struct dm_struct *)dm_void;
3022 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3023 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3024 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
3025 #ifdef CFG_DIG_DAMPING_CHK
3026 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
3027 #endif
3028 u8 igi = dig_t->cur_ig_value;
3029 u8 new_igi = 0x20;
3030 u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
3031 u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
3032 u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
3033 u32 fa_cnt = falm_cnt->cnt_all;
3034 boolean dfs_mode_en = false, is_performance = true;
3035 u8 rssi_min = dm->rssi_min;
3036 u8 igi_upper_rssi_min = 0;
3037 u8 offset = 15;
3038
3039 if (!(dm->original_dig_restore)) {
3040 if (tdma_h_igi == 0)
3041 tdma_h_igi = igi;
3042
3043 fa_cnt = falm_cnt_acc->cnt_all_1sec;
3044 }
3045
3046 if (phydm_dig_abort(dm)) {
3047 dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
3048 return;
3049 }
3050
3051 /*@Mode Decision*/
3052 dfs_mode_en = false;
3053 is_performance = true;
3054
3055 /*@Abs Boundary Decision*/
3056 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
3057
3058 if (!dm->is_linked) {
3059 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
3060 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
3061 } else if (dm->is_dfs_band) {
3062 if (*dm->band_width == CHANNEL_WIDTH_20){
3063 if (dm->support_ic_type &
3064 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
3065 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
3066 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
3067 else
3068 dig_t->dm_dig_min = DIG_MIN_DFS;
3069 }
3070 else
3071 dig_t->dm_dig_min = DIG_MIN_DFS;
3072 }
3073 else
3074 dig_t->dm_dig_min = DIG_MIN_DFS;
3075
3076 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3077 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3078 } else {
3079 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
3080 /*service > 2 devices*/
3081 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3082 #if (DIG_HW == 1)
3083 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
3084 #else
3085 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3086 #endif
3087 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
3088 /*service 1 devices*/
3089 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
3090 #if (RTL8822B_SUPPORT == 1)
3091 if (dm->is_dig_low_bond)
3092 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE_22B;
3093 else
3094 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3095 #else
3096 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3097 #endif
3098 }
3099
3100 #if 0
3101 if (dm->support_ic_type &
3102 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
3103 dig_t->dm_dig_min = 0x1c;
3104 else if (dm->support_ic_type & ODM_RTL8197F)
3105 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
3106 else
3107 #endif
3108 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
3109 }
3110 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
3111 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
3112
3113 /*@Dyn Boundary by RSSI*/
3114 if (!dm->is_linked) {
3115 /*@if no link, always stay at lower bound*/
3116 tdma_h_dym_max = dig_t->dig_max_of_min;
3117 tdma_h_dym_min = dig_t->dm_dig_min;
3118
3119 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
3120 tdma_h_dym_max, tdma_h_dym_min);
3121 } else {
3122 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
3123 dm->rssi_min, offset);
3124
3125 /* @DIG lower bound in H-state*/
3126 if (dm->is_dfs_band)
3127 tdma_h_dym_min = DIG_MIN_DFS;
3128 else if (rssi_min < dig_t->dm_dig_min)
3129 tdma_h_dym_min = dig_t->dm_dig_min;
3130 else
3131 tdma_h_dym_min = rssi_min; // turbo not considered yet
3132
3133 #ifdef CFG_DIG_DAMPING_CHK
3134 /*@Limit Dyn min by damping*/
3135 if (dig_t->dig_dl_en &&
3136 dig_rc->damping_limit_en &&
3137 tdma_h_dym_min < dig_rc->damping_limit_val) {
3138 PHYDM_DBG(dm, DBG_DIG,
3139 "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
3140 tdma_h_dym_min, dig_rc->damping_limit_val);
3141
3142 tdma_h_dym_min = dig_rc->damping_limit_val;
3143 }
3144 #endif
3145
3146 /*@DIG upper bound in H-state*/
3147 igi_upper_rssi_min = rssi_min + offset;
3148 if (igi_upper_rssi_min > dig_t->dm_dig_max)
3149 tdma_h_dym_max = dig_t->dm_dig_max;
3150 else
3151 tdma_h_dym_max = igi_upper_rssi_min;
3152
3153 /* @1 Force Lower Bound for AntDiv */
3154 /*@
3155 *if (!dm->is_one_entry_only &&
3156 *(dm->support_ability & ODM_BB_ANT_DIV) &&
3157 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
3158 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
3159 * if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
3160 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
3161 * else
3162 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
3163 */
3164 /*@
3165 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
3166 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
3167 *}
3168 */
3169 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
3170 tdma_h_dym_max, tdma_h_dym_min);
3171 }
3172
3173 /*@Abnormal Case Check*/
3174 /*@Abnormal low higher bound case*/
3175 if (tdma_h_dym_max < dig_t->dm_dig_min)
3176 tdma_h_dym_max = dig_t->dm_dig_min;
3177 /*@Abnormal lower bound case*/
3178 if (tdma_h_dym_min > tdma_h_dym_max)
3179 tdma_h_dym_min = tdma_h_dym_max;
3180
3181 PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
3182 tdma_h_dym_max, tdma_h_dym_min);
3183
3184 /*@False Alarm Threshold Decision*/
3185 phydm_fa_threshold_check(dm, dfs_mode_en);
3186
3187 /*@Adjust Initial Gain by False Alarm*/
3188 /*Select new IGI by FA */
3189 if (!(dm->original_dig_restore)) {
3190 tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
3191 &tdma_h_dym_max,
3192 &tdma_h_dym_min,
3193 dfs_mode_en);
3194 } else {
3195 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3196 }
3197
3198 /*Update status*/
3199 if (!(dm->original_dig_restore)) {
3200 if (dig_t->tdma_force_h_igi == 0xff)
3201 dig_t->cur_ig_value_tdma = tdma_h_igi;
3202 else
3203 dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi;
3204 dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
3205 dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
3206 #if 0
3207 /*odm_write_dig(dm, tdma_h_igi);*/
3208 #endif
3209 } else {
3210 odm_write_dig(dm, new_igi);
3211 }
3212 }
3213
phydm_fa_cnt_acc(void * dm_void,boolean tdma_dig_block_1sec_flag,u8 cur_tdma_dig_state)3214 void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
3215 u8 cur_tdma_dig_state)
3216 {
3217 struct dm_struct *dm = (struct dm_struct *)dm_void;
3218 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3219 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
3220 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3221 u8 factor_num = 0;
3222 u8 factor_denum = 1;
3223 u8 total_state_number = 0;
3224
3225 if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
3226 falm_cnt_acc = &dm->false_alm_cnt_acc_low;
3227 else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
3228
3229 falm_cnt_acc = &dm->false_alm_cnt_acc;
3230 /*@
3231 *PHYDM_DBG(dm, DBG_DIG,
3232 * "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
3233 * cur_tdma_dig_state, tdma_dig_block_1sec_flag);
3234 */
3235 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
3236 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
3237 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
3238 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
3239 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
3240 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
3241 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
3242 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
3243 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
3244 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
3245 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
3246 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
3247 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
3248 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
3249 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
3250 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
3251 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
3252 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
3253 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
3254 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
3255 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
3256 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
3257
3258 /*@
3259 *PHYDM_DBG(dm, DBG_DIG,
3260 * "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3261 * falm_cnt->cnt_cck_cca,
3262 * falm_cnt->cnt_ofdm_cca,
3263 * falm_cnt->cnt_cca_all);
3264 *PHYDM_DBG(dm, DBG_DIG,
3265 * "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3266 * falm_cnt->cnt_cck_fail,
3267 * falm_cnt->cnt_ofdm_fail,
3268 * falm_cnt->cnt_all);
3269 */
3270 if (tdma_dig_block_1sec_flag) {
3271 total_state_number = dm->tdma_dig_state_number;
3272
3273 if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
3274 factor_num = total_state_number;
3275 factor_denum = total_state_number - 1;
3276 } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
3277 factor_num = total_state_number;
3278 factor_denum = 1;
3279 }
3280
3281 falm_cnt_acc->cnt_all_1sec =
3282 falm_cnt_acc->cnt_all * factor_num / factor_denum;
3283 falm_cnt_acc->cnt_cca_all_1sec =
3284 falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
3285 falm_cnt_acc->cnt_cck_fail_1sec =
3286 falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
3287
3288 PHYDM_DBG(dm, DBG_DIG,
3289 "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3290 falm_cnt_acc->cnt_cck_cca,
3291 falm_cnt_acc->cnt_ofdm_cca,
3292 falm_cnt_acc->cnt_cca_all);
3293 PHYDM_DBG(dm, DBG_DIG,
3294 "[ACC FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
3295 falm_cnt_acc->cnt_cck_fail,
3296 falm_cnt_acc->cnt_ofdm_fail,
3297 falm_cnt_acc->cnt_all);
3298
3299 }
3300 }
3301 #endif /*@#ifdef IS_USE_NEW_TDMA*/
3302 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
3303
phydm_dig_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3304 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
3305 u32 *_out_len)
3306 {
3307 struct dm_struct *dm = (struct dm_struct *)dm_void;
3308 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3309 char help[] = "-h";
3310 u32 var1[10] = {0};
3311 u32 used = *_used;
3312 u32 out_len = *_out_len;
3313 u8 i = 0;
3314
3315 if ((strcmp(input[1], help) == 0)) {
3316 PDM_SNPF(out_len, used, output + used, out_len - used,
3317 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
3318 PDM_SNPF(out_len, used, output + used, out_len - used,
3319 "{1} {Damping Limit en}\n");
3320 #ifdef PHYDM_TDMA_DIG_SUPPORT
3321 PDM_SNPF(out_len, used, output + used, out_len - used,
3322 "{2} {original_dig_restore = %d}\n",
3323 dm->original_dig_restore);
3324 PDM_SNPF(out_len, used, output + used, out_len - used,
3325 "{3} {tdma_dig_timer_ms = %d}\n",
3326 dm->tdma_dig_timer_ms);
3327 PDM_SNPF(out_len, used, output + used, out_len - used,
3328 "{4} {tdma_dig_state_number = %d}\n",
3329 dm->tdma_dig_state_number);
3330 PDM_SNPF(out_len, used, output + used, out_len - used,
3331 "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n",
3332 dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi);
3333 #endif
3334 PDM_SNPF(out_len, used, output + used, out_len - used,
3335 "{6} {fw_dig_en}\n");
3336 } else {
3337 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
3338
3339 for (i = 1; i < 10; i++)
3340 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
3341
3342 if (var1[0] == 0) {
3343 if (var1[1] == 1) {
3344 dig_t->is_dbg_fa_th = true;
3345 dig_t->fa_th[0] = (u16)var1[2];
3346 dig_t->fa_th[1] = (u16)var1[3];
3347 dig_t->fa_th[2] = (u16)var1[4];
3348
3349 PDM_SNPF(out_len, used, output + used,
3350 out_len - used,
3351 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
3352 dig_t->fa_th[0], dig_t->fa_th[1],
3353 dig_t->fa_th[2]);
3354 } else {
3355 dig_t->is_dbg_fa_th = false;
3356 }
3357 #ifdef PHYDM_TDMA_DIG_SUPPORT
3358 } else if (var1[0] == 2) {
3359 dm->original_dig_restore = (u8)var1[1];
3360 if (dm->original_dig_restore == 1) {
3361 PDM_SNPF(out_len, used, output + used,
3362 out_len - used, "Disable TDMA-DIG\n");
3363 } else {
3364 PDM_SNPF(out_len, used, output + used,
3365 out_len - used, "Enable TDMA-DIG\n");
3366 }
3367 } else if (var1[0] == 3) {
3368 dm->tdma_dig_timer_ms = (u8)var1[1];
3369 PDM_SNPF(out_len, used, output + used,
3370 out_len - used, "tdma_dig_timer_ms = %d\n",
3371 dm->tdma_dig_timer_ms);
3372 } else if (var1[0] == 4) {
3373 dm->tdma_dig_state_number = (u8)var1[1];
3374 PDM_SNPF(out_len, used, output + used,
3375 out_len - used, "tdma_dig_state_number = %d\n",
3376 dm->tdma_dig_state_number);
3377 } else if (var1[0] == 5) {
3378 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
3379 if (var1[1] == 0) {
3380 dig_t->tdma_force_l_igi = (u8)var1[2];
3381 PDM_SNPF(out_len, used, output + used,
3382 out_len - used,
3383 "force L-state IGI = %2x\n",
3384 dig_t->tdma_force_l_igi);
3385 } else if (var1[1] == 1) {
3386 dig_t->tdma_force_h_igi = (u8)var1[2];
3387 PDM_SNPF(out_len, used, output + used,
3388 out_len - used,
3389 "force H-state IGI = %2x\n",
3390 dig_t->tdma_force_h_igi);
3391 }
3392 #endif
3393 }
3394
3395 #ifdef CFG_DIG_DAMPING_CHK
3396 else if (var1[0] == 1) {
3397 dig_t->dig_dl_en = (u8)var1[1];
3398 /*@*/
3399 }
3400 #endif
3401 else if (var1[0] == 6) {
3402 phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]);
3403 PDM_SNPF(out_len, used, output + used, out_len - used,
3404 "fw_dig_enable = %2x\n", dig_t->fw_dig_enable);
3405 }
3406 }
3407 *_used = used;
3408 *_out_len = out_len;
3409 }
3410
3411 #ifdef CONFIG_MCC_DM
3412 #if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
phydm_mcc_igi_clr(void * dm_void,u8 clr_port)3413 void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
3414 {
3415 struct dm_struct *dm = (struct dm_struct *)dm_void;
3416 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3417
3418 mcc_dm->mcc_rssi[clr_port] = 0xff;
3419 mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
3420 mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
3421 }
3422
phydm_mcc_igi_chk(void * dm_void)3423 void phydm_mcc_igi_chk(void *dm_void)
3424 {
3425 struct dm_struct *dm = (struct dm_struct *)dm_void;
3426 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3427
3428 if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
3429 mcc_dm->mcc_dm_val[0][1] == 0xff) {
3430 mcc_dm->mcc_dm_reg[0] = 0xffff;
3431 mcc_dm->mcc_reg_id[0] = 0xff;
3432 }
3433 if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
3434 mcc_dm->mcc_dm_val[1][1] == 0xff) {
3435 mcc_dm->mcc_dm_reg[1] = 0xffff;
3436 mcc_dm->mcc_reg_id[1] = 0xff;
3437 }
3438 }
3439
phydm_mcc_igi_cal(void * dm_void)3440 void phydm_mcc_igi_cal(void *dm_void)
3441 {
3442 struct dm_struct *dm = (struct dm_struct *)dm_void;
3443 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3444 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3445 u8 shift = 0;
3446 u8 igi_val0, igi_val1;
3447
3448 if (mcc_dm->mcc_rssi[0] == 0xff)
3449 phydm_mcc_igi_clr(dm, 0);
3450 if (mcc_dm->mcc_rssi[1] == 0xff)
3451 phydm_mcc_igi_clr(dm, 1);
3452 phydm_mcc_igi_chk(dm);
3453 igi_val0 = mcc_dm->mcc_rssi[0] - shift;
3454 igi_val1 = mcc_dm->mcc_rssi[1] - shift;
3455
3456 if (igi_val0 < DIG_MIN_PERFORMANCE)
3457 igi_val0 = DIG_MIN_PERFORMANCE;
3458
3459 if (igi_val1 < DIG_MIN_PERFORMANCE)
3460 igi_val1 = DIG_MIN_PERFORMANCE;
3461
3462 switch (dm->ic_ip_series) {
3463 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
3464 case PHYDM_IC_JGR3:
3465 phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
3466 phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
3467 break;
3468 #endif
3469 default:
3470 phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);
3471 phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);
3472 break;
3473 }
3474
3475 PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
3476 mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
3477 mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
3478 }
3479 #endif /*#if (RTL8822B_SUPPORT)*/
3480 #endif /*#ifdef CONFIG_MCC_DM*/
3481