1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDM_CCK_PD_H__ 27 #define __PHYDM_CCK_PD_H__ 28 29 /* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/ 30 #define CCK_PD_VERSION "4.0" 31 32 /*@ 33 * 1 ============================================================ 34 * 1 Definition 35 * 1 ============================================================ 36 */ 37 #define CCK_FA_MA_RESET 0xffffffff 38 39 #define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/ 40 #define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/ 41 #define MAXVALID_CS_RATIO 0x1f 42 /*@Run time flag of CCK_PD HW type*/ 43 #define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\ 44 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\ 45 ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\ 46 ODM_RTL8195A | ODM_RTL8188F) 47 48 #define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\ 49 ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/ 50 51 #define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C) 52 /*@extend for different bw & path*/ 53 54 #define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/ 55 56 /*@Compile time flag of CCK_PD HW type*/ 57 #if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\ 58 RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\ 59 RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\ 60 RTL8195A_SUPPORT || RTL8188F_SUPPORT) 61 #define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/ 62 #endif 63 64 #if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\ 65 RTL8710B_SUPPORT || RTL8195B_SUPPORT) 66 #define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/ 67 #endif 68 69 #if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 70 #define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/ 71 #endif 72 73 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 74 #define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/ 75 #endif 76 /*@ 77 * 1 ============================================================ 78 * 1 enumeration 79 * 1 ============================================================ 80 */ 81 enum cckpd_lv { 82 CCK_PD_LV_INIT = 0xff, 83 CCK_PD_LV_0 = 0, 84 CCK_PD_LV_1 = 1, 85 CCK_PD_LV_2 = 2, 86 CCK_PD_LV_3 = 3, 87 CCK_PD_LV_4 = 4, 88 CCK_PD_LV_MAX = 5 89 }; 90 91 enum cckpd_mode { 92 CCK_BW20_1R = 0, 93 CCK_BW20_2R = 1, 94 CCK_BW20_3R = 2, 95 CCK_BW20_4R = 3, 96 CCK_BW40_1R = 4, 97 CCK_BW40_2R = 5, 98 CCK_BW40_3R = 6, 99 CCK_BW40_4R = 7 100 }; 101 102 enum dcc_mode { 103 DCC_DIG = 0, 104 DCC_CCK_PD = 1 105 }; 106 107 enum phydm_cck_pd_trend { 108 CCKPD_STABLE = 0, 109 CCKPD_INCREASING = 1, 110 CCKPD_DECREASING = 2 111 }; 112 113 /*@ 114 * 1 ============================================================ 115 * 1 structure 116 * 1 ============================================================ 117 */ 118 119 #ifdef PHYDM_SUPPORT_CCKPD 120 121 #ifdef PHYDM_DCC_ENHANCE 122 struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/ 123 boolean dcc_en; 124 enum dcc_mode dcc_mode; 125 u32 dig_execute_cnt; 126 u8 dcc_ratio; 127 }; 128 #endif 129 130 struct phydm_cckpd_struct { 131 u8 cckpd_hw_type; 132 u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/ 133 u32 cck_fa_ma; 134 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 135 u8 pause_lv; 136 u8 cck_n_rx; 137 u16 cck_fa_th[2]; 138 enum channel_width cck_bw; 139 enum cckpd_lv cck_pd_lv; 140 #ifdef PHYDM_COMPILE_CCKPD_TYPE2 141 u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/ 142 u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/ 143 #endif 144 #ifdef PHYDM_COMPILE_CCKPD_TYPE3 145 /*Default value*/ 146 u8 cck_pd_20m_1r; 147 u8 cck_pd_20m_2r; 148 u8 cck_pd_40m_1r; 149 u8 cck_pd_40m_2r; 150 u8 cck_cs_ratio_20m_1r; 151 u8 cck_cs_ratio_20m_2r; 152 u8 cck_cs_ratio_40m_1r; 153 u8 cck_cs_ratio_40m_2r; 154 /*Current value*/ 155 u8 cur_cck_pd_20m_1r; 156 u8 cur_cck_pd_20m_2r; 157 u8 cur_cck_pd_40m_1r; 158 u8 cur_cck_pd_40m_2r; 159 u8 cur_cck_cs_ratio_20m_1r; 160 u8 cur_cck_cs_ratio_20m_2r; 161 u8 cur_cck_cs_ratio_40m_1r; 162 u8 cur_cck_cs_ratio_40m_2r; 163 #endif 164 #ifdef PHYDM_COMPILE_CCKPD_TYPE4 165 /*@[bw][nrx][0:PD/1:CS][lv]*/ 166 u8 cckpd_jgr3[2][4][2][CCK_PD_LV_MAX]; 167 #endif 168 }; 169 #endif 170 171 /*@ 172 * 1 ============================================================ 173 * 1 function prototype 174 * 1 ============================================================ 175 */ 176 void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len); 177 178 void phydm_cck_pd_th(void *dm_void); 179 180 void phydm_cck_pd_init(void *dm_void); 181 182 #ifdef PHYDM_DCC_ENHANCE 183 void phydm_cckpd_type4_dcc(void *dm_void); 184 185 void phydm_dig_cckpd_coex(void *dm_void); 186 187 void phydm_dig_cckpd_coex_init(void *dm_void); 188 189 void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used, 190 char *output, u32 *_out_len); 191 #endif 192 #endif 193