1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMANTDIV_H__ 27 #define __PHYDMANTDIV_H__ 28 29 /*@#define ANTDIV_VERSION "2.0" //2014.11.04*/ 30 /*@#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ 31 /*@#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ 32 /*@#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen,remove 92c 92d 8723a*/ 33 /*@#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna*/ 34 /*@diversity when BT is enable for 8723B*/ 35 /*@#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not*/ 36 /*@need to check the antenna is control by BT,*/ 37 /*@because antenna diversity only works when */ 38 /*@BT is disable or radio off*/ 39 /*@#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart */ 40 /*@Antenna 2. Add 8188F SW S0S1 Antenna*/ 41 /*@Diversity*/ 42 /*@#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna*/ 43 /*@detection result from BT-coex. for 8723B,*/ 44 /*@not from PHYDM*/ 45 /*@#define ANTDIV_VERSION "3.6"*/ /*@2015.11.16 Stanley */ 46 /*@#define ANTDIV_VERSION "3.7" 2015.11.20 Dino Add SmartAnt FAT Patch */ 47 /*@#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic*/ 48 /*@training packet num */ 49 /*@#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for*/ 50 /*@converting single & two smtant, and add cmd*/ 51 /*@for adjust truth table */ 52 #define ANTDIV_VERSION "4.0" /*@2017.05.25 Mark, Add SW antenna diversity*/ 53 /*@for 8821c because HW transient issue */ 54 55 /* @1 ============================================================ 56 * 1 Definition 57 * 1 ============================================================ 58 */ 59 60 #define ANTDIV_INIT 0xff 61 #define MAIN_ANT 1 /*@ant A or ant Main or S1*/ 62 #define AUX_ANT 2 /*@AntB or ant Aux or S0*/ 63 #define MAX_ANT 3 /* @3 for AP using*/ 64 65 #define ANT1_2G 0 66 /* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ 67 #define ANT2_2G 1 68 /* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ 69 /*smart antenna*/ 70 #define SUPPORT_RF_PATH_NUM 4 71 #define SUPPORT_BEAM_PATTERN_NUM 4 72 #define NUM_ANTENNA_8821A 2 73 74 #define SUPPORT_BEAM_SET_PATTERN_NUM 16 75 76 #define NO_FIX_TX_ANT 0 77 #define FIX_TX_AT_MAIN 1 78 #define FIX_AUX_AT_MAIN 2 79 80 /* @Antenna Diversty Control type */ 81 #define ODM_AUTO_ANT 0 82 #define ODM_FIX_MAIN_ANT 1 83 #define ODM_FIX_AUX_ANT 2 84 85 #define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\ 86 ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\ 87 ODM_RTL8197F | ODM_RTL8721D) 88 #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\ 89 ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B) 90 #define ODM_JGR3_ANTDIV_SUPPORT ODM_RTL8197G 91 #define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\ 92 ODM_JGR3_ANTDIV_SUPPORT) 93 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) 94 #define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) 95 96 #define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\ 97 ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\ 98 ODM_RTL8197F | ODM_RTL8197G) 99 #define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\ 100 ODM_RTL8821C | ODM_RTL8822B) 101 102 #define ODM_ANTDIV_SUPPORT_IC (ODM_ANTDIV_2G_SUPPORT_IC | ODM_ANTDIV_5G_SUPPORT_IC) 103 104 #define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\ 105 ODM_RTL8197G) 106 107 #define ODM_ANTDIV_2G BIT(0) 108 #define ODM_ANTDIV_5G BIT(1) 109 110 #define ANTDIV_ON 1 111 #define ANTDIV_OFF 0 112 113 #define ANT_PATH_A 0 114 #define ANT_PATH_B 1 115 #define ANT_PATH_AB 2 116 117 #define FAT_ON 1 118 #define FAT_OFF 0 119 120 #define TX_BY_DESC 1 121 #define TX_BY_REG 0 122 123 #define RSSI_METHOD 0 124 #define EVM_METHOD 1 125 #define CRC32_METHOD 2 126 #define TP_METHOD 3 127 128 #define INIT_ANTDIV_TIMMER 0 129 #define CANCEL_ANTDIV_TIMMER 1 130 #define RELEASE_ANTDIV_TIMMER 2 131 132 #define CRC32_FAIL 1 133 #define CRC32_OK 0 134 135 #define evm_rssi_th_high 25 136 #define evm_rssi_th_low 20 137 138 #define NORMAL_STATE_MIAN 1 139 #define NORMAL_STATE_AUX 2 140 #define TRAINING_STATE 3 141 142 #define FORCE_RSSI_DIFF 10 143 144 #define HT_IDX 16 145 #define VHT_IDX 20 146 147 #define CSI_ON 1 148 #define CSI_OFF 0 149 150 #define DIVON_CSIOFF 1 151 #define DIVOFF_CSION 2 152 153 #define BDC_DIV_TRAIN_STATE 0 154 #define bdc_bfer_train_state 1 155 #define BDC_DECISION_STATE 2 156 #define BDC_BF_HOLD_STATE 3 157 #define BDC_DIV_HOLD_STATE 4 158 159 #define BDC_MODE_1 1 160 #define BDC_MODE_2 2 161 #define BDC_MODE_3 3 162 #define BDC_MODE_4 4 163 #define BDC_MODE_NULL 0xff 164 165 /*SW S0S1 antenna diversity*/ 166 #define SWAW_STEP_INIT 0xff 167 #define SWAW_STEP_PEEK 0 168 #define SWAW_STEP_DETERMINE 1 169 170 #define RSSI_CHECK_RESET_PERIOD 10 171 #define RSSI_CHECK_THRESHOLD 50 172 173 /*@Hong Lin Smart antenna*/ 174 #define HL_SMTANT_2WIRE_DATA_LEN 24 175 176 #if (RTL8723D_SUPPORT == 1) 177 #ifndef CONFIG_ANTDIV_PERIOD 178 #define CONFIG_ANTDIV_PERIOD 1 179 #endif 180 #endif 181 /* @1 ============================================================ 182 * 1 structure 183 * 1 ============================================================ 184 */ 185 186 187 struct sw_antenna_switch { 188 u8 double_chk_flag; 189 /*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/ 190 /*@check this antenna again*/ 191 u8 try_flag; 192 s32 pre_rssi; 193 u8 cur_antenna; 194 u8 pre_ant; 195 u8 rssi_trying; 196 u8 reset_idx; 197 u8 train_time; 198 u8 train_time_flag; 199 /*@base on RSSI difference between two antennas*/ 200 struct phydm_timer_list sw_antdiv_timer; 201 u32 pkt_cnt_sw_ant_div_by_ctrl_frame; 202 boolean is_sw_ant_div_by_ctrl_frame; 203 204 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 205 #if USE_WORKITEM 206 RT_WORK_ITEM phydm_sw_antenna_switch_workitem; 207 #endif 208 #endif 209 210 /* @AntDect (Before link Antenna Switch check) need to be moved*/ 211 u16 single_ant_counter; 212 u16 dual_ant_counter; 213 u16 aux_fail_detec_counter; 214 u16 retry_counter; 215 u8 swas_no_link_state; 216 u32 swas_no_link_bk_reg948; 217 boolean ANTA_ON; /*To indicate ant A is or not*/ 218 boolean ANTB_ON; /*@To indicate ant B is on or not*/ 219 boolean pre_aux_fail_detec; 220 boolean rssi_ant_dect_result; 221 u8 ant_5g; 222 u8 ant_2g; 223 }; 224 225 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 226 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 227 struct _BF_DIV_COEX_ { 228 boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM]; 229 boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM]; 230 u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; 231 u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; 232 233 u8 bd_ccoex_type_wbfer; 234 u8 num_txbfee_client; 235 u8 num_txbfer_client; 236 u8 bdc_try_counter; 237 u8 bdc_hold_counter; 238 u8 bdc_mode; 239 u8 bdc_active_mode; 240 u8 BDC_state; 241 u8 bdc_rx_idle_update_counter; 242 u8 num_client; 243 u8 pre_num_client; 244 u8 num_bf_tar; 245 u8 num_div_tar; 246 247 boolean is_all_div_sta_idle; 248 boolean is_all_bf_sta_idle; 249 boolean bdc_try_flag; 250 boolean BF_pass; 251 boolean DIV_pass; 252 }; 253 #endif 254 #endif 255 256 struct phydm_fat_struct { 257 u8 bssid[6]; 258 u8 antsel_rx_keep_0; 259 u8 antsel_rx_keep_1; 260 u8 antsel_rx_keep_2; 261 u8 antsel_rx_keep_3; 262 u32 ant_sum_rssi[7]; 263 u32 ant_rssi_cnt[7]; 264 u32 ant_ave_rssi[7]; 265 u8 fat_state; 266 u8 fat_state_cnt; 267 u32 train_idx; 268 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 269 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 270 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 271 u16 main_ht_cnt[HT_IDX]; 272 u16 aux_ht_cnt[HT_IDX]; 273 u16 main_vht_cnt[VHT_IDX]; 274 u16 aux_vht_cnt[VHT_IDX]; 275 u16 main_sum[ODM_ASSOCIATE_ENTRY_NUM]; 276 u16 aux_sum[ODM_ASSOCIATE_ENTRY_NUM]; 277 u16 main_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 278 u16 aux_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 279 u16 main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; 280 u16 aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; 281 u16 main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; 282 u16 aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; 283 u8 rx_idle_ant; 284 u8 rx_idle_ant2; 285 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 286 u8 ant_div_on_off; 287 u8 div_path_type; 288 boolean is_become_linked; 289 boolean get_stats; 290 u32 min_max_rssi; 291 u8 idx_ant_div_counter_2g; 292 u8 idx_ant_div_counter_5g; 293 u8 ant_div_2g_5g; 294 295 #ifdef ODM_EVM_ENHANCE_ANTDIV 296 /*@For 1SS RX phy rate*/ 297 u32 main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; 298 u32 aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; 299 u32 main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 300 u32 aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 301 302 /*@For 2SS RX phy rate*/ 303 u32 main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/ 304 u32 aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/ 305 u32 main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 306 u32 aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 307 308 boolean evm_method_enable; 309 u8 target_ant_evm; 310 u8 target_ant_crc32; 311 u8 target_ant_tp; 312 u8 target_ant_enhance; 313 u8 pre_target_ant_enhance; 314 u16 main_mpdu_ok_cnt; 315 u16 aux_mpdu_ok_cnt; 316 317 u32 crc32_ok_cnt; 318 u32 crc32_fail_cnt; 319 u32 main_crc32_ok_cnt; 320 u32 aux_crc32_ok_cnt; 321 u32 main_crc32_fail_cnt; 322 u32 aux_crc32_fail_cnt; 323 324 u32 main_tp; 325 u32 aux_tp; 326 u32 main_tp_cnt; 327 u32 aux_tp_cnt; 328 329 u8 pre_antdiv_rssi; 330 u8 pre_antdiv_tp; 331 #endif 332 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 333 u32 cck_ctrl_frame_cnt_main; 334 u32 cck_ctrl_frame_cnt_aux; 335 u32 ofdm_ctrl_frame_cnt_main; 336 u32 ofdm_ctrl_frame_cnt_aux; 337 u32 main_ctrl_sum; 338 u32 aux_ctrl_sum; 339 u32 main_ctrl_cnt; 340 u32 aux_ctrl_cnt; 341 #endif 342 u8 b_fix_tx_ant; 343 boolean fix_ant_bfee; 344 boolean enable_ctrl_frame_antdiv; 345 boolean use_ctrl_frame_antdiv; 346 boolean *is_no_csi_feedback; 347 boolean force_antdiv_type; 348 u8 antdiv_type_dbg; 349 u8 hw_antsw_occur; 350 u8 *p_force_tx_by_desc; 351 u8 force_tx_by_desc; 352 /*@A temp value, will hook to driver team's outer parameter later*/ 353 u8 *p_default_s0_s1; 354 u8 default_s0_s1; 355 }; 356 357 /* @1 ============================================================ 358 * 1 enumeration 359 * 1 ============================================================ 360 */ 361 362 enum fat_state /*@Fast antenna training*/ 363 { 364 FAT_BEFORE_LINK_STATE = 0, 365 FAT_PREPARE_STATE = 1, 366 FAT_TRAINING_STATE = 2, 367 FAT_DECISION_STATE = 3 368 }; 369 370 enum ant_div_type { 371 NO_ANTDIV = 0xFF, 372 CG_TRX_HW_ANTDIV = 0x01, 373 CGCS_RX_HW_ANTDIV = 0x02, 374 FIXED_HW_ANTDIV = 0x03, 375 CG_TRX_SMART_ANTDIV = 0x04, 376 CGCS_RX_SW_ANTDIV = 0x05, 377 S0S1_SW_ANTDIV = 0x06, /*@8723B intrnal switch S0 S1*/ 378 S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ 379 HL_SW_SMART_ANT_TYPE1 = 0x10, 380 /*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/ 381 /*@and each ant. is equipped with 4 antenna patterns*/ 382 HL_SW_SMART_ANT_TYPE2 = 0x11 383 /*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ 384 }; 385 386 /* @1 ============================================================ 387 * 1 function prototype 388 * 1 ============================================================ 389 */ 390 391 void odm_stop_antenna_switch_dm(void *dm_void); 392 393 void phydm_enable_antenna_diversity(void *dm_void); 394 395 void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/ 396 ); 397 398 #define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link 399 400 void odm_sw_ant_div_rest_after_link(void *dm_void); 401 402 void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path); 403 404 void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch); 405 406 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 407 408 void phydm_antdiv_reset_statistic(void *dm_void, u32 macid); 409 410 void odm_update_rx_idle_ant(void *dm_void, u8 ant); 411 412 void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant); 413 414 void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len); 415 416 #if (RTL8723B_SUPPORT == 1) 417 void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant, 418 u32 optional_ant); 419 #endif 420 421 #if (RTL8188F_SUPPORT == 1) 422 void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant); 423 #endif 424 425 #if (RTL8723D_SUPPORT == 1) 426 427 void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant); 428 429 void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant, 430 u32 optional_ant); 431 432 #endif 433 434 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY 435 436 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 437 void odm_sw_antdiv_callback(struct phydm_timer_list *timer); 438 439 void odm_sw_antdiv_workitem_callback(void *context); 440 441 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 442 443 void odm_sw_antdiv_workitem_callback(void *context); 444 445 void odm_sw_antdiv_callback(void *function_context); 446 447 #endif 448 449 void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step); 450 451 void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux, 452 u32 rx_pwdb_all); 453 454 void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void, 455 void *phy_info_void, 456 void *pkt_info_void); 457 458 #endif 459 460 #ifdef ODM_EVM_ENHANCE_ANTDIV 461 void phydm_evm_sw_antdiv_init(void *dm_void); 462 463 void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void); 464 465 void phydm_antdiv_reset_rx_rate(void *dm_void); 466 467 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 468 void phydm_evm_antdiv_callback(struct phydm_timer_list *timer); 469 470 void phydm_evm_antdiv_workitem_callback(void *context); 471 472 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 473 void phydm_evm_antdiv_callback(void *dm_void); 474 475 void phydm_evm_antdiv_workitem_callback(void *context); 476 477 #else 478 void phydm_evm_antdiv_callback(void *dm_void); 479 #endif 480 481 #endif 482 483 void odm_hw_ant_div(void *dm_void); 484 485 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ 486 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) 487 void odm_fast_ant_training( 488 void *dm_void); 489 490 void odm_fast_ant_training_callback(void *dm_void); 491 492 void odm_fast_ant_training_work_item_callback(void *dm_void); 493 #endif 494 495 void odm_ant_div_init(void *dm_void); 496 497 void odm_ant_div(void *dm_void); 498 499 void odm_antsel_statistics(void *dm_void, void *phy_info_void, 500 u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method, 501 u8 is_cck_rate); 502 503 void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void, 504 void *pkt_info_void); 505 506 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 507 void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id); 508 509 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) 510 511 struct tx_desc; 512 /*@declared tx_desc here or compile error happened when enabled 8822B*/ 513 514 void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv, 515 struct tx_desc *pdesc, unsigned short aid); 516 517 #if 1 /*@def def CONFIG_WLAN_HAL*/ 518 void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv, 519 void *pdesc_data, u16 aid); 520 #endif /*@#ifdef CONFIG_WLAN_HAL*/ 521 #endif 522 523 void odm_ant_div_config(void *dm_void); 524 525 void odm_ant_div_timers(void *dm_void, u8 state); 526 527 void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used, 528 char *output, u32 *_out_len); 529 530 void odm_ant_div_reset(void *dm_void); 531 532 void odm_antenna_diversity_init(void *dm_void); 533 534 void odm_antenna_diversity(void *dm_void); 535 #endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/ 536 #endif /*@#ifndef __ODMANTDIV_H__*/ 537