1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 /*******************************************************
34 * when antenna test utility is on or some testing need to disable antenna
35 * diversity call this function to disable all ODM related mechanisms which
36 * will switch antenna.
37 *****************************************************
38 */
39 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
40
41 #if (RTL8721D_SUPPORT == 1)
42
odm_update_rx_idle_ant_8721d(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)43 void odm_update_rx_idle_ant_8721d(void *dm_void, u8 ant, u32 default_ant,
44 u32 optional_ant)
45 {
46 struct dm_struct *dm = (struct dm_struct *)dm_void;
47 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
48
49 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
50 /*@Default RX*/
51 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
52 /*@Optional RX*/
53 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
54 /*@Default TX*/
55 fat_tab->rx_idle_ant = ant;
56 }
57
odm_trx_hw_ant_div_init_8721d(void * dm_void)58 void odm_trx_hw_ant_div_init_8721d(void *dm_void)
59 {
60 struct dm_struct *dm = (struct dm_struct *)dm_void;
61
62 PHYDM_DBG(dm, DBG_ANT_DIV,
63 "[8721D] AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV]\n");
64
65 /*@BT Coexistence*/
66 /*@keep antsel_map when GNT_BT = 1*/
67 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
68 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
69 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
70 /* @Disable hw antsw & fast_train.antsw when BT TX/RX */
71 odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
72
73 switch (dm->antdiv_gpio) {
74 case ANTDIV_GPIO_PA2PA4: {
75 PAD_CMD(_PA_2, ENABLE);
76 Pinmux_Config(_PA_2, PINMUX_FUNCTION_RFE);
77 PAD_CMD(_PA_4, ENABLE);
78 Pinmux_Config(_PA_4, PINMUX_FUNCTION_RFE);
79 break;
80 }
81 case ANTDIV_GPIO_PA5PA6: {
82 PAD_CMD(_PA_5, ENABLE);
83 Pinmux_Config(_PA_5, PINMUX_FUNCTION_RFE);
84 PAD_CMD(_PA_6, ENABLE);
85 Pinmux_Config(_PA_6, PINMUX_FUNCTION_RFE);
86 break;
87 }
88 case ANTDIV_GPIO_PA12PA13: {
89 PAD_CMD(_PA_12, ENABLE);
90 Pinmux_Config(_PA_12, PINMUX_FUNCTION_RFE);
91 PAD_CMD(_PA_13, ENABLE);
92 Pinmux_Config(_PA_13, PINMUX_FUNCTION_RFE);
93 break;
94 }
95 case ANTDIV_GPIO_PA14PA15: {
96 PAD_CMD(_PA_14, ENABLE);
97 Pinmux_Config(_PA_14, PINMUX_FUNCTION_RFE);
98 PAD_CMD(_PA_15, ENABLE);
99 Pinmux_Config(_PA_15, PINMUX_FUNCTION_RFE);
100 break;
101 }
102 case ANTDIV_GPIO_PA16PA17: {
103 PAD_CMD(_PA_16, ENABLE);
104 Pinmux_Config(_PA_16, PINMUX_FUNCTION_RFE);
105 PAD_CMD(_PA_17, ENABLE);
106 Pinmux_Config(_PA_17, PINMUX_FUNCTION_RFE);
107 break;
108 }
109 case ANTDIV_GPIO_PB1PB2: {
110 PAD_CMD(_PB_1, ENABLE);
111 Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE);
112 PAD_CMD(_PB_2, ENABLE);
113 Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE);
114 break;
115 }
116 case ANTDIV_GPIO_PB26PB29: {
117 PAD_CMD(_PB_26, ENABLE);
118 Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE);
119 PAD_CMD(_PB_29, ENABLE);
120 Pinmux_Config(_PB_29, PINMUX_FUNCTION_RFE);
121 break;
122 }
123 default: {
124 }
125 }
126
127 if (dm->antdiv_gpio == ANTDIV_GPIO_PA12PA13 ||
128 dm->antdiv_gpio == ANTDIV_GPIO_PA14PA15 ||
129 dm->antdiv_gpio == ANTDIV_GPIO_PA16PA17 ||
130 dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2) {
131 /* ANT_SEL_P, ANT_SEL_N */
132 odm_set_bb_reg(dm, R_0x930, 0xF, 8);
133 odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
134 odm_set_bb_reg(dm, R_0x92c, BIT(1) | BIT(0), 2);
135 odm_set_bb_reg(dm, R_0x944, 0x00000003, 0x3);
136 } else if (dm->antdiv_gpio == ANTDIV_GPIO_PA2PA4 ||
137 dm->antdiv_gpio == ANTDIV_GPIO_PA5PA6 ||
138 dm->antdiv_gpio == ANTDIV_GPIO_PB26PB29) {
139 /* TRSW_P, TRSW_N */
140 odm_set_bb_reg(dm, R_0x930, 0xF00, 8);
141 odm_set_bb_reg(dm, R_0x930, 0xF000, 8);
142 odm_set_bb_reg(dm, R_0x92c, BIT(3) | BIT(2), 2);
143 odm_set_bb_reg(dm, R_0x944, 0x0000000C, 0x3);
144 }
145
146 u32 sysreg208 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
147
148 sysreg208 |= BIT(28);
149 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, sysreg208);
150
151 u32 sysreg344 =
152 HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL);
153
154 sysreg344 |= BIT(9);
155 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
156
157 u32 sysreg280 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
158
159 sysreg280 |= 0x7;
160 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, sysreg280);
161
162 sysreg344 |= BIT(8);
163 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
164
165 sysreg344 |= BIT(0);
166 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
167
168 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
169 odm_set_bb_reg(dm, R_0x804, 0xF00, 1); /* r_keep_rfpin */
170
171 /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/
172 /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
173 /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
174 /*@GNT_WL tx*/
175 odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
176
177 /*@Mapping Table*/
178 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
179 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
180 /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
181 /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
182
183 /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
184 odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
185 /* @Low-to-High threshold for WLBB_SEL_RF_ON */
186 /*when OFDM enable */
187 odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
188 /* @High-to-Low threshold for WLBB_SEL_RF_ON */
189 /* when OFDM enable */
190 odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
191 /* @b Low-to-High threshold for WLBB_SEL_RF_ON*/
192 /*when OFDM disable ( only CCK ) */
193 odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
194 /* @High-to-Low threshold for WLBB_SEL_RF_ON*/
195 /* when OFDM disable ( only CCK ) */
196 odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
197
198 /*OFDM HW AntDiv Parameters*/
199 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
200 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
201 odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
202
203 /*@CCK HW AntDiv Parameters*/
204 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
205 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 0);
206 odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
207
208 odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
209 odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
210 odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
211 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
212 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
213
214 /*@disable antenna training */
215 odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
216 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
217 }
218 #endif
219
odm_stop_antenna_switch_dm(void * dm_void)220 void odm_stop_antenna_switch_dm(void *dm_void)
221 {
222 struct dm_struct *dm = (struct dm_struct *)dm_void;
223 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
224 /* @disable ODM antenna diversity */
225 dm->support_ability &= ~ODM_BB_ANT_DIV;
226 if (fat_tab->div_path_type == ANT_PATH_A)
227 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
228 else if (fat_tab->div_path_type == ANT_PATH_B)
229 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
230 else if (fat_tab->div_path_type == ANT_PATH_AB)
231 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
232 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
233 PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
234 }
235
phydm_enable_antenna_diversity(void * dm_void)236 void phydm_enable_antenna_diversity(void *dm_void)
237 {
238 struct dm_struct *dm = (struct dm_struct *)dm_void;
239
240 dm->support_ability |= ODM_BB_ANT_DIV;
241 dm->antdiv_select = 0;
242 PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
243 odm_antenna_diversity_init(dm);
244 }
245
odm_set_ant_config(void * dm_void,u8 ant_setting)246 void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,...*/)
247 {
248 struct dm_struct *dm = (struct dm_struct *)dm_void;
249
250 if (dm->support_ic_type == ODM_RTL8723B) {
251 if (ant_setting == 0) /* @ant A*/
252 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);
253 else if (ant_setting == 1)
254 odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);
255 } else if (dm->support_ic_type == ODM_RTL8723D) {
256 if (ant_setting == 0) /* @ant A*/
257 odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);
258 else if (ant_setting == 1)
259 odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);
260 }
261 }
262
263 /* ****************************************************** */
264
odm_sw_ant_div_rest_after_link(void * dm_void)265 void odm_sw_ant_div_rest_after_link(void *dm_void)
266 {
267 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
268 struct dm_struct *dm = (struct dm_struct *)dm_void;
269 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
270 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
271 u32 i;
272
273 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
274 swat_tab->try_flag = SWAW_STEP_INIT;
275 swat_tab->rssi_trying = 0;
276 swat_tab->double_chk_flag = 0;
277 fat_tab->rx_idle_ant = MAIN_ANT;
278
279 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
280 phydm_antdiv_reset_statistic(dm, i);
281 }
282
283 #endif
284 }
285
phydm_n_on_off(void * dm_void,u8 swch,u8 path)286 void phydm_n_on_off(void *dm_void, u8 swch, u8 path)
287 {
288 struct dm_struct *dm = (struct dm_struct *)dm_void;
289 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
290
291 if (path == ANT_PATH_A) {
292 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
293 } else if (path == ANT_PATH_B) {
294 odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
295 } else if (path == ANT_PATH_AB) {
296 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
297 odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
298 }
299 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
300 #if (RTL8723D_SUPPORT == 1)
301 /*@Mingzhi 2017-05-08*/
302 if (dm->support_ic_type == ODM_RTL8723D) {
303 if (swch == ANTDIV_ON) {
304 odm_set_bb_reg(dm, R_0xce0, BIT(1), 1);
305 odm_set_bb_reg(dm, R_0x948, BIT(6), 1);
306 /*@1:HW ctrl 0:SW ctrl*/
307 } else {
308 odm_set_bb_reg(dm, R_0xce0, BIT(1), 0);
309 odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
310 /*@1:HW ctrl 0:SW ctrl*/
311 }
312 }
313 #endif
314 }
315
phydm_ac_on_off(void * dm_void,u8 swch,u8 path)316 void phydm_ac_on_off(void *dm_void, u8 swch, u8 path)
317 {
318 struct dm_struct *dm = (struct dm_struct *)dm_void;
319 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
320
321 if (dm->support_ic_type & ODM_RTL8812) {
322 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
323 /* OFDM AntDiv function block enable */
324 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
325 /* @CCK AntDiv function block enable */
326 } else if (dm->support_ic_type & ODM_RTL8822B) {
327 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
328 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
329 if (path == ANT_PATH_A) {
330 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
331 } else if (path == ANT_PATH_B) {
332 odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
333 } else if (path == ANT_PATH_AB) {
334 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
335 odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
336 }
337 } else {
338 odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);
339 /* OFDM AntDiv function block enable */
340
341 if (dm->cut_version >= ODM_CUT_C &&
342 dm->support_ic_type == ODM_RTL8821 &&
343 dm->ant_div_type != S0S1_SW_ANTDIV) {
344 PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
345 (swch == ANTDIV_ON) ? "ON" : "OFF");
346 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
347 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
348 /* @CCK AntDiv function block enable */
349 } else if (dm->support_ic_type == ODM_RTL8821C) {
350 PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
351 (swch == ANTDIV_ON) ? "ON" : "OFF");
352 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
353 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
354 /* @CCK AntDiv function block enable */
355 }
356 }
357 }
358
phydm_jgr3_on_off(void * dm_void,u8 swch,u8 path)359 void phydm_jgr3_on_off(void *dm_void, u8 swch, u8 path)
360 {
361 struct dm_struct *dm = (struct dm_struct *)dm_void;
362 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
363
364 odm_set_bb_reg(dm, R_0x8a0, BIT(17), swch);
365 /* OFDM AntDiv function block enable */
366 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
367 /* @CCK AntDiv function block enable */
368 }
369
odm_ant_div_on_off(void * dm_void,u8 swch,u8 path)370 void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)
371 {
372 struct dm_struct *dm = (struct dm_struct *)dm_void;
373 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
374
375 if (fat_tab->ant_div_on_off != swch) {
376 if (dm->ant_div_type == S0S1_SW_ANTDIV)
377 return;
378
379 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
380 PHYDM_DBG(dm, DBG_ANT_DIV,
381 "(( Turn %s )) N-Series HW-AntDiv block\n",
382 (swch == ANTDIV_ON) ? "ON" : "OFF");
383 phydm_n_on_off(dm, swch, path);
384
385 } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
386 PHYDM_DBG(dm, DBG_ANT_DIV,
387 "(( Turn %s )) AC-Series HW-AntDiv block\n",
388 (swch == ANTDIV_ON) ? "ON" : "OFF");
389 phydm_ac_on_off(dm, swch, path);
390 } else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
391 PHYDM_DBG(dm, DBG_ANT_DIV,
392 "(( Turn %s )) JGR3 HW-AntDiv block\n",
393 (swch == ANTDIV_ON) ? "ON" : "OFF");
394 phydm_jgr3_on_off(dm, swch, path);
395 }
396 }
397 fat_tab->ant_div_on_off = swch;
398 }
399
odm_tx_by_tx_desc_or_reg(void * dm_void,u8 swch)400 void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)
401 {
402 struct dm_struct *dm = (struct dm_struct *)dm_void;
403 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
404 u8 enable;
405
406 if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
407 enable = (swch == TX_BY_DESC) ? 1 : 0;
408 else
409 enable = 0; /*@Force TX by Reg*/
410
411 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
412 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
413 odm_set_bb_reg(dm, R_0x80c, BIT(21), enable);
414 else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
415 odm_set_bb_reg(dm, R_0x900, BIT(18), enable);
416 else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
417 odm_set_bb_reg(dm, R_0x186c, BIT(1), enable);
418
419 PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n",
420 (enable == TX_BY_DESC) ? "DESC" : "REG");
421 }
422 }
423
phydm_antdiv_reset_statistic(void * dm_void,u32 macid)424 void phydm_antdiv_reset_statistic(void *dm_void, u32 macid)
425 {
426 struct dm_struct *dm = (struct dm_struct *)dm_void;
427 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
428
429 fat_tab->main_sum[macid] = 0;
430 fat_tab->aux_sum[macid] = 0;
431 fat_tab->main_cnt[macid] = 0;
432 fat_tab->aux_cnt[macid] = 0;
433 fat_tab->main_sum_cck[macid] = 0;
434 fat_tab->aux_sum_cck[macid] = 0;
435 fat_tab->main_cnt_cck[macid] = 0;
436 fat_tab->aux_cnt_cck[macid] = 0;
437 }
438
phydm_fast_training_enable(void * dm_void,u8 swch)439 void phydm_fast_training_enable(void *dm_void, u8 swch)
440 {
441 struct dm_struct *dm = (struct dm_struct *)dm_void;
442 u8 enable;
443
444 if (swch == FAT_ON)
445 enable = 1;
446 else
447 enable = 0;
448
449 PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
450
451 if (dm->support_ic_type == ODM_RTL8188E) {
452 odm_set_bb_reg(dm, R_0xe08, BIT(16), enable);
453 /*@enable fast training*/
454 } else if (dm->support_ic_type == ODM_RTL8192E) {
455 odm_set_bb_reg(dm, R_0xb34, BIT(28), enable);
456 /*@enable fast training (path-A)*/
457 #if 0
458 odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);
459 /*enable fast training (path-B)*/
460 #endif
461 } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
462 odm_set_bb_reg(dm, R_0x900, BIT(19), enable);
463 /*@enable fast training */
464 }
465 }
466
phydm_keep_rx_ack_ant_by_tx_ant_time(void * dm_void,u32 time)467 void phydm_keep_rx_ack_ant_by_tx_ant_time(void *dm_void, u32 time)
468 {
469 struct dm_struct *dm = (struct dm_struct *)dm_void;
470
471 /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
472 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
473 odm_set_bb_reg(dm, R_0xe20, 0xf00000, time);
474 else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
475 odm_set_bb_reg(dm, R_0x818, 0xf00000, time);
476 }
477
phydm_update_rx_idle_ac(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant,u32 default_tx_ant)478 void phydm_update_rx_idle_ac(void *dm_void, u8 ant, u32 default_ant,
479 u32 optional_ant, u32 default_tx_ant)
480 {
481 struct dm_struct *dm = (struct dm_struct *)dm_void;
482
483 u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
484 /* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to */
485 /* @prevnt incorrect 0xc08 bit0-15.We still not know why it is changed*/
486 value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) |
487 BIT(5) | BIT(4) | BIT(3));
488 value16 |= ((u16)default_ant << 3);
489 value16 |= ((u16)optional_ant << 6);
490 value16 |= ((u16)default_tx_ant << 9);
491 odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
492 #if 0
493 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x380000, default_ant);
494 /* @Default RX */
495 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x1c00000, optional_ant);
496 /* Optional RX */
497 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0xe000000, default_ant);
498 /* @Default TX */
499 #endif
500 }
501
phydm_update_rx_idle_n(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant,u32 default_tx_ant)502 void phydm_update_rx_idle_n(void *dm_void, u8 ant, u32 default_ant,
503 u32 optional_ant, u32 default_tx_ant)
504 {
505 struct dm_struct *dm = (struct dm_struct *)dm_void;
506 u32 value32;
507
508 if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
509 odm_set_bb_reg(dm, R_0xb38, 0x38, default_ant);
510 /* @Default RX */
511 odm_set_bb_reg(dm, R_0xb38, 0x1c0, optional_ant);
512 /* Optional RX */
513 odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
514 /* @Default TX */
515 #if (RTL8723B_SUPPORT == 1)
516 } else if (dm->support_ic_type == ODM_RTL8723B) {
517 value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);
518
519 if (value32 != 0x280)
520 odm_update_rx_idle_ant_8723b(dm, ant, default_ant,
521 optional_ant);
522 else
523 PHYDM_DBG(dm, DBG_ANT_DIV,
524 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
525 #endif
526
527 #if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/
528 } else if (dm->support_ic_type == ODM_RTL8723D) {
529 phydm_set_tx_ant_pwr_8723d(dm, ant);
530 odm_update_rx_idle_ant_8723d(dm, ant, default_ant,
531 optional_ant);
532 #endif
533
534 #if (RTL8721D_SUPPORT == 1)
535 } else if (dm->support_ic_type == ODM_RTL8721D) {
536 odm_update_rx_idle_ant_8721d(dm, ant, default_ant,
537 optional_ant);
538 #endif
539 } else {
540 /*@8188E & 8188F*/
541 /*@ if (dm->support_ic_type == ODM_RTL8723D) {*/
542 /*#if (RTL8723D_SUPPORT == 1)*/
543 /* phydm_set_tx_ant_pwr_8723d(dm, ant);*/
544 /*#endif*/
545 /* }*/
546 #if (RTL8188F_SUPPORT == 1)
547 if (dm->support_ic_type == ODM_RTL8188F)
548 phydm_update_rx_idle_antenna_8188F(dm, default_ant);
549 #endif
550
551 odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);/*@Default RX*/
552 odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
553 /*Optional RX*/
554 odm_set_bb_reg(dm, R_0x860, 0x7000, default_tx_ant);
555 /*@Default TX*/
556 }
557 }
558
phydm_update_rx_idle_jgr3(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant,u32 default_tx_ant)559 void phydm_update_rx_idle_jgr3(void *dm_void, u8 ant, u32 default_ant,
560 u32 optional_ant, u32 default_tx_ant)
561 {
562 struct dm_struct *dm = (struct dm_struct *)dm_void;
563 u32 value32;
564
565 odm_set_bb_reg(dm, R_0x1884, 0xf0, default_ant);/*@Default RX*/
566 odm_set_bb_reg(dm, R_0x1884, 0xf00, optional_ant);
567 /*Optional RX*/
568 odm_set_bb_reg(dm, R_0x1884, 0xf000, default_tx_ant);
569 /*@Default TX*/
570 }
odm_update_rx_idle_ant(void * dm_void,u8 ant)571 void odm_update_rx_idle_ant(void *dm_void, u8 ant)
572 {
573 struct dm_struct *dm = (struct dm_struct *)dm_void;
574 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
575 u32 default_ant, optional_ant, value32, default_tx_ant;
576
577 if (fat_tab->rx_idle_ant != ant) {
578 PHYDM_DBG(dm, DBG_ANT_DIV,
579 "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n",
580 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
581
582 if (!(dm->support_ic_type & ODM_RTL8723B))
583 fat_tab->rx_idle_ant = ant;
584
585 if (ant == MAIN_ANT) {
586 default_ant = ANT1_2G;
587 optional_ant = ANT2_2G;
588 } else {
589 default_ant = ANT2_2G;
590 optional_ant = ANT1_2G;
591 }
592
593 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
594 default_tx_ant = (fat_tab->b_fix_tx_ant ==
595 FIX_TX_AT_MAIN) ? 0 : 1;
596 else
597 default_tx_ant = default_ant;
598
599 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
600 phydm_update_rx_idle_n(dm, ant, default_ant,
601 optional_ant, default_tx_ant);
602 } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
603 phydm_update_rx_idle_ac(dm, ant, default_ant,
604 optional_ant, default_tx_ant);
605 } else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
606 phydm_update_rx_idle_jgr3(dm, ant, default_ant,
607 optional_ant, default_tx_ant);
608 }
609 /*PathA Resp Tx*/
610 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
611 ODM_RTL8814A))
612 odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);
613 else if (dm->support_ic_type == ODM_RTL8188E)
614 odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);
615 else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
616 odm_set_mac_reg(dm, R_0x6f8, 0xf, default_tx_ant);
617 else
618 odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);
619
620 } else { /* @fat_tab->rx_idle_ant == ant */
621 PHYDM_DBG(dm, DBG_ANT_DIV,
622 "[ Stay in Ori-ant ] rx_idle_ant =%s\n",
623 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
624 fat_tab->rx_idle_ant = ant;
625 }
626 }
627
phydm_update_rx_idle_ant_pathb(void * dm_void,u8 ant)628 void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)
629 {
630 struct dm_struct *dm = (struct dm_struct *)dm_void;
631 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
632 u32 default_ant, optional_ant, value32, default_tx_ant;
633
634 if (fat_tab->rx_idle_ant2 != ant) {
635 PHYDM_DBG(dm, DBG_ANT_DIV,
636 "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n",
637 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
638 if (ant == MAIN_ANT) {
639 default_ant = ANT1_2G;
640 optional_ant = ANT2_2G;
641 } else {
642 default_ant = ANT2_2G;
643 optional_ant = ANT1_2G;
644 }
645
646 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
647 default_tx_ant = (fat_tab->b_fix_tx_ant ==
648 FIX_TX_AT_MAIN) ? 0 : 1;
649 else
650 default_tx_ant = default_ant;
651 if (dm->support_ic_type & ODM_RTL8822B) {
652 u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);
653
654 v16 &= ~(0xff8);/*0xE08[11:3]*/
655 v16 |= ((u16)default_ant << 3);
656 v16 |= ((u16)optional_ant << 6);
657 v16 |= ((u16)default_tx_ant << 9);
658 odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);
659 odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);
660 /*PathB Resp Tx*/
661 }
662 } else {
663 /* fat_tab->rx_idle_ant2 == ant */
664 PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n",
665 (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
666 fat_tab->rx_idle_ant2 = ant;
667 }
668 }
669
phydm_set_antdiv_val(void * dm_void,u32 * val_buf,u8 val_len)670 void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len)
671 {
672 struct dm_struct *dm = (struct dm_struct *)dm_void;
673
674 if (!(dm->support_ability & ODM_BB_ANT_DIV))
675 return;
676
677 if (val_len != 1) {
678 PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
679 return;
680 }
681
682 odm_update_rx_idle_ant(dm, (u8)(*val_buf));
683 }
684
odm_update_tx_ant(void * dm_void,u8 ant,u32 mac_id)685 void odm_update_tx_ant(void *dm_void, u8 ant, u32 mac_id)
686 {
687 struct dm_struct *dm = (struct dm_struct *)dm_void;
688 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
689 u8 tx_ant;
690
691 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
692 ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ?
693 MAIN_ANT : AUX_ANT;
694
695 if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
696 tx_ant = ant;
697 else {
698 if (ant == MAIN_ANT)
699 tx_ant = ANT1_2G;
700 else
701 tx_ant = ANT2_2G;
702 }
703
704 fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
705 fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
706 fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
707
708 PHYDM_DBG(dm, DBG_ANT_DIV,
709 "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n",
710 mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
711 #if 0
712 PHYDM_DBG(dm, DBG_ANT_DIV,
713 "antsel_tr_mux=(( 3'b%d%d%d ))\n",
714 fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
715 fat_tab->antsel_a[mac_id]);
716 #endif
717 }
718
719 #ifdef PHYDM_BEAMFORMING_SUPPORT
720 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
721
odm_bdc_init(void * dm_void)722 void odm_bdc_init(
723 void *dm_void)
724 {
725 struct dm_struct *dm = (struct dm_struct *)dm_void;
726 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
727
728 PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
729 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
730 dm_bdc_table->bdc_mode = BDC_MODE_NULL;
731 dm_bdc_table->bdc_try_flag = 0;
732 dm_bdc_table->bd_ccoex_type_wbfer = 0;
733 dm->bdc_holdstate = 0xff;
734
735 if (dm->support_ic_type == ODM_RTL8192E) {
736 odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);
737 odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);
738 } else if (dm->support_ic_type == ODM_RTL8812) {
739 odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008);
740 /* @0x9b0[30:0] = 01081008 */
741 odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0);
742 /* @0x9b4[31:0] = 00000000 */
743 }
744 }
745
odm_CSI_on_off(void * dm_void,u8 CSI_en)746 void odm_CSI_on_off(
747 void *dm_void,
748 u8 CSI_en)
749 {
750 struct dm_struct *dm = (struct dm_struct *)dm_void;
751 if (CSI_en == CSI_ON) {
752 if (dm->support_ic_type == ODM_RTL8192E)
753 odm_set_mac_reg(dm, R_0xd84, BIT(11), 1);
754 /* @0xd84[11]=1 */
755 else if (dm->support_ic_type == ODM_RTL8812)
756 odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1);
757 /* @0x9b0[31]=1 */
758
759 } else if (CSI_en == CSI_OFF) {
760 if (dm->support_ic_type == ODM_RTL8192E)
761 odm_set_mac_reg(dm, R_0xd84, BIT(11), 0);
762 /* @0xd84[11]=0 */
763 else if (dm->support_ic_type == ODM_RTL8812)
764 odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0);
765 /* @0x9b0[31]=0 */
766 }
767 }
768
odm_bd_ccoex_type_with_bfer_client(void * dm_void,u8 swch)769 void odm_bd_ccoex_type_with_bfer_client(
770 void *dm_void,
771 u8 swch)
772 {
773 struct dm_struct *dm = (struct dm_struct *)dm_void;
774 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
775 u8 bd_ccoex_type_wbfer;
776
777 if (swch == DIVON_CSIOFF) {
778 PHYDM_DBG(dm, DBG_ANT_DIV,
779 "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
780 bd_ccoex_type_wbfer = 1;
781
782 if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
783 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
784 odm_CSI_on_off(dm, CSI_OFF);
785 dm_bdc_table->bd_ccoex_type_wbfer = 1;
786 }
787 } else if (swch == DIVOFF_CSION) {
788 PHYDM_DBG(dm, DBG_ANT_DIV,
789 "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
790 bd_ccoex_type_wbfer = 2;
791
792 if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
793 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
794 odm_CSI_on_off(dm, CSI_ON);
795 dm_bdc_table->bd_ccoex_type_wbfer = 2;
796 }
797 }
798 }
799
odm_bf_ant_div_mode_arbitration(void * dm_void)800 void odm_bf_ant_div_mode_arbitration(
801 void *dm_void)
802 {
803 struct dm_struct *dm = (struct dm_struct *)dm_void;
804 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
805 u8 current_bdc_mode;
806
807 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
808 PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
809
810 /* @2 mode 1 */
811 if (dm_bdc_table->num_txbfee_client != 0 &&
812 dm_bdc_table->num_txbfer_client == 0) {
813 current_bdc_mode = BDC_MODE_1;
814
815 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
816 dm_bdc_table->bdc_mode = BDC_MODE_1;
817 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
818 dm_bdc_table->bdc_rx_idle_update_counter = 1;
819 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
820 }
821
822 PHYDM_DBG(dm, DBG_ANT_DIV,
823 "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
824 }
825 /* @2 mode 2 */
826 else if ((dm_bdc_table->num_txbfee_client == 0) &&
827 (dm_bdc_table->num_txbfer_client != 0)) {
828 current_bdc_mode = BDC_MODE_2;
829
830 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
831 dm_bdc_table->bdc_mode = BDC_MODE_2;
832 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
833 dm_bdc_table->bdc_try_flag = 0;
834 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
835 }
836 PHYDM_DBG(dm, DBG_ANT_DIV,
837 "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
838 }
839 /* @2 mode 3 */
840 else if ((dm_bdc_table->num_txbfee_client != 0) &&
841 (dm_bdc_table->num_txbfer_client != 0)) {
842 current_bdc_mode = BDC_MODE_3;
843
844 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
845 dm_bdc_table->bdc_mode = BDC_MODE_3;
846 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
847 dm_bdc_table->bdc_try_flag = 0;
848 dm_bdc_table->bdc_rx_idle_update_counter = 1;
849 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
850 }
851
852 PHYDM_DBG(dm, DBG_ANT_DIV,
853 "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
854 }
855 /* @2 mode 4 */
856 else if ((dm_bdc_table->num_txbfee_client == 0) &&
857 (dm_bdc_table->num_txbfer_client == 0)) {
858 current_bdc_mode = BDC_MODE_4;
859
860 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
861 dm_bdc_table->bdc_mode = BDC_MODE_4;
862 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
863 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
864 }
865
866 PHYDM_DBG(dm, DBG_ANT_DIV,
867 "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
868 }
869 #endif
870 }
871
odm_div_train_state_setting(void * dm_void)872 void odm_div_train_state_setting(
873 void *dm_void)
874 {
875 struct dm_struct *dm = (struct dm_struct *)dm_void;
876 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
877
878 PHYDM_DBG(dm, DBG_ANT_DIV,
879 "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n");
880 dm_bdc_table->bdc_try_counter = 2;
881 dm_bdc_table->bdc_try_flag = 1;
882 dm_bdc_table->BDC_state = bdc_bfer_train_state;
883 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
884 }
885
odm_bd_ccoex_bfee_rx_div_arbitration(void * dm_void)886 void odm_bd_ccoex_bfee_rx_div_arbitration(
887 void *dm_void)
888 {
889 struct dm_struct *dm = (struct dm_struct *)dm_void;
890 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
891 boolean stop_bf_flag;
892 u8 bdc_active_mode;
893
894 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
895
896 PHYDM_DBG(dm, DBG_ANT_DIV,
897 "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n",
898 dm_bdc_table->num_txbfee_client,
899 dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
900 PHYDM_DBG(dm, DBG_ANT_DIV,
901 "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n",
902 dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
903
904 /* @2 [ MIB control ] */
905 if (dm->bdc_holdstate == 2) {
906 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
907 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
908 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
909 return;
910 } else if (dm->bdc_holdstate == 1) {
911 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
912 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
913 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
914 return;
915 }
916
917 /* @------------------------------------------------------------ */
918
919 /* @2 mode 2 & 3 */
920 if (dm_bdc_table->bdc_mode == BDC_MODE_2 ||
921 dm_bdc_table->bdc_mode == BDC_MODE_3) {
922 PHYDM_DBG(dm, DBG_ANT_DIV,
923 "\n{ Try_flag, Try_counter } = { %d , %d }\n",
924 dm_bdc_table->bdc_try_flag,
925 dm_bdc_table->bdc_try_counter);
926 PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n",
927 dm_bdc_table->bd_ccoex_type_wbfer);
928
929 /* @All Client have Bfer-Cap------------------------------- */
930 if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) {
931 /* @BFer STA Only?: yes */
932 PHYDM_DBG(dm, DBG_ANT_DIV,
933 "BFer STA only? (( Yes ))\n");
934 dm_bdc_table->bdc_try_flag = 0;
935 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
936 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
937 return;
938 } else
939 PHYDM_DBG(dm, DBG_ANT_DIV,
940 "BFer STA only? (( No ))\n");
941 if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
942 PHYDM_DBG(dm, DBG_ANT_DIV,
943 "All DIV-STA are idle, but BF-STA not\n");
944 dm_bdc_table->bdc_try_flag = 0;
945 dm_bdc_table->BDC_state = bdc_bfer_train_state;
946 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
947 return;
948 } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
949 PHYDM_DBG(dm, DBG_ANT_DIV,
950 "All BF-STA are idle, but DIV-STA not\n");
951 dm_bdc_table->bdc_try_flag = 0;
952 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
953 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
954 return;
955 }
956
957 /* Select active mode-------------------------------------- */
958 if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */
959 if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
960 PHYDM_DBG(dm, DBG_ANT_DIV,
961 "Select active mode (( 1 ))\n");
962 dm_bdc_table->bdc_active_mode = 1;
963 } else {
964 PHYDM_DBG(dm, DBG_ANT_DIV,
965 "Select active mode (( 2 ))\n");
966 dm_bdc_table->bdc_active_mode = 2;
967 }
968 dm_bdc_table->bdc_try_flag = 0;
969 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
970 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
971 return;
972 } else { /* num_bf_tar > 0 */
973 if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
974 PHYDM_DBG(dm, DBG_ANT_DIV,
975 "Select active mode (( 3 ))\n");
976 dm_bdc_table->bdc_active_mode = 3;
977 dm_bdc_table->bdc_try_flag = 0;
978 dm_bdc_table->BDC_state = bdc_bfer_train_state;
979 odm_bd_ccoex_type_with_bfer_client(dm,
980 DIVOFF_CSION)
981 ;
982 return;
983 } else { /* Selsect_4 */
984 bdc_active_mode = 4;
985 PHYDM_DBG(dm, DBG_ANT_DIV,
986 "Select active mode (( 4 ))\n");
987
988 if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
989 dm_bdc_table->bdc_active_mode = 4;
990 PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n");
991 return;
992 }
993 }
994 }
995
996 #if 1
997 if (dm->bdc_holdstate == 0xff) {
998 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
999 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1000 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
1001 return;
1002 }
1003 #endif
1004
1005 /* @Does Client number changed ? ------------------------------- */
1006 if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
1007 dm_bdc_table->bdc_try_flag = 0;
1008 dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
1009 PHYDM_DBG(dm, DBG_ANT_DIV,
1010 "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n");
1011 }
1012 dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
1013
1014 if (dm_bdc_table->bdc_try_flag == 0) {
1015 /* @2 DIV_TRAIN_STATE (mode 2-0) */
1016 if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
1017 odm_div_train_state_setting(dm);
1018 /* @2 BFer_TRAIN_STATE (mode 2-1) */
1019 else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
1020 PHYDM_DBG(dm, DBG_ANT_DIV,
1021 "*****[2-1. BFer_TRAIN_STATE ]*****\n");
1022
1023 #if 0
1024 /* @if(dm_bdc_table->num_bf_tar==0) */
1025 /* @{ */
1026 /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
1027 /* odm_div_train_state_setting( dm); */
1028 /* @} */
1029 /* else */ /* num_bf_tar != 0 */
1030 /* @{ */
1031 #endif
1032 dm_bdc_table->bdc_try_counter = 2;
1033 dm_bdc_table->bdc_try_flag = 1;
1034 dm_bdc_table->BDC_state = BDC_DECISION_STATE;
1035 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1036 PHYDM_DBG(dm, DBG_ANT_DIV,
1037 "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
1038 /* @} */
1039 }
1040 /* @2 DECISION_STATE (mode 2-2) */
1041 else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
1042 PHYDM_DBG(dm, DBG_ANT_DIV,
1043 "*****[2-2. DECISION_STATE]*****\n");
1044 #if 0
1045 /* @if(dm_bdc_table->num_bf_tar==0) */
1046 /* @{ */
1047 /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
1048 /* odm_div_train_state_setting( dm); */
1049 /* @} */
1050 /* else */ /* num_bf_tar != 0 */
1051 /* @{ */
1052 #endif
1053 if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
1054 stop_bf_flag = true;
1055 else
1056 stop_bf_flag = false;
1057
1058 PHYDM_DBG(dm, DBG_ANT_DIV,
1059 "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n",
1060 dm_bdc_table->BF_pass,
1061 dm_bdc_table->DIV_pass, stop_bf_flag);
1062
1063 if (stop_bf_flag == true) { /* @DIV_en */
1064 dm_bdc_table->bdc_hold_counter = 10; /* @20 */
1065 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1066 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
1067 PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
1068 } else { /* @BF_en */
1069 dm_bdc_table->bdc_hold_counter = 10; /* @20 */
1070 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1071 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
1072 PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
1073 }
1074 /* @} */
1075 }
1076 /* @2 BF-HOLD_STATE (mode 2-3) */
1077 else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
1078 PHYDM_DBG(dm, DBG_ANT_DIV,
1079 "*****[2-3. BF_HOLD_STATE ]*****\n");
1080
1081 PHYDM_DBG(dm, DBG_ANT_DIV,
1082 "bdc_hold_counter = (( %d ))\n",
1083 dm_bdc_table->bdc_hold_counter);
1084
1085 if (dm_bdc_table->bdc_hold_counter == 1) {
1086 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
1087 odm_div_train_state_setting(dm);
1088 } else {
1089 dm_bdc_table->bdc_hold_counter--;
1090
1091 #if 0
1092 /* @if(dm_bdc_table->num_bf_tar==0) */
1093 /* @{ */
1094 /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
1095 /* odm_div_train_state_setting( dm); */
1096 /* @} */
1097 /* else */ /* num_bf_tar != 0 */
1098 /* @{ */
1099 /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */
1100 #endif
1101 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
1102 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
1103 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
1104 /* @} */
1105 }
1106 }
1107 /* @2 DIV-HOLD_STATE (mode 2-4) */
1108 else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
1109 PHYDM_DBG(dm, DBG_ANT_DIV,
1110 "*****[2-4. DIV_HOLD_STATE ]*****\n");
1111
1112 PHYDM_DBG(dm, DBG_ANT_DIV,
1113 "bdc_hold_counter = (( %d ))\n",
1114 dm_bdc_table->bdc_hold_counter);
1115
1116 if (dm_bdc_table->bdc_hold_counter == 1) {
1117 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
1118 odm_div_train_state_setting(dm);
1119 } else {
1120 dm_bdc_table->bdc_hold_counter--;
1121 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
1122 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
1123 PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
1124 }
1125 }
1126
1127 } else if (dm_bdc_table->bdc_try_flag == 1) {
1128 /* @2 Set Training counter */
1129 if (dm_bdc_table->bdc_try_counter > 1) {
1130 dm_bdc_table->bdc_try_counter--;
1131 if (dm_bdc_table->bdc_try_counter == 1)
1132 dm_bdc_table->bdc_try_flag = 0;
1133
1134 PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
1135 /* return ; */
1136 }
1137 }
1138 }
1139
1140 PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
1141
1142 #endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
1143 }
1144
1145 #endif
1146 #endif /* @#ifdef PHYDM_BEAMFORMING_SUPPORT*/
1147
1148 #if (RTL8188E_SUPPORT == 1)
1149
odm_rx_hw_ant_div_init_88e(void * dm_void)1150 void odm_rx_hw_ant_div_init_88e(void *dm_void)
1151 {
1152 struct dm_struct *dm = (struct dm_struct *)dm_void;
1153 u32 value32;
1154 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1155
1156 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1157
1158 /* @MAC setting */
1159 value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
1160 odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
1161 value32 | (BIT(23) | BIT(25)));
1162 /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1163 /* Pin Settings */
1164 odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1165 /* reg870[8]=1'b0, reg870[9]=1'b0 */
1166 /* antsel antselb by HW */
1167 odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1168 /* reg864[10]=1'b0 */ /* antsel2 by HW */
1169 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
1170 /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
1171 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
1172 /* regb2c[31]=1'b1 */ /* output at CG only */
1173 /* OFDM Settings */
1174 odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1175 /* @CCK Settings */
1176 odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1177 /* @Fix CCK PHY status report issue */
1178 odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1179 /* @CCK complete HW AntDiv within 64 samples */
1180
1181 odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001);
1182 /* @antenna mapping table */
1183
1184 fat_tab->enable_ctrl_frame_antdiv = 1;
1185 }
1186
odm_trx_hw_ant_div_init_88e(void * dm_void)1187 void odm_trx_hw_ant_div_init_88e(void *dm_void)
1188 {
1189 struct dm_struct *dm = (struct dm_struct *)dm_void;
1190 u32 value32;
1191 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1192
1193
1194 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1195
1196 /* @MAC setting */
1197 value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
1198 odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
1199 value32 | (BIT(23) | BIT(25)));
1200 /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1201 /* Pin Settings */
1202 odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1203 /* reg870[8]=1'b0, reg870[9]=1'b0 */
1204 /* antsel antselb by HW */
1205 odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1206 /* reg864[10]=1'b0 */ /* antsel2 by HW */
1207 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
1208 /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
1209 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
1210 /* regb2c[31]=1'b1 */ /* output at CG only */
1211 /* OFDM Settings */
1212 odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1213 /* @CCK Settings */
1214 odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1215 /* @Fix CCK PHY status report issue */
1216 odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1217 /* @CCK complete HW AntDiv within 64 samples */
1218
1219 /* @antenna mapping table */
1220 if (!dm->is_mp_chip) { /* testchip */
1221 odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x700, 1);
1222 /* Reg858[10:8]=3'b001 */
1223 odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x3800, 2);
1224 /* Reg858[13:11]=3'b010 */
1225 } else /* @MPchip */
1226 odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201);
1227 /*Reg914=3'b010, Reg915=3'b001*/
1228
1229 fat_tab->enable_ctrl_frame_antdiv = 1;
1230 }
1231
1232 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
odm_smart_hw_ant_div_init_88e(void * dm_void)1233 void odm_smart_hw_ant_div_init_88e(
1234 void *dm_void)
1235 {
1236 struct dm_struct *dm = (struct dm_struct *)dm_void;
1237 u32 value32, i;
1238 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1239
1240 PHYDM_DBG(dm, DBG_ANT_DIV,
1241 "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
1242
1243 #if 0
1244 if (*dm->mp_mode == true) {
1245 PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n",
1246 dm->ant_div_type);
1247 return;
1248 }
1249 #endif
1250
1251 fat_tab->train_idx = 0;
1252 fat_tab->fat_state = FAT_PREPARE_STATE;
1253
1254 dm->fat_comb_a = 5;
1255 dm->antdiv_intvl = 0x64; /* @100ms */
1256
1257 for (i = 0; i < 6; i++)
1258 fat_tab->bssid[i] = 0;
1259 for (i = 0; i < (dm->fat_comb_a); i++) {
1260 fat_tab->ant_sum_rssi[i] = 0;
1261 fat_tab->ant_rssi_cnt[i] = 0;
1262 fat_tab->ant_ave_rssi[i] = 0;
1263 }
1264
1265 /* @MAC setting */
1266 value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);
1267 odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1268 value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
1269 odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
1270 /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
1271 /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */
1272
1273 /* @Match MAC ADDR */
1274 odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);
1275 odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
1276
1277 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
1278 odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
1279 odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
1280 odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */
1281 odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);
1282
1283 /* @antenna mapping table */
1284 if (dm->fat_comb_a == 2) {
1285 if (!dm->is_mp_chip) { /* testchip */
1286 odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
1287 odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
1288 } else { /* @MPchip */
1289 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);
1290 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);
1291 }
1292 } else {
1293 if (!dm->is_mp_chip) { /* testchip */
1294 odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
1295 odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
1296 odm_set_bb_reg(dm, R_0x878, BIT(16), 0);
1297 odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */
1298 odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
1299 odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
1300 odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
1301 odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
1302 odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
1303 } else { /* @MPchip */
1304 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */
1305 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */
1306 odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */
1307 odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */
1308 odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */
1309 odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */
1310 odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */
1311 odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */
1312 }
1313 }
1314
1315 /* @Default ant setting when no fast training */
1316 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */
1317 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
1318 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */
1319
1320 /* @Enter Traing state */
1321 odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */
1322
1323 #if 0
1324 /* SW Control */
1325 /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
1326 /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
1327 /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
1328 /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
1329 /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
1330 /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
1331 #endif
1332 }
1333 #endif
1334
1335 #endif /* @#if (RTL8188E_SUPPORT == 1) */
1336
1337 #if (RTL8192E_SUPPORT == 1)
odm_rx_hw_ant_div_init_92e(void * dm_void)1338 void odm_rx_hw_ant_div_init_92e(void *dm_void)
1339 {
1340 struct dm_struct *dm = (struct dm_struct *)dm_void;
1341 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1342
1343 #if 0
1344 if (*dm->mp_mode == true) {
1345 odm_ant_div_on_off(dm, ANTDIV_OFF);
1346 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1347 /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1348 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);
1349 /* @1:CG, 0:CS */
1350 return;
1351 }
1352 #endif
1353
1354 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1355
1356 /* Pin Settings */
1357 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1358 /* reg870[8]=1'b0, antsel is controled by HWs */
1359 odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
1360 /* regc50[8]=1'b1 CS/CG switching is controled by HWs*/
1361
1362 /* @Mapping table */
1363 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1364 /* @antenna mapping table */
1365
1366 /* OFDM Settings */
1367 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1368 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1369
1370 /* @CCK Settings */
1371 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1372 /* Select which path to receive for CCK_1 & CCK_2 */
1373 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1374 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1375 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1376 /* @Fix CCK PHY status report issue */
1377 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1378 /* @CCK complete HW AntDiv within 64 samples */
1379
1380 #ifdef ODM_EVM_ENHANCE_ANTDIV
1381 phydm_evm_sw_antdiv_init(dm);
1382 #endif
1383 }
1384
odm_trx_hw_ant_div_init_92e(void * dm_void)1385 void odm_trx_hw_ant_div_init_92e(void *dm_void)
1386 {
1387 struct dm_struct *dm = (struct dm_struct *)dm_void;
1388
1389 #if 0
1390 if (*dm->mp_mode == true) {
1391 odm_ant_div_on_off(dm, ANTDIV_OFF);
1392 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1393 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */
1394 return;
1395 }
1396 #endif
1397
1398 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1399
1400 /* @3 --RFE pin setting--------- */
1401 /* @[MAC] */
1402 odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
1403 /* @DBG PAD Driving control (GPIO 8) */
1404 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
1405 odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
1406 /* @[BB] */
1407 odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */
1408 odm_set_bb_reg(dm, R_0x944, BIT(8), 1);
1409 odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0);
1410 /* r_rfe_path_sel_ (RFE_CTRL_3) */
1411 odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0);
1412 /* r_rfe_path_sel_ (RFE_CTRL_8) */
1413 odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */
1414 odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */
1415 odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */
1416 odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
1417 odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1418 /* @3 ------------------------- */
1419
1420 /* Pin Settings */
1421 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1422 /* path-A */ /* disable CS/CG switch */
1423
1424 #if 0
1425 /* @Let it follows PHY_REG for bit9 setting */
1426 if (dm->priv->pshare->rf_ft_var.use_ext_pa ||
1427 dm->priv->pshare->rf_ft_var.use_ext_lna)
1428 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);/* path-A output at CS */
1429 else
1430 odm_set_bb_reg(dm, R_0xc50, BIT(9), 0);
1431 /* path-A output at CG ->normal power */
1432 #endif
1433
1434 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1435 /* path-A*/ /* antsel antselb by HW */
1436 odm_set_bb_reg(dm, R_0xb38, BIT(10), 0);/* path-A*/ /* antsel2 by HW */
1437
1438 /* @Mapping table */
1439 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1440 /* @antenna mapping table */
1441
1442 /* OFDM Settings */
1443 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1444 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1445
1446 /* @CCK Settings */
1447 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1448 /* Select which path to receive for CCK_1 & CCK_2 */
1449 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1450 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1451 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1452 /* @Fix CCK PHY status report issue */
1453 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1454 /* @CCK complete HW AntDiv within 64 samples */
1455
1456 #ifdef ODM_EVM_ENHANCE_ANTDIV
1457 phydm_evm_sw_antdiv_init(dm);
1458 #endif
1459 }
1460
1461 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
odm_smart_hw_ant_div_init_92e(void * dm_void)1462 void odm_smart_hw_ant_div_init_92e(
1463 void *dm_void)
1464 {
1465 struct dm_struct *dm = (struct dm_struct *)dm_void;
1466
1467 PHYDM_DBG(dm, DBG_ANT_DIV,
1468 "***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
1469 }
1470 #endif
1471
1472 #endif /* @#if (RTL8192E_SUPPORT == 1) */
1473
1474 #if (RTL8192F_SUPPORT == 1)
odm_rx_hw_ant_div_init_92f(void * dm_void)1475 void odm_rx_hw_ant_div_init_92f(void *dm_void)
1476 {
1477 struct dm_struct *dm = (struct dm_struct *)dm_void;
1478 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1479
1480 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1481
1482 /* Pin Settings */
1483 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1484 /* reg870[8]=1'b0, "antsel" is controlled by HWs */
1485 odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
1486 /* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */
1487
1488 /* @Mapping table */
1489 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1490 /* @antenna mapping table */
1491
1492 /* OFDM Settings */
1493 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1494 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1495
1496 /* @CCK Settings */
1497 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1498 /* Select which path to receive for CCK_1 & CCK_2 */
1499 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1500 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1501 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1502 /* @Fix CCK PHY status report issue */
1503 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1504 /* @CCK complete HW AntDiv within 64 samples */
1505
1506 #ifdef ODM_EVM_ENHANCE_ANTDIV
1507 phydm_evm_sw_antdiv_init(dm);
1508 #endif
1509 }
1510
odm_trx_hw_ant_div_init_92f(void * dm_void)1511 void odm_trx_hw_ant_div_init_92f(void *dm_void)
1512
1513 {
1514 struct dm_struct *dm = (struct dm_struct *)dm_void;
1515
1516 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1517 /* @3 --RFE pin setting--------- */
1518 /* @[MAC] */
1519 odm_set_mac_reg(dm, R_0x1048, BIT(0), 1);
1520 /* @DBG PAD Driving control (gpioA_0) */
1521 odm_set_mac_reg(dm, R_0x1048, BIT(1), 1);
1522 /* @DBG PAD Driving control (gpioA_1) */
1523 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
1524 odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0);
1525 /* @gpioA_0,gpioA_1*/
1526 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
1527 /* @[BB] */
1528 odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */
1529 odm_set_bb_reg(dm, R_0x944, BIT(9), 1);
1530 odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0);
1531 /* r_rfe_path_sel_ (RFE_CTRL_8) */
1532 odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0);
1533 /* r_rfe_path_sel_ (RFE_CTRL_9) */
1534 odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */
1535 odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv (RFE_CTRL_8) */
1536 odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv (RFE_CTRL_9) */
1537 odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1538 odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */
1539 /* @3 ------------------------- */
1540
1541 /* Pin Settings */
1542 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1543 /* path-A,disable CS/CG switch */
1544 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1545 /* path-A*, antsel antselb by HW */
1546 odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */
1547
1548 /* @Mapping table */
1549 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1550 /* @antenna mapping table */
1551
1552 /* OFDM Settings */
1553 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1554 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1555
1556 /* @CCK Settings */
1557 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1558 /* Select which path to receive for CCK_1 & CCK_2 */
1559 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1560 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1561 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1562 /* @Fix CCK PHY status report issue */
1563 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1564 /* @CCK complete HW AntDiv within 64 samples */
1565
1566 #ifdef ODM_EVM_ENHANCE_ANTDIV
1567 phydm_evm_sw_antdiv_init(dm);
1568 #endif
1569 }
1570
1571 #endif /* @#if (RTL8192F_SUPPORT == 1) */
1572
1573 #if (RTL8822B_SUPPORT == 1)
phydm_trx_hw_ant_div_init_22b(void * dm_void)1574 void phydm_trx_hw_ant_div_init_22b(void *dm_void)
1575 {
1576 struct dm_struct *dm = (struct dm_struct *)dm_void;
1577
1578 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1579
1580 /* Pin Settings */
1581 odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);
1582 odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);
1583 odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);
1584 /* @------------------------- */
1585
1586 /* @Mapping table */
1587 /* @antenna mapping table */
1588 odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);
1589
1590 /* OFDM Settings */
1591 /* thershold */
1592 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);
1593 /* @bias */
1594 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);
1595 odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);
1596
1597 /* @CCK Settings */
1598 /* Select which path to receive for CCK_1 & CCK_2 */
1599 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1600 /* @Fix CCK PHY status report issue */
1601 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1602 /* @CCK complete HW AntDiv within 64 samples */
1603 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1604 /* @BT Coexistence */
1605 /* @keep antsel_map when GNT_BT = 1 */
1606 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
1607 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1608 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
1609 /* response TX ant by RX ant */
1610 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1611 #if (defined(CONFIG_2T4R_ANTENNA))
1612 PHYDM_DBG(dm, DBG_ANT_DIV,
1613 "***8822B AntDiv_Init => 2T4R case\n");
1614 /* Pin Settings */
1615 odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);
1616 odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);
1617 odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);
1618 /* @BT Coexistence */
1619 odm_set_bb_reg(dm, R_0xeac, BIT(9), 1);
1620 /* @keep antsel_map when GNT_BT = 1 */
1621 /* Mapping table */
1622 /* antenna mapping table */
1623 odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);
1624 /*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/
1625 #endif
1626
1627 #ifdef ODM_EVM_ENHANCE_ANTDIV
1628 phydm_evm_sw_antdiv_init(dm);
1629 #endif
1630 }
1631 #endif /* @#if (RTL8822B_SUPPORT == 1) */
1632
1633 #if (RTL8197F_SUPPORT == 1)
phydm_rx_hw_ant_div_init_97f(void * dm_void)1634 void phydm_rx_hw_ant_div_init_97f(void *dm_void)
1635 {
1636 struct dm_struct *dm = (struct dm_struct *)dm_void;
1637 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1638
1639 #if 0
1640 if (*dm->mp_mode == true) {
1641 odm_ant_div_on_off(dm, ANTDIV_OFF);
1642 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1643 /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
1644 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */
1645 return;
1646 }
1647 #endif
1648 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1649
1650 /* Pin Settings */
1651 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1652 /* reg870[8]=1'b0, */ /* "antsel" is controlled by HWs */
1653 odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
1654 /* regc50[8]=1'b1 *//*"CS/CG switching" is controlled by HWs */
1655
1656 /* @Mapping table */
1657 odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
1658 /* @antenna mapping table */
1659
1660 /* OFDM Settings */
1661 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1662 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1663
1664 /* @CCK Settings */
1665 odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1666 /* Select which path to receive for CCK_1 & CCK_2 */
1667 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
1668 /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1669 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1670 /* @Fix CCK PHY status report issue */
1671 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1672 /* @CCK complete HW AntDiv within 64 samples */
1673
1674 #ifdef ODM_EVM_ENHANCE_ANTDIV
1675 phydm_evm_sw_antdiv_init(dm);
1676 #endif
1677 }
1678 #endif //#if (RTL8197F_SUPPORT == 1)
1679
1680 #if (RTL8197G_SUPPORT == 1)
phydm_rx_hw_ant_div_init_97g(void * dm_void)1681 void phydm_rx_hw_ant_div_init_97g(void *dm_void)
1682 {
1683 struct dm_struct *dm = (struct dm_struct *)dm_void;
1684 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1685
1686 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1687
1688 /* Pin Settings */
1689 odm_set_bb_reg(dm, R_0x1884, BIT(23), 0);
1690 /* reg1844[23]=1'b0 *//*"CS/CG switching" is controlled by HWs*/
1691 odm_set_bb_reg(dm, R_0x1884, BIT(16), 1);
1692 /* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/
1693
1694 /* @Mapping table */
1695 odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100);
1696 /* @antenna mapping table */
1697
1698 /* OFDM Settings */
1699 odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */
1700 odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */
1701
1702
1703 #ifdef ODM_EVM_ENHANCE_ANTDIV
1704 phydm_evm_sw_antdiv_init(dm);
1705 #endif
1706 }
1707 #endif //#if (RTL8197F_SUPPORT == 1)
1708
1709 #if (RTL8723D_SUPPORT == 1)
odm_trx_hw_ant_div_init_8723d(void * dm_void)1710 void odm_trx_hw_ant_div_init_8723d(void *dm_void)
1711 {
1712 struct dm_struct *dm = (struct dm_struct *)dm_void;
1713
1714 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
1715
1716 /*@BT Coexistence*/
1717 /*@keep antsel_map when GNT_BT = 1*/
1718 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
1719 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1720 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
1721 /* @Disable hw antsw & fast_train.antsw when BT TX/RX */
1722 odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
1723
1724 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1725 #if 0
1726 /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/
1727 /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
1728 /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
1729 #endif
1730 /*@GNT_WL tx*/
1731 odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
1732
1733 /*@Mapping Table*/
1734 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1735 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);
1736 #if 0
1737 /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
1738 /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
1739 #endif
1740
1741 /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
1742 odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
1743 /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
1744 odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
1745 /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
1746 odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
1747 /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/
1748 odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
1749 /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */
1750 odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
1751
1752 /*OFDM HW AntDiv Parameters*/
1753 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
1754 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
1755 odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
1756
1757 /*@CCK HW AntDiv Parameters*/
1758 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1759 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1760 odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
1761
1762 odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
1763 odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
1764 odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
1765 odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
1766 odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
1767
1768 /*@disable antenna training */
1769 odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
1770 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1771 }
1772 /*@Mingzhi 2017-05-08*/
1773
odm_s0s1_sw_ant_div_init_8723d(void * dm_void)1774 void odm_s0s1_sw_ant_div_init_8723d(void *dm_void)
1775 {
1776 struct dm_struct *dm = (struct dm_struct *)dm_void;
1777 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
1778 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1779
1780 PHYDM_DBG(dm, DBG_ANT_DIV,
1781 "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
1782
1783 /*@keep antsel_map when GNT_BT = 1*/
1784 odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
1785
1786 /* @Disable antsw when GNT_BT=1 */
1787 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
1788
1789 /* @Mapping Table */
1790 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1791 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
1792
1793 /* Output Pin Settings */
1794 #if 0
1795 /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
1796 #endif
1797 odm_set_bb_reg(dm, R_0x870, BIT(8), 1);
1798 odm_set_bb_reg(dm, R_0x870, BIT(9), 1);
1799
1800 /* Status init */
1801 fat_tab->is_become_linked = false;
1802 swat_tab->try_flag = SWAW_STEP_INIT;
1803 swat_tab->double_chk_flag = 0;
1804 swat_tab->cur_antenna = MAIN_ANT;
1805 swat_tab->pre_ant = MAIN_ANT;
1806 dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
1807
1808 /* @2 [--For HW Bug setting] */
1809 odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */
1810 }
1811
odm_update_rx_idle_ant_8723d(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)1812 void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
1813 u32 optional_ant)
1814 {
1815 struct dm_struct *dm = (struct dm_struct *)dm_void;
1816 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1817 void *adapter = dm->adapter;
1818 u8 count = 0;
1819
1820 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1821 /*score board to BT ,a002:WL to do ant-div*/
1822 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);
1823 ODM_delay_us(50);
1824 #endif
1825 #if 0
1826 /* odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); */
1827 #endif
1828 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
1829 odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);
1830 odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);
1831 }
1832 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
1833 /*@Default RX*/
1834 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
1835 /*Optional RX*/
1836 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
1837 /*@Default TX*/
1838 fat_tab->rx_idle_ant = ant;
1839 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1840 /*score board to BT ,a000:WL@S1 a001:WL@S0*/
1841 if (default_ant == ANT1_2G)
1842 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);
1843 else
1844 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);
1845 #endif
1846 }
1847
phydm_set_tx_ant_pwr_8723d(void * dm_void,u8 ant)1848 void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant)
1849 {
1850 struct dm_struct *dm = (struct dm_struct *)dm_void;
1851 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1852 void *adapter = dm->adapter;
1853
1854 fat_tab->rx_idle_ant = ant;
1855
1856 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1857 ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
1858 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1859 rtw_hal_set_tx_power_level(adapter, *dm->channel);
1860 #endif
1861 }
1862 #endif
1863
1864 #if (RTL8723B_SUPPORT == 1)
odm_trx_hw_ant_div_init_8723b(void * dm_void)1865 void odm_trx_hw_ant_div_init_8723b(void *dm_void)
1866 {
1867 struct dm_struct *dm = (struct dm_struct *)dm_void;
1868
1869 PHYDM_DBG(dm, DBG_ANT_DIV,
1870 "***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
1871
1872 /* @Mapping Table */
1873 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1874 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
1875
1876 /* OFDM HW AntDiv Parameters */
1877 odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */
1878 odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */
1879
1880 /* @CCK HW AntDiv Parameters */
1881 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1882 /* patch for clk from 88M to 80M */
1883 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1884 /* @do 64 samples */
1885
1886 /* @BT Coexistence */
1887 odm_set_bb_reg(dm, R_0x864, BIT(12), 0);
1888 /* @keep antsel_map when GNT_BT = 1 */
1889 odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
1890 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1891
1892 /* Output Pin Settings */
1893 odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1894
1895 odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
1896 /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */
1897 odm_set_bb_reg(dm, R_0x948, BIT(7), 0);
1898
1899 odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
1900 odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
1901 odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
1902 /* select DPDT_P and DPDT_N as output pin */
1903
1904 odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */
1905 odm_set_bb_reg(dm, R_0x944, BIT(31), 0);
1906
1907 odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */
1908 odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */
1909
1910 odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */
1911 odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
1912
1913 /* @2 [--For HW Bug setting] */
1914 if (dm->ant_type == ODM_AUTO_ANT)
1915 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
1916 /* @CCK AntDiv function block enable */
1917 }
1918
odm_s0s1_sw_ant_div_init_8723b(void * dm_void)1919 void odm_s0s1_sw_ant_div_init_8723b(void *dm_void)
1920 {
1921 struct dm_struct *dm = (struct dm_struct *)dm_void;
1922 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
1923 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1924
1925 PHYDM_DBG(dm, DBG_ANT_DIV,
1926 "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
1927
1928 /* @Mapping Table */
1929 odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1930 odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
1931
1932 #if 0
1933 /* Output Pin Settings */
1934 /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
1935 #endif
1936 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1937
1938 fat_tab->is_become_linked = false;
1939 swat_tab->try_flag = SWAW_STEP_INIT;
1940 swat_tab->double_chk_flag = 0;
1941
1942 /* @2 [--For HW Bug setting] */
1943 odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */
1944 }
1945
odm_update_rx_idle_ant_8723b(void * dm_void,u8 ant,u32 default_ant,u32 optional_ant)1946 void odm_update_rx_idle_ant_8723b(
1947 void *dm_void,
1948 u8 ant,
1949 u32 default_ant,
1950 u32 optional_ant)
1951 {
1952 struct dm_struct *dm = (struct dm_struct *)dm_void;
1953 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1954 void *adapter = dm->adapter;
1955 u8 count = 0;
1956 /*u8 u1_temp;*/
1957 /*u8 h2c_parameter;*/
1958
1959 if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {
1960 PHYDM_DBG(dm, DBG_ANT_DIV,
1961 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
1962 return;
1963 }
1964
1965 #if 0
1966 /* Send H2C command to FW */
1967 /* @Enable wifi calibration */
1968 h2c_parameter = true;
1969 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1970
1971 /* @Check if H2C command sucess or not (0x1e6) */
1972 u1_temp = odm_read_1byte(dm, 0x1e6);
1973 while ((u1_temp != 0x1) && (count < 100)) {
1974 ODM_delay_us(10);
1975 u1_temp = odm_read_1byte(dm, 0x1e6);
1976 count++;
1977 }
1978 PHYDM_DBG(dm, DBG_ANT_DIV,
1979 "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n",
1980 u1_temp, count);
1981
1982 if (u1_temp == 0x1) {
1983 /* @Check if BT is doing IQK (0x1e7) */
1984 count = 0;
1985 u1_temp = odm_read_1byte(dm, 0x1e7);
1986 while ((!(u1_temp & BIT(0))) && (count < 100)) {
1987 ODM_delay_us(50);
1988 u1_temp = odm_read_1byte(dm, 0x1e7);
1989 count++;
1990 }
1991 PHYDM_DBG(dm, DBG_ANT_DIV,
1992 "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n",
1993 u1_temp, count);
1994
1995 if (u1_temp & BIT(0)) {
1996 odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
1997 odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
1998 odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);
1999 /* @Default RX */
2000 odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
2001 /* @Optional RX */
2002 odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
2003 /* @Default TX */
2004 fat_tab->rx_idle_ant = ant;
2005
2006 /* Set TX AGC by S0/S1 */
2007 /* Need to consider Linux driver */
2008 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2009 adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
2010 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2011 rtw_hal_set_tx_power_level(adapter, *dm->channel);
2012 #endif
2013
2014 /* Set IQC by S0/S1 */
2015 odm_set_iqc_by_rfpath(dm, default_ant);
2016 PHYDM_DBG(dm, DBG_ANT_DIV,
2017 "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
2018 } else
2019 PHYDM_DBG(dm, DBG_ANT_DIV,
2020 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
2021 } else
2022 PHYDM_DBG(dm, DBG_ANT_DIV,
2023 "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
2024
2025 /* Send H2C command to FW */
2026 /* @Disable wifi calibration */
2027 h2c_parameter = false;
2028 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
2029 #else
2030
2031 odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
2032 odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
2033 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
2034 /*@Default RX*/
2035 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
2036 /*Optional RX*/
2037 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
2038 /*@Default TX*/
2039 fat_tab->rx_idle_ant = ant;
2040
2041 /* Set TX AGC by S0/S1 */
2042 /* Need to consider Linux driver */
2043 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2044 ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
2045 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2046 rtw_hal_set_tx_power_level(adapter, *dm->channel);
2047 #endif
2048
2049 /* Set IQC by S0/S1 */
2050 odm_set_iqc_by_rfpath(dm, default_ant);
2051 PHYDM_DBG(dm, DBG_ANT_DIV,
2052 "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
2053
2054 #endif
2055 }
2056
2057 boolean
phydm_is_bt_enable_8723b(void * dm_void)2058 phydm_is_bt_enable_8723b(void *dm_void)
2059 {
2060 struct dm_struct *dm = (struct dm_struct *)dm_void;
2061 u32 bt_state;
2062 #if 0
2063 /*u32 reg75;*/
2064
2065 /*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/
2066 /*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/
2067 #endif
2068 odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
2069 bt_state = odm_get_bb_reg(dm, R_0xa0, 0xf);
2070 #if 0
2071 /*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/
2072 #endif
2073
2074 if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)
2075 return true;
2076 else
2077 return false;
2078 }
2079 #endif /* @#if (RTL8723B_SUPPORT == 1) */
2080
2081 #if (RTL8821A_SUPPORT == 1)
2082
odm_trx_hw_ant_div_init_8821a(void * dm_void)2083 void odm_trx_hw_ant_div_init_8821a(void *dm_void)
2084 {
2085 struct dm_struct *dm = (struct dm_struct *)dm_void;
2086
2087 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2088
2089 /* Output Pin Settings */
2090 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2091
2092 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2093 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2094
2095 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2096
2097 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2098 /* select DPDT_P and DPDT_N as output pin */
2099 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2100 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2101 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2102 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2103 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2104
2105 /* @Mapping Table */
2106 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2107 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2108
2109 /* OFDM HW AntDiv Parameters */
2110 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2111 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2112
2113 /* @CCK HW AntDiv Parameters */
2114 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2115 /* patch for clk from 88M to 80M */
2116 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2117
2118 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2119 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2120 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2121 /* @CCK AntDiv function block enable */
2122
2123 /* @BT Coexistence */
2124 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2125 /* @keep antsel_map when GNT_BT = 1 */
2126 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2127 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2128
2129 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2130 /* settling time of antdiv by RF LNA = 100ns */
2131
2132 /* response TX ant by RX ant */
2133 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2134 }
2135
odm_s0s1_sw_ant_div_init_8821a(void * dm_void)2136 void odm_s0s1_sw_ant_div_init_8821a(void *dm_void)
2137 {
2138 struct dm_struct *dm = (struct dm_struct *)dm_void;
2139 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2140
2141 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2142
2143 /* Output Pin Settings */
2144 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2145
2146 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2147 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2148
2149 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2150
2151 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2152 /* select DPDT_P and DPDT_N as output pin */
2153 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2154 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2155 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2156 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2157 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2158
2159 /* @Mapping Table */
2160 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2161 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2162
2163 /* OFDM HW AntDiv Parameters */
2164 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2165 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2166
2167 /* @CCK HW AntDiv Parameters */
2168 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2169 /* patch for clk from 88M to 80M */
2170 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2171
2172 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2173 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2174 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2175 /* @CCK AntDiv function block enable */
2176
2177 /* @BT Coexistence */
2178 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2179 /* @keep antsel_map when GNT_BT = 1 */
2180 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2181 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2182
2183 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2184 /* settling time of antdiv by RF LNA = 100ns */
2185
2186 /* response TX ant by RX ant */
2187 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2188
2189 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2190
2191 swat_tab->try_flag = SWAW_STEP_INIT;
2192 swat_tab->double_chk_flag = 0;
2193 swat_tab->cur_antenna = MAIN_ANT;
2194 swat_tab->pre_ant = MAIN_ANT;
2195 swat_tab->swas_no_link_state = 0;
2196 }
2197 #endif /* @#if (RTL8821A_SUPPORT == 1) */
2198
2199 #if (RTL8821C_SUPPORT == 1)
odm_trx_hw_ant_div_init_8821c(void * dm_void)2200 void odm_trx_hw_ant_div_init_8821c(void *dm_void)
2201 {
2202 struct dm_struct *dm = (struct dm_struct *)dm_void;
2203
2204 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2205 /* Output Pin Settings */
2206 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2207
2208 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2209 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2210
2211 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2212
2213 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2214 /* select DPDT_P and DPDT_N as output pin */
2215 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2216 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2217 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2218 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2219 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2220
2221 /* @Mapping Table */
2222 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2223 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2224
2225 /* OFDM HW AntDiv Parameters */
2226 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2227 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
2228
2229 /* @CCK HW AntDiv Parameters */
2230 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2231 /* patch for clk from 88M to 80M */
2232 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2233
2234 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2235 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2236 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2237 /* @CCK AntDiv function block enable */
2238
2239 /* @BT Coexistence */
2240 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2241 /* @keep antsel_map when GNT_BT = 1 */
2242 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2243 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2244
2245 /* Timming issue */
2246 odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);
2247 /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
2248 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2249 /* settling time of antdiv by RF LNA = 100ns */
2250
2251 /* response TX ant by RX ant */
2252 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2253 }
2254
phydm_s0s1_sw_ant_div_init_8821c(void * dm_void)2255 void phydm_s0s1_sw_ant_div_init_8821c(void *dm_void)
2256 {
2257 struct dm_struct *dm = (struct dm_struct *)dm_void;
2258 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2259
2260 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2261
2262 /* Output Pin Settings */
2263 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2264
2265 odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
2266 odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
2267
2268 odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
2269
2270 odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
2271 /* select DPDT_P and DPDT_N as output pin */
2272 odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
2273 odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
2274 odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
2275 odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
2276 odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
2277
2278 /* @Mapping Table */
2279 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2280 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2281
2282 /* OFDM HW AntDiv Parameters */
2283 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2284 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */
2285
2286 /* @CCK HW AntDiv Parameters */
2287 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2288 /* patch for clk from 88M to 80M */
2289 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2290
2291 odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
2292 /* @ANTSEL_CCK sent to the smart_antenna circuit */
2293 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
2294 /* @CCK AntDiv function block enable */
2295
2296 /* @BT Coexistence */
2297 odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
2298 /* @keep antsel_map when GNT_BT = 1 */
2299 odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
2300 /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
2301
2302 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2303 /* settling time of antdiv by RF LNA = 100ns */
2304
2305 /* response TX ant by RX ant */
2306 odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
2307
2308 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2309
2310 swat_tab->try_flag = SWAW_STEP_INIT;
2311 swat_tab->double_chk_flag = 0;
2312 swat_tab->cur_antenna = MAIN_ANT;
2313 swat_tab->pre_ant = MAIN_ANT;
2314 swat_tab->swas_no_link_state = 0;
2315 }
2316 #endif /* @#if (RTL8821C_SUPPORT == 1) */
2317
2318 #if (RTL8881A_SUPPORT == 1)
odm_trx_hw_ant_div_init_8881a(void * dm_void)2319 void odm_trx_hw_ant_div_init_8881a(void *dm_void)
2320 {
2321 struct dm_struct *dm = (struct dm_struct *)dm_void;
2322
2323 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2324
2325 /* Output Pin Settings */
2326 /* @[SPDT related] */
2327 odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
2328 odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
2329 odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
2330 odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);
2331 odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);
2332 odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */
2333 odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */
2334
2335 /* @Mapping Table */
2336 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2337 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2338
2339 /* OFDM HW AntDiv Parameters */
2340 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2341 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
2342 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2343 /* settling time of antdiv by RF LNA = 100ns */
2344
2345 /* @CCK HW AntDiv Parameters */
2346 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2347 /* patch for clk from 88M to 80M */
2348 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2349
2350 /* @2 [--For HW Bug setting] */
2351
2352 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2353 /* TX ant by Reg *//* A-cut bug */
2354 }
2355
2356 #endif /* @#if (RTL8881A_SUPPORT == 1) */
2357
2358 #if (RTL8812A_SUPPORT == 1)
odm_trx_hw_ant_div_init_8812a(void * dm_void)2359 void odm_trx_hw_ant_div_init_8812a(void *dm_void)
2360 {
2361 struct dm_struct *dm = (struct dm_struct *)dm_void;
2362
2363 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2364
2365 /* @3 */ /* @3 --RFE pin setting--------- */
2366 /* @[BB] */
2367 odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0);
2368 /* @disable SW switch */
2369 odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);
2370 odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */
2371 odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
2372 odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);
2373 odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);
2374 odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */
2375 odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */
2376 /* @3 ------------------------- */
2377
2378 /* @Mapping Table */
2379 odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2380 odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2381
2382 /* OFDM HW AntDiv Parameters */
2383 odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2384 odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
2385 odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
2386 /* settling time of antdiv by RF LNA = 100ns */
2387
2388 /* @CCK HW AntDiv Parameters */
2389 odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
2390 /* patch for clk from 88M to 80M */
2391 odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2392
2393 /* @2 [--For HW Bug setting] */
2394
2395 odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
2396 /* TX ant by Reg */ /* A-cut bug */
2397 }
2398
2399 #endif /* @#if (RTL8812A_SUPPORT == 1) */
2400
2401 #if (RTL8188F_SUPPORT == 1)
odm_s0s1_sw_ant_div_init_8188f(void * dm_void)2402 void odm_s0s1_sw_ant_div_init_8188f(void *dm_void)
2403 {
2404 struct dm_struct *dm = (struct dm_struct *)dm_void;
2405 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
2406 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2407
2408 PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
2409
2410 #if 0
2411 /*@GPIO setting*/
2412 /*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */
2413 /*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/
2414 /*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/
2415 /*enable_output for P_GPIO[4:3]*/
2416 /*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
2417 /*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
2418 #endif
2419
2420 if (dm->support_ic_type == ODM_RTL8188F) {
2421 if (dm->support_interface == ODM_ITRF_USB)
2422 odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);
2423 /*@enable_output for P_GPIO[4:3]*/
2424 else if (dm->support_interface == ODM_ITRF_SDIO)
2425 odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1);
2426 /*@enable_output for P_GPIO[2]*/
2427 }
2428
2429 fat_tab->is_become_linked = false;
2430 swat_tab->try_flag = SWAW_STEP_INIT;
2431 swat_tab->double_chk_flag = 0;
2432 }
2433
phydm_update_rx_idle_antenna_8188F(void * dm_void,u32 default_ant)2434 void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant)
2435 {
2436 struct dm_struct *dm = (struct dm_struct *)dm_void;
2437 u8 codeword;
2438
2439 if (dm->support_ic_type == ODM_RTL8188F) {
2440 if (dm->support_interface == ODM_ITRF_USB) {
2441 if (default_ant == ANT1_2G)
2442 codeword = 1; /*@2'b01*/
2443 else
2444 codeword = 2; /*@2'b10*/
2445 odm_set_mac_reg(dm, R_0x44, 0x1800, codeword);
2446 /*@GPIO[4:3] output value*/
2447 } else if (dm->support_interface == ODM_ITRF_SDIO) {
2448 if (default_ant == ANT1_2G) {
2449 codeword = 0; /*@1'b0*/
2450 odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
2451 odm_set_bb_reg(dm, R_0x860, 0x300, 0x1);
2452 } else {
2453 codeword = 1; /*@1'b1*/
2454 odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
2455 odm_set_bb_reg(dm, R_0x860, 0x300, 0x2);
2456 }
2457 odm_set_mac_reg(dm, R_0x44, BIT(10), codeword);
2458 /*@GPIO[2] output value*/
2459 }
2460 }
2461 }
2462 #endif
2463
2464 #ifdef ODM_EVM_ENHANCE_ANTDIV
phydm_rx_rate_for_antdiv(void * dm_void,void * pkt_info_void)2465 void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void)
2466 {
2467 struct dm_struct *dm = (struct dm_struct *)dm_void;
2468 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2469 struct phydm_perpkt_info_struct *pktinfo = NULL;
2470 u8 data_rate = 0;
2471
2472 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
2473 data_rate = pktinfo->data_rate & 0x7f;
2474
2475 if (!fat_tab->get_stats)
2476 return;
2477
2478 if (fat_tab->antsel_rx_keep_0 == ANT1_2G) {
2479 if (data_rate >= ODM_RATEMCS0 &&
2480 data_rate <= ODM_RATEMCS15)
2481 fat_tab->main_ht_cnt[data_rate - ODM_RATEMCS0]++;
2482 else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
2483 data_rate <= ODM_RATEVHTSS2MCS9)
2484 fat_tab->main_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
2485 } else { /*ANT2_2G*/
2486 if (data_rate >= ODM_RATEMCS0 &&
2487 data_rate <= ODM_RATEMCS15)
2488 fat_tab->aux_ht_cnt[data_rate - ODM_RATEMCS0]++;
2489 else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
2490 data_rate <= ODM_RATEVHTSS2MCS9)
2491 fat_tab->aux_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
2492 }
2493 }
2494
phydm_antdiv_reset_rx_rate(void * dm_void)2495 void phydm_antdiv_reset_rx_rate(void *dm_void)
2496 {
2497 struct dm_struct *dm = (struct dm_struct *)dm_void;
2498 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2499
2500 odm_memory_set(dm, &fat_tab->main_ht_cnt[0], 0, HT_IDX * 2);
2501 odm_memory_set(dm, &fat_tab->aux_ht_cnt[0], 0, HT_IDX * 2);
2502 odm_memory_set(dm, &fat_tab->main_vht_cnt[0], 0, VHT_IDX * 2);
2503 odm_memory_set(dm, &fat_tab->aux_vht_cnt[0], 0, VHT_IDX * 2);
2504 }
2505
phydm_statistics_evm_1ss(void * dm_void,void * phy_info_void,u8 antsel_tr_mux,u32 id,u32 utility)2506 void phydm_statistics_evm_1ss(void *dm_void, void *phy_info_void,
2507 u8 antsel_tr_mux, u32 id, u32 utility)
2508 {
2509 struct dm_struct *dm = (struct dm_struct *)dm_void;
2510 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2511 struct phydm_phyinfo_struct *phy_info = NULL;
2512
2513 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
2514 if (antsel_tr_mux == ANT1_2G) {
2515 fat_tab->main_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
2516 << 5);
2517 fat_tab->main_evm_cnt[id]++;
2518 } else {
2519 fat_tab->aux_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
2520 << 5);
2521 fat_tab->aux_evm_cnt[id]++;
2522 }
2523 }
2524
phydm_statistics_evm_2ss(void * dm_void,void * phy_info_void,u8 antsel_tr_mux,u32 id,u32 utility)2525 void phydm_statistics_evm_2ss(void *dm_void, void *phy_info_void,
2526 u8 antsel_tr_mux, u32 id, u32 utility)
2527 {
2528 struct dm_struct *dm = (struct dm_struct *)dm_void;
2529 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2530 struct phydm_phyinfo_struct *phy_info = NULL;
2531
2532 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
2533 if (antsel_tr_mux == ANT1_2G) {
2534 fat_tab->main_evm_2ss_sum[id][0] += phy_info->rx_mimo_evm_dbm[0]
2535 << 5;
2536 fat_tab->main_evm_2ss_sum[id][1] += phy_info->rx_mimo_evm_dbm[1]
2537 << 5;
2538 fat_tab->main_evm_2ss_cnt[id]++;
2539
2540 } else {
2541 fat_tab->aux_evm_2ss_sum[id][0] += (phy_info->rx_mimo_evm_dbm[0]
2542 << 5);
2543 fat_tab->aux_evm_2ss_sum[id][1] += (phy_info->rx_mimo_evm_dbm[1]
2544 << 5);
2545 fat_tab->aux_evm_2ss_cnt[id]++;
2546 }
2547 }
2548
phydm_evm_sw_antdiv_init(void * dm_void)2549 void phydm_evm_sw_antdiv_init(void *dm_void)
2550 {
2551 struct dm_struct *dm = (struct dm_struct *)dm_void;
2552 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2553
2554 /*@EVM enhance AntDiv method init----------------*/
2555 fat_tab->evm_method_enable = 0;
2556 fat_tab->fat_state = NORMAL_STATE_MIAN;
2557 fat_tab->fat_state_cnt = 0;
2558 fat_tab->pre_antdiv_rssi = 0;
2559
2560 dm->antdiv_intvl = 30;
2561 dm->antdiv_delay = 20;
2562 dm->antdiv_train_num = 4;
2563 if (dm->support_ic_type & ODM_RTL8192E)
2564 odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);
2565 dm->antdiv_evm_en = 1;
2566 /*@dm->antdiv_period=1;*/
2567 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2568 dm->evm_antdiv_period = 1;
2569 #else
2570 dm->evm_antdiv_period = 3;
2571 #endif
2572 dm->stop_antdiv_rssi_th = 3;
2573 dm->stop_antdiv_tp_th = 80;
2574 dm->antdiv_tp_period = 3;
2575 dm->stop_antdiv_tp_diff_th = 5;
2576 }
2577
odm_evm_fast_ant_reset(void * dm_void)2578 void odm_evm_fast_ant_reset(void *dm_void)
2579 {
2580 struct dm_struct *dm = (struct dm_struct *)dm_void;
2581 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2582
2583 fat_tab->evm_method_enable = 0;
2584 if (fat_tab->div_path_type == ANT_PATH_A)
2585 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
2586 else if (fat_tab->div_path_type == ANT_PATH_B)
2587 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
2588 else if (fat_tab->div_path_type == ANT_PATH_AB)
2589 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
2590 fat_tab->fat_state = NORMAL_STATE_MIAN;
2591 fat_tab->fat_state_cnt = 0;
2592 dm->antdiv_period = 0;
2593 odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
2594 }
2595
odm_evm_enhance_ant_div(void * dm_void)2596 void odm_evm_enhance_ant_div(void *dm_void)
2597 {
2598 struct dm_struct *dm = (struct dm_struct *)dm_void;
2599 u32 main_rssi, aux_rssi;
2600 u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
2601 u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
2602 u32 main_2ss_evm[2], aux_2ss_evm[2];
2603 u32 main_1ss_evm, aux_1ss_evm;
2604 u32 main_2ss_evm_sum, aux_2ss_evm_sum;
2605 u8 score_EVM = 0, score_CRC = 0;
2606 u8 rssi_larger_ant = 0;
2607 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2608 u32 value32, i, mac_id;
2609 boolean main_above1 = false, aux_above1 = false;
2610 boolean force_antenna = false;
2611 struct cmn_sta_info *sta;
2612 u32 main_tp_avg, aux_tp_avg;
2613 u8 curr_rssi, rssi_diff;
2614 u32 tp_diff, tp_diff_avg;
2615 u16 main_max_cnt = 0, aux_max_cnt = 0;
2616 u16 main_max_idx = 0, aux_max_idx = 0;
2617 u16 main_cnt_all = 0, aux_cnt_all = 0;
2618 u8 rate_num = dm->num_rf_path;
2619 u8 rate_ss_shift = 0;
2620 u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
2621 u8 target_ant_evm_1ss, target_ant_evm_2ss;
2622 u8 decision_evm_ss;
2623 u8 next_ant;
2624
2625 fat_tab->target_ant_enhance = 0xFF;
2626
2627 if ((dm->support_ic_type & ODM_EVM_ANTDIV_IC)) {
2628 if (dm->is_one_entry_only) {
2629 #if 0
2630 /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
2631 #endif
2632 mac_id = dm->one_entry_macid;
2633 sta = dm->phydm_sta_info[mac_id];
2634
2635 main_rssi = (fat_tab->main_cnt[mac_id] != 0) ? (fat_tab->main_sum[mac_id] / fat_tab->main_cnt[mac_id]) : 0;
2636 aux_rssi = (fat_tab->aux_cnt[mac_id] != 0) ? (fat_tab->aux_sum[mac_id] / fat_tab->aux_cnt[mac_id]) : 0;
2637
2638 if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
2639 diff_rssi = FORCE_RSSI_DIFF;
2640 else if (main_rssi != 0 && aux_rssi != 0)
2641 diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
2642
2643 if (main_rssi >= aux_rssi)
2644 rssi_larger_ant = MAIN_ANT;
2645 else
2646 rssi_larger_ant = AUX_ANT;
2647
2648 PHYDM_DBG(dm, DBG_ANT_DIV,
2649 "Main_Cnt=(( %d )), main_rssi=(( %d ))\n",
2650 fat_tab->main_cnt[mac_id], main_rssi);
2651 PHYDM_DBG(dm, DBG_ANT_DIV,
2652 "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n",
2653 fat_tab->aux_cnt[mac_id], aux_rssi);
2654
2655 if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)
2656 /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */
2657 ) {
2658 PHYDM_DBG(dm, DBG_ANT_DIV,
2659 "> TH_H || evm_method_enable==1\n");
2660
2661 if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {
2662 PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
2663
2664 /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
2665 if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {
2666 if (fat_tab->fat_state_cnt == 0) {
2667 /*Reset EVM 1SS Method */
2668 fat_tab->main_evm_sum[mac_id] = 0;
2669 fat_tab->aux_evm_sum[mac_id] = 0;
2670 fat_tab->main_evm_cnt[mac_id] = 0;
2671 fat_tab->aux_evm_cnt[mac_id] = 0;
2672 /*Reset EVM 2SS Method */
2673 fat_tab->main_evm_2ss_sum[mac_id][0] = 0;
2674 fat_tab->main_evm_2ss_sum[mac_id][1] = 0;
2675 fat_tab->aux_evm_2ss_sum[mac_id][0] = 0;
2676 fat_tab->aux_evm_2ss_sum[mac_id][1] = 0;
2677 fat_tab->main_evm_2ss_cnt[mac_id] = 0;
2678 fat_tab->aux_evm_2ss_cnt[mac_id] = 0;
2679
2680 /*Reset TP Method */
2681 fat_tab->main_tp = 0;
2682 fat_tab->aux_tp = 0;
2683 fat_tab->main_tp_cnt = 0;
2684 fat_tab->aux_tp_cnt = 0;
2685 phydm_antdiv_reset_rx_rate(dm);
2686
2687 /*Reset CRC Method */
2688 fat_tab->main_crc32_ok_cnt = 0;
2689 fat_tab->main_crc32_fail_cnt = 0;
2690 fat_tab->aux_crc32_ok_cnt = 0;
2691 fat_tab->aux_crc32_fail_cnt = 0;
2692
2693 #ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
2694 if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {
2695 /*@1. Skip training: RSSI*/
2696 #if 0
2697 /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
2698 #endif
2699 curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
2700 rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
2701
2702 PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
2703
2704 fat_tab->pre_antdiv_rssi = curr_rssi;
2705 if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)
2706 rssi_return = 1;
2707
2708 /*@2. Skip training: TP Diff*/
2709 tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
2710
2711 PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
2712 fat_tab->pre_antdiv_tp = dm->rx_tp;
2713 if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))
2714 tp_diff_return = 1;
2715
2716 PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
2717 /*@3. Skip training: TP*/
2718 if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
2719 tp_return = 1;
2720
2721 PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
2722 /*@4. Joint Return Decision*/
2723 if (tp_return) {
2724 if (tp_diff_return || rssi_diff) {
2725 PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
2726 return;
2727 }
2728 }
2729 }
2730 #endif
2731
2732 fat_tab->evm_method_enable = 1;
2733 if (fat_tab->div_path_type == ANT_PATH_A)
2734 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
2735 else if (fat_tab->div_path_type == ANT_PATH_B)
2736 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
2737 else if (fat_tab->div_path_type == ANT_PATH_AB)
2738 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
2739 dm->antdiv_period = dm->evm_antdiv_period;
2740 odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
2741 fat_tab->fat_state_cnt++;
2742 fat_tab->get_stats = false;
2743 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
2744 odm_update_rx_idle_ant(dm, next_ant);
2745 PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
2746 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
2747 } else if ((fat_tab->fat_state_cnt % 2) != 0) {
2748 fat_tab->fat_state_cnt++;
2749 fat_tab->get_stats = true;
2750 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
2751 } else if ((fat_tab->fat_state_cnt % 2) == 0) {
2752 fat_tab->fat_state_cnt++;
2753 fat_tab->get_stats = false;
2754 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
2755 odm_update_rx_idle_ant(dm, next_ant);
2756 PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
2757 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
2758 }
2759 }
2760 /*@Decision state: 4==============================================================*/
2761 else {
2762 fat_tab->get_stats = false;
2763 fat_tab->fat_state_cnt = 0;
2764 PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
2765
2766 /* @3 [CRC32 statistic] */
2767 #if 0
2768 if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {
2769 fat_tab->target_ant_crc32 = MAIN_ANT;
2770 force_antenna = true;
2771 PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
2772 } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
2773 fat_tab->target_ant_crc32 = AUX_ANT;
2774 force_antenna = true;
2775 PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
2776 } else
2777 #endif
2778 {
2779 if (fat_tab->main_crc32_fail_cnt <= 5)
2780 fat_tab->main_crc32_fail_cnt = 5;
2781
2782 if (fat_tab->aux_crc32_fail_cnt <= 5)
2783 fat_tab->aux_crc32_fail_cnt = 5;
2784
2785 if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
2786 main_above1 = true;
2787
2788 if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
2789 aux_above1 = true;
2790
2791 if (main_above1 == true && aux_above1 == false) {
2792 force_antenna = true;
2793 fat_tab->target_ant_crc32 = MAIN_ANT;
2794 } else if (main_above1 == false && aux_above1 == true) {
2795 force_antenna = true;
2796 fat_tab->target_ant_crc32 = AUX_ANT;
2797 } else if (main_above1 == true && aux_above1 == true) {
2798 main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
2799 aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
2800 fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
2801
2802 if (main_crc_utility != 0 && aux_crc_utility != 0) {
2803 if (main_crc_utility >= aux_crc_utility)
2804 utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
2805 else
2806 utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
2807 }
2808 } else if (main_above1 == false && aux_above1 == false) {
2809 if (fat_tab->main_crc32_ok_cnt == 0)
2810 fat_tab->main_crc32_ok_cnt = 1;
2811 if (fat_tab->aux_crc32_ok_cnt == 0)
2812 fat_tab->aux_crc32_ok_cnt = 1;
2813
2814 main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
2815 aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
2816 fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
2817
2818 if (main_crc_utility != 0 && aux_crc_utility != 0) {
2819 if (main_crc_utility >= aux_crc_utility)
2820 utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
2821 else
2822 utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
2823 }
2824 }
2825 }
2826 odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */
2827 PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
2828 PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
2829 PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2830
2831 for (i = 0; i < HT_IDX; i++) {
2832 main_cnt_all += fat_tab->main_ht_cnt[i];
2833 aux_cnt_all += fat_tab->aux_ht_cnt[i];
2834
2835 if (fat_tab->main_ht_cnt[i] > main_max_cnt) {
2836 main_max_cnt = fat_tab->main_ht_cnt[i];
2837 main_max_idx = i;
2838 }
2839
2840 if (fat_tab->aux_ht_cnt[i] > aux_max_cnt) {
2841 aux_max_cnt = fat_tab->aux_ht_cnt[i];
2842 aux_max_idx = i;
2843 }
2844 }
2845
2846 for (i = 0; i < rate_num; i++) {
2847 rate_ss_shift = (i << 3);
2848 PHYDM_DBG(dm, DBG_ANT_DIV, "*main_ht_cnt HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
2849 (rate_ss_shift), (rate_ss_shift + 7),
2850 fat_tab->main_ht_cnt[rate_ss_shift + 0], fat_tab->main_ht_cnt[rate_ss_shift + 1],
2851 fat_tab->main_ht_cnt[rate_ss_shift + 2], fat_tab->main_ht_cnt[rate_ss_shift + 3],
2852 fat_tab->main_ht_cnt[rate_ss_shift + 4], fat_tab->main_ht_cnt[rate_ss_shift + 5],
2853 fat_tab->main_ht_cnt[rate_ss_shift + 6], fat_tab->main_ht_cnt[rate_ss_shift + 7]);
2854 }
2855
2856 for (i = 0; i < rate_num; i++) {
2857 rate_ss_shift = (i << 3);
2858 PHYDM_DBG(dm, DBG_ANT_DIV, "*aux_ht_cnt HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
2859 (rate_ss_shift), (rate_ss_shift + 7),
2860 fat_tab->aux_ht_cnt[rate_ss_shift + 0], fat_tab->aux_ht_cnt[rate_ss_shift + 1],
2861 fat_tab->aux_ht_cnt[rate_ss_shift + 2], fat_tab->aux_ht_cnt[rate_ss_shift + 3],
2862 fat_tab->aux_ht_cnt[rate_ss_shift + 4], fat_tab->aux_ht_cnt[rate_ss_shift + 5],
2863 fat_tab->aux_ht_cnt[rate_ss_shift + 6], fat_tab->aux_ht_cnt[rate_ss_shift + 7]);
2864 }
2865
2866 /* @3 [EVM statistic] */
2867 /*@1SS EVM*/
2868 main_1ss_evm = (fat_tab->main_evm_cnt[mac_id] != 0) ? (fat_tab->main_evm_sum[mac_id] / fat_tab->main_evm_cnt[mac_id]) : 0;
2869 aux_1ss_evm = (fat_tab->aux_evm_cnt[mac_id] != 0) ? (fat_tab->aux_evm_sum[mac_id] / fat_tab->aux_evm_cnt[mac_id]) : 0;
2870 target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
2871
2872 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", fat_tab->main_evm_cnt[mac_id], main_1ss_evm);
2873 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", fat_tab->aux_evm_cnt[mac_id], aux_1ss_evm);
2874
2875 /*@2SS EVM*/
2876 main_2ss_evm[0] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][0] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
2877 main_2ss_evm[1] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][1] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
2878 main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
2879
2880 aux_2ss_evm[0] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][0] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
2881 aux_2ss_evm[1] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][1] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
2882 aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
2883
2884 target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
2885
2886 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
2887 fat_tab->main_evm_2ss_cnt[mac_id], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
2888 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
2889 fat_tab->aux_evm_2ss_cnt[mac_id], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
2890
2891 if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
2892 decision_evm_ss = 2;
2893 main_evm = main_2ss_evm_sum;
2894 aux_evm = aux_2ss_evm_sum;
2895 fat_tab->target_ant_evm = target_ant_evm_2ss;
2896 } else {
2897 decision_evm_ss = 1;
2898 main_evm = main_1ss_evm;
2899 aux_evm = aux_1ss_evm;
2900 fat_tab->target_ant_evm = target_ant_evm_1ss;
2901 }
2902
2903 if ((main_evm == 0 || aux_evm == 0))
2904 diff_EVM = 100;
2905 else if (main_evm >= aux_evm)
2906 diff_EVM = main_evm - aux_evm;
2907 else
2908 diff_EVM = aux_evm - main_evm;
2909
2910 PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2911
2912 //3 [TP statistic]
2913 main_tp_avg = (fat_tab->main_tp_cnt != 0) ? (fat_tab->main_tp / fat_tab->main_tp_cnt) : 0;
2914 aux_tp_avg = (fat_tab->aux_tp_cnt != 0) ? (fat_tab->aux_tp / fat_tab->aux_tp_cnt) : 0;
2915 tp_diff_avg = DIFF_2(main_tp_avg, aux_tp_avg);
2916 fat_tab->target_ant_tp = (tp_diff_avg < 100) ? (fat_tab->pre_target_ant_enhance) : ((main_tp_avg >= aux_tp_avg) ? MAIN_ANT : AUX_ANT);
2917
2918 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->main_tp_cnt, main_tp_avg);
2919 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->aux_tp_cnt, aux_tp_avg);
2920 PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2921
2922 /*Reset TP Method */
2923 fat_tab->main_tp = 0;
2924 fat_tab->aux_tp = 0;
2925 fat_tab->main_tp_cnt = 0;
2926 fat_tab->aux_tp_cnt = 0;
2927
2928 /* @2 [ Decision state ] */
2929 #if 1
2930 if (main_max_idx == aux_max_idx && ((main_cnt_all + aux_cnt_all) != 0)) {
2931 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision EVM, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
2932 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2933 } else {
2934 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision TP, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
2935 fat_tab->target_ant_enhance = fat_tab->target_ant_tp;
2936 }
2937 #else
2938 if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
2939 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2940
2941 if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
2942 fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
2943 else
2944 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2945 }
2946 #if 0
2947 else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
2948 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2949 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
2950 }
2951 #endif
2952 else if (diff_EVM >= 20) {
2953 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2954 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2955 } else if (utility_ratio >= 6 && force_antenna == false) {
2956 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2957 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
2958 } else {
2959 PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2960
2961 if (force_antenna == true)
2962 score_CRC = 2;
2963 else if (utility_ratio >= 5) /*@>2.5*/
2964 score_CRC = 2;
2965 else if (utility_ratio >= 4) /*@>2*/
2966 score_CRC = 1;
2967 else
2968 score_CRC = 0;
2969
2970 if (diff_EVM >= 15)
2971 score_EVM = 3;
2972 else if (diff_EVM >= 10)
2973 score_EVM = 2;
2974 else if (diff_EVM >= 5)
2975 score_EVM = 1;
2976 else
2977 score_EVM = 0;
2978
2979 if (score_CRC > score_EVM)
2980 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
2981 else if (score_CRC < score_EVM)
2982 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2983 else
2984 fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
2985 }
2986 #endif
2987 fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
2988
2989 PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2990 }
2991 } else { /* RSSI< = evm_rssi_th_low */
2992 PHYDM_DBG(dm, DBG_ANT_DIV, "[ <TH_L: escape from > TH_L ]\n");
2993 odm_evm_fast_ant_reset(dm);
2994 }
2995 } else {
2996 PHYDM_DBG(dm, DBG_ANT_DIV,
2997 "[escape from> TH_H || evm_method_enable==1]\n");
2998 odm_evm_fast_ant_reset(dm);
2999 }
3000 } else {
3001 PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n");
3002 odm_evm_fast_ant_reset(dm);
3003 }
3004 }
3005 }
3006
3007 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_evm_antdiv_callback(struct phydm_timer_list * timer)3008 void phydm_evm_antdiv_callback(
3009 struct phydm_timer_list *timer)
3010 {
3011 void *adapter = (void *)timer->Adapter;
3012 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3013 struct dm_struct *dm = &hal_data->DM_OutSrc;
3014
3015 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
3016 #if USE_WORKITEM
3017 odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
3018 #else
3019 {
3020 odm_hw_ant_div(dm);
3021 }
3022 #endif
3023 #else
3024 odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
3025 #endif
3026 }
3027
phydm_evm_antdiv_workitem_callback(void * context)3028 void phydm_evm_antdiv_workitem_callback(
3029 void *context)
3030 {
3031 void *adapter = (void *)context;
3032 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3033 struct dm_struct *dm = &hal_data->DM_OutSrc;
3034
3035 odm_hw_ant_div(dm);
3036 }
3037
3038 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_evm_antdiv_callback(void * dm_void)3039 void phydm_evm_antdiv_callback(void *dm_void)
3040 {
3041 struct dm_struct *dm = (struct dm_struct *)dm_void;
3042 void *padapter = dm->adapter;
3043
3044 if (*dm->is_net_closed)
3045 return;
3046 if (dm->support_interface == ODM_ITRF_PCIE) {
3047 odm_hw_ant_div(dm);
3048 } else {
3049 /* @Can't do I/O in timer callback*/
3050 phydm_run_in_thread_cmd(dm,
3051 phydm_evm_antdiv_workitem_callback,
3052 padapter);
3053 }
3054 }
3055
phydm_evm_antdiv_workitem_callback(void * context)3056 void phydm_evm_antdiv_workitem_callback(void *context)
3057 {
3058 void *adapter = (void *)context;
3059 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3060 struct dm_struct *dm = &hal_data->odmpriv;
3061
3062 odm_hw_ant_div(dm);
3063 }
3064
3065 #else
phydm_evm_antdiv_callback(void * dm_void)3066 void phydm_evm_antdiv_callback(
3067 void *dm_void)
3068 {
3069 struct dm_struct *dm = (struct dm_struct *)dm_void;
3070
3071 PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
3072 odm_hw_ant_div(dm);
3073 }
3074 #endif
3075
3076 #endif
3077
odm_hw_ant_div(void * dm_void)3078 void odm_hw_ant_div(void *dm_void)
3079 {
3080 struct dm_struct *dm = (struct dm_struct *)dm_void;
3081 u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
3082 u32 main_rssi, aux_rssi, mian_cnt, aux_cnt, local_max_rssi;
3083 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3084 u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;
3085 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3086 struct cmn_sta_info *sta;
3087
3088 #ifdef PHYDM_BEAMFORMING_SUPPORT
3089 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3090 struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
3091 u32 TH1 = 500000;
3092 u32 TH2 = 10000000;
3093 u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
3094 u8 monitor_rssi_threshold = 30;
3095
3096 dm_bdc_table->BF_pass = true;
3097 dm_bdc_table->DIV_pass = true;
3098 dm_bdc_table->is_all_div_sta_idle = true;
3099 dm_bdc_table->is_all_bf_sta_idle = true;
3100 dm_bdc_table->num_bf_tar = 0;
3101 dm_bdc_table->num_div_tar = 0;
3102 dm_bdc_table->num_client = 0;
3103 #endif
3104 #endif
3105
3106 if (!dm->is_linked) { /* @is_linked==False */
3107 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
3108
3109 if (fat_tab->is_become_linked) {
3110 if (fat_tab->div_path_type == ANT_PATH_A)
3111 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3112 else if (fat_tab->div_path_type == ANT_PATH_B)
3113 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
3114 else if (fat_tab->div_path_type == ANT_PATH_AB)
3115 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
3116 odm_update_rx_idle_ant(dm, MAIN_ANT);
3117 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3118 dm->antdiv_period = 0;
3119
3120 fat_tab->is_become_linked = dm->is_linked;
3121 }
3122 return;
3123 } else {
3124 if (!fat_tab->is_become_linked) {
3125 PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
3126 if (fat_tab->div_path_type == ANT_PATH_A)
3127 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
3128 else if (fat_tab->div_path_type == ANT_PATH_B)
3129 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
3130 else if (fat_tab->div_path_type == ANT_PATH_AB)
3131 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
3132 #if 0
3133 /*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/
3134
3135 /* @if(dm->support_ic_type == ODM_RTL8821 ) */
3136 /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
3137 /* CCK AntDiv function disable */
3138
3139 /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
3140 /* @else if(dm->support_ic_type == ODM_RTL8881A) */
3141 /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
3142 /* CCK AntDiv function disable */
3143 /* @#endif */
3144
3145 /* @else if(dm->support_ic_type == ODM_RTL8723B ||*/
3146 /* @dm->support_ic_type == ODM_RTL8812) */
3147 /* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */
3148 /* CCK AntDiv function disable */
3149 #endif
3150
3151 fat_tab->is_become_linked = dm->is_linked;
3152
3153 if (dm->support_ic_type == ODM_RTL8723B &&
3154 dm->ant_div_type == CG_TRX_HW_ANTDIV) {
3155 odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
3156 /* @DPDT_P = ANTSEL[0] for 8723B AntDiv */
3157 odm_set_bb_reg(dm, R_0x930, 0xF, 8);
3158 /* @DPDT_N = ANTSEL[0] */
3159 }
3160
3161 /* @ BDC Init */
3162 #ifdef PHYDM_BEAMFORMING_SUPPORT
3163 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3164 odm_bdc_init(dm);
3165 #endif
3166 #endif
3167
3168 #ifdef ODM_EVM_ENHANCE_ANTDIV
3169 odm_evm_fast_ant_reset(dm);
3170 #endif
3171 }
3172 }
3173
3174 if (!(*fat_tab->p_force_tx_by_desc)) {
3175 if (dm->is_one_entry_only)
3176 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3177 else
3178 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
3179 }
3180
3181 #ifdef ODM_EVM_ENHANCE_ANTDIV
3182 if (dm->antdiv_evm_en == 1) {
3183 odm_evm_enhance_ant_div(dm);
3184 if (fat_tab->fat_state_cnt != 0)
3185 return;
3186 } else
3187 odm_evm_fast_ant_reset(dm);
3188 #endif
3189
3190 /* @2 BDC mode Arbitration */
3191 #ifdef PHYDM_BEAMFORMING_SUPPORT
3192 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3193 if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
3194 odm_bf_ant_div_mode_arbitration(dm);
3195 #endif
3196 #endif
3197
3198 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3199 sta = dm->phydm_sta_info[i];
3200 if (!is_sta_active(sta)) {
3201 phydm_antdiv_reset_statistic(dm, i);
3202 continue;
3203 }
3204
3205 /* @2 Caculate RSSI per Antenna */
3206 if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
3207 mian_cnt = fat_tab->main_cnt[i];
3208 aux_cnt = fat_tab->aux_cnt[i];
3209 main_rssi = (mian_cnt != 0) ?
3210 (fat_tab->main_sum[i] / mian_cnt) : 0;
3211 aux_rssi = (aux_cnt != 0) ?
3212 (fat_tab->aux_sum[i] / aux_cnt) : 0;
3213 target_ant = (mian_cnt == aux_cnt) ?
3214 fat_tab->rx_idle_ant :
3215 ((mian_cnt >= aux_cnt) ?
3216 MAIN_ANT : AUX_ANT);
3217 /*Use counter number for OFDM*/
3218
3219 } else { /*@CCK only case*/
3220 mian_cnt = fat_tab->main_cnt_cck[i];
3221 aux_cnt = fat_tab->aux_cnt_cck[i];
3222 main_rssi = (mian_cnt != 0) ?
3223 (fat_tab->main_sum_cck[i] / mian_cnt) : 0;
3224 aux_rssi = (aux_cnt != 0) ?
3225 (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
3226 target_ant = (main_rssi == aux_rssi) ?
3227 fat_tab->rx_idle_ant :
3228 ((main_rssi >= aux_rssi) ?
3229 MAIN_ANT : AUX_ANT);
3230 /*Use RSSI for CCK only case*/
3231 }
3232
3233 PHYDM_DBG(dm, DBG_ANT_DIV,
3234 "*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n",
3235 i, fat_tab->main_cnt[i],
3236 fat_tab->main_cnt_cck[i], main_rssi);
3237 PHYDM_DBG(dm, DBG_ANT_DIV,
3238 "*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n",
3239 i, fat_tab->aux_cnt[i],
3240 fat_tab->aux_cnt_cck[i], aux_rssi);
3241
3242 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
3243 /* @ Select max_rssi for DIG */
3244 if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)
3245 ant_div_max_rssi = local_max_rssi;
3246 if (local_max_rssi > max_rssi)
3247 max_rssi = local_max_rssi;
3248
3249 /* @ Select RX Idle Antenna */
3250 if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
3251 rx_idle_ant = target_ant;
3252 min_max_rssi = local_max_rssi;
3253 }
3254
3255 #ifdef ODM_EVM_ENHANCE_ANTDIV
3256 if (dm->antdiv_evm_en == 1) {
3257 if (fat_tab->target_ant_enhance != 0xFF) {
3258 target_ant = fat_tab->target_ant_enhance;
3259 rx_idle_ant = fat_tab->target_ant_enhance;
3260 }
3261 }
3262 #endif
3263
3264 /* @2 Select TX Antenna */
3265 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
3266 #ifdef PHYDM_BEAMFORMING_SUPPORT
3267 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3268 if (dm_bdc_table->w_bfee_client[i] == 0)
3269 #endif
3270 #endif
3271 {
3272 odm_update_tx_ant(dm, target_ant, i);
3273 }
3274 }
3275
3276 /* @------------------------------------------------------------ */
3277
3278 #ifdef PHYDM_BEAMFORMING_SUPPORT
3279 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3280
3281 dm_bdc_table->num_client++;
3282
3283 if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
3284 /* @2 Byte counter */
3285
3286 ma_rx_temp = sta->rx_moving_average_tp; /* RX TP ( bit /sec) */
3287
3288 if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
3289 dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;
3290 else
3291 dm_bdc_table->MA_rx_TP[i] = ma_rx_temp;
3292
3293 if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {
3294 if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */
3295 dm_bdc_table->num_bf_tar++;
3296
3297 if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
3298 improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */
3299 dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
3300 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);
3301 }
3302 } else { /* @DIV_Target */
3303 dm_bdc_table->num_div_tar++;
3304
3305 if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
3306 degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */
3307 dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
3308 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);
3309 }
3310 }
3311 }
3312
3313 if (ma_rx_temp > TH1) {
3314 if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */
3315 dm_bdc_table->is_all_bf_sta_idle = false;
3316 else /* @DIV_Target */
3317 dm_bdc_table->is_all_div_sta_idle = false;
3318 }
3319
3320 PHYDM_DBG(dm, DBG_ANT_DIV,
3321 "*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n",
3322 i, dm_bdc_table->w_bfee_client[i],
3323 dm_bdc_table->w_bfer_client[i]);
3324
3325 if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
3326 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]);
3327
3328 else
3329 PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]);
3330 }
3331 #endif
3332 #endif
3333
3334 #ifdef PHYDM_BEAMFORMING_SUPPORT
3335 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3336 if (dm_bdc_table->bdc_try_flag == 0)
3337 #endif
3338 #endif
3339 {
3340 phydm_antdiv_reset_statistic(dm, i);
3341 }
3342 }
3343
3344 /* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
3345 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3346 PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n",
3347 (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3348
3349 #ifdef PHYDM_BEAMFORMING_SUPPORT
3350 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3351 if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
3352 PHYDM_DBG(dm, DBG_ANT_DIV,
3353 "*** bdc_rx_idle_update_counter = (( %d ))\n",
3354 dm_bdc_table->bdc_rx_idle_update_counter);
3355
3356 if (dm_bdc_table->bdc_rx_idle_update_counter == 1) {
3357 PHYDM_DBG(dm, DBG_ANT_DIV,
3358 "***Update RxIdle Antenna!!!\n");
3359 dm_bdc_table->bdc_rx_idle_update_counter = 30;
3360 odm_update_rx_idle_ant(dm, rx_idle_ant);
3361 } else {
3362 dm_bdc_table->bdc_rx_idle_update_counter--;
3363 PHYDM_DBG(dm, DBG_ANT_DIV,
3364 "***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n");
3365 }
3366 } else
3367 #endif
3368 #endif
3369 odm_update_rx_idle_ant(dm, rx_idle_ant);
3370 #else
3371
3372 odm_update_rx_idle_ant(dm, rx_idle_ant);
3373
3374 #endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
3375
3376 /* @2 BDC Main Algorithm */
3377 #ifdef PHYDM_BEAMFORMING_SUPPORT
3378 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3379 if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
3380 odm_bd_ccoex_bfee_rx_div_arbitration(dm);
3381
3382 dm_bdc_table->num_txbfee_client = 0;
3383 dm_bdc_table->num_txbfer_client = 0;
3384 #endif
3385 #endif
3386
3387 if (ant_div_max_rssi == 0)
3388 dig_t->ant_div_rssi_max = dm->rssi_min;
3389 else
3390 dig_t->ant_div_rssi_max = ant_div_max_rssi;
3391
3392 PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n");
3393 }
3394
3395 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3396
odm_s0s1_sw_ant_div_reset(void * dm_void)3397 void odm_s0s1_sw_ant_div_reset(void *dm_void)
3398 {
3399 struct dm_struct *dm = (struct dm_struct *)dm_void;
3400 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3401 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3402
3403 fat_tab->is_become_linked = false;
3404 swat_tab->try_flag = SWAW_STEP_INIT;
3405 swat_tab->double_chk_flag = 0;
3406
3407 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n",
3408 __func__, fat_tab->is_become_linked);
3409 }
3410
phydm_sw_antdiv_train_time(void * dm_void)3411 void phydm_sw_antdiv_train_time(void *dm_void)
3412 {
3413 struct dm_struct *dm = (struct dm_struct *)dm_void;
3414 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3415 u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0;
3416 u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
3417 u8 train_time_temp;
3418
3419 if (dm->traffic_load == TRAFFIC_HIGH) {
3420 train_time_temp = swat_tab->train_time;
3421
3422 if (swat_tab->train_time_flag == 3) {
3423 high_traffic_train_time_l = 0xa;
3424
3425 if (train_time_temp <= 16)
3426 train_time_temp = high_traffic_train_time_l;
3427 else
3428 train_time_temp -= 16;
3429
3430 } else if (swat_tab->train_time_flag == 2) {
3431 train_time_temp -= 8;
3432 high_traffic_train_time_l = 0xf;
3433 } else if (swat_tab->train_time_flag == 1) {
3434 train_time_temp -= 4;
3435 high_traffic_train_time_l = 0x1e;
3436 } else if (swat_tab->train_time_flag == 0) {
3437 train_time_temp += 8;
3438 high_traffic_train_time_l = 0x28;
3439 }
3440
3441 if (dm->support_ic_type == ODM_RTL8188F) {
3442 if (dm->support_interface == ODM_ITRF_SDIO)
3443 high_traffic_train_time_l += 0xa;
3444 }
3445
3446 /* @-- */
3447 if (train_time_temp > high_traffic_train_time_u)
3448 train_time_temp = high_traffic_train_time_u;
3449
3450 else if (train_time_temp < high_traffic_train_time_l)
3451 train_time_temp = high_traffic_train_time_l;
3452
3453 swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
3454
3455 PHYDM_DBG(dm, DBG_ANT_DIV,
3456 "train_time_flag=((%d)), train_time=((%d))\n",
3457 swat_tab->train_time_flag,
3458 swat_tab->train_time);
3459
3460 } else if ((dm->traffic_load == TRAFFIC_MID) ||
3461 (dm->traffic_load == TRAFFIC_LOW)) {
3462 train_time_temp = swat_tab->train_time;
3463
3464 if (swat_tab->train_time_flag == 3) {
3465 low_traffic_train_time_l = 10;
3466 if (train_time_temp < 50)
3467 train_time_temp = low_traffic_train_time_l;
3468 else
3469 train_time_temp -= 50;
3470 } else if (swat_tab->train_time_flag == 2) {
3471 train_time_temp -= 30;
3472 low_traffic_train_time_l = 36;
3473 } else if (swat_tab->train_time_flag == 1) {
3474 train_time_temp -= 10;
3475 low_traffic_train_time_l = 40;
3476 } else {
3477 train_time_temp += 10;
3478 low_traffic_train_time_l = 50;
3479 }
3480
3481 if (dm->support_ic_type == ODM_RTL8188F) {
3482 if (dm->support_interface == ODM_ITRF_SDIO)
3483 low_traffic_train_time_l += 10;
3484 }
3485
3486 /* @-- */
3487 if (train_time_temp >= low_traffic_train_time_u)
3488 train_time_temp = low_traffic_train_time_u;
3489
3490 else if (train_time_temp <= low_traffic_train_time_l)
3491 train_time_temp = low_traffic_train_time_l;
3492
3493 swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
3494
3495 PHYDM_DBG(dm, DBG_ANT_DIV,
3496 "train_time_flag=((%d)) , train_time=((%d))\n",
3497 swat_tab->train_time_flag, swat_tab->train_time);
3498
3499 } else {
3500 swat_tab->train_time = 0xc8; /*@200ms*/
3501 }
3502 }
3503
phydm_sw_antdiv_decision(void * dm_void)3504 void phydm_sw_antdiv_decision(void *dm_void)
3505 {
3506 struct dm_struct *dm = (struct dm_struct *)dm_void;
3507 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3508 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3509 u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
3510 u32 main_rssi, aux_rssi;
3511 u8 rx_idle_ant = swat_tab->pre_ant;
3512 u8 target_ant = swat_tab->pre_ant, next_ant = 0;
3513 struct cmn_sta_info *entry = NULL;
3514 u32 main_cnt = 0, aux_cnt = 0, main_sum = 0, aux_sum = 0;
3515 u32 main_ctrl_cnt = 0, aux_ctrl_cnt = 0;
3516 boolean is_by_ctrl_frame = false;
3517 boolean cond_23d_main, cond_23d_aux;
3518 u64 pkt_cnt_total = 0;
3519
3520 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3521 entry = dm->phydm_sta_info[i];
3522 if (!is_sta_active(entry)) {
3523 phydm_antdiv_reset_statistic(dm, i);
3524 continue;
3525 }
3526
3527 /* @2 Caculate RSSI per Antenna */
3528 if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
3529 main_cnt = (u32)fat_tab->main_cnt[i];
3530 aux_cnt = (u32)fat_tab->aux_cnt[i];
3531 main_rssi = (main_cnt != 0) ?
3532 (fat_tab->main_sum[i] / main_cnt) : 0;
3533 aux_rssi = (aux_cnt != 0) ?
3534 (fat_tab->aux_sum[i] / aux_cnt) : 0;
3535 if (dm->support_ic_type == ODM_RTL8723D) {
3536 cond_23d_main = (aux_cnt > main_cnt) &&
3537 ((main_rssi - aux_rssi < 5) ||
3538 (aux_rssi > main_rssi));
3539 cond_23d_aux = (main_cnt > aux_cnt) &&
3540 ((aux_rssi - main_rssi < 5) ||
3541 (main_rssi > aux_rssi));
3542 if (swat_tab->pre_ant == MAIN_ANT) {
3543 if (main_cnt == 0)
3544 target_ant = (aux_cnt != 0) ?
3545 AUX_ANT :
3546 swat_tab->pre_ant;
3547 else
3548 target_ant = cond_23d_main ?
3549 AUX_ANT :
3550 swat_tab->pre_ant;
3551 } else {
3552 if (aux_cnt == 0)
3553 target_ant = (main_cnt != 0) ?
3554 MAIN_ANT :
3555 swat_tab->pre_ant;
3556 else
3557 target_ant = cond_23d_aux ?
3558 MAIN_ANT :
3559 swat_tab->pre_ant;
3560 }
3561 } else {
3562 if (swat_tab->pre_ant == MAIN_ANT) {
3563 target_ant = (aux_rssi > main_rssi) ?
3564 AUX_ANT :
3565 swat_tab->pre_ant;
3566 } else if (swat_tab->pre_ant == AUX_ANT) {
3567 target_ant = (main_rssi > aux_rssi) ?
3568 MAIN_ANT :
3569 swat_tab->pre_ant;
3570 }
3571 }
3572 } else { /*@CCK only case*/
3573 main_cnt = fat_tab->main_cnt_cck[i];
3574 aux_cnt = fat_tab->aux_cnt_cck[i];
3575 main_rssi = (main_cnt != 0) ?
3576 (fat_tab->main_sum_cck[i] / main_cnt) : 0;
3577 aux_rssi = (aux_cnt != 0) ?
3578 (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
3579 target_ant = (main_rssi == aux_rssi) ?
3580 swat_tab->pre_ant :
3581 ((main_rssi >= aux_rssi) ?
3582 MAIN_ANT : AUX_ANT);
3583 /*Use RSSI for CCK only case*/
3584 }
3585 local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
3586 local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
3587
3588 PHYDM_DBG(dm, DBG_ANT_DIV,
3589 "*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n",
3590 fat_tab->main_cnt_cck[i], fat_tab->aux_cnt_cck[i]);
3591 PHYDM_DBG(dm, DBG_ANT_DIV,
3592 "*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n",
3593 fat_tab->main_cnt[i], fat_tab->aux_cnt[i]);
3594 PHYDM_DBG(dm, DBG_ANT_DIV,
3595 "*** main_Cnt = (( %d )) , aux_Cnt = (( %d ))\n",
3596 main_cnt, aux_cnt);
3597 PHYDM_DBG(dm, DBG_ANT_DIV,
3598 "*** main_rssi= (( %d )) , aux_rssi = (( %d ))\n",
3599 main_rssi, aux_rssi);
3600 PHYDM_DBG(dm, DBG_ANT_DIV,
3601 "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i,
3602 (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3603
3604 /* @2 Select RX Idle Antenna */
3605
3606 if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
3607 rx_idle_ant = target_ant;
3608 min_max_rssi = local_max_rssi;
3609 PHYDM_DBG(dm, DBG_ANT_DIV,
3610 "*** local_max_rssi-local_min_rssi = ((%d))\n",
3611 (local_max_rssi - local_min_rssi));
3612
3613 if ((local_max_rssi - local_min_rssi) > 8) {
3614 if (local_min_rssi != 0) {
3615 swat_tab->train_time_flag = 3;
3616 } else {
3617 if (min_max_rssi > RSSI_CHECK_THRESHOLD)
3618 swat_tab->train_time_flag = 0;
3619 else
3620 swat_tab->train_time_flag = 3;
3621 }
3622 } else if ((local_max_rssi - local_min_rssi) > 5) {
3623 swat_tab->train_time_flag = 2;
3624 } else if ((local_max_rssi - local_min_rssi) > 2) {
3625 swat_tab->train_time_flag = 1;
3626 } else {
3627 swat_tab->train_time_flag = 0;
3628 }
3629 }
3630
3631 /* @2 Select TX Antenna */
3632 if (target_ant == MAIN_ANT)
3633 fat_tab->antsel_a[i] = ANT1_2G;
3634 else
3635 fat_tab->antsel_a[i] = ANT2_2G;
3636
3637 phydm_antdiv_reset_statistic(dm, i);
3638 pkt_cnt_total += (main_cnt + aux_cnt);
3639 }
3640
3641 if (swat_tab->is_sw_ant_div_by_ctrl_frame) {
3642 odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);
3643 is_by_ctrl_frame = true;
3644 }
3645
3646 PHYDM_DBG(dm, DBG_ANT_DIV,
3647 "Control frame packet counter = %d, data frame packet counter = %llu\n",
3648 swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total);
3649
3650 if (min_max_rssi == 0xff || ((pkt_cnt_total <
3651 (swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) &&
3652 dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
3653 min_max_rssi = 0;
3654 PHYDM_DBG(dm, DBG_ANT_DIV,
3655 "Check RSSI of control frame because min_max_rssi == 0xff\n");
3656 PHYDM_DBG(dm, DBG_ANT_DIV, "is_by_ctrl_frame = %d\n",
3657 is_by_ctrl_frame);
3658
3659 if (is_by_ctrl_frame) {
3660 main_ctrl_cnt = fat_tab->main_ctrl_cnt;
3661 aux_ctrl_cnt = fat_tab->aux_ctrl_cnt;
3662 main_rssi = (main_ctrl_cnt != 0) ?
3663 (fat_tab->main_ctrl_sum / main_ctrl_cnt) :
3664 0;
3665 aux_rssi = (aux_ctrl_cnt != 0) ?
3666 (fat_tab->aux_ctrl_sum / aux_ctrl_cnt) : 0;
3667
3668 if (main_ctrl_cnt <= 1 &&
3669 fat_tab->cck_ctrl_frame_cnt_main >= 1)
3670 main_rssi = 0;
3671
3672 if (aux_ctrl_cnt <= 1 &&
3673 fat_tab->cck_ctrl_frame_cnt_aux >= 1)
3674 aux_rssi = 0;
3675
3676 if (main_rssi != 0 || aux_rssi != 0) {
3677 rx_idle_ant = (main_rssi == aux_rssi) ?
3678 swat_tab->pre_ant :
3679 ((main_rssi >= aux_rssi) ?
3680 MAIN_ANT : AUX_ANT);
3681 local_max_rssi = (main_rssi >= aux_rssi) ?
3682 main_rssi : aux_rssi;
3683 local_min_rssi = (main_rssi >= aux_rssi) ?
3684 aux_rssi : main_rssi;
3685
3686 if ((local_max_rssi - local_min_rssi) > 8)
3687 swat_tab->train_time_flag = 3;
3688 else if ((local_max_rssi - local_min_rssi) > 5)
3689 swat_tab->train_time_flag = 2;
3690 else if ((local_max_rssi - local_min_rssi) > 2)
3691 swat_tab->train_time_flag = 1;
3692 else
3693 swat_tab->train_time_flag = 0;
3694
3695 PHYDM_DBG(dm, DBG_ANT_DIV,
3696 "Control frame: main_rssi = %d, aux_rssi = %d\n",
3697 main_rssi, aux_rssi);
3698 PHYDM_DBG(dm, DBG_ANT_DIV,
3699 "rx_idle_ant decided by control frame = %s\n",
3700 (rx_idle_ant == MAIN_ANT ?
3701 "MAIN" : "AUX"));
3702 }
3703 }
3704 }
3705
3706 fat_tab->min_max_rssi = min_max_rssi;
3707 swat_tab->try_flag = SWAW_STEP_PEEK;
3708
3709 if (swat_tab->double_chk_flag == 1) {
3710 swat_tab->double_chk_flag = 0;
3711
3712 if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {
3713 PHYDM_DBG(dm, DBG_ANT_DIV,
3714 " [Double check] min_max_rssi ((%d)) > %d again!!\n",
3715 fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
3716
3717 odm_update_rx_idle_ant(dm, rx_idle_ant);
3718
3719 PHYDM_DBG(dm, DBG_ANT_DIV,
3720 "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
3721 } else {
3722 PHYDM_DBG(dm, DBG_ANT_DIV,
3723 " [Double check] min_max_rssi ((%d)) <= %d !!\n",
3724 fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
3725
3726 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
3727 AUX_ANT : MAIN_ANT;
3728 swat_tab->try_flag = SWAW_STEP_PEEK;
3729 swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
3730 PHYDM_DBG(dm, DBG_ANT_DIV,
3731 "[set try_flag=0] Normal state: Need to tryg again!!\n\n\n");
3732 }
3733 } else {
3734 if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)
3735 swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
3736
3737 swat_tab->pre_ant = rx_idle_ant;
3738 odm_update_rx_idle_ant(dm, rx_idle_ant);
3739 PHYDM_DBG(dm, DBG_ANT_DIV,
3740 "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
3741 }
3742 }
3743
odm_s0s1_sw_ant_div(void * dm_void,u8 step)3744 void odm_s0s1_sw_ant_div(void *dm_void, u8 step)
3745 {
3746 struct dm_struct *dm = (struct dm_struct *)dm_void;
3747 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
3748 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3749 u32 value32;
3750 u8 next_ant = 0;
3751
3752 if (!dm->is_linked) { /* @is_linked==False */
3753 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
3754 if (fat_tab->is_become_linked == true) {
3755 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3756 if (dm->support_ic_type == ODM_RTL8723B) {
3757 PHYDM_DBG(dm, DBG_ANT_DIV,
3758 "Set REG 948[9:6]=0x0\n");
3759 odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0);
3760 }
3761 fat_tab->is_become_linked = dm->is_linked;
3762 }
3763 return;
3764 } else {
3765 if (fat_tab->is_become_linked == false) {
3766 PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
3767
3768 if (dm->support_ic_type == ODM_RTL8723B) {
3769 value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
3770
3771 #if (RTL8723B_SUPPORT == 1)
3772 if (value32 == 0x0)
3773 odm_update_rx_idle_ant_8723b(dm,
3774 MAIN_ANT,
3775 ANT1_2G,
3776 ANT2_2G);
3777 else if (value32 == 0x1)
3778 odm_update_rx_idle_ant_8723b(dm,
3779 AUX_ANT,
3780 ANT2_2G,
3781 ANT1_2G);
3782 #endif
3783
3784 PHYDM_DBG(dm, DBG_ANT_DIV,
3785 "8723B: First link! Force antenna to %s\n",
3786 (value32 == 0x0 ? "MAIN" : "AUX"));
3787 }
3788
3789 if (dm->support_ic_type == ODM_RTL8723D) {
3790 value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
3791 #if (RTL8723D_SUPPORT == 1)
3792 if (value32 == 0x0)
3793 odm_update_rx_idle_ant_8723d(dm,
3794 MAIN_ANT,
3795 ANT1_2G,
3796 ANT2_2G);
3797 else if (value32 == 0x1)
3798 odm_update_rx_idle_ant_8723d(dm,
3799 AUX_ANT,
3800 ANT2_2G,
3801 ANT1_2G);
3802 PHYDM_DBG(dm, DBG_ANT_DIV,
3803 "8723D: First link! Force antenna to %s\n",
3804 (value32 == 0x0 ? "MAIN" : "AUX"));
3805 #endif
3806 }
3807 fat_tab->is_become_linked = dm->is_linked;
3808 }
3809 }
3810
3811 if (!(*fat_tab->p_force_tx_by_desc)) {
3812 if (dm->is_one_entry_only == true)
3813 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3814 else
3815 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
3816 }
3817
3818 PHYDM_DBG(dm, DBG_ANT_DIV,
3819 "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
3820 __LINE__, swat_tab->try_flag, step,
3821 swat_tab->double_chk_flag);
3822
3823 /* @ Handling step mismatch condition. */
3824 /* @ Peak step is not finished at last time. */
3825 /* @ Recover the variable and check again. */
3826 if (step != swat_tab->try_flag) {
3827 PHYDM_DBG(dm, DBG_ANT_DIV,
3828 "[step != try_flag] Need to Reset After Link\n");
3829 odm_sw_ant_div_rest_after_link(dm);
3830 }
3831
3832 if (swat_tab->try_flag == SWAW_STEP_INIT) {
3833 swat_tab->try_flag = SWAW_STEP_PEEK;
3834 swat_tab->train_time_flag = 0;
3835 PHYDM_DBG(dm, DBG_ANT_DIV,
3836 "[set try_flag = 0] Prepare for peek!\n\n");
3837 return;
3838
3839 } else {
3840 /* @1 Normal state (Begin Trying) */
3841 if (swat_tab->try_flag == SWAW_STEP_PEEK) {
3842 PHYDM_DBG(dm, DBG_ANT_DIV,
3843 "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n",
3844 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,
3845 dm->traffic_load);
3846 phydm_sw_antdiv_train_time(dm);
3847
3848 PHYDM_DBG(dm, DBG_ANT_DIV,
3849 "Current min_max_rssi is ((%d))\n",
3850 fat_tab->min_max_rssi);
3851
3852 /* @---reset index--- */
3853 if (swat_tab->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
3854 fat_tab->min_max_rssi = 0;
3855 swat_tab->reset_idx = 0;
3856 }
3857 PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n",
3858 swat_tab->reset_idx);
3859
3860 swat_tab->reset_idx++;
3861
3862 /* @---double check flag--- */
3863 if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD &&
3864 swat_tab->double_chk_flag == 0) {
3865 PHYDM_DBG(dm, DBG_ANT_DIV,
3866 " min_max_rssi is ((%d)), and > %d\n",
3867 fat_tab->min_max_rssi,
3868 RSSI_CHECK_THRESHOLD);
3869
3870 swat_tab->double_chk_flag = 1;
3871 swat_tab->try_flag = SWAW_STEP_DETERMINE;
3872 swat_tab->rssi_trying = 0;
3873
3874 PHYDM_DBG(dm, DBG_ANT_DIV,
3875 "Test the current ant for (( %d )) ms again\n",
3876 swat_tab->train_time);
3877 odm_update_rx_idle_ant(dm,
3878 fat_tab->rx_idle_ant);
3879 odm_set_timer(dm, &swat_tab->sw_antdiv_timer,
3880 swat_tab->train_time); /*@ms*/
3881 return;
3882 }
3883
3884 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
3885 AUX_ANT : MAIN_ANT;
3886
3887 swat_tab->try_flag = SWAW_STEP_DETERMINE;
3888
3889 if (swat_tab->reset_idx <= 1)
3890 swat_tab->rssi_trying = 2;
3891 else
3892 swat_tab->rssi_trying = 1;
3893
3894 odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);
3895 PHYDM_DBG(dm, DBG_ANT_DIV,
3896 "[set try_flag=1] Normal state: Begin Trying!!\n");
3897
3898 } else if ((swat_tab->try_flag == SWAW_STEP_DETERMINE) &&
3899 (swat_tab->double_chk_flag == 0)) {
3900 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
3901 AUX_ANT : MAIN_ANT;
3902 swat_tab->rssi_trying--;
3903 }
3904
3905 /* @1 Decision state */
3906 if (swat_tab->try_flag == SWAW_STEP_DETERMINE &&
3907 swat_tab->rssi_trying == 0) {
3908 phydm_sw_antdiv_decision(dm);
3909 return;
3910 }
3911 }
3912
3913 /* @1 4.Change TRX antenna */
3914
3915 PHYDM_DBG(dm, DBG_ANT_DIV,
3916 "rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n",
3917 swat_tab->rssi_trying,
3918 (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"),
3919 (next_ant == MAIN_ANT ? "MAIN" : "AUX"));
3920
3921 odm_update_rx_idle_ant(dm, next_ant);
3922
3923 /* @1 5.Reset Statistics */
3924
3925 fat_tab->rx_idle_ant = next_ant;
3926
3927 if (dm->support_ic_type == ODM_RTL8723D) {
3928 if (fat_tab->rx_idle_ant == MAIN_ANT) {
3929 fat_tab->main_sum[0] = 0;
3930 fat_tab->main_cnt[0] = 0;
3931 fat_tab->main_sum_cck[0] = 0;
3932 fat_tab->main_cnt_cck[0] = 0;
3933 } else {
3934 fat_tab->aux_sum[0] = 0;
3935 fat_tab->aux_cnt[0] = 0;
3936 fat_tab->aux_sum_cck[0] = 0;
3937 fat_tab->aux_cnt_cck[0] = 0;
3938 }
3939 }
3940
3941 if (dm->support_ic_type == ODM_RTL8188F) {
3942 if (dm->support_interface == ODM_ITRF_SDIO) {
3943 ODM_delay_us(200);
3944
3945 if (fat_tab->rx_idle_ant == MAIN_ANT) {
3946 fat_tab->main_sum[0] = 0;
3947 fat_tab->main_cnt[0] = 0;
3948 fat_tab->main_sum_cck[0] = 0;
3949 fat_tab->main_cnt_cck[0] = 0;
3950 } else {
3951 fat_tab->aux_sum[0] = 0;
3952 fat_tab->aux_cnt[0] = 0;
3953 fat_tab->aux_sum_cck[0] = 0;
3954 fat_tab->aux_cnt_cck[0] = 0;
3955 }
3956 }
3957 }
3958 /* @1 6.Set next timer (Trying state) */
3959 PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n",
3960 (next_ant == MAIN_ANT ? "MAIN" : "AUX"),
3961 swat_tab->train_time);
3962 odm_set_timer(dm, &swat_tab->sw_antdiv_timer, swat_tab->train_time);
3963 /*@ms*/
3964 }
3965
3966 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_sw_antdiv_callback(struct phydm_timer_list * timer)3967 void odm_sw_antdiv_callback(struct phydm_timer_list *timer)
3968 {
3969 void *adapter = (void *)timer->Adapter;
3970 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3971 struct sw_antenna_switch *swat_tab = &hal_data->DM_OutSrc.dm_swat_table;
3972
3973 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
3974 #if USE_WORKITEM
3975 odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
3976 #else
3977 {
3978 #if 0
3979 /* @dbg_print("SW_antdiv_Callback"); */
3980 #endif
3981 odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
3982 }
3983 #endif
3984 #else
3985 odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
3986 #endif
3987 }
3988
odm_sw_antdiv_workitem_callback(void * context)3989 void odm_sw_antdiv_workitem_callback(void *context)
3990 {
3991 void *adapter = (void *)context;
3992 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3993
3994 #if 0
3995 /* @dbg_print("SW_antdiv_Workitem_Callback"); */
3996 #endif
3997 odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
3998 }
3999
4000 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4001
odm_sw_antdiv_workitem_callback(void * context)4002 void odm_sw_antdiv_workitem_callback(void *context)
4003 {
4004 void *
4005 adapter = (void *)context;
4006 HAL_DATA_TYPE
4007 *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
4008
4009 #if 0
4010 /*@dbg_print("SW_antdiv_Workitem_Callback");*/
4011 #endif
4012 odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);
4013 }
4014
odm_sw_antdiv_callback(void * function_context)4015 void odm_sw_antdiv_callback(void *function_context)
4016 {
4017 struct dm_struct *dm = (struct dm_struct *)function_context;
4018 void *padapter = dm->adapter;
4019 if (*dm->is_net_closed == true)
4020 return;
4021
4022 #if 0 /* @Can't do I/O in timer callback*/
4023 odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
4024 #else
4025 rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback,
4026 padapter);
4027 #endif
4028 }
4029
4030 #endif
4031
odm_s0s1_sw_ant_div_by_ctrl_frame(void * dm_void,u8 step)4032 void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step)
4033 {
4034 struct dm_struct *dm = (struct dm_struct *)dm_void;
4035 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4036 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4037
4038 switch (step) {
4039 case SWAW_STEP_PEEK:
4040 swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
4041 swat_tab->is_sw_ant_div_by_ctrl_frame = true;
4042 fat_tab->main_ctrl_cnt = 0;
4043 fat_tab->aux_ctrl_cnt = 0;
4044 fat_tab->main_ctrl_sum = 0;
4045 fat_tab->aux_ctrl_sum = 0;
4046 fat_tab->cck_ctrl_frame_cnt_main = 0;
4047 fat_tab->cck_ctrl_frame_cnt_aux = 0;
4048 fat_tab->ofdm_ctrl_frame_cnt_main = 0;
4049 fat_tab->ofdm_ctrl_frame_cnt_aux = 0;
4050 PHYDM_DBG(dm, DBG_ANT_DIV,
4051 "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n");
4052 break;
4053 case SWAW_STEP_DETERMINE:
4054 swat_tab->is_sw_ant_div_by_ctrl_frame = false;
4055 PHYDM_DBG(dm, DBG_ANT_DIV,
4056 "odm_S0S1_SwAntDivForAPMode(): Stop peek\n");
4057 break;
4058 default:
4059 swat_tab->is_sw_ant_div_by_ctrl_frame = false;
4060 break;
4061 }
4062 }
4063
odm_antsel_statistics_ctrl(void * dm_void,u8 antsel_tr_mux,u32 rx_pwdb_all)4064 void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,
4065 u32 rx_pwdb_all)
4066 {
4067 struct dm_struct *dm = (struct dm_struct *)dm_void;
4068 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4069
4070 if (antsel_tr_mux == ANT1_2G) {
4071 fat_tab->main_ctrl_sum += rx_pwdb_all;
4072 fat_tab->main_ctrl_cnt++;
4073 } else {
4074 fat_tab->aux_ctrl_sum += rx_pwdb_all;
4075 fat_tab->aux_ctrl_cnt++;
4076 }
4077 }
4078
odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void * dm_void,void * phy_info_void,void * pkt_info_void)4079 void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
4080 void *phy_info_void,
4081 void *pkt_info_void
4082 /* struct phydm_phyinfo_struct* phy_info, */
4083 /* struct phydm_perpkt_info_struct* pktinfo */
4084 )
4085 {
4086 struct dm_struct *dm = (struct dm_struct *)dm_void;
4087 struct phydm_phyinfo_struct *phy_info = NULL;
4088 struct phydm_perpkt_info_struct *pktinfo = NULL;
4089 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4090 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4091 u8 rssi_cck;
4092
4093 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
4094 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
4095
4096 if (!(dm->support_ability & ODM_BB_ANT_DIV))
4097 return;
4098
4099 if (dm->ant_div_type != S0S1_SW_ANTDIV)
4100 return;
4101
4102 /* @In try state */
4103 if (!swat_tab->is_sw_ant_div_by_ctrl_frame)
4104 return;
4105
4106 /* No HW error and match receiver address */
4107 if (!pktinfo->is_to_self)
4108 return;
4109
4110 swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame++;
4111
4112 if (pktinfo->is_cck_rate) {
4113 rssi_cck = phy_info->rx_mimo_signal_strength[RF_PATH_A];
4114 fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4115 ANT1_2G : ANT2_2G;
4116
4117 if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
4118 fat_tab->cck_ctrl_frame_cnt_main++;
4119 else
4120 fat_tab->cck_ctrl_frame_cnt_aux++;
4121
4122 odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
4123 rssi_cck);
4124 } else {
4125 fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
4126 ANT1_2G : ANT2_2G;
4127
4128 if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
4129 fat_tab->ofdm_ctrl_frame_cnt_main++;
4130 else
4131 fat_tab->ofdm_ctrl_frame_cnt_aux++;
4132
4133 odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
4134 phy_info->rx_pwdb_all);
4135 }
4136 }
4137
4138 #endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
4139
odm_set_next_mac_addr_target(void * dm_void)4140 void odm_set_next_mac_addr_target(void *dm_void)
4141 {
4142 struct dm_struct *dm = (struct dm_struct *)dm_void;
4143 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4144 struct cmn_sta_info *entry;
4145 u32 value32, i;
4146
4147 PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__);
4148
4149 if (dm->is_linked) {
4150 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
4151 if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
4152 fat_tab->train_idx = 0;
4153 else
4154 fat_tab->train_idx++;
4155
4156 entry = dm->phydm_sta_info[fat_tab->train_idx];
4157
4158 if (is_sta_active(entry)) {
4159 /*@Match MAC ADDR*/
4160 value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];
4161
4162 odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/
4163
4164 value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];
4165
4166 odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/
4167
4168 PHYDM_DBG(dm, DBG_ANT_DIV,
4169 "fat_tab->train_idx=%d\n",
4170 fat_tab->train_idx);
4171
4172 PHYDM_DBG(dm, DBG_ANT_DIV,
4173 "Training MAC addr = %x:%x:%x:%x:%x:%x\n",
4174 entry->mac_addr[5],
4175 entry->mac_addr[4],
4176 entry->mac_addr[3],
4177 entry->mac_addr[2],
4178 entry->mac_addr[1],
4179 entry->mac_addr[0]);
4180
4181 break;
4182 }
4183 }
4184 }
4185 }
4186
4187 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4188
odm_fast_ant_training(void * dm_void)4189 void odm_fast_ant_training(
4190 void *dm_void)
4191 {
4192 struct dm_struct *dm = (struct dm_struct *)dm_void;
4193 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4194
4195 u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
4196 u8 i, target_ant_path_a = 0;
4197 boolean is_pkt_filter_macth_path_a = false;
4198 #if (RTL8192E_SUPPORT == 1)
4199 u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
4200 u8 target_ant_path_b = 0;
4201 boolean is_pkt_filter_macth_path_b = false;
4202 #endif
4203
4204 if (!dm->is_linked) { /* @is_linked==False */
4205 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
4206
4207 if (fat_tab->is_become_linked == true) {
4208 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4209 phydm_fast_training_enable(dm, FAT_OFF);
4210 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4211 fat_tab->is_become_linked = dm->is_linked;
4212 }
4213 return;
4214 } else {
4215 if (fat_tab->is_become_linked == false) {
4216 PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n");
4217 fat_tab->is_become_linked = dm->is_linked;
4218 }
4219 }
4220
4221 if (!(*fat_tab->p_force_tx_by_desc)) {
4222 if (dm->is_one_entry_only == true)
4223 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4224 else
4225 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4226 }
4227
4228 if (dm->support_ic_type == ODM_RTL8188E)
4229 odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));
4230 #if (RTL8192E_SUPPORT == 1)
4231 else if (dm->support_ic_type == ODM_RTL8192E) {
4232 odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */
4233 odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */
4234 }
4235 #endif
4236
4237 PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__);
4238
4239 /* @1 TRAINING STATE */
4240 if (fat_tab->fat_state == FAT_TRAINING_STATE) {
4241 /* @2 Caculate RSSI per Antenna */
4242
4243 /* @3 [path-A]--------------------------- */
4244 for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */
4245 if (fat_tab->ant_rssi_cnt[i] == 0)
4246 fat_tab->ant_ave_rssi[i] = 0;
4247 else {
4248 fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];
4249 is_pkt_filter_macth_path_a = true;
4250 }
4251
4252 if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {
4253 max_rssi_path_a = fat_tab->ant_ave_rssi[i];
4254 pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
4255 target_ant_path_a = i;
4256 } else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {
4257 if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {
4258 max_rssi_path_a = fat_tab->ant_ave_rssi[i];
4259 pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
4260 target_ant_path_a = i;
4261 }
4262 }
4263
4264 PHYDM_DBG(
4265 "*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n",
4266 i, fat_tab->ant_rssi_cnt[i],
4267 fat_tab->ant_ave_rssi[i]);
4268 }
4269
4270 #if 0
4271 #if (RTL8192E_SUPPORT == 1)
4272 /* @3 [path-B]--------------------------- */
4273 for (i = 0; i < (dm->fat_comb_b); i++) {
4274 if (fat_tab->antRSSIcnt_pathB[i] == 0)
4275 fat_tab->antAveRSSI_pathB[i] = 0;
4276 else { /* @(ant_rssi_cnt[i] != 0) */
4277 fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];
4278 is_pkt_filter_macth_path_b = true;
4279 }
4280 if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {
4281 max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
4282 pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];
4283 target_ant_path_b = (u8)i;
4284 }
4285 if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {
4286 if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {
4287 max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
4288 target_ant_path_b = (u8)i;
4289 }
4290 }
4291 if (dm->fat_print_rssi == 1) {
4292 PHYDM_DBG(dm, DBG_ANT_DIV,
4293 "***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n",
4294 i, fat_tab->antSumRSSI_pathB[i], i,
4295 fat_tab->antRSSIcnt_pathB[i], i,
4296 fat_tab->antAveRSSI_pathB[i]);
4297 }
4298 }
4299 #endif
4300 #endif
4301
4302 /* @1 DECISION STATE */
4303
4304 /* @2 Select TRX Antenna */
4305
4306 phydm_fast_training_enable(dm, FAT_OFF);
4307
4308 /* @3 [path-A]--------------------------- */
4309 if (is_pkt_filter_macth_path_a == false) {
4310 #if 0
4311 /* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */
4312 #endif
4313 PHYDM_DBG(dm, DBG_ANT_DIV,
4314 "{path-A}: None Packet is matched\n");
4315 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4316 } else {
4317 PHYDM_DBG(
4318 "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n",
4319 target_ant_path_a, max_rssi_path_a);
4320
4321 /* @3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */
4322 if (dm->support_ic_type == ODM_RTL8188E)
4323 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
4324 else if (dm->support_ic_type == ODM_RTL8192E)
4325 odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
4326
4327 /* @3 [ update TX ant ] */
4328 odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));
4329
4330 if (target_ant_path_a == 0)
4331 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4332 }
4333 #if 0
4334 #if (RTL8192E_SUPPORT == 1)
4335 /* @3 [path-B]--------------------------- */
4336 if (is_pkt_filter_macth_path_b == false) {
4337 if (dm->fat_print_rssi == 1)
4338 PHYDM_DBG(dm, DBG_ANT_DIV,
4339 "***[%d]{path-B}: None Packet is matched\n\n\n",
4340 __LINE__);
4341 } else {
4342 if (dm->fat_print_rssi == 1) {
4343 PHYDM_DBG(dm, DBG_ANT_DIV,
4344 " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n",
4345 target_ant_path_b, max_rssi_path_b);
4346 }
4347 odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* @Default RX is Omni, Optional RX is the best decision by FAT */
4348 odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */
4349
4350 fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;
4351 }
4352 #endif
4353 #endif
4354
4355 /* @2 Reset counter */
4356 for (i = 0; i < (dm->fat_comb_a); i++) {
4357 fat_tab->ant_sum_rssi[i] = 0;
4358 fat_tab->ant_rssi_cnt[i] = 0;
4359 }
4360 /*@
4361 #if (RTL8192E_SUPPORT == 1)
4362 for(i=0; i<=(dm->fat_comb_b); i++)
4363 {
4364 fat_tab->antSumRSSI_pathB[i] = 0;
4365 fat_tab->antRSSIcnt_pathB[i] = 0;
4366 }
4367 #endif
4368 */
4369
4370 fat_tab->fat_state = FAT_PREPARE_STATE;
4371 return;
4372 }
4373
4374 /* @1 NORMAL STATE */
4375 if (fat_tab->fat_state == FAT_PREPARE_STATE) {
4376 PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n");
4377
4378 odm_set_next_mac_addr_target(dm);
4379
4380 /* @2 Prepare Training */
4381 fat_tab->fat_state = FAT_TRAINING_STATE;
4382 phydm_fast_training_enable(dm, FAT_ON);
4383 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4384 /* @enable HW AntDiv */
4385 PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n");
4386
4387 odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */
4388 }
4389 }
4390
odm_fast_ant_training_callback(void * dm_void)4391 void odm_fast_ant_training_callback(
4392 void *dm_void)
4393 {
4394 struct dm_struct *dm = (struct dm_struct *)dm_void;
4395
4396 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4397 if (*(dm->is_net_closed) == true)
4398 return;
4399 #endif
4400
4401 #if USE_WORKITEM
4402 odm_schedule_work_item(&dm->fast_ant_training_workitem);
4403 #else
4404 PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
4405 odm_fast_ant_training(dm);
4406 #endif
4407 }
4408
odm_fast_ant_training_work_item_callback(void * dm_void)4409 void odm_fast_ant_training_work_item_callback(
4410 void *dm_void)
4411 {
4412 struct dm_struct *dm = (struct dm_struct *)dm_void;
4413
4414 PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
4415 odm_fast_ant_training(dm);
4416 }
4417
4418 #endif
4419
odm_ant_div_init(void * dm_void)4420 void odm_ant_div_init(void *dm_void)
4421 {
4422 struct dm_struct *dm = (struct dm_struct *)dm_void;
4423 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4424 struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
4425
4426 if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
4427 PHYDM_DBG(dm, DBG_ANT_DIV,
4428 "[Return!!!] Not Support Antenna Diversity Function\n");
4429 return;
4430 }
4431 /* @--- */
4432 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4433 if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
4434 PHYDM_DBG(dm, DBG_ANT_DIV,
4435 "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n");
4436 if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
4437 return;
4438 } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
4439 PHYDM_DBG(dm, DBG_ANT_DIV,
4440 "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n");
4441 if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
4442 return;
4443 } else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
4444 PHYDM_DBG(dm, DBG_ANT_DIV,
4445 "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n");
4446
4447 #endif
4448 /* @--- */
4449
4450 /* @2 [--General---] */
4451 dm->antdiv_period = 0;
4452
4453 fat_tab->is_become_linked = false;
4454 fat_tab->ant_div_on_off = 0xff;
4455
4456 /* @3 - AP - */
4457 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4458
4459 #ifdef PHYDM_BEAMFORMING_SUPPORT
4460 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4461 odm_bdc_init(dm);
4462 #endif
4463 #endif
4464
4465 /* @3 - WIN - */
4466 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4467 swat_tab->ant_5g = MAIN_ANT;
4468 swat_tab->ant_2g = MAIN_ANT;
4469 #endif
4470
4471 /* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
4472 if (fat_tab->div_path_type == ANT_PATH_A)
4473 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4474 else if (fat_tab->div_path_type == ANT_PATH_B)
4475 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
4476 else if (fat_tab->div_path_type == ANT_PATH_AB)
4477 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
4478
4479 dm->ant_type = ODM_AUTO_ANT;
4480
4481 fat_tab->rx_idle_ant = 0xff;
4482 /*to make RX-idle-antenna will be updated absolutly*/
4483 odm_update_rx_idle_ant(dm, MAIN_ANT);
4484 phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0);
4485 /* Timming issue: keep Rx ant after tx for ACK(5 x 3.2 mu = 16mu sec)*/
4486
4487 /* @2 [---Set TX Antenna---] */
4488 if (!fat_tab->p_force_tx_by_desc) {
4489 fat_tab->force_tx_by_desc = 0;
4490 fat_tab->p_force_tx_by_desc = &fat_tab->force_tx_by_desc;
4491 }
4492 PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_by_desc = %d\n",
4493 *fat_tab->p_force_tx_by_desc);
4494
4495 if (*fat_tab->p_force_tx_by_desc)
4496 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4497 else
4498 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4499
4500 /* @2 [--88E---] */
4501 if (dm->support_ic_type == ODM_RTL8188E) {
4502 #if (RTL8188E_SUPPORT == 1)
4503 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4504 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4505 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
4506
4507 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
4508 dm->ant_div_type != CG_TRX_HW_ANTDIV &&
4509 dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
4510 PHYDM_DBG(dm, DBG_ANT_DIV,
4511 "[Return!!!] 88E Not Supprrt This AntDiv type\n");
4512 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4513 return;
4514 }
4515
4516 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4517 odm_rx_hw_ant_div_init_88e(dm);
4518 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4519 odm_trx_hw_ant_div_init_88e(dm);
4520 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4521 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4522 odm_smart_hw_ant_div_init_88e(dm);
4523 #endif
4524 #endif
4525 }
4526
4527 /* @2 [--92E---] */
4528 #if (RTL8192E_SUPPORT == 1)
4529 else if (dm->support_ic_type == ODM_RTL8192E) {
4530 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4531 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4532 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
4533
4534 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
4535 dm->ant_div_type != CG_TRX_HW_ANTDIV &&
4536 dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
4537 PHYDM_DBG(dm, DBG_ANT_DIV,
4538 "[Return!!!] 8192E Not Supprrt This AntDiv type\n");
4539 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4540 return;
4541 }
4542
4543 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4544 odm_rx_hw_ant_div_init_92e(dm);
4545 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4546 odm_trx_hw_ant_div_init_92e(dm);
4547 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4548 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4549 odm_smart_hw_ant_div_init_92e(dm);
4550 #endif
4551 }
4552 #endif
4553
4554 /* @2 [--92F---] */
4555 #if (RTL8192F_SUPPORT == 1)
4556 else if (dm->support_ic_type == ODM_RTL8192F) {
4557 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4558 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4559 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
4560
4561 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
4562 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4563 PHYDM_DBG(dm, DBG_ANT_DIV,
4564 "[Return!!!] 8192F Not Supprrt This AntDiv type\n");
4565 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4566 return;
4567 }
4568 }
4569 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4570 odm_rx_hw_ant_div_init_92f(dm);
4571 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4572 odm_trx_hw_ant_div_init_92f(dm);
4573 }
4574 #endif
4575
4576 #if (RTL8197F_SUPPORT == 1)
4577 else if (dm->support_ic_type == ODM_RTL8197F) {
4578 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4579
4580 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
4581 PHYDM_DBG(dm, DBG_ANT_DIV,
4582 "[Return!!!] 8197F Not Supprrt This AntDiv type\n");
4583 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4584 return;
4585 }
4586 phydm_rx_hw_ant_div_init_97f(dm);
4587 }
4588 #endif
4589
4590 #if (RTL8197G_SUPPORT == 1)
4591 else if (dm->support_ic_type == ODM_RTL8197G) {
4592 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
4593
4594 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
4595 PHYDM_DBG(dm, DBG_ANT_DIV,
4596 "[Return!!!] 8197F Not Supprrt This AntDiv type\n");
4597 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4598 return;
4599 }
4600 phydm_rx_hw_ant_div_init_97g(dm);
4601 }
4602 #endif
4603 /* @2 [--8723B---] */
4604 #if (RTL8723B_SUPPORT == 1)
4605 else if (dm->support_ic_type == ODM_RTL8723B) {
4606 dm->ant_div_type = S0S1_SW_ANTDIV;
4607 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4608
4609 if (dm->ant_div_type != S0S1_SW_ANTDIV &&
4610 dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4611 PHYDM_DBG(dm, DBG_ANT_DIV,
4612 "[Return!!!] 8723B Not Supprrt This AntDiv type\n");
4613 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4614 return;
4615 }
4616
4617 if (dm->ant_div_type == S0S1_SW_ANTDIV)
4618 odm_s0s1_sw_ant_div_init_8723b(dm);
4619 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4620 odm_trx_hw_ant_div_init_8723b(dm);
4621 }
4622 #endif
4623 /*@2 [--8723D---]*/
4624 #if (RTL8723D_SUPPORT == 1)
4625 else if (dm->support_ic_type == ODM_RTL8723D) {
4626 if (fat_tab->p_default_s0_s1 == NULL) {
4627 fat_tab->default_s0_s1 = 1;
4628 fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
4629 }
4630 PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
4631 *fat_tab->p_default_s0_s1);
4632
4633 if (*fat_tab->p_default_s0_s1 == true)
4634 odm_update_rx_idle_ant(dm, MAIN_ANT);
4635 else
4636 odm_update_rx_idle_ant(dm, AUX_ANT);
4637
4638 if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
4639 odm_trx_hw_ant_div_init_8723d(dm);
4640 else if (dm->ant_div_type == S0S1_SW_ANTDIV)
4641 odm_s0s1_sw_ant_div_init_8723d(dm);
4642 else {
4643 PHYDM_DBG(dm, DBG_ANT_DIV,
4644 "[Return!!!] 8723D Not Supprrt This AntDiv type\n");
4645 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4646 return;
4647 }
4648 }
4649 #endif
4650 #if (RTL8721D_SUPPORT == 1)
4651 else if (dm->support_ic_type == ODM_RTL8721D) {
4652 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4653
4654 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4655 PHYDM_DBG(dm, DBG_ANT_DIV,
4656 "[Return!!!] 8721D Not Supprrt This AntDiv type\n");
4657 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4658 return;
4659 }
4660 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4661 odm_trx_hw_ant_div_init_8721d(dm);
4662 }
4663 #endif
4664 /* @2 [--8811A 8821A---] */
4665 #if (RTL8821A_SUPPORT == 1)
4666 else if (dm->support_ic_type == ODM_RTL8821) {
4667 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
4668 dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
4669
4670 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
4671 odm_trx_hw_ant_div_init_8821a(dm);
4672 phydm_hl_smart_ant_type1_init_8821a(dm);
4673 } else
4674 #endif
4675 {
4676 #ifdef ODM_CONFIG_BT_COEXIST
4677 dm->ant_div_type = S0S1_SW_ANTDIV;
4678 #else
4679 dm->ant_div_type = CG_TRX_HW_ANTDIV;
4680 #endif
4681
4682 if (dm->ant_div_type != CG_TRX_HW_ANTDIV &&
4683 dm->ant_div_type != S0S1_SW_ANTDIV) {
4684 PHYDM_DBG(dm, DBG_ANT_DIV,
4685 "[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n");
4686 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4687 return;
4688 }
4689 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4690 odm_trx_hw_ant_div_init_8821a(dm);
4691 else if (dm->ant_div_type == S0S1_SW_ANTDIV)
4692 odm_s0s1_sw_ant_div_init_8821a(dm);
4693 }
4694 }
4695 #endif
4696
4697 /* @2 [--8821C---] */
4698 #if (RTL8821C_SUPPORT == 1)
4699 else if (dm->support_ic_type == ODM_RTL8821C) {
4700 dm->ant_div_type = S0S1_SW_ANTDIV;
4701 if (dm->ant_div_type != S0S1_SW_ANTDIV) {
4702 PHYDM_DBG(dm, DBG_ANT_DIV,
4703 "[Return!!!] 8821C Not Supprrt This AntDiv type\n");
4704 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4705 return;
4706 }
4707 phydm_s0s1_sw_ant_div_init_8821c(dm);
4708 odm_trx_hw_ant_div_init_8821c(dm);
4709 }
4710 #endif
4711
4712 /* @2 [--8881A---] */
4713 #if (RTL8881A_SUPPORT == 1)
4714 else if (dm->support_ic_type == ODM_RTL8881A) {
4715 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4716 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4717
4718 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
4719 odm_trx_hw_ant_div_init_8881a(dm);
4720 } else {
4721 PHYDM_DBG(dm, DBG_ANT_DIV,
4722 "[Return!!!] 8881A Not Supprrt This AntDiv type\n");
4723 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4724 return;
4725 }
4726
4727 odm_trx_hw_ant_div_init_8881a(dm);
4728 }
4729 #endif
4730
4731 /* @2 [--8812---] */
4732 #if (RTL8812A_SUPPORT == 1)
4733 else if (dm->support_ic_type == ODM_RTL8812) {
4734 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4735
4736 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4737 PHYDM_DBG(dm, DBG_ANT_DIV,
4738 "[Return!!!] 8812A Not Supprrt This AntDiv type\n");
4739 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4740 return;
4741 }
4742 odm_trx_hw_ant_div_init_8812a(dm);
4743 }
4744 #endif
4745
4746 /*@[--8188F---]*/
4747 #if (RTL8188F_SUPPORT == 1)
4748 else if (dm->support_ic_type == ODM_RTL8188F) {
4749 dm->ant_div_type = S0S1_SW_ANTDIV;
4750 odm_s0s1_sw_ant_div_init_8188f(dm);
4751 }
4752 #endif
4753
4754 /*@[--8822B---]*/
4755 #if (RTL8822B_SUPPORT == 1)
4756 else if (dm->support_ic_type == ODM_RTL8822B) {
4757 dm->ant_div_type = CG_TRX_HW_ANTDIV;
4758
4759 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4760 PHYDM_DBG(dm, DBG_ANT_DIV,
4761 "[Return!!!] 8822B Not Supprrt This AntDiv type\n");
4762 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4763 return;
4764 }
4765 phydm_trx_hw_ant_div_init_22b(dm);
4766 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
4767 dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
4768
4769 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
4770 phydm_hl_smart_ant_type2_init_8822b(dm);
4771 #endif
4772 }
4773 #endif
4774
4775 /*@PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",*/
4776 /*dm->support_ic_type);*/
4777 /*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",*/
4778 /* (dm->support_ability & ODM_BB_ANT_DIV)>>6);*/
4779 /*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);*/
4780 }
4781
odm_ant_div(void * dm_void)4782 void odm_ant_div(void *dm_void)
4783 {
4784 struct dm_struct *dm = (struct dm_struct *)dm_void;
4785 void *adapter = dm->adapter;
4786 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4787 #if (defined(CONFIG_HL_SMART_ANTENNA))
4788 struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
4789 #endif
4790
4791 if (!(dm->support_ability & ODM_BB_ANT_DIV))
4792 return;
4793
4794 #ifdef ODM_EVM_ENHANCE_ANTDIV
4795 if (dm->is_linked) {
4796 PHYDM_DBG(dm, DBG_ANT_DIV,
4797 "tp_active_occur=((%d)), evm_method_enable=((%d))\n",
4798 dm->tp_active_occur, fat_tab->evm_method_enable);
4799
4800 if (dm->tp_active_occur == 1 &&
4801 fat_tab->evm_method_enable == 1) {
4802 fat_tab->idx_ant_div_counter_5g = dm->antdiv_period;
4803 fat_tab->idx_ant_div_counter_2g = dm->antdiv_period;
4804 }
4805 }
4806 #endif
4807
4808 if (*dm->band_type == ODM_BAND_5G) {
4809 if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {
4810 fat_tab->idx_ant_div_counter_5g++;
4811 return;
4812 } else
4813 fat_tab->idx_ant_div_counter_5g = 0;
4814 } else if (*dm->band_type == ODM_BAND_2_4G) {
4815 if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {
4816 fat_tab->idx_ant_div_counter_2g++;
4817 return;
4818 } else
4819 fat_tab->idx_ant_div_counter_2g = 0;
4820 }
4821
4822 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
4823
4824 if (fat_tab->enable_ctrl_frame_antdiv) {
4825 if (dm->data_frame_num <= 10 && dm->is_linked)
4826 fat_tab->use_ctrl_frame_antdiv = 1;
4827 else
4828 fat_tab->use_ctrl_frame_antdiv = 0;
4829
4830 PHYDM_DBG(dm, DBG_ANT_DIV,
4831 "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n",
4832 fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);
4833 dm->data_frame_num = 0;
4834 }
4835
4836 {
4837 #ifdef PHYDM_BEAMFORMING_SUPPORT
4838
4839 enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);
4840 PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n",
4841 dm->is_bt_continuous_turn);
4842 PHYDM_DBG(dm, DBG_ANT_DIV,
4843 "[ AntDiv Beam Cap ] cap= ((%d))\n", beamform_cap);
4844 if (!dm->is_bt_continuous_turn) {
4845 if ((beamform_cap & BEAMFORMEE_CAP) &&
4846 (!(*fat_tab->is_no_csi_feedback))) {
4847 /* @BFmee On && Div On->Div Off */
4848 PHYDM_DBG(dm, DBG_ANT_DIV,
4849 "[ AntDiv : OFF ] BFmee ==1; cap= ((%d))\n",
4850 beamform_cap);
4851 PHYDM_DBG(dm, DBG_ANT_DIV,
4852 "[ AntDiv BF] is_no_csi_feedback= ((%d))\n",
4853 *(fat_tab->is_no_csi_feedback));
4854 if (fat_tab->fix_ant_bfee == 0) {
4855 odm_ant_div_on_off(dm, ANTDIV_OFF,
4856 ANT_PATH_A);
4857 fat_tab->fix_ant_bfee = 1;
4858 }
4859 return;
4860 } else { /* @BFmee Off && Div Off->Div On */
4861 if (fat_tab->fix_ant_bfee == 1 &&
4862 dm->is_linked) {
4863 PHYDM_DBG(dm, DBG_ANT_DIV,
4864 "[ AntDiv : ON ] BFmee ==0; cap=((%d))\n",
4865 beamform_cap);
4866 PHYDM_DBG(dm, DBG_ANT_DIV,
4867 "[ AntDiv BF] is_no_csi_feedback= ((%d))\n",
4868 *fat_tab->is_no_csi_feedback);
4869 if (dm->ant_div_type != S0S1_SW_ANTDIV)
4870 odm_ant_div_on_off(dm, ANTDIV_ON
4871 , ANT_PATH_A)
4872 ;
4873 fat_tab->fix_ant_bfee = 0;
4874 }
4875 }
4876 } else {
4877 if (fat_tab->div_path_type == ANT_PATH_A)
4878 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4879 else if (fat_tab->div_path_type == ANT_PATH_B)
4880 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
4881 else if (fat_tab->div_path_type == ANT_PATH_AB)
4882 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
4883 }
4884 #endif
4885 }
4886 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
4887 /* @----------just for fool proof */
4888
4889 if (dm->antdiv_rssi)
4890 dm->debug_components |= DBG_ANT_DIV;
4891 else
4892 dm->debug_components &= ~DBG_ANT_DIV;
4893
4894 if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
4895 if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
4896 return;
4897 } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
4898 if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
4899 return;
4900 }
4901 #endif
4902
4903 /* @---------- */
4904
4905 if (dm->antdiv_select == 1)
4906 dm->ant_type = ODM_FIX_MAIN_ANT;
4907 else if (dm->antdiv_select == 2)
4908 dm->ant_type = ODM_FIX_AUX_ANT;
4909 else { /* @if (dm->antdiv_select==0) */
4910 dm->ant_type = ODM_AUTO_ANT;
4911
4912 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4913 /*Stop Antenna diversity for CMW500 testing case*/
4914 if (dm->consecutive_idlel_time >= 10) {
4915 dm->ant_type = ODM_FIX_MAIN_ANT;
4916 PHYDM_DBG(dm, DBG_ANT_DIV,
4917 "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n",
4918 dm->consecutive_idlel_time);
4919 }
4920 #endif
4921 }
4922
4923 /*PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (%d), pre_ant_type= (%d)\n",*/
4924 /*dm->ant_type,dm->pre_ant_type); */
4925
4926 if (dm->ant_type != ODM_AUTO_ANT) {
4927 PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
4928 (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
4929
4930 if (dm->ant_type != dm->pre_ant_type) {
4931 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4932 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4933
4934 if (dm->ant_type == ODM_FIX_MAIN_ANT)
4935 odm_update_rx_idle_ant(dm, MAIN_ANT);
4936 else if (dm->ant_type == ODM_FIX_AUX_ANT)
4937 odm_update_rx_idle_ant(dm, AUX_ANT);
4938 }
4939 dm->pre_ant_type = dm->ant_type;
4940 return;
4941 } else {
4942 if (dm->ant_type != dm->pre_ant_type) {
4943 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4944 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4945 }
4946 dm->pre_ant_type = dm->ant_type;
4947 }
4948 #if (defined(CONFIG_2T4R_ANTENNA))
4949 if (dm->ant_type2 != ODM_AUTO_ANT) {
4950 PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n",
4951 (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
4952
4953 if (dm->ant_type2 != dm->pre_ant_type2) {
4954 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
4955 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4956
4957 if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
4958 phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
4959 else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
4960 phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
4961 }
4962 dm->pre_ant_type2 = dm->ant_type2;
4963 return;
4964 }
4965 if (dm->ant_type2 != dm->pre_ant_type2) {
4966 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
4967 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4968 }
4969 dm->pre_ant_type2 = dm->ant_type2;
4970
4971 #endif
4972
4973 /*@ ----------------------------------------------- */
4974 /*@ [--8188E--] */
4975 if (dm->support_ic_type == ODM_RTL8188E) {
4976 #if (RTL8188E_SUPPORT == 1)
4977 if (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
4978 dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4979 odm_hw_ant_div(dm);
4980
4981 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
4982 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4983 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4984 odm_fast_ant_training(dm);
4985 #endif
4986
4987 #endif
4988 }
4989 /*@ [--8192E--] */
4990 #if (RTL8192E_SUPPORT == 1)
4991 else if (dm->support_ic_type == ODM_RTL8192E) {
4992 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV ||
4993 dm->ant_div_type == CG_TRX_HW_ANTDIV)
4994 odm_hw_ant_div(dm);
4995
4996 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
4997 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4998 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4999 odm_fast_ant_training(dm);
5000 #endif
5001 }
5002 #endif
5003 /*@ [--8197F--] */
5004 #if (RTL8197F_SUPPORT == 1)
5005 else if (dm->support_ic_type == ODM_RTL8197F) {
5006 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5007 odm_hw_ant_div(dm);
5008 }
5009 #endif
5010
5011 /*@ [--8197G--] */
5012 #if (RTL8197G_SUPPORT == 1)
5013 else if (dm->support_ic_type == ODM_RTL8197G) {
5014 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5015 odm_hw_ant_div(dm);
5016 }
5017 #endif
5018
5019 #if (RTL8723B_SUPPORT == 1)
5020 /*@ [--8723B---] */
5021 else if (dm->support_ic_type == ODM_RTL8723B) {
5022 if (phydm_is_bt_enable_8723b(dm)) {
5023 PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n");
5024 if (fat_tab->is_become_linked == true) {
5025 PHYDM_DBG(dm, DBG_ANT_DIV,
5026 "Set REG 948[9:6]=0x0\n");
5027 if (dm->support_ic_type == ODM_RTL8723B)
5028 odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0)
5029 ;
5030
5031 fat_tab->is_become_linked = false;
5032 }
5033 } else {
5034 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5035 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5036 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5037 #endif
5038 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5039 odm_hw_ant_div(dm);
5040 }
5041 }
5042 #endif
5043 /*@ [--8723D--]*/
5044 #if (RTL8723D_SUPPORT == 1)
5045 else if (dm->support_ic_type == ODM_RTL8723D) {
5046 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5047 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5048 if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {
5049 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5050 dm->antdiv_counter--;
5051 } else {
5052 dm->antdiv_counter--;
5053 }
5054 if (dm->antdiv_counter == 0)
5055 dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
5056 #endif
5057 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5058 odm_hw_ant_div(dm);
5059 }
5060 }
5061 #endif
5062 #if (RTL8721D_SUPPORT == 1)
5063 else if (dm->support_ic_type == ODM_RTL8721D) {
5064 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5065 odm_hw_ant_div(dm);
5066 }
5067 }
5068 #endif
5069 /*@ [--8821A--] */
5070 #if (RTL8821A_SUPPORT == 1)
5071 else if (dm->support_ic_type == ODM_RTL8821) {
5072 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
5073 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
5074 if (sat_tab->fix_beam_pattern_en != 0) {
5075 PHYDM_DBG(dm, DBG_ANT_DIV,
5076 " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
5077 sat_tab->fix_beam_pattern_codeword);
5078 /*return;*/
5079 } else {
5080 odm_fast_ant_training_hl_smart_antenna_type1(dm);
5081 }
5082
5083 } else
5084 #endif
5085 {
5086 #ifdef ODM_CONFIG_BT_COEXIST
5087 if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/
5088 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5089 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5090 PHYDM_DBG(dm, DBG_ANT_DIV,
5091 " [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n");
5092 /*odm_set_bb_reg(dm, 0x8d4, BIT24, 1);*/
5093 if (fat_tab->is_become_linked == true)
5094 odm_ant_div_on_off(dm,
5095 ANTDIV_ON,
5096 ANT_PATH_A);
5097 }
5098
5099 } else { /*@BT enabled*/
5100
5101 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5102 dm->ant_div_type = S0S1_SW_ANTDIV;
5103 PHYDM_DBG(dm, DBG_ANT_DIV,
5104 " [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n");
5105 /*odm_set_bb_reg(dm, 0x8d4, BIT24, 0);*/
5106 odm_ant_div_on_off(dm, ANTDIV_OFF,
5107 ANT_PATH_A);
5108 }
5109 }
5110 #endif
5111
5112 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5113 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5114 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5115 #endif
5116 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5117 odm_hw_ant_div(dm);
5118 }
5119 }
5120 }
5121 #endif
5122
5123 /*@ [--8821C--] */
5124 #if (RTL8821C_SUPPORT == 1)
5125 else if (dm->support_ic_type == ODM_RTL8821C) {
5126 if (!dm->is_bt_continuous_turn) {
5127 dm->ant_div_type = S0S1_SW_ANTDIV;
5128 PHYDM_DBG(dm, DBG_ANT_DIV,
5129 "is_bt_continuous_turn = ((%d)) ==> SW AntDiv\n",
5130 dm->is_bt_continuous_turn);
5131
5132 } else {
5133 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5134 PHYDM_DBG(dm, DBG_ANT_DIV,
5135 "is_bt_continuous_turn = ((%d)) ==> HW AntDiv\n",
5136 dm->is_bt_continuous_turn);
5137 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
5138 }
5139
5140 if (fat_tab->force_antdiv_type)
5141 dm->ant_div_type = fat_tab->antdiv_type_dbg;
5142
5143 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5144 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5145 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5146 #endif
5147 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
5148 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
5149 odm_hw_ant_div(dm);
5150 }
5151 }
5152 #endif
5153
5154 /* @ [--8881A--] */
5155 #if (RTL8881A_SUPPORT == 1)
5156 else if (dm->support_ic_type == ODM_RTL8881A)
5157 odm_hw_ant_div(dm);
5158 #endif
5159
5160 /*@ [--8812A--] */
5161 #if (RTL8812A_SUPPORT == 1)
5162 else if (dm->support_ic_type == ODM_RTL8812)
5163 odm_hw_ant_div(dm);
5164 #endif
5165
5166 #if (RTL8188F_SUPPORT == 1)
5167 /*@ [--8188F--]*/
5168 else if (dm->support_ic_type == ODM_RTL8188F) {
5169 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5170 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
5171 #endif
5172 }
5173 #endif
5174
5175 /*@ [--8822B--]*/
5176 #if (RTL8822B_SUPPORT == 1)
5177 else if (dm->support_ic_type == ODM_RTL8822B) {
5178 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
5179 odm_hw_ant_div(dm);
5180 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
5181 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
5182 if (sat_tab->fix_beam_pattern_en != 0)
5183 PHYDM_DBG(dm, DBG_ANT_DIV,
5184 " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
5185 sat_tab->fix_beam_pattern_codeword);
5186 else
5187 phydm_fast_ant_training_hl_smart_antenna_type2(dm);
5188 }
5189 #endif
5190 }
5191 #endif
5192 }
5193
odm_antsel_statistics(void * dm_void,void * phy_info_void,u8 antsel_tr_mux,u32 mac_id,u32 utility,u8 method,u8 is_cck_rate)5194 void odm_antsel_statistics(void *dm_void, void *phy_info_void,
5195 u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
5196 u8 is_cck_rate)
5197 {
5198 struct dm_struct *dm = (struct dm_struct *)dm_void;
5199 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5200 struct phydm_phyinfo_struct *phy_info = NULL;
5201
5202 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5203
5204 if (method == RSSI_METHOD) {
5205 if (is_cck_rate) {
5206 if (antsel_tr_mux == ANT1_2G) {
5207 /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
5208 if (fat_tab->main_sum_cck[mac_id] > 65435)
5209 return;
5210
5211 fat_tab->main_sum_cck[mac_id] += (u16)utility;
5212 fat_tab->main_cnt_cck[mac_id]++;
5213 } else {
5214 if (fat_tab->aux_sum_cck[mac_id] > 65435)
5215 return;
5216
5217 fat_tab->aux_sum_cck[mac_id] += (u16)utility;
5218 fat_tab->aux_cnt_cck[mac_id]++;
5219 }
5220
5221 } else { /*ofdm rate*/
5222
5223 if (antsel_tr_mux == ANT1_2G) {
5224 if (fat_tab->main_sum[mac_id] > 65435)
5225 return;
5226
5227 fat_tab->main_sum[mac_id] += (u16)utility;
5228 fat_tab->main_cnt[mac_id]++;
5229 } else {
5230 if (fat_tab->aux_sum[mac_id] > 65435)
5231 return;
5232
5233 fat_tab->aux_sum[mac_id] += (u16)utility;
5234 fat_tab->aux_cnt[mac_id]++;
5235 }
5236 }
5237 }
5238 #ifdef ODM_EVM_ENHANCE_ANTDIV
5239 else if (method == EVM_METHOD) {
5240 if (!fat_tab->get_stats)
5241 return;
5242
5243 if (dm->rate_ss == 1) {
5244 phydm_statistics_evm_1ss(dm, phy_info, antsel_tr_mux,
5245 mac_id, utility);
5246 } else { /*@>= 2SS*/
5247 phydm_statistics_evm_2ss(dm, phy_info, antsel_tr_mux,
5248 mac_id, utility);
5249 }
5250
5251 } else if (method == CRC32_METHOD) {
5252 if (antsel_tr_mux == ANT1_2G) {
5253 fat_tab->main_crc32_ok_cnt += utility;
5254 fat_tab->main_crc32_fail_cnt++;
5255 } else {
5256 fat_tab->aux_crc32_ok_cnt += utility;
5257 fat_tab->aux_crc32_fail_cnt++;
5258 }
5259
5260 } else if (method == TP_METHOD) {
5261 if (!fat_tab->get_stats)
5262 return;
5263 if (utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) {
5264 if (antsel_tr_mux == ANT1_2G) {
5265 fat_tab->main_tp += (phy_rate_table[utility])
5266 << 5;
5267 fat_tab->main_tp_cnt++;
5268 } else {
5269 fat_tab->aux_tp += (phy_rate_table[utility])
5270 << 5;
5271 fat_tab->aux_tp_cnt++;
5272 }
5273 }
5274 }
5275 #endif
5276 }
5277
odm_process_rssi_smart(void * dm_void,void * phy_info_void,void * pkt_info_void,u8 rx_power_ant0)5278 void odm_process_rssi_smart(void *dm_void, void *phy_info_void,
5279 void *pkt_info_void, u8 rx_power_ant0)
5280 {
5281 struct dm_struct *dm = (struct dm_struct *)dm_void;
5282 struct phydm_phyinfo_struct *phy_info = NULL;
5283 struct phydm_perpkt_info_struct *pktinfo = NULL;
5284 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5285
5286 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5287 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
5288
5289 if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) &&
5290 pktinfo->is_packet_to_self &&
5291 fat_tab->fat_state == FAT_TRAINING_STATE) {
5292 /* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */
5293 u8 antsel_tr_mux;
5294
5295 antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) |
5296 (fat_tab->antsel_rx_keep_1 << 1) |
5297 fat_tab->antsel_rx_keep_0;
5298 fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
5299 fat_tab->ant_rssi_cnt[antsel_tr_mux]++;
5300 }
5301 }
5302
odm_process_rssi_normal(void * dm_void,void * phy_info_void,void * pkt_info_void,u8 rx_pwr0)5303 void odm_process_rssi_normal(void *dm_void, void *phy_info_void,
5304 void *pkt_info_void, u8 rx_pwr0)
5305 {
5306 struct dm_struct *dm = (struct dm_struct *)dm_void;
5307 struct phydm_phyinfo_struct *phy_info = NULL;
5308 struct phydm_perpkt_info_struct *pktinfo = NULL;
5309 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5310 u8 rx_evm0, rx_evm1;
5311 boolean b_main;
5312
5313 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5314 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
5315 rx_evm0 = phy_info->rx_mimo_signal_quality[0];
5316 rx_evm1 = phy_info->rx_mimo_signal_quality[1];
5317
5318 if (!(pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv))
5319 return;
5320
5321 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
5322 if (pktinfo->is_cck_rate ||
5323 dm->support_ic_type == ODM_RTL8188F) {
5324
5325 b_main = (fat_tab->rx_idle_ant == MAIN_ANT);
5326 fat_tab->antsel_rx_keep_0 = b_main ? ANT1_2G : ANT2_2G;
5327 }
5328
5329 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5330 pktinfo->station_id, rx_pwr0, RSSI_METHOD,
5331 pktinfo->is_cck_rate);
5332 } else {
5333 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5334 pktinfo->station_id, rx_pwr0, RSSI_METHOD,
5335 pktinfo->is_cck_rate);
5336
5337 #ifdef ODM_EVM_ENHANCE_ANTDIV
5338 if (!(dm->support_ic_type & ODM_EVM_ANTDIV_IC))
5339 return;
5340 if (pktinfo->is_cck_rate)
5341 return;
5342
5343 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5344 pktinfo->station_id, rx_evm0, EVM_METHOD,
5345 pktinfo->is_cck_rate);
5346 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
5347 pktinfo->station_id, pktinfo->data_rate,
5348 TP_METHOD, pktinfo->is_cck_rate);
5349 #endif
5350 }
5351 }
5352
odm_process_rssi_for_ant_div(void * dm_void,void * phy_info_void,void * pkt_info_void)5353 void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
5354 void *pkt_info_void)
5355 {
5356 struct dm_struct *dm = (struct dm_struct *)dm_void;
5357 struct phydm_phyinfo_struct *phy_info = NULL;
5358 struct phydm_perpkt_info_struct *pktinfo = NULL;
5359 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5360 #if (defined(CONFIG_HL_SMART_ANTENNA))
5361 struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
5362 u32 beam_tmp;
5363 u8 next_ant;
5364 u8 train_pkt_number;
5365 #endif
5366 boolean b_main;
5367 u8 rx_power_ant0, rx_power_ant1;
5368 u8 rx_evm_ant0, rx_evm_ant1;
5369 u8 rssi_avg;
5370 u64 rssi_linear = 0;
5371
5372 phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
5373 pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
5374 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
5375 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
5376 rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];
5377 rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];
5378
5379 if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {
5380 if (rx_power_ant1 < 100) {
5381 rssi_linear = phydm_db_2_linear(rx_power_ant0) +
5382 phydm_db_2_linear(rx_power_ant1);
5383 /* @Rounding and removing fractional bits */
5384 rssi_linear = (rssi_linear +
5385 (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
5386 /* @Calculate average RSSI */
5387 rssi_linear = DIVIDED_2(rssi_linear);
5388 /* @averaged PWDB */
5389 rssi_avg = (u8)odm_convert_to_db(rssi_linear);
5390 }
5391
5392 } else {
5393 rx_power_ant0 = (u8)phy_info->rx_pwdb_all;
5394 rssi_avg = rx_power_ant0;
5395 }
5396
5397 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
5398 if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))
5399 phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/
5400 else
5401 #endif
5402
5403 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
5404 #ifdef CONFIG_FAT_PATCH
5405 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {
5406 /*@[Beacon]*/
5407 if (pktinfo->is_packet_beacon) {
5408 sat_tab->beacon_counter++;
5409 PHYDM_DBG(dm, DBG_ANT_DIV,
5410 "MatchBSSID_beacon_counter = ((%d))\n",
5411 sat_tab->beacon_counter);
5412
5413 if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
5414 if (sat_tab->ant_num > 1) {
5415 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
5416 odm_update_rx_idle_ant(dm, next_ant);
5417 }
5418
5419 sat_tab->update_beam_idx++;
5420
5421 PHYDM_DBG(dm, DBG_ANT_DIV,
5422 "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
5423 sat_tab->pre_beacon_counter,
5424 sat_tab->pkt_counter,
5425 sat_tab->update_beam_idx);
5426
5427 sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
5428 sat_tab->pkt_counter = 0;
5429 }
5430 }
5431 /*@[data]*/
5432 else if (pktinfo->is_packet_to_self) {
5433 if (sat_tab->pkt_skip_statistic_en == 0) {
5434 /*@
5435 PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
5436 pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
5437 */
5438 PHYDM_DBG(dm, DBG_ANT_DIV,
5439 "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
5440 pktinfo->station_id,
5441 sat_tab->pkt_counter,
5442 fat_tab->antsel_rx_keep_0,
5443 sat_tab->fast_training_beam_num,
5444 rx_power_ant0);
5445
5446 sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
5447 sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
5448 sat_tab->pkt_counter++;
5449
5450 #if 1
5451 train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];
5452 #else
5453 train_pkt_number = sat_tab->per_beam_training_pkt_num;
5454 #endif
5455
5456 /*Swich Antenna erery N pkts*/
5457 if (sat_tab->pkt_counter == train_pkt_number) {
5458 if (sat_tab->ant_num > 1) {
5459 PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number);
5460 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
5461 odm_update_rx_idle_ant(dm, next_ant);
5462 }
5463
5464 sat_tab->update_beam_idx++;
5465 PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
5466 sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);
5467
5468 sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
5469 sat_tab->pkt_counter = 0;
5470 }
5471 }
5472 }
5473
5474 /*Swich Beam after switch "sat_tab->ant_num" antennas*/
5475 if (sat_tab->update_beam_idx == sat_tab->ant_num) {
5476 sat_tab->update_beam_idx = 0;
5477 sat_tab->pkt_counter = 0;
5478 beam_tmp = sat_tab->fast_training_beam_num;
5479
5480 if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
5481 fat_tab->fat_state = FAT_DECISION_STATE;
5482
5483 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
5484 if (dm->support_interface == ODM_ITRF_PCIE)
5485 odm_fast_ant_training_hl_smart_antenna_type1(dm);
5486 #endif
5487 #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
5488 if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
5489 odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
5490 #endif
5491
5492 } else {
5493 sat_tab->fast_training_beam_num++;
5494 PHYDM_DBG(dm, DBG_ANT_DIV,
5495 "Update Beam_num (( %d )) -> (( %d ))\n",
5496 beam_tmp,
5497 sat_tab->fast_training_beam_num);
5498 phydm_set_all_ant_same_beam_num(dm);
5499
5500 fat_tab->fat_state = FAT_TRAINING_STATE;
5501 }
5502 }
5503 }
5504 #else
5505
5506 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
5507 if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
5508 pktinfo->is_packet_to_self &&
5509 fat_tab->fat_state == FAT_TRAINING_STATE) {
5510 if (sat_tab->pkt_skip_statistic_en == 0) {
5511 /*@
5512 PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
5513 pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
5514 */
5515 PHYDM_DBG(dm, DBG_ANT_DIV,
5516 "StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
5517 pktinfo->station_id,
5518 fat_tab->antsel_rx_keep_0,
5519 pktinfo->is_packet_to_self,
5520 sat_tab->fast_training_beam_num,
5521 rx_power_ant0);
5522
5523 sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
5524 sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
5525 sat_tab->pkt_counter++;
5526
5527 /*swich beam every N pkt*/
5528 if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {
5529 sat_tab->pkt_counter = 0;
5530 beam_tmp = sat_tab->fast_training_beam_num;
5531
5532 if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
5533 fat_tab->fat_state = FAT_DECISION_STATE;
5534
5535 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
5536 if (dm->support_interface == ODM_ITRF_PCIE)
5537 odm_fast_ant_training_hl_smart_antenna_type1(dm);
5538 #endif
5539 #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
5540 if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
5541 odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
5542 #endif
5543
5544 } else {
5545 sat_tab->fast_training_beam_num++;
5546 phydm_set_all_ant_same_beam_num(dm);
5547
5548 fat_tab->fat_state = FAT_TRAINING_STATE;
5549 PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num);
5550 }
5551 }
5552 }
5553 }
5554 }
5555 #endif
5556 else
5557 #endif
5558 if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
5559 odm_process_rssi_smart(dm, phy_info, pktinfo,
5560 rx_power_ant0);
5561 } else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */
5562 odm_process_rssi_normal(dm, phy_info, pktinfo,
5563 rx_power_ant0);
5564 }
5565 #if 0
5566 /* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",
5567 * pktinfo->is_cck_rate, phy_info->rx_pwdb_all);
5568 * PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",
5569 * fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1,
5570 * fat_tab->antsel_rx_keep_0);
5571 */
5572 #endif
5573 }
5574
5575 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
odm_set_tx_ant_by_tx_info(void * dm_void,u8 * desc,u8 mac_id)5576 void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id)
5577 {
5578 struct dm_struct *dm = (struct dm_struct *)dm_void;
5579 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5580
5581 if (!(dm->support_ability & ODM_BB_ANT_DIV))
5582 return;
5583
5584 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5585 return;
5586
5587 if (dm->support_ic_type == (ODM_RTL8723B | ODM_RTL8721D)) {
5588 #if (RTL8723B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
5589 SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);
5590 /*PHYDM_DBG(dm,DBG_ANT_DIV,
5591 * "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
5592 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
5593 * fat_tab->antsel_a[mac_id]);
5594 */
5595 #endif
5596 } else if (dm->support_ic_type == ODM_RTL8821) {
5597 #if (RTL8821A_SUPPORT == 1)
5598 SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);
5599 /*PHYDM_DBG(dm,DBG_ANT_DIV,
5600 * "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
5601 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
5602 * fat_tab->antsel_a[mac_id]);
5603 */
5604 #endif
5605 } else if (dm->support_ic_type == ODM_RTL8188E) {
5606 #if (RTL8188E_SUPPORT == 1)
5607 SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);
5608 SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);
5609 SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);
5610 /*PHYDM_DBG(dm,DBG_ANT_DIV,
5611 * "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
5612 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
5613 * fat_tab->antsel_a[mac_id]);
5614 */
5615 #endif
5616 } else if (dm->support_ic_type == ODM_RTL8821C) {
5617 #if (RTL8821C_SUPPORT == 1)
5618 SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);
5619 /*PHYDM_DBG(dm,DBG_ANT_DIV,
5620 * "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
5621 * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
5622 * fat_tab->antsel_a[mac_id]);
5623 */
5624 #endif
5625 } else if (dm->support_ic_type == ODM_RTL8822B) {
5626 #if (RTL8822B_SUPPORT == 1)
5627 SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);
5628 #endif
5629
5630 }
5631 }
5632 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
5633
odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv * priv,struct tx_desc * pdesc,unsigned short aid)5634 void odm_set_tx_ant_by_tx_info(
5635 struct rtl8192cd_priv *priv,
5636 struct tx_desc *pdesc,
5637 unsigned short aid)
5638 {
5639 struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
5640 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5641
5642 if (!(dm->support_ability & ODM_BB_ANT_DIV))
5643 return;
5644
5645 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5646 return;
5647
5648 if (dm->support_ic_type == ODM_RTL8881A) {
5649 #if 0
5650 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */
5651 #endif
5652 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
5653 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
5654 } else if (dm->support_ic_type == ODM_RTL8192E) {
5655 #if 0
5656 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */
5657 #endif
5658 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
5659 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
5660 } else if (dm->support_ic_type == ODM_RTL8197F) {
5661 #if 0
5662 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */
5663 #endif
5664 pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
5665 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
5666 } else if (dm->support_ic_type == ODM_RTL8822B) {
5667 pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
5668 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
5669 } else if (dm->support_ic_type == ODM_RTL8188E) {
5670 #if 0
5671 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
5672 #endif
5673 pdesc->Dword2 &= set_desc(~BIT(24));
5674 pdesc->Dword2 &= set_desc(~BIT(25));
5675 pdesc->Dword7 &= set_desc(~BIT(29));
5676
5677 pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);
5678 pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);
5679 pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);
5680
5681 } else if (dm->support_ic_type == ODM_RTL8812) {
5682 /*@[path-A]*/
5683 #if 0
5684 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
5685 #endif
5686
5687 pdesc->Dword6 &= set_desc(~BIT(16));
5688 pdesc->Dword6 &= set_desc(~BIT(17));
5689 pdesc->Dword6 &= set_desc(~BIT(18));
5690
5691 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
5692 pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);
5693 pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);
5694 }
5695 }
5696
5697 #if 1 /*@def CONFIG_WLAN_HAL*/
odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv * priv,void * pdesc_data,u16 aid)5698 void odm_set_tx_ant_by_tx_info_hal(
5699 struct rtl8192cd_priv *priv,
5700 void *pdesc_data,
5701 u16 aid)
5702 {
5703 struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
5704 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5705 PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
5706
5707 if (!(dm->support_ability & ODM_BB_ANT_DIV))
5708 return;
5709
5710 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5711 return;
5712
5713 if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A |
5714 ODM_RTL8197F | ODM_RTL8822B)) {
5715 #if 0
5716 /*panic_printk("[%s] [%d] **odm_set_tx_ant_by_tx_info_hal**\n",
5717 * __FUNCTION__,__LINE__);
5718 */
5719 #endif
5720 pdescdata->ant_sel = 1;
5721 pdescdata->ant_sel_a = fat_tab->antsel_a[aid];
5722 }
5723 }
5724 #endif /*@#ifdef CONFIG_WLAN_HAL*/
5725
5726 #endif
5727
odm_ant_div_config(void * dm_void)5728 void odm_ant_div_config(void *dm_void)
5729 {
5730 struct dm_struct *dm = (struct dm_struct *)dm_void;
5731 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5732 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
5733 PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n");
5734 /*@
5735 if(dm->support_ic_type==ODM_RTL8723B)
5736 {
5737 if((!dm->swat_tab.ANTA_ON || !dm->swat_tab.ANTB_ON))
5738 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5739 }
5740 */
5741 #if (defined(CONFIG_2T3R_ANTENNA))
5742 #if (RTL8822B_SUPPORT == 1)
5743 dm->rfe_type = ANT_2T3R_RFE_TYPE;
5744 #endif
5745 #endif
5746
5747 #if (defined(CONFIG_2T4R_ANTENNA))
5748 #if (RTL8822B_SUPPORT == 1)
5749 dm->rfe_type = ANT_2T4R_RFE_TYPE;
5750 #endif
5751 #endif
5752
5753 if (dm->support_ic_type == ODM_RTL8723D)
5754 dm->ant_div_type = S0S1_SW_ANTDIV;
5755 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
5756
5757 PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n");
5758
5759 if (dm->support_ic_type == ODM_RTL8723B)
5760 dm->ant_div_type = S0S1_SW_ANTDIV;
5761
5762 if (dm->support_ic_type == ODM_RTL8723D)
5763 dm->ant_div_type = S0S1_SW_ANTDIV;
5764 #elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
5765
5766 PHYDM_DBG(dm, DBG_ANT_DIV, "IOT Config Antenna Diversity\n");
5767
5768 if (dm->support_ic_type == ODM_RTL8721D)
5769 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5770
5771 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
5772
5773 PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n");
5774
5775 /* @2 [ NOT_SUPPORT_ANTDIV ] */
5776 #if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
5777 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5778 PHYDM_DBG(dm, DBG_ANT_DIV,
5779 "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n");
5780
5781 /* @2 [ 2G&5G_SUPPORT_ANTDIV ] */
5782 #elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
5783 PHYDM_DBG(dm, DBG_ANT_DIV,
5784 "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n");
5785 fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
5786
5787 if (dm->support_ic_type & ODM_ANTDIV_SUPPORT)
5788 dm->support_ability |= ODM_BB_ANT_DIV;
5789 if (*dm->band_type == ODM_BAND_5G) {
5790 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
5791 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5792 PHYDM_DBG(dm, DBG_ANT_DIV,
5793 "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5794 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5795 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) ||\
5796 defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
5797 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5798 PHYDM_DBG(dm, DBG_ANT_DIV,
5799 "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5800 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5801 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
5802 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5803 PHYDM_DBG(dm, DBG_ANT_DIV,
5804 "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
5805 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
5806 dm->ant_div_type = S0S1_SW_ANTDIV;
5807 PHYDM_DBG(dm, DBG_ANT_DIV,
5808 "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
5809 #endif
5810 } else if (*dm->band_type == ODM_BAND_2_4G) {
5811 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
5812 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5813 PHYDM_DBG(dm, DBG_ANT_DIV,
5814 "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5815 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) ||\
5816 defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
5817 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5818 PHYDM_DBG(dm, DBG_ANT_DIV,
5819 "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5820 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5821 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5822 PHYDM_DBG(dm, DBG_ANT_DIV,
5823 "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
5824 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
5825 dm->ant_div_type = S0S1_SW_ANTDIV;
5826 PHYDM_DBG(dm, DBG_ANT_DIV,
5827 "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
5828 #endif
5829 }
5830
5831 /* @2 [ 5G_SUPPORT_ANTDIV ] */
5832 #elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
5833 PHYDM_DBG(dm, DBG_ANT_DIV,
5834 "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
5835 panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
5836 fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);
5837 if (*dm->band_type == ODM_BAND_5G) {
5838 if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
5839 dm->support_ability |= ODM_BB_ANT_DIV;
5840 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
5841 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5842 PHYDM_DBG(dm, DBG_ANT_DIV,
5843 "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5844 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5845 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
5846 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5847 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5848 PHYDM_DBG(dm, DBG_ANT_DIV,
5849 "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5850 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
5851 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5852 PHYDM_DBG(dm, DBG_ANT_DIV,
5853 "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
5854 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
5855 dm->ant_div_type = S0S1_SW_ANTDIV;
5856 PHYDM_DBG(dm, DBG_ANT_DIV,
5857 "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
5858 #endif
5859 } else if (*dm->band_type == ODM_BAND_2_4G) {
5860 PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n");
5861 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5862 }
5863
5864 /* @2 [ 2G_SUPPORT_ANTDIV ] */
5865 #elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
5866 PHYDM_DBG(dm, DBG_ANT_DIV,
5867 "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n");
5868 fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);
5869 if (*dm->band_type == ODM_BAND_2_4G) {
5870 if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
5871 dm->support_ability |= ODM_BB_ANT_DIV;
5872 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
5873 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5874 PHYDM_DBG(dm, DBG_ANT_DIV,
5875 "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5876 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
5877 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5878 PHYDM_DBG(dm, DBG_ANT_DIV,
5879 "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5880 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5881 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5882 PHYDM_DBG(dm, DBG_ANT_DIV,
5883 "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
5884 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
5885 dm->ant_div_type = S0S1_SW_ANTDIV;
5886 PHYDM_DBG(dm, DBG_ANT_DIV,
5887 "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
5888 #endif
5889 } else if (*dm->band_type == ODM_BAND_5G) {
5890 PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n");
5891 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5892 }
5893 #endif
5894
5895 if (!(dm->support_ic_type & ODM_ANTDIV_SUPPORT_IC)) {
5896 fat_tab->ant_div_2g_5g = 0;
5897 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5898 }
5899 #endif
5900
5901 PHYDM_DBG(dm, DBG_ANT_DIV,
5902 "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n",
5903 ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));
5904 PHYDM_DBG(dm, DBG_ANT_DIV,
5905 "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n",
5906 dm->dm_fat_table.b_fix_tx_ant);
5907 }
5908
odm_ant_div_timers(void * dm_void,u8 state)5909 void odm_ant_div_timers(void *dm_void, u8 state)
5910 {
5911 struct dm_struct *dm = (struct dm_struct *)dm_void;
5912 if (state == INIT_ANTDIV_TIMMER) {
5913 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5914 odm_initialize_timer(dm,
5915 &dm->dm_swat_table.sw_antdiv_timer,
5916 (void *)odm_sw_antdiv_callback, NULL,
5917 "sw_antdiv_timer");
5918 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
5919 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5920 odm_initialize_timer(dm, &dm->fast_ant_training_timer,
5921 (void *)odm_fast_ant_training_callback,
5922 NULL, "fast_ant_training_timer");
5923 #endif
5924
5925 #ifdef ODM_EVM_ENHANCE_ANTDIV
5926 odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,
5927 (void *)phydm_evm_antdiv_callback, NULL,
5928 "evm_fast_ant_training_timer");
5929 #endif
5930 } else if (state == CANCEL_ANTDIV_TIMMER) {
5931 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5932 odm_cancel_timer(dm,
5933 &dm->dm_swat_table.sw_antdiv_timer);
5934 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
5935 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5936 odm_cancel_timer(dm, &dm->fast_ant_training_timer);
5937 #endif
5938
5939 #ifdef ODM_EVM_ENHANCE_ANTDIV
5940 odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);
5941 #endif
5942 } else if (state == RELEASE_ANTDIV_TIMMER) {
5943 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5944 odm_release_timer(dm,
5945 &dm->dm_swat_table.sw_antdiv_timer);
5946 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
5947 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5948 odm_release_timer(dm, &dm->fast_ant_training_timer);
5949 #endif
5950
5951 #ifdef ODM_EVM_ENHANCE_ANTDIV
5952 odm_release_timer(dm, &dm->evm_fast_ant_training_timer);
5953 #endif
5954 }
5955 }
5956
phydm_antdiv_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)5957 void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
5958 char *output, u32 *_out_len)
5959 {
5960 struct dm_struct *dm = (struct dm_struct *)dm_void;
5961 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5962 u32 used = *_used;
5963 u32 out_len = *_out_len;
5964 u32 dm_value[10] = {0};
5965 char help[] = "-h";
5966 u8 i, input_idx = 0;
5967
5968 for (i = 0; i < 5; i++) {
5969 if (input[i + 1]) {
5970 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
5971 input_idx++;
5972 }
5973 }
5974
5975 if (input_idx == 0)
5976 return;
5977
5978 if ((strcmp(input[1], help) == 0)) {
5979 PDM_SNPF(out_len, used, output + used, out_len - used,
5980 "{1} {0:auto, 1:fix main, 2:fix auto}\n");
5981 PDM_SNPF(out_len, used, output + used, out_len - used,
5982 "{2} {antdiv_period}\n");
5983 #if (RTL8821C_SUPPORT == 1)
5984 PDM_SNPF(out_len, used, output + used, out_len - used,
5985 "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n");
5986 #endif
5987
5988 } else if (dm_value[0] == 1) {
5989 /*@fixed or auto antenna*/
5990 if (dm_value[1] == 0) {
5991 dm->ant_type = ODM_AUTO_ANT;
5992 PDM_SNPF(out_len, used, output + used, out_len - used,
5993 "AntDiv: Auto\n");
5994 } else if (dm_value[1] == 1) {
5995 dm->ant_type = ODM_FIX_MAIN_ANT;
5996 PDM_SNPF(out_len, used, output + used, out_len - used,
5997 "AntDiv: Fix Main\n");
5998 } else if (dm_value[1] == 2) {
5999 dm->ant_type = ODM_FIX_AUX_ANT;
6000 PDM_SNPF(out_len, used, output + used, out_len - used,
6001 "AntDiv: Fix Aux\n");
6002 }
6003
6004 if (dm->ant_type != ODM_AUTO_ANT) {
6005 odm_stop_antenna_switch_dm(dm);
6006 if (dm->ant_type == ODM_FIX_MAIN_ANT)
6007 odm_update_rx_idle_ant(dm, MAIN_ANT);
6008 else if (dm->ant_type == ODM_FIX_AUX_ANT)
6009 odm_update_rx_idle_ant(dm, AUX_ANT);
6010 } else {
6011 phydm_enable_antenna_diversity(dm);
6012 }
6013 dm->pre_ant_type = dm->ant_type;
6014 } else if (dm_value[0] == 2) {
6015 /*@dynamic period for AntDiv*/
6016 dm->antdiv_period = (u8)dm_value[1];
6017 PDM_SNPF(out_len, used, output + used, out_len - used,
6018 "AntDiv_period=((%d))\n", dm->antdiv_period);
6019 }
6020 #if (RTL8821C_SUPPORT == 1)
6021 else if (dm_value[0] == 3 &&
6022 dm->support_ic_type == ODM_RTL8821C) {
6023 /*Only for 8821C*/
6024 if (dm_value[1] == 0) {
6025 fat_tab->force_antdiv_type = false;
6026 PDM_SNPF(out_len, used, output + used, out_len - used,
6027 "[8821C] AntDiv: Default\n");
6028 } else if (dm_value[1] == 1) {
6029 fat_tab->force_antdiv_type = true;
6030 fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;
6031 PDM_SNPF(out_len, used, output + used, out_len - used,
6032 "[8821C] AntDiv: HW diversity\n");
6033 } else if (dm_value[1] == 2) {
6034 fat_tab->force_antdiv_type = true;
6035 fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;
6036 PDM_SNPF(out_len, used, output + used, out_len - used,
6037 "[8821C] AntDiv: SW diversity\n");
6038 }
6039 }
6040 #endif
6041 #ifdef ODM_EVM_ENHANCE_ANTDIV
6042 else if (dm_value[0] == 4) {
6043 if (dm_value[1] == 0) {
6044 /*@init parameters for EVM AntDiv*/
6045 phydm_evm_sw_antdiv_init(dm);
6046 PDM_SNPF(out_len, used, output + used, out_len - used,
6047 "init evm antdiv parameters\n");
6048 } else if (dm_value[1] == 1) {
6049 /*training number for EVM AntDiv*/
6050 dm->antdiv_train_num = (u8)dm_value[2];
6051 PDM_SNPF(out_len, used, output + used, out_len - used,
6052 "antdiv_train_num = ((%d))\n",
6053 dm->antdiv_train_num);
6054 } else if (dm_value[1] == 2) {
6055 /*training interval for EVM AntDiv*/
6056 dm->antdiv_intvl = (u8)dm_value[2];
6057 PDM_SNPF(out_len, used, output + used, out_len - used,
6058 "antdiv_intvl = ((%d))\n",
6059 dm->antdiv_intvl);
6060 } else if (dm_value[1] == 3) {
6061 /*@function period for EVM AntDiv*/
6062 dm->evm_antdiv_period = (u8)dm_value[2];
6063 PDM_SNPF(out_len, used, output + used, out_len - used,
6064 "evm_antdiv_period = ((%d))\n",
6065 dm->evm_antdiv_period);
6066 } else if (dm_value[1] == 100) {/*show parameters*/
6067 PDM_SNPF(out_len, used, output + used, out_len - used,
6068 "ant_type = ((%d))\n", dm->ant_type);
6069 PDM_SNPF(out_len, used, output + used, out_len - used,
6070 "antdiv_train_num = ((%d))\n",
6071 dm->antdiv_train_num);
6072 PDM_SNPF(out_len, used, output + used, out_len - used,
6073 "antdiv_intvl = ((%d))\n",
6074 dm->antdiv_intvl);
6075 PDM_SNPF(out_len, used, output + used, out_len - used,
6076 "evm_antdiv_period = ((%d))\n",
6077 dm->evm_antdiv_period);
6078 }
6079 }
6080 #ifdef CONFIG_2T4R_ANTENNA
6081 else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/
6082
6083 if (dm_value[1] == 0) {
6084 dm->ant_type2 = ODM_AUTO_ANT;
6085 PDM_SNPF(out_len, used, output + used, out_len - used,
6086 "AntDiv: PathB Auto\n");
6087 } else if (dm_value[1] == 1) {
6088 dm->ant_type2 = ODM_FIX_MAIN_ANT;
6089 PDM_SNPF(out_len, used, output + used, out_len - used,
6090 "AntDiv: PathB Fix Main\n");
6091 } else if (dm_value[1] == 2) {
6092 dm->ant_type2 = ODM_FIX_AUX_ANT;
6093 PDM_SNPF(out_len, used, output + used, out_len - used,
6094 "AntDiv: PathB Fix Aux\n");
6095 }
6096
6097 if (dm->ant_type2 != ODM_AUTO_ANT) {
6098 odm_stop_antenna_switch_dm(dm);
6099 if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
6100 phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
6101 else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
6102 phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
6103 } else {
6104 phydm_enable_antenna_diversity(dm);
6105 }
6106 dm->pre_ant_type2 = dm->ant_type2;
6107 }
6108 #endif
6109 #endif
6110 *_used = used;
6111 *_out_len = out_len;
6112 }
6113
odm_ant_div_reset(void * dm_void)6114 void odm_ant_div_reset(void *dm_void)
6115 {
6116 struct dm_struct *dm = (struct dm_struct *)dm_void;
6117
6118 if (!(dm->support_ability & ODM_BB_ANT_DIV))
6119 return;
6120
6121 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
6122 if (dm->ant_div_type == S0S1_SW_ANTDIV)
6123 odm_s0s1_sw_ant_div_reset(dm);
6124 #endif
6125 }
6126
odm_antenna_diversity_init(void * dm_void)6127 void odm_antenna_diversity_init(void *dm_void)
6128 {
6129 struct dm_struct *dm = (struct dm_struct *)dm_void;
6130
6131 odm_ant_div_config(dm);
6132 odm_ant_div_init(dm);
6133 }
6134
odm_antenna_diversity(void * dm_void)6135 void odm_antenna_diversity(void *dm_void)
6136 {
6137 struct dm_struct *dm = (struct dm_struct *)dm_void;
6138
6139 if (*dm->mp_mode)
6140 return;
6141
6142 if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
6143 PHYDM_DBG(dm, DBG_ANT_DIV,
6144 "[Return!!!] Not Support Antenna Diversity Function\n");
6145 return;
6146 }
6147
6148 if (dm->pause_ability & ODM_BB_ANT_DIV) {
6149 PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n",
6150 dm->pause_lv_table.lv_antdiv);
6151 return;
6152 }
6153
6154 odm_ant_div(dm);
6155 }
6156 #endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
6157
6158