1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __HALDMOUTSRC_H__ 27 #define __HALDMOUTSRC_H__ 28 29 /*@============================================================*/ 30 /*@include files*/ 31 /*@============================================================*/ 32 /*PHYDM header*/ 33 #include "phydm_pre_define.h" 34 #include "phydm_features.h" 35 #include "phydm_dig.h" 36 #ifdef CONFIG_PATH_DIVERSITY 37 #include "phydm_pathdiv.h" 38 #endif 39 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 40 #include "phydm_antdiv.h" 41 #endif 42 43 #include "phydm_soml.h" 44 45 #ifdef CONFIG_SMART_ANTENNA 46 #include "phydm_smt_ant.h" 47 #endif 48 #ifdef CONFIG_ANT_DETECTION 49 #include "phydm_antdect.h" 50 #endif 51 #include "phydm_rainfo.h" 52 #ifdef CONFIG_DYNAMIC_TX_TWR 53 #include "phydm_dynamictxpower.h" 54 #endif 55 #include "phydm_cfotracking.h" 56 #include "phydm_adaptivity.h" 57 #include "phydm_dfs.h" 58 #include "phydm_ccx.h" 59 #include "txbf/phydm_hal_txbf_api.h" 60 #if (PHYDM_LA_MODE_SUPPORT) 61 #include "phydm_adc_sampling.h" 62 #endif 63 #ifdef CONFIG_PSD_TOOL 64 #include "phydm_psd.h" 65 #endif 66 #ifdef PHYDM_PRIMARY_CCA 67 #include "phydm_primary_cca.h" 68 #endif 69 #include "phydm_cck_pd.h" 70 #include "phydm_rssi_monitor.h" 71 #ifdef PHYDM_AUTO_DEGBUG 72 #include "phydm_auto_dbg.h" 73 #endif 74 #include "phydm_math_lib.h" 75 #include "phydm_noisemonitor.h" 76 #include "phydm_api.h" 77 #ifdef PHYDM_POWER_TRAINING_SUPPORT 78 #include "phydm_pow_train.h" 79 #endif 80 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 81 #include "phydm_lna_sat.h" 82 #endif 83 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 84 #include "phydm_pmac_tx_setting.h" 85 #endif 86 #ifdef PHYDM_MP_SUPPORT 87 #include "phydm_mp.h" 88 #endif 89 90 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 91 #include "phydm_cck_rx_pathdiv.h" 92 #endif 93 94 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 95 #include "phydm_beamforming.h" 96 #endif 97 98 #ifdef CONFIG_DIRECTIONAL_BF 99 #include "phydm_direct_bf.h" 100 #endif 101 102 #include "phydm_regtable.h" 103 104 /*@HALRF header*/ 105 #include "halrf/halrf_iqk.h" 106 #include "halrf/halrf_dpk.h" 107 #include "halrf/halrf.h" 108 #include "halrf/halrf_powertracking.h" 109 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 110 #include "halrf/halphyrf_ap.h" 111 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 112 #include "halrf/halphyrf_ce.h" 113 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 114 #include "halrf/halphyrf_win.h" 115 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 116 #include "halrf/halphyrf_iot.h" 117 #endif 118 119 extern const u16 phy_rate_table[84]; 120 121 /*@============================================================*/ 122 /*@Definition */ 123 /*@============================================================*/ 124 125 /* Traffic load decision */ 126 #define TRAFFIC_NO_TP 0 127 #define TRAFFIC_ULTRA_LOW 1 128 #define TRAFFIC_LOW 2 129 #define TRAFFIC_MID 3 130 #define TRAFFIC_HIGH 4 131 132 #define NONE 0 133 134 #if defined(DM_ODM_CE_MAC80211) 135 #define MAX_2(x, y) \ 136 __max2(typeof(x), typeof(y), \ 137 x, y) 138 #define __max2(t1, t2, x, y) ({ \ 139 t1 m80211_max1 = (x); \ 140 t2 m80211_max2 = (y); \ 141 m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) 142 143 #define MIN_2(x, y) \ 144 __min2(typeof(x), typeof(y), \ 145 x, y) 146 #define __min2(t1, t2, x, y) ({ \ 147 t1 m80211_min1 = (x); \ 148 t2 m80211_min2 = (y); \ 149 m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) 150 151 #define DIFF_2(x, y) \ 152 __diff2(typeof(x), typeof(y), \ 153 x, y) 154 #define __diff2(t1, t2, x, y) ({ \ 155 t1 __d1 = (x); \ 156 t2 __d2 = (y); \ 157 (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) 158 #else 159 #define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) 160 #define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) 161 #define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) 162 #endif 163 164 #define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) 165 #define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) 166 167 #if defined(DM_ODM_CE_MAC80211) 168 #define BYTE_DUPLICATE_2_DWORD(B0) ({ \ 169 u32 __b_dup = (B0);\ 170 (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ 171 }) 172 #else 173 #define BYTE_DUPLICATE_2_DWORD(B0) \ 174 (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) 175 #endif 176 #define BYTE_2_DWORD(B3, B2, B1, B0) \ 177 (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) 178 #define BIT_2_BYTE(B3, B2, B1, B0) \ 179 (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) 180 181 /*@For cmn sta info*/ 182 #if defined(DM_ODM_CE_MAC80211) 183 #define is_sta_active(sta) ({ \ 184 struct cmn_sta_info *__sta = (sta); \ 185 ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ 186 }) 187 188 #define IS_FUNC_EN(name) ({ \ 189 u8 *__is_func_name = (name); \ 190 (__is_func_name) && (*__is_func_name); \ 191 }) 192 #else 193 #define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 194 195 #define IS_FUNC_EN(name) ((name) && (*name)) 196 #endif 197 198 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 199 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 200 #else 201 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 202 #endif 203 204 #define PHY_HIST_SIZE 12 205 #define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) 206 207 /*@============================================================*/ 208 /*structure and define*/ 209 /*@============================================================*/ 210 211 #define dm_type_by_fw 0 212 #define dm_type_by_driver 1 213 214 #ifdef BB_RAM_SUPPORT 215 216 struct phydm_bb_ram_per_sta { 217 /* @Reg0x1E84 for RAM I/O*/ 218 boolean hw_igi_en; 219 boolean tx_pwr_offset0_en; 220 boolean tx_pwr_offset1_en; 221 /* @ macid from 0 to 63, above 63 => mapping to 63*/ 222 u8 macid_addr; 223 /* @hw_igi value for paths after packet Tx in a period of time*/ 224 u8 hw_igi; 225 /* @tx_pwr_offset0 offset for Tx power index*/ 226 s8 tx_pwr_offset0; 227 s8 tx_pwr_offset1; 228 229 }; 230 231 struct phydm_bb_ram_ctrl { 232 /*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/ 233 struct phydm_bb_ram_per_sta pram_sta_ctrl[64]; 234 /*------------ For table2 do not set power offset by macid --------*/ 235 /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ 236 boolean tx_pwr_ofst_reg0_en; 237 u8 tx_pwr_ofst_reg0; 238 /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ 239 boolean tx_pwr_ofst_reg1_en; 240 u8 tx_pwr_ofst_reg1; 241 boolean hwigi_watchdog_en; 242 }; 243 244 #endif 245 246 struct phydm_phystatus_statistic { 247 /*@[CCK]*/ 248 u32 rssi_cck_sum; 249 u32 rssi_cck_cnt; 250 u32 rssi_beacon_sum[RF_PATH_MEM_SIZE]; 251 u32 rssi_beacon_cnt; 252 #ifdef PHYSTS_3RD_TYPE_SUPPORT 253 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 254 u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1]; 255 #endif 256 #endif 257 /*@[OFDM]*/ 258 u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; 259 u32 rssi_ofdm_cnt; 260 u32 evm_ofdm_sum; 261 u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; 262 u16 evm_ofdm_hist[PHY_HIST_SIZE]; 263 u16 snr_ofdm_hist[PHY_HIST_SIZE]; 264 /*@[1SS]*/ 265 u32 rssi_1ss_cnt; 266 u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; 267 u32 evm_1ss_sum; 268 u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; 269 u16 evm_1ss_hist[PHY_HIST_SIZE]; 270 u16 snr_1ss_hist[PHY_HIST_SIZE]; 271 /*@[2SS]*/ 272 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 273 u32 rssi_2ss_cnt; 274 u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; 275 u32 evm_2ss_sum[2]; 276 u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; 277 u16 evm_2ss_hist[2][PHY_HIST_SIZE]; 278 u16 snr_2ss_hist[2][PHY_HIST_SIZE]; 279 #endif 280 /*@[3SS]*/ 281 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 282 u32 rssi_3ss_cnt; 283 u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; 284 u32 evm_3ss_sum[3]; 285 u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; 286 u16 evm_3ss_hist[3][PHY_HIST_SIZE]; 287 u16 snr_3ss_hist[3][PHY_HIST_SIZE]; 288 #endif 289 /*@[4SS]*/ 290 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 291 u32 rssi_4ss_cnt; 292 u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; 293 u32 evm_4ss_sum[4]; 294 u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; 295 u16 evm_4ss_hist[4][PHY_HIST_SIZE]; 296 u16 snr_4ss_hist[4][PHY_HIST_SIZE]; 297 #endif 298 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 299 u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/ 300 u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/ 301 u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE]; 302 #endif 303 }; 304 305 struct phydm_phystatus_avg { 306 /*@[CCK]*/ 307 u8 rssi_cck_avg; 308 u8 rssi_beacon_avg[RF_PATH_MEM_SIZE]; 309 #ifdef PHYSTS_3RD_TYPE_SUPPORT 310 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 311 u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1]; 312 #endif 313 #endif 314 /*@[OFDM]*/ 315 u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; 316 u8 evm_ofdm_avg; 317 u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; 318 /*@[1SS]*/ 319 u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; 320 u8 evm_1ss_avg; 321 u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; 322 /*@[2SS]*/ 323 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 324 u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; 325 u8 evm_2ss_avg[2]; 326 u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; 327 #endif 328 /*@[3SS]*/ 329 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 330 u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; 331 u8 evm_3ss_avg[3]; 332 u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; 333 #endif 334 /*@[4SS]*/ 335 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 336 u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; 337 u8 evm_4ss_avg[4]; 338 u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; 339 #endif 340 }; 341 342 struct odm_phy_dbg_info { 343 /*@ODM Write,debug info*/ 344 u32 num_qry_phy_status_cck; 345 u32 num_qry_phy_status_ofdm; 346 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) 347 u32 num_qry_mu_pkt; 348 u32 num_qry_bf_pkt; 349 u16 num_mu_vht_pkt[VHT_RATE_NUM]; 350 boolean is_ldpc_pkt; 351 boolean is_stbc_pkt; 352 u8 num_of_ppdu[4]; 353 u8 gid_num[4]; 354 #endif 355 u32 condi_num; /*@condition number U(18,4)*/ 356 u8 condi_num_cdf[CN_CNT_MAX]; 357 u8 num_qry_beacon_pkt; 358 u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ 359 u8 beacon_phy_rate; 360 u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ 361 u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ 362 u16 show_phy_sts_cnt; 363 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 364 u16 num_qry_ht_pkt[HT_RATE_NUM]; 365 u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ 366 boolean ht_pkt_not_zero; 367 boolean low_bw_20_occur; 368 #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) 369 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 370 u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ 371 boolean vht_pkt_not_zero; 372 boolean low_bw_40_occur; 373 #endif 374 u16 snr_hist_th[PHY_HIST_TH_SIZE]; 375 u16 evm_hist_th[PHY_HIST_TH_SIZE]; 376 #ifdef PHYSTS_3RD_TYPE_SUPPORT 377 u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/ 378 u8 condition_num_seg0; 379 u8 eigen_val[4]; 380 s16 cfo_tail[4]; /*per-path's cfo_tail */ 381 #endif 382 struct phydm_phystatus_statistic physts_statistic_info; 383 struct phydm_phystatus_avg phystatus_statistic_avg; 384 }; 385 386 enum odm_cmninfo { 387 /*@Fixed value*/ 388 /*@-----------HOOK BEFORE REG INIT-----------*/ 389 ODM_CMNINFO_PLATFORM = 0, 390 ODM_CMNINFO_ABILITY, 391 ODM_CMNINFO_INTERFACE, 392 ODM_CMNINFO_MP_TEST_CHIP, 393 ODM_CMNINFO_IC_TYPE, 394 ODM_CMNINFO_CUT_VER, 395 ODM_CMNINFO_FAB_VER, 396 ODM_CMNINFO_FW_VER, 397 ODM_CMNINFO_FW_SUB_VER, 398 ODM_CMNINFO_RF_TYPE, 399 ODM_CMNINFO_RFE_TYPE, 400 ODM_CMNINFO_DPK_EN, 401 ODM_CMNINFO_BOARD_TYPE, 402 ODM_CMNINFO_PACKAGE_TYPE, 403 ODM_CMNINFO_EXT_LNA, 404 ODM_CMNINFO_5G_EXT_LNA, 405 ODM_CMNINFO_EXT_PA, 406 ODM_CMNINFO_5G_EXT_PA, 407 ODM_CMNINFO_GPA, 408 ODM_CMNINFO_APA, 409 ODM_CMNINFO_GLNA, 410 ODM_CMNINFO_ALNA, 411 ODM_CMNINFO_TDMA, 412 ODM_CMNINFO_EXT_TRSW, 413 ODM_CMNINFO_EXT_LNA_GAIN, 414 ODM_CMNINFO_PATCH_ID, 415 ODM_CMNINFO_BINHCT_TEST, 416 ODM_CMNINFO_BWIFI_TEST, 417 ODM_CMNINFO_SMART_CONCURRENT, 418 ODM_CMNINFO_CONFIG_BB_RF, 419 ODM_CMNINFO_IQKPAOFF, 420 ODM_CMNINFO_HUBUSBMODE, 421 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 422 ODM_CMNINFO_TX_TP, 423 ODM_CMNINFO_RX_TP, 424 ODM_CMNINFO_SOUNDING_SEQ, 425 ODM_CMNINFO_REGRFKFREEENABLE, 426 ODM_CMNINFO_RFKFREEENABLE, 427 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 428 ODM_CMNINFO_VALID_PATH_SET, 429 ODM_CMNINFO_EFUSE0X3D8, 430 ODM_CMNINFO_EFUSE0X3D7, 431 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 432 ODM_CMNINFO_X_CAP_SETTING, 433 ODM_CMNINFO_ADVANCE_OTA, 434 ODM_CMNINFO_HP_HWID, 435 ODM_CMNINFO_HUAWEI_HWID, 436 ODM_CMNINFO_ATHEROS_HWID, 437 ODM_CMNINFO_TSSI_ENABLE, /*also for cmn_info_update*/ 438 ODM_CMNINFO_DIS_DPD, 439 ODM_CMNINFO_POWER_VOLTAGE, 440 ODM_CMNINFO_ANTDIV_GPIO, 441 ODM_CMNINFO_EN_AUTO_BW_TH, 442 ODM_CMNINFO_PEAK_DETECT_MODE, 443 /*@-----------HOOK BEFORE REG INIT-----------*/ 444 445 /*@Dynamic value:*/ 446 447 /*@--------- POINTER REFERENCE-----------*/ 448 ODM_CMNINFO_TX_UNI, 449 ODM_CMNINFO_RX_UNI, 450 ODM_CMNINFO_BAND, 451 ODM_CMNINFO_SEC_CHNL_OFFSET, 452 ODM_CMNINFO_SEC_MODE, 453 ODM_CMNINFO_BW, 454 ODM_CMNINFO_CHNL, 455 ODM_CMNINFO_FORCED_RATE, 456 ODM_CMNINFO_ANT_DIV, 457 ODM_CMNINFO_PATH_DIV, 458 ODM_CMNINFO_ADAPTIVE_SOML, 459 ODM_CMNINFO_ADAPTIVITY, 460 ODM_CMNINFO_SCAN, 461 ODM_CMNINFO_POWER_SAVING, 462 ODM_CMNINFO_ONE_PATH_CCA, 463 ODM_CMNINFO_DRV_STOP, 464 ODM_CMNINFO_PNP_IN, 465 ODM_CMNINFO_INIT_ON, 466 ODM_CMNINFO_ANT_TEST, 467 ODM_CMNINFO_NET_CLOSED, 468 ODM_CMNINFO_P2P_LINK, 469 ODM_CMNINFO_FCS_MODE, 470 ODM_CMNINFO_IS1ANTENNA, 471 ODM_CMNINFO_RFDEFAULTPATH, 472 ODM_CMNINFO_DFS_MASTER_ENABLE, 473 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 474 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 475 ODM_CMNINFO_SOFT_AP_MODE, 476 ODM_CMNINFO_MP_MODE, 477 ODM_CMNINFO_INTERRUPT_MASK, 478 ODM_CMNINFO_BB_OPERATION_MODE, 479 ODM_CMNINFO_BF_ANTDIV_DECISION, 480 ODM_CMNINFO_MANUAL_SUPPORTABILITY, 481 ODM_CMNINFO_EN_DYM_BW_INDICATION, 482 /*@--------- POINTER REFERENCE-----------*/ 483 484 /*@------------CALL BY VALUE-------------*/ 485 ODM_CMNINFO_WIFI_DIRECT, 486 ODM_CMNINFO_WIFI_DISPLAY, 487 ODM_CMNINFO_LINK_IN_PROGRESS, 488 ODM_CMNINFO_LINK, 489 ODM_CMNINFO_CMW500LINK, 490 ODM_CMNINFO_STATION_STATE, 491 ODM_CMNINFO_RSSI_MIN, 492 ODM_CMNINFO_RSSI_MIN_BY_PATH, 493 ODM_CMNINFO_DBG_COMP, 494 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 495 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 496 ODM_CMNINFO_RF_ANTENNA_TYPE, 497 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 498 ODM_CMNINFO_BE_FIX_TX_ANT, 499 ODM_CMNINFO_BT_ENABLED, 500 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 501 ODM_CMNINFO_BT_HS_RSSI, 502 ODM_CMNINFO_BT_OPERATION, 503 ODM_CMNINFO_BT_LIMITED_DIG, 504 ODM_CMNINFO_AP_TOTAL_NUM, 505 ODM_CMNINFO_POWER_TRAINING, 506 ODM_CMNINFO_DFS_REGION_DOMAIN, 507 ODM_CMNINFO_BT_CONTINUOUS_TURN, 508 ODM_CMNINFO_IS_DOWNLOAD_FW, 509 ODM_CMNINFO_PHYDM_PATCH_ID, 510 ODM_CMNINFO_RRSR_VAL, 511 ODM_CMNINFO_LINKED_BF_SUPPORT, 512 ODM_CMNINFO_FLATNESS_TYPE, 513 /*@------------CALL BY VALUE-------------*/ 514 515 /*@Dynamic ptr array hook itms.*/ 516 ODM_CMNINFO_STA_STATUS, 517 ODM_CMNINFO_MAX, 518 519 }; 520 521 enum phydm_rfe_bb_source_sel { 522 PAPE_2G = 0, 523 PAPE_5G = 1, 524 LNA0N_2G = 2, 525 LNAON_5G = 3, 526 TRSW = 4, 527 TRSW_B = 5, 528 GNT_BT = 6, 529 ZERO = 7, 530 ANTSEL_0 = 8, 531 ANTSEL_1 = 9, 532 ANTSEL_2 = 0xa, 533 ANTSEL_3 = 0xb, 534 ANTSEL_4 = 0xc, 535 ANTSEL_5 = 0xd, 536 ANTSEL_6 = 0xe, 537 ANTSEL_7 = 0xf 538 }; 539 540 enum phydm_info_query { 541 PHYDM_INFO_FA_OFDM, 542 PHYDM_INFO_FA_CCK, 543 PHYDM_INFO_FA_TOTAL, 544 PHYDM_INFO_CCA_OFDM, 545 PHYDM_INFO_CCA_CCK, 546 PHYDM_INFO_CCA_ALL, 547 PHYDM_INFO_CRC32_OK_VHT, 548 PHYDM_INFO_CRC32_OK_HT, 549 PHYDM_INFO_CRC32_OK_LEGACY, 550 PHYDM_INFO_CRC32_OK_CCK, 551 PHYDM_INFO_CRC32_ERROR_VHT, 552 PHYDM_INFO_CRC32_ERROR_HT, 553 PHYDM_INFO_CRC32_ERROR_LEGACY, 554 PHYDM_INFO_CRC32_ERROR_CCK, 555 PHYDM_INFO_EDCCA_FLAG, 556 PHYDM_INFO_OFDM_ENABLE, 557 PHYDM_INFO_CCK_ENABLE, 558 PHYDM_INFO_CRC32_OK_HT_AGG, 559 PHYDM_INFO_CRC32_ERROR_HT_AGG, 560 PHYDM_INFO_DBG_PORT_0, 561 PHYDM_INFO_CURR_IGI, 562 PHYDM_INFO_RSSI_MIN, 563 PHYDM_INFO_RSSI_MAX, 564 PHYDM_INFO_CLM_RATIO, 565 PHYDM_INFO_NHM_RATIO, 566 PHYDM_INFO_NHM_NOISE_PWR, 567 PHYDM_INFO_NHM_PWR, 568 569 }; 570 571 enum phydm_api { 572 PHYDM_API_NBI = 1, 573 PHYDM_API_CSI_MASK = 2, 574 }; 575 576 enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ 577 578 F00_DIG = 0, 579 F01_RA_MASK = 1, 580 F02_DYN_TXPWR = 2, 581 F03_FA_CNT = 3, 582 F04_RSSI_MNTR = 4, 583 F05_CCK_PD = 5, 584 F06_ANT_DIV = 6, 585 F07_SMT_ANT = 7, 586 F08_PWR_TRAIN = 8, 587 F09_RA = 9, 588 F10_PATH_DIV = 10, 589 F11_DFS = 11, 590 F12_DYN_ARFR = 12, 591 F13_ADPTVTY = 13, 592 F14_CFO_TRK = 14, 593 F15_ENV_MNTR = 15, 594 F16_PRI_CCA = 16, 595 F17_ADPTV_SOML = 17, 596 F18_LNA_SAT_CHK = 18, 597 }; 598 599 /*@=[PHYDM supportability]==========================================*/ 600 enum odm_ability { 601 ODM_BB_DIG = BIT(F00_DIG), 602 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 603 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 604 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 605 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 606 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 607 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 608 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 609 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 610 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 611 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 612 ODM_BB_DFS = BIT(F11_DFS), 613 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 614 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 615 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 616 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 617 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 618 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 619 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 620 }; 621 622 /*@=[PHYDM Debug Component]=====================================*/ 623 enum phydm_dbg_comp { 624 /*@BB Driver Functions*/ 625 DBG_DIG = BIT(F00_DIG), 626 DBG_RA_MASK = BIT(F01_RA_MASK), 627 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 628 DBG_FA_CNT = BIT(F03_FA_CNT), 629 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 630 DBG_CCKPD = BIT(F05_CCK_PD), 631 DBG_ANT_DIV = BIT(F06_ANT_DIV), 632 DBG_SMT_ANT = BIT(F07_SMT_ANT), 633 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 634 DBG_RA = BIT(F09_RA), 635 DBG_PATH_DIV = BIT(F10_PATH_DIV), 636 DBG_DFS = BIT(F11_DFS), 637 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 638 DBG_ADPTVTY = BIT(F13_ADPTVTY), 639 DBG_CFO_TRK = BIT(F14_CFO_TRK), 640 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 641 DBG_PRI_CCA = BIT(F16_PRI_CCA), 642 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 643 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 644 /*Neet to re-arrange*/ 645 DBG_PHY_STATUS = BIT(20), 646 DBG_TMP = BIT(21), 647 DBG_FW_TRACE = BIT(22), 648 DBG_TXBF = BIT(23), 649 DBG_COMMON_FLOW = BIT(24), 650 DBG_COMP_MCC = BIT(25), 651 DBG_FW_DM = BIT(26), 652 DBG_DM_SUMMARY = BIT(27), 653 ODM_PHY_CONFIG = BIT(28), 654 ODM_COMP_INIT = BIT(29), 655 DBG_CMN = BIT(30),/*@common*/ 656 ODM_COMP_API = BIT(31) 657 }; 658 659 /*@=========================================================*/ 660 661 /*@ODM_CMNINFO_ONE_PATH_CCA*/ 662 enum odm_cca_path { 663 ODM_CCA_2R = 0, 664 ODM_CCA_1R_A = 1, 665 ODM_CCA_1R_B = 2, 666 }; 667 668 enum phy_reg_pg_type { 669 PHY_REG_PG_RELATIVE_VALUE = 0, 670 PHY_REG_PG_EXACT_VALUE = 1 671 }; 672 673 enum phydm_offload_ability { 674 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 675 PHYDM_RF_IQK_OFFLOAD = BIT(1), 676 PHYDM_RF_DPK_OFFLOAD = BIT(2), 677 }; 678 679 enum phydm_init_result { 680 PHYDM_INIT_SUCCESS = 0, 681 PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1 682 }; 683 684 struct phydm_pause_lv { 685 s8 lv_dig; 686 s8 lv_cckpd; 687 s8 lv_antdiv; 688 s8 lv_adapt; 689 s8 lv_adsl; 690 }; 691 692 struct phydm_func_poiner { 693 void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); 694 }; 695 696 struct pkt_process_info { 697 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 698 /*@send phystatus in each sampling time*/ 699 boolean physts_auto_swch_en; 700 u8 mac_ppdu_cnt; 701 u8 phy_ppdu_cnt; /*change with phy cca cnt*/ 702 u8 page_bitmap_target; 703 u8 page_bitmap_record; 704 u8 ppdu_phy_rate; 705 u8 ppdu_macid; 706 boolean is_1st_mpdu; 707 #endif 708 u8 lna_idx; 709 u8 vga_idx; 710 }; 711 712 #ifdef ODM_CONFIG_BT_COEXIST 713 struct phydm_bt_info { 714 boolean is_bt_enabled; /*@BT is enabled*/ 715 boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ 716 u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ 717 boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ 718 boolean is_bt_limited_dig; /*@BT is busy.*/ 719 }; 720 #endif 721 722 struct phydm_iot_center { 723 boolean is_linked_cmw500; 724 u8 win_patch_id; /*Customer ID*/ 725 boolean patch_id_100f0401; 726 boolean patch_id_10120200; 727 boolean patch_id_40010700; 728 boolean patch_id_021f0800; 729 u32 phydm_patch_id; /*temp for CCX IOT */ 730 }; 731 732 #if (RTL8822B_SUPPORT) 733 struct drp_rtl8822b_struct { 734 enum bb_path path_judge; 735 u16 path_a_cck_fa; 736 u16 path_b_cck_fa; 737 }; 738 #endif 739 740 #ifdef CONFIG_MCC_DM 741 #define MCC_DM_REG_NUM 32 742 struct _phydm_mcc_dm_ { 743 u8 mcc_pre_status; 744 u8 mcc_reg_id[MCC_DM_REG_NUM]; 745 u16 mcc_dm_reg[MCC_DM_REG_NUM]; 746 u8 mcc_dm_val[MCC_DM_REG_NUM][2]; 747 /*mcc DIG*/ 748 u8 mcc_rssi[2]; 749 /*u8 mcc_igi[2];*/ 750 751 /* need to be config by driver*/ 752 u8 mcc_status; 753 u8 sta_macid[2][NUM_STA]; 754 u16 mcc_rf_ch[2]; 755 756 }; 757 #endif 758 759 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 760 struct phydm_physts { 761 u8 cck_gi_u_bnd; 762 u8 cck_gi_l_bnd; 763 }; 764 #endif 765 766 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 767 #if (RT_PLATFORM != PLATFORM_LINUX) 768 typedef 769 #endif 770 771 struct dm_struct { 772 #else/*for AP, CE Team*/ 773 struct dm_struct { 774 #endif 775 /*@Add for different team use temporarily*/ 776 void *adapter; /*@For CE/NIC team*/ 777 struct rtl8192cd_priv *priv; /*@For AP team*/ 778 boolean odm_ready; 779 enum phy_reg_pg_type phy_reg_pg_value_type; 780 u8 phy_reg_pg_version; 781 u64 support_ability; /*@PHYDM function Supportability*/ 782 u64 pause_ability; /*@PHYDM function pause Supportability*/ 783 u64 debug_components; 784 u8 cmn_dbg_msg_period; 785 u8 cmn_dbg_msg_cnt; 786 u32 fw_debug_components; 787 u32 num_qry_phy_status_all; /*@CCK + OFDM*/ 788 u32 last_num_qry_phy_status_all; 789 u32 rx_pwdb_ave; 790 boolean is_init_hw_info_by_rfe; 791 boolean is_R2R_CCA_MASKT_TIME_SHORT; 792 793 //TSSI 794 u8 en_tssi_mode; 795 796 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 797 boolean is_cck_high_power; 798 u8 rf_path_rx_enable; 799 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 800 801 /* @COMMON INFORMATION */ 802 803 /*@Init value*/ 804 /*@-----------HOOK BEFORE REG INIT-----------*/ 805 806 u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ 807 u8 normal_rx_path; 808 u8 valid_path_set; /*@use for single rx path only*/ 809 boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ 810 u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ 811 u32 support_ic_type; /*@PHYDM supported IC*/ 812 enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ 813 u8 ic_ip_series; /*N/AC/JGR3*/ 814 enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ 815 u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 816 u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ 817 u8 fw_version; 818 u8 fw_sub_version; 819 u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 820 u8 rfe_type; 821 u8 board_type; 822 u8 package_type; 823 u16 type_glna; 824 u16 type_gpa; 825 u16 type_alna; 826 u16 type_apa; 827 u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ 828 u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ 829 u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ 830 u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ 831 u8 efuse0x3d7; /*@with Efuse number*/ 832 u8 efuse0x3d8; 833 u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ 834 u8 ext_lna_gain; /*@gain of external lna*/ 835 boolean is_in_hct_test; 836 u8 wifi_test; 837 boolean is_dual_mac_smart_concurrent; 838 u32 bk_support_ability; /*SD4 only*/ 839 u8 with_extenal_ant_switch; 840 /*@cck agc relative*/ 841 boolean cck_new_agc; 842 s8 cck_lna_gain_table[8]; 843 u8 cck_sat_cnt_th_init; 844 /*@-------------------------------------*/ 845 u32 phydm_sys_up_time; 846 u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ 847 u32 soft_ap_special_setting; 848 boolean boolean_dummy; 849 s8 s8_dummy; 850 u8 u8_dummy; 851 u16 u16_dummy; 852 u32 u32_dummy; 853 u8 rfe_hwsetting_band; 854 u8 p_advance_ota; 855 boolean hp_hw_id; 856 boolean BOOLEAN_temp; 857 boolean is_dfs_band; 858 u8 is_rx_blocking_en; 859 u16 fw_offload_ability; 860 boolean is_download_fw; 861 boolean en_dis_dpd; 862 u16 dis_dpd_rate; 863 u8 en_auto_bw_th; 864 #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT) 865 u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX]; 866 u32 bp_0x9b0; 867 #endif 868 #if (RTL8822C_SUPPORT) 869 u8 ofdm_rxagc_l_bnd[16]; 870 boolean l_bnd_detect[16]; 871 u16 agc_rf_gain_ori[16][64];/*[table][mp_gain_idx]*/ 872 u16 agc_rf_gain[16][64];/*[table][mp_gain_idx]*/ 873 u8 agc_table_cnt; 874 boolean is_agc_tab_pos_shift; 875 u8 agc_table_shift; 876 #endif 877 /*@-----------HOOK BEFORE REG INIT-----------*/ 878 /*@===========================================================*/ 879 /*@====[ CALL BY Reference ]=========================================*/ 880 /*@===========================================================*/ 881 882 u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ 883 u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ 884 u8 *band_type; /*@2.4G/5G = 0/1*/ 885 u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ 886 u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 887 u8 *band_width; /*@20M/40M/80M = 0/1/2*/ 888 u8 *channel; /*@central CH number*/ 889 boolean *is_scan_in_process; 890 boolean *is_power_saving; 891 boolean *is_tdma; 892 u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ 893 u8 *antenna_test; 894 boolean *is_net_closed; 895 boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ 896 /*@--------- For 8723B IQK-------------------------------------*/ 897 boolean *is_1_antenna; 898 u8 *rf_default_path; /* @0:S1, 1:S0 */ 899 /*@-----------------------------------------------------------*/ 900 901 u16 *forced_data_rate; 902 u8 *enable_antdiv; 903 u8 *enable_pathdiv; 904 u8 *en_adap_soml; 905 u8 *edcca_mode; 906 u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ 907 boolean *is_fw_dw_rsvd_page_in_progress; 908 u32 *current_tx_tp; 909 u32 *current_rx_tp; 910 u8 *sounding_seq; 911 u32 *soft_ap_mode; 912 u8 *mp_mode; 913 u32 *interrupt_mask; 914 u8 *bb_op_mode; 915 u32 *manual_supportability; 916 u8 *dis_dym_bw_indication; 917 /*@===========================================================*/ 918 /*@====[ CALL BY VALUE ]===========================================*/ 919 /*@===========================================================*/ 920 921 u8 disable_phydm_watchdog; 922 boolean is_link_in_process; 923 boolean is_wifi_direct; 924 boolean is_wifi_display; 925 boolean is_linked; 926 boolean pre_is_linked; 927 boolean first_connect; 928 boolean first_disconnect; 929 boolean bsta_state; 930 u8 rssi_min; 931 u8 rssi_min_macid; 932 u8 pre_rssi_min; 933 u8 rssi_max; 934 u8 rssi_max_macid; 935 u8 rssi_min_by_path; 936 boolean is_mp_chip; 937 boolean is_one_entry_only; 938 u32 one_entry_macid; 939 u32 one_entry_tp; 940 u32 pre_one_entry_tp; 941 u16 one_entry_avg_phy_rate; 942 u16 one_entry_rx_utility; 943 u8 pre_number_linked_client; 944 u8 number_linked_client; 945 u8 pre_number_active_client; 946 u8 number_active_client; 947 boolean is_disable_phy_api; 948 u8 rssi_a; 949 u8 rssi_b; 950 u8 rssi_c; 951 u8 rssi_d; 952 s8 rxsc_80; 953 s8 rxsc_40; 954 s8 rxsc_20; 955 s8 rxsc_l; 956 u64 rssi_trsw; 957 u64 rssi_trsw_h; 958 u64 rssi_trsw_l; 959 u64 rssi_trsw_iso; 960 u8 tx_ant_status; /*TX path enable*/ 961 u8 rx_ant_status; /*RX path enable*/ 962 #ifdef PHYDM_COMPILE_ABOVE_4SS 963 enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ 964 #endif 965 #ifdef PHYDM_COMPILE_ABOVE_3SS 966 enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ 967 #endif 968 #ifdef PHYDM_COMPILE_ABOVE_2SS 969 enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ 970 #endif 971 enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ 972 u8 cck_lna_idx; 973 u8 cck_vga_idx; 974 u8 curr_station_id; 975 u8 ofdm_agc_idx[4]; 976 u8 rx_rate; 977 u8 rate_ss; 978 u8 tx_rate; 979 u8 linked_interval; 980 u8 pre_channel; 981 u32 txagc_offset_value_a; 982 boolean is_txagc_offset_positive_a; 983 u32 txagc_offset_value_b; 984 boolean is_txagc_offset_positive_b; 985 u8 ap_total_num; 986 boolean flatness_type; 987 /*@[traffic]*/ 988 u8 traffic_load; 989 u8 pre_traffic_load; 990 u32 tx_tp; /*@Mbps*/ 991 u32 rx_tp; /*@Mbps*/ 992 u32 total_tp; /*@Mbps*/ 993 u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ 994 u64 cur_tx_ok_cnt; 995 u64 cur_rx_ok_cnt; 996 u64 last_tx_ok_cnt; 997 u64 last_rx_ok_cnt; 998 u16 consecutive_idlel_time; /*@unit: second*/ 999 /*@---------------------------*/ 1000 boolean is_bb_swing_offset_positive_a; 1001 boolean is_bb_swing_offset_positive_b; 1002 1003 /*@[DIG]*/ 1004 boolean MPDIG_2G; /*off MPDIG*/ 1005 u8 times_2g; /*@for MP DIG*/ 1006 u8 force_igi; /*@for debug*/ 1007 boolean is_dig_low_bond; 1008 1009 /*@[TDMA-DIG]*/ 1010 u8 tdma_dig_timer_ms; 1011 u8 tdma_dig_state_number; 1012 u8 tdma_dig_low_upper_bond; 1013 u8 force_tdma_low_igi; 1014 u8 force_tdma_high_igi; 1015 u8 fix_expire_to_zero; 1016 boolean original_dig_restore; 1017 /*@---------------------------*/ 1018 1019 /*@[AntDiv]*/ 1020 u8 ant_div_type; 1021 u8 antdiv_rssi; 1022 u8 fat_comb_a; 1023 u8 fat_comb_b; 1024 u8 antdiv_intvl; 1025 u8 antdiv_delay; 1026 u8 ant_type; 1027 u8 ant_type2; 1028 u8 pre_ant_type; 1029 u8 pre_ant_type2; 1030 u8 antdiv_period; 1031 u8 evm_antdiv_period; 1032 u8 antdiv_select; 1033 u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ 1034 u8 stop_antdiv_rssi_th; 1035 u16 stop_antdiv_tp_diff_th; 1036 u16 stop_antdiv_tp_th; 1037 u8 antdiv_tp_period; 1038 u16 tp_active_th; 1039 u8 tp_active_occur; 1040 u8 path_select; 1041 u8 antdiv_evm_en; 1042 u8 bdc_holdstate; 1043 u8 antdiv_counter; 1044 /*@---------------------------*/ 1045 1046 u8 ndpa_period; 1047 boolean h2c_rarpt_connect; 1048 boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ 1049 u8 print_agc; 1050 u8 la_mode; 1051 /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 1052 u8 current_rf_set_8821c; 1053 u8 default_rf_set_8821c; 1054 u8 current_ant_num_8821c; 1055 u8 default_ant_num_8821c; 1056 u8 rfe_type_expand; 1057 /*@-----------------------------------------------------------*/ 1058 /*@---For Adaptivtiy---------------------------------------------*/ 1059 s8 TH_L2H_default; 1060 s8 th_edcca_hl_diff_default; 1061 s8 th_l2h_ini; 1062 s8 th_edcca_hl_diff; 1063 boolean carrier_sense_enable; 1064 /*@-----------------------------------------------------------*/ 1065 u8 pre_dbg_priority; 1066 u8 nbi_set_result; 1067 u8 c2h_cmd_start; 1068 u8 fw_debug_trace[60]; 1069 u8 pre_c2h_seq; 1070 boolean fw_buff_is_enpty; 1071 u32 data_frame_num; 1072 /*@--- for spur detection ---------------------------------------*/ 1073 boolean en_reg_mntr_bb; 1074 boolean en_reg_mntr_rf; 1075 boolean en_reg_mntr_mac; 1076 boolean en_reg_mntr_byte; 1077 /*@--------------------------------------------------------------*/ 1078 #if (RTL8814B_SUPPORT || RTL8812F_SUPPORT || RTL8198F_SUPPORT) 1079 u8 dsde_sel; 1080 u8 nbi_path_sel; 1081 u8 csi_wgt; 1082 #endif 1083 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT) 1084 u8 csi_wgt_th_db[5]; /*@wgt 4,3,2,1,0 */ 1085 /* ^ ^ ^ ^ ^ */ 1086 #endif 1087 /*@------------------------------------------*/ 1088 1089 /*@--- for noise detection ---------------------------------------*/ 1090 boolean is_noisy_state; 1091 boolean noisy_decision; /*@b_noisy*/ 1092 boolean pre_b_noisy; 1093 u32 noisy_decision_smooth; 1094 /*@-----------------------------------------------------------*/ 1095 1096 /*@--- for MCC ant weighting ------------------------------------*/ 1097 boolean is_stop_dym_ant_weighting; 1098 /*@-----------------------------------------------------------*/ 1099 1100 boolean is_disable_dym_ecs; 1101 boolean is_disable_dym_ant_weighting; 1102 struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 1103 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ 1104 1105 #if (RATE_ADAPTIVE_SUPPORT) 1106 u16 currmin_rpt_time; 1107 struct _phydm_txstatistic_ hw_stats; 1108 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 1109 /*Use mac_id as array index. STA mac_id=0*/ 1110 /*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 1111 #endif 1112 /*@2012/02/14 MH Add to share 88E ra with other SW team*/ 1113 /*We need to colelct all support abilit to a proper area.*/ 1114 boolean ra_support88e; 1115 boolean *is_driver_stopped; 1116 boolean *is_driver_is_going_to_pnp_set_power_sleep; 1117 boolean *pinit_adpt_in_progress; 1118 boolean is_user_assign_level; 1119 u8 RSSI_BT; /*@come from BT*/ 1120 1121 /*@---PSD Relative ---------------------------------------------*/ 1122 boolean is_psd_in_process; 1123 boolean is_psd_active; 1124 /*@-----------------------------------------------------------*/ 1125 1126 boolean bsomlenabled; /* @D-SoML control */ 1127 u8 no_ndp_cnts; 1128 u16 ndp_cnt_pre; 1129 boolean is_beamformed; 1130 u8 linked_bf_support; 1131 boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ 1132 u32 n_iqk_cnt; 1133 u32 n_iqk_ok_cnt; 1134 u32 n_iqk_fail_cnt; 1135 1136 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 1137 boolean config_bbrf; 1138 #endif 1139 boolean is_disable_power_training; 1140 boolean is_bt_continuous_turn; 1141 u8 enhance_pwr_th[3]; 1142 u8 set_pwr_th[3]; 1143 /*@----------Dyn Tx Pwr ---------------------------------------*/ 1144 #ifdef BB_RAM_SUPPORT 1145 struct phydm_bb_ram_ctrl p_bb_ram_ctrl; 1146 #endif 1147 u8 dynamic_tx_high_power_lvl; 1148 void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); 1149 u8 last_dtp_lvl; 1150 u8 min_power_index; 1151 u32 tx_agc_ofdm_18_6; 1152 /*-------------------------------------------------------------*/ 1153 u8 rx_pkt_type; 1154 1155 #ifdef CONFIG_PHYDM_DFS_MASTER 1156 u8 dfs_region_domain; 1157 u8 *dfs_master_enabled; 1158 /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ 1159 u8 radar_detect_dbg_parm_en; 1160 u32 radar_detect_reg_918; 1161 u32 radar_detect_reg_91c; 1162 u32 radar_detect_reg_920; 1163 u32 radar_detect_reg_924; 1164 1165 u32 radar_detect_reg_a40; 1166 u32 radar_detect_reg_a44; 1167 u32 radar_detect_reg_a48; 1168 u32 radar_detect_reg_a4c; 1169 u32 radar_detect_reg_a50; 1170 u32 radar_detect_reg_a54; 1171 1172 u32 radar_detect_reg_f54; 1173 u32 radar_detect_reg_f58; 1174 u32 radar_detect_reg_f5c; 1175 u32 radar_detect_reg_f70; 1176 u32 radar_detect_reg_f74; 1177 /*@---For zero-wait DFS---------------------------------------*/ 1178 boolean seg1_dfs_flag; 1179 /*@-----------------------------------------------------------*/ 1180 /*@-----------------------------------------------------------*/ 1181 #endif 1182 1183 /*@=== RTL8721D ===*/ 1184 #if (RTL8721D_SUPPORT) 1185 boolean cbw20_adc80; 1186 boolean invalid_mode; 1187 u8 power_voltage; 1188 u8 cca_cbw20_lev; 1189 u8 cca_cbw40_lev; 1190 u8 antdiv_gpio; 1191 u8 peak_detect_mode; 1192 #endif 1193 1194 /*@=== PHYDM Timer ========================================== (start)*/ 1195 1196 struct phydm_timer_list mpt_dig_timer; 1197 struct phydm_timer_list fast_ant_training_timer; 1198 #ifdef ODM_EVM_ENHANCE_ANTDIV 1199 struct phydm_timer_list evm_fast_ant_training_timer; 1200 #endif 1201 #ifdef PHYDM_TDMA_DIG_SUPPORT 1202 struct phydm_timer_list tdma_dig_timer; 1203 #endif 1204 struct phydm_timer_list sbdcnt_timer; 1205 1206 /*@=== PHYDM Workitem ======================================= (start)*/ 1207 1208 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1209 #if USE_WORKITEM 1210 RT_WORK_ITEM fast_ant_training_workitem; 1211 RT_WORK_ITEM ra_rpt_workitem; 1212 RT_WORK_ITEM sbdcnt_workitem; 1213 RT_WORK_ITEM phydm_evm_antdiv_workitem; 1214 #ifdef PHYDM_TDMA_DIG_SUPPORT 1215 RT_WORK_ITEM phydm_tdma_dig_workitem; 1216 #endif 1217 #endif 1218 #endif 1219 1220 /*@=== PHYDM Structure ======================================== (start)*/ 1221 struct phydm_func_poiner phydm_func_handler; 1222 struct phydm_iot_center iot_table; 1223 1224 #ifdef ODM_CONFIG_BT_COEXIST 1225 struct phydm_bt_info bt_info_table; 1226 #endif 1227 1228 struct pkt_process_info pkt_proc_struct; 1229 struct phydm_adaptivity_struct adaptivity; 1230 #ifdef CONFIG_PHYDM_DFS_MASTER 1231 struct _DFS_STATISTICS dfs; 1232 #endif 1233 struct odm_noise_monitor noise_level; 1234 struct odm_phy_dbg_info phy_dbg_info; 1235 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1236 struct odm_phy_dbg_info phy_dbg_info_win_bkp; 1237 #endif 1238 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 1239 struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; 1240 #endif 1241 1242 #ifdef CONFIG_ADAPTIVE_SOML 1243 struct adaptive_soml dm_soml_table; 1244 #endif 1245 1246 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 1247 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1248 struct _BF_DIV_COEX_ dm_bdc_table; 1249 #endif 1250 1251 #if (defined(CONFIG_HL_SMART_ANTENNA)) 1252 struct smt_ant_honbo dm_sat_table; 1253 #endif 1254 #endif 1255 1256 #if (defined(CONFIG_SMART_ANTENNA)) 1257 struct smt_ant smtant_table; 1258 #endif 1259 1260 struct _hal_rf_ rf_table; /*@for HALRF function*/ 1261 struct dm_rf_calibration_struct rf_calibrate_info; 1262 struct dm_iqk_info IQK_info; 1263 struct dm_dpk_info dpk_info; 1264 struct dm_dack_info dack_info; 1265 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 1266 struct phydm_fat_struct dm_fat_table; 1267 struct sw_antenna_switch dm_swat_table; 1268 #endif 1269 struct phydm_dig_struct dm_dig_table; 1270 1271 #ifdef PHYDM_SUPPORT_CCKPD 1272 struct phydm_cckpd_struct dm_cckpd_table; 1273 1274 #ifdef PHYDM_DCC_ENHANCE 1275 struct phydm_dcc_struct dm_dcc_info; /*dig cckpd coex*/ 1276 #endif 1277 #endif 1278 1279 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 1280 struct phydm_lna_sat_t dm_lna_sat_info; 1281 #endif 1282 1283 #ifdef CONFIG_MCC_DM 1284 struct _phydm_mcc_dm_ mcc_dm; 1285 #endif 1286 1287 #ifdef PHYDM_PRIMARY_CCA 1288 struct phydm_pricca_struct dm_pri_cca; 1289 #endif 1290 1291 struct ra_table dm_ra_table; 1292 struct phydm_fa_struct false_alm_cnt; 1293 #ifdef PHYDM_TDMA_DIG_SUPPORT 1294 struct phydm_fa_acc_struct false_alm_cnt_acc; 1295 #ifdef IS_USE_NEW_TDMA 1296 struct phydm_fa_acc_struct false_alm_cnt_acc_low; 1297 #endif 1298 #endif 1299 struct phydm_cfo_track_struct dm_cfo_track; 1300 struct ccx_info dm_ccx_info; 1301 1302 struct odm_power_trim_data power_trim_data; 1303 #if (RTL8822B_SUPPORT) 1304 struct drp_rtl8822b_struct phydm_rtl8822b; 1305 #endif 1306 1307 #ifdef CONFIG_PSD_TOOL 1308 struct psd_info dm_psd_table; 1309 #endif 1310 1311 #if (PHYDM_LA_MODE_SUPPORT) 1312 struct rt_adcsmp adcsmp; 1313 #endif 1314 1315 #if (defined(CONFIG_PATH_DIVERSITY)) 1316 struct _ODM_PATH_DIVERSITY_ dm_path_div; 1317 #endif 1318 1319 #if (defined(CONFIG_ANT_DETECTION)) 1320 struct _ANT_DETECTED_INFO ant_detected_info; 1321 #endif 1322 1323 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1324 #ifdef PHYDM_BEAMFORMING_SUPPORT 1325 struct _RT_BEAMFORMING_INFO beamforming_info; 1326 #endif 1327 #endif 1328 #ifdef PHYDM_AUTO_DEGBUG 1329 struct phydm_auto_dbg_struct auto_dbg_table; 1330 #endif 1331 1332 struct phydm_pause_lv pause_lv_table; 1333 struct phydm_api_stuc api_table; 1334 #ifdef PHYDM_POWER_TRAINING_SUPPORT 1335 struct phydm_pow_train_stuc pow_train_table; 1336 #endif 1337 1338 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 1339 struct phydm_pmac_tx dm_pmac_tx_table; 1340 #endif 1341 1342 #ifdef PHYDM_MP_SUPPORT 1343 struct phydm_mp dm_mp_table; 1344 #endif 1345 1346 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 1347 struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table; 1348 #endif 1349 /*@==========================================================*/ 1350 1351 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 1352 /*@-------------------phydm_phystatus report --------------------*/ 1353 struct phydm_physts dm_physts_table; 1354 #endif 1355 1356 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1357 1358 #if (RT_PLATFORM != PLATFORM_LINUX) 1359 } dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ 1360 #else 1361 }; 1362 #endif 1363 1364 #else /*@for AP,CE Team*/ 1365 }; 1366 #endif 1367 1368 enum phydm_adv_ota { 1369 PHYDM_PATHB_1RCCA = BIT(0), 1370 PHYDM_HP_OTA_SETTING_A = BIT(1), 1371 PHYDM_HP_OTA_SETTING_B = BIT(2), 1372 PHYDM_ASUS_OTA_SETTING = BIT(3), 1373 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 1374 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 1375 PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), 1376 1377 }; 1378 1379 enum phydm_bb_op_mode { 1380 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 1381 PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ 1382 }; 1383 1384 enum phydm_structure_type { 1385 PHYDM_FALSEALMCNT, 1386 PHYDM_CFOTRACK, 1387 PHYDM_ADAPTIVITY, 1388 PHYDM_DFS, 1389 PHYDM_ROMINFO, 1390 1391 }; 1392 1393 enum odm_bb_config_type { 1394 CONFIG_BB_PHY_REG, 1395 CONFIG_BB_AGC_TAB, 1396 CONFIG_BB_AGC_TAB_2G, 1397 CONFIG_BB_AGC_TAB_5G, 1398 CONFIG_BB_PHY_REG_PG, 1399 CONFIG_BB_PHY_REG_MP, 1400 CONFIG_BB_AGC_TAB_DIFF, 1401 CONFIG_BB_RF_CAL_INIT, 1402 }; 1403 1404 enum odm_rf_config_type { 1405 CONFIG_RF_RADIO, 1406 CONFIG_RF_TXPWR_LMT, 1407 CONFIG_RF_SYN_RADIO, 1408 }; 1409 1410 enum odm_fw_config_type { 1411 CONFIG_FW_NIC, 1412 CONFIG_FW_NIC_2, 1413 CONFIG_FW_AP, 1414 CONFIG_FW_AP_2, 1415 CONFIG_FW_MP, 1416 CONFIG_FW_WOWLAN, 1417 CONFIG_FW_WOWLAN_2, 1418 CONFIG_FW_AP_WOWLAN, 1419 CONFIG_FW_BT, 1420 }; 1421 1422 /*status code*/ 1423 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1424 enum rt_status { 1425 RT_STATUS_SUCCESS, 1426 RT_STATUS_FAILURE, 1427 RT_STATUS_PENDING, 1428 RT_STATUS_RESOURCE, 1429 RT_STATUS_INVALID_CONTEXT, 1430 RT_STATUS_INVALID_PARAMETER, 1431 RT_STATUS_NOT_SUPPORT, 1432 RT_STATUS_OS_API_FAILED, 1433 }; 1434 #endif /*@end of enum rt_status definition*/ 1435 1436 void 1437 phydm_watchdog_lps(struct dm_struct *dm); 1438 1439 void 1440 phydm_watchdog_lps_32k(struct dm_struct *dm); 1441 1442 void 1443 phydm_txcurrentcalibration(struct dm_struct *dm); 1444 1445 void 1446 phydm_dm_early_init(struct dm_struct *dm); 1447 1448 enum phydm_init_result 1449 odm_dm_init(struct dm_struct *dm); 1450 1451 void 1452 odm_dm_reset(struct dm_struct *dm); 1453 1454 void 1455 phydm_fwoffload_ability_init(struct dm_struct *dm, 1456 enum phydm_offload_ability offload_ability); 1457 1458 void 1459 phydm_fwoffload_ability_clear(struct dm_struct *dm, 1460 enum phydm_offload_ability offload_ability); 1461 1462 void 1463 phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, 1464 char *output, u32 *_out_len); 1465 1466 void 1467 phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); 1468 1469 void 1470 phydm_watchdog(struct dm_struct *dm); 1471 1472 void 1473 phydm_watchdog_mp(struct dm_struct *dm); 1474 1475 void 1476 phydm_pause_func_init(void *dm_void); 1477 1478 u8 1479 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, 1480 enum phydm_pause_type pause_type, 1481 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); 1482 1483 void 1484 phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, 1485 char *output, u32 *_out_len); 1486 1487 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, 1488 enum phydm_pause_type pause_type, u8 rssi); 1489 1490 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx, 1491 boolean enable); 1492 1493 void 1494 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); 1495 1496 void 1497 odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); 1498 1499 void 1500 odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); 1501 1502 u32 1503 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); 1504 1505 void 1506 odm_init_all_timers(struct dm_struct *dm); 1507 1508 void 1509 odm_cancel_all_timers(struct dm_struct *dm); 1510 1511 void 1512 odm_release_all_timers(struct dm_struct *dm); 1513 1514 void * 1515 phydm_get_structure(struct dm_struct *dm, u8 structure_type); 1516 1517 void 1518 phydm_dc_cancellation(struct dm_struct *dm); 1519 1520 void 1521 phydm_receiver_blocking(void *dm_void); 1522 1523 void 1524 phydm_dyn_bw_indication(void *dm_void); 1525 1526 void 1527 phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en); 1528 1529 1530 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH 1531 void 1532 phydm_tx_collsion_th_init(void *dm_void); 1533 1534 void 1535 phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r); 1536 #endif 1537 1538 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1539 void 1540 odm_init_all_work_items( 1541 struct dm_struct *dm 1542 ); 1543 void 1544 odm_free_all_work_items( 1545 struct dm_struct *dm 1546 ); 1547 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1548 1549 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1550 void 1551 odm_dtc(struct dm_struct *dm); 1552 #endif 1553 1554 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1555 void 1556 odm_init_all_threads( 1557 struct dm_struct *dm 1558 ); 1559 1560 void 1561 odm_stop_all_threads( 1562 struct dm_struct *dm 1563 ); 1564 #endif 1565 1566 #endif 1567